1
Standard Products
UT54ACTS899
9-bit Latchable Transceiver with Parity Generator/Checker
Datasheet
May 16, 2012
www.aeroflex.com/Logic
FEATURES
Latchable transceiver with output source/ sink of 24m A
Option to select generate parity and check or "feed-through"
data/parity in directions A-t o-B or B -to -A
Independent latch enable for A-to-B and B-to-A directions
Select pin for ODD/EVEN parity
ERRA and ERRB output pins for parity checking
Ability to simultaneously generate and check parity
m Commercial CMOS
Operational environment:
- Total dose: 100K rad(Si)
- Single Event Latchup immune
- SEU immune
Standard Microcircuit Drawing 5962-06240
- QML compliant part
Package:
- 28-pin ceramic flatpack
DESCRIPTION
The UT54ACTS899 is a 9-bit to 9-bit parity tran sceiver with
transparent latches. The device can operate as a feed-through
transceiver or it can generate/check parity from the 8-bit data
busses in either direction. The UT54ACTS899 features inde-
pendent latch enables for the A-to-B direction and the B-to-A
direction, a select pin for ODD/EVEN parity, and separate
error signal output pins for checking parity.
PIN DESCRIP TION
Inputs Outputs
A0-A7 A Bus Data Inputs/Data Outputs
B0-B7 B Bus Data Inputs/Data Outputs
APAR, BPAR A and B Bus Parity Inputs
ODD/EVEN ODD/EVEN Parity Select, Active LOW for
EVEN Parity
GBA, GAB Output Enables for A or B Bus, Active Low
SEL Select Pin for Feed-through or Generate
Mode, LOW for Generate Mode
LEA, LEB Latch Enables for A and B Latches, HIGH
for Transparent Mode
ERRA, ERRB Error Signals for Checking Generated Par -
ity with Parity In, LOW if Error Occurs
28-Lead Flatpack
Pinout
1
2
3
4
5
7
6
28
27
26
25
24
22
23
ODD/EVEN
ERRA
LEA
A0
A1
A2
A3
VDD
GAB
B0
B1
B2
B4
821
A4 B5
B3
920
A5 B6
10 19
A6 B7
A7
APAR
GBA
VSS
11
12
13
14
18
17
16
15
BPAR
LEB
SEL
ERRB
2
LOGIC DIAGRAM
9-bit
Transparent
Latch
9-bit
Output
Buffer
9-bit
Output
Buffer
9-bit
Transparent
Latch
LEA
A0
A1
A2
A3
A4
A5
A6
A7
APAR
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(10)
(11)
(12)
GBA (13)
Parity
Generator
B0
B1
B2
B3
B4
B5
B6
B7
BPAR
(26)
(25)
(24)
(23)
(22)
(21)
(20)
(19)
(18)
OE GAB
(27)
LEB(17)
ERRA
(2)
Parity
Generator
ERRB
(15)
SEL (16)
ODD/EVEN (1)
1
0
mux
1
0
mux
OE LE
LE
3
FUNCTIONAL DESCRIPTION
The UT54ACTS899 has three principal modes of operation
which are outlined below. These modes apply to both A-to-B
and B-to-A directions.
- Bus A (B) communicates to Bus B (A), parity is generated
and passed on to the B (A) Bus as BPAR (APAR). If LEB
(LEA) is HIGH and the Mode Select (SEL) is LOW , the parity
generated from B[0:7] (A[0:7]) can be checked and moni-
tored by ERRB (ERRA).
FUNCTIONAL TABLE
- Bus A (B) communicates to Bus B (A) in a feed-through mode
if SEL is HIGH. Parity is still generated and checked as
ERRA and ERRB in the feed-through mode (can be used as
an interrupt to signal a data/parity bit error to the CPU).
- Independent Latch Enables (LEA and LEB) allow other per-
mutations of generating/checking. (see Function T able below)
H = High voltage level
L = Low voltage level
X = Do not care
Note 1: O/E = ODD/EVEN
INPUTS OPERATION
GAB GBA SEL LEA LEB
H H X X X Busses A and B are Tri-State (input A & B simultaneously)
H L L L H Generates parity from B[0:7] based on O/E (Note 1). Generated parity --> APAR.
Generated parity checked against BPAR and output as ERRB.
H L L H H Generates parity from B[0:7] based on O/E. Generated parity --> APAR.
Generated parity checked against BPAR and output as ERRB.
Generated parity also fed back through the A latch for generate/check as ERRA.
H L L X L Generates parity from B latch data based on O/E. Generated parity --> APAR.
Generated parity checked against latched BPAR and output as ERRB.
H L H X H BPAR/B[0:7] --> APAR/A[0:7] Feed-through mode.
Generated parity checked against BPAR and output as ERRB.
H L H H H BPAR/B[0:7] --> APAR/A[0:7] Feed-through mode.
Generated parity checked against BPAR and output as ERRB.
APAR/A[0:7] fed back through the A latch for generate/check as ERRA.
L H L H L Generates parity from A[0:7] based on O/E. Generated parity --> BPAR.
Generated parity checked against APAR and output as ERRA.
L H L H H Generates parity from A[0:7] based on O/E. Generated parity --> BPAR.
Generated parity checked against APAR and output as ERRA.
Generated parity also fed back through the B latch for generate/check as ERRB.
L H L L X Generates parity from A latch data based on O/E. Generated parity --> BPAR.
Generated parity checked against latched APAR and output as ERRA.
L H H H L APAR/A[0:7)]--> BPAR/B[0:7] Feed-through mode.
Generated parity checked against APAR and output as ERRA.
L H H H H APAR/A[0:7] --> BPAR/B[0:7] Feed-through mode.
Generated parity checked against APAR and output as ERRA.
BPAR/B[0:7] fed back through the B latch for generate/check as ERRB.
L L X X X Output to A bus and B bus (NOT ALLOWED).
4
RADIATION HARDNE SS SPECIFICATIONS 1
Notes:
1. Logic will not latchup during radiation ex posure within the limits defined in the table.
2. Not tested, inherent of CMOS technology.
ABSOLUTE MAXIMUM RATINGS1
Note:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, functional operation of the d e vice at
these or any other conditions beyo nd limits indicated in the opera tional sections is not recommended. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability and performance.
RECOMMENDED OPERATING CONDITIONS
PARAMETER LIMIT UNITS
Total Dose 1.0E5 rads(Si)
SEU Onset LET >108 MeV-cm2/mg
SEL Immune >108 MeV-cm2/mg
Neutron Fluence21.0E14 n/cm2
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage -0.3 to 6.0 V
VI/O Voltage any pin during operation -0.3 to VDD +0.3 V
TSTG Storage Temperature range -65 to +150 C
TJMaximum junction temperature +175 C
JC Thermal resistance junction to case 20 C/W
IIDC input current +10 mA
PDMaximum power dissipation mW
SYMBOL PARAMETER LIMIT UNITS
VDD Supply voltage 4.5 to 5.5 V
VIN Input voltage any pin 0 to VDD V
TC Temperature range -55 to +125 oC
tINRISE
tINFALL
Maximum input rise or fall time
(VIN transitioning between VIL (m ax) and VIH (min)) 20 ns
5
DC ELECTRICAL CHARACTERISTICS* 1
( VDD = 3.3 + 0.3V, TC = -55C to +125C); Unless otherwise noted, Tc is per the temperature ordered
SYMBOL PARAMETER CONDITION MIN MAX UNIT
VIL Low level input voltage2 VDD from 4.5V to 5.5V 0.8 V
VIH High level input voltag e2 VDD from 4.5V to 5.5V 2.0 V
IIN Input leakage current VDD from 4.5 to 5.5
VIN = VDD or VSS
-1 1 A
IOZ Three-state output leakage current VDD from 4.5 to 5.5
VIN = VDD or VSS
-10 10 A
IOS Short-circuit output current3, 4 VO = VDD or VSS
VDD from 4.5 to 5.5
-600 600 mA
VOL1 Low-level output voltage5IOL= 24mA -55C, +25oC
IOL= 24mA +125oC
IOL= 100A
VIN = 2.0V or 0.8V
VDD = 4.5 to 5.5
0.4
0.5
0.2
V
VOL2 Low-level output voltage5, 6 IOL= 50mA -55C, +25oC
VIN = 2.0V or 0.8V
VDD = 5.5V +125oC
0.8
1.0
V
VOH1 High-level output voltage5IOH= -24mA -55, +25oC
IOH= -24mA +125oC
IOH= -100A
VIN = 2.0V or 0.8V
VDD = 4.5 to 5.5V
VDD - 0.64
VDD - 0.8
VDD - 0.2
V
VOH2 High-level output voltage5, 6 IOH= -50mA -55C, 25oC
VIN = 2.0V or 0.8V +125oC
VDD = 5.5V
VDD -1.1
VDD -1.25
V
VIC+ Positive input clamp voltage For input under test, IIN = +18mA
VDD = 0.0V
0.4 1.5 V
VIC- Negative input clamp voltage For input under test, IIN = -18mA
VDD = open
-1.5 -0.4 V
6
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25×C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. All specifications valid for radiation dose 1E5 rad(Si) per MIL-STD-883, Method 1019.
2. Functional tests are conducted in accordance with MIL-STD-883 with the following input test conditions: VIH = VIH(min) + 20%, - 0%; VIL = VIL(max) + 0%, -
50%, as specified herein, for TTL, CMOS, or Schmitt compatible inputs. Devices may be tested using any input voltage within the above specified range, but are
guaranteed to VIH(min) and VIL(max).
3. Not more than one output may be shorted at a time for maximum duration of one second.
4. Supplied as a design limit, but not guaranteed or tested.
5. Per MIL-PRF-38535, for current density 5.0E5 amps/cm2, the maximum product of load capacitance (per output buffer) times frequency should not exceed 3,765
pF-MHz.
6. Transmission driving tests are performed at VDD = 5.5V, only one output loaded at a time with a duration not to exceed 2ms. The test is guaranteed, if not tested,
for VIN=VIH minimum or VIL maximum.
7. Power dissipation specified per switching output.
8. Guaranteed by characterization.
9. Power does not include power contribution of any CMOS output sink current.
10. Capacitance measured for initial qualification and when design changes may affect the value. Capacitance is measured between the designated terminal and VSS
at frequency of 1MHz and a signal amplitude of 50mV rms maximum.
Ptotal Power dissipation7, 8, 9 CL = 20pF
VDD from 4.5 to 5.5
1.0 mW/
MHz
IDDQ Standby Supply Current VDD
Pre-Rad 25oC
Pre-Rad -55oC to +125oC
Post-Rad 25oC
VIN = VDD or VSS
VDD = 5.5
OE=VDD
OE=VDD
OE=VDD
10
160
A
A
IDDQ Quiescent Supply Current Delta, TTL in-
put level
Pre-Rad 25oC, Pre-Rad -55oC to +125oC
Post-Rad 25oC
For input under test
VIN = VDD - 2.1V
For other inputs
VIN = VDD or VSS
VDD = 5.5V
1.6
mA
CIN Input capacitance 10 = 1MHz @ 0V
VDD from 4.5 to 5.5
21 pF
COUT Output capacitance10 = 1MHz @ 0V
VDD from 4.5 to 5.5
21 pF
7
AC ELECTRICAL CHARACTERISTICS 1
(VDD = 3.3 + 0.3V, TC = -55C to +125C); Unless othe rwi se noted, Tc is per the temperature ordered)
SYMBOL PARAMETER MINIMUM MAXIMUM UNIT
tPHL1 Propagation Delay - An, Bn to Bn, An 4.0 11.5 ns
tPLH1 Propagation Delay - An, Bn to Bn, An 4.0 11.5 ns
tPHL2 Propagation Delay - APAR, BPAR to BPA R, APAR 4.0 11.5 ns
tPLH2 Propagation Delay - APAR, BPAR to BPA R , APAR 4.0 11.5 ns
tPHL3 Propagation Delay - An, Bn to BPAR, APAR 5.0 12.0 ns
tPLH3 Propagation Delay - An, Bn to BPAR, APAR 5.0 12.0 ns
tPHL4 Propagation Delay - An, Bn to ERRA, ERRB 5.0 12.0 ns
tPLH4 Propagation Delay - An, Bn to ERRA, ERRB 5.0 12.0 ns
tPHL5 Propagation Delay - ODD/EVEN to ERRA, ERRB 4.0 9.0 ns
tPLH5 Propagation Delay - ODD /EVEN to ERRA, ERRB 4.0 9.0 ns
tPHL6 Propagation Delay - ODD/EVEN to APAR, BPAR 4.0 9.0 ns
tPLH6 Propagation Delay - ODD /EVEN to APAR, BPAR 4.0 9.0 ns
tPHL7 Propagation Delay - APAR, BPAR to ERRA, ERRB 4.0 9.0 ns
tPLH7 Propagation Delay - APAR, BPAR to ERRA, ERRB 4.0 9.0 ns
tPHL8 Propagation Delay - SEL to APAR, BPAR 3.5 8.5 ns
tPLH8 Propagation Delay - SEL to APAR, BPAR 3.5 8.5 ns
tPHL9 Propagation Delay - LEA, LEB to Bn, An 3.5 8.5 ns
tPLH9 Propagation Delay - LEA, LEB to An, Bn 3.5 8.5 ns
tPHL10 Propagation Delay - LEA, LEB to BPAR, APAR 4.0 9.0 ns
tPLH10 Propagation Delay - LEA, LEB to APAR, BPAR 4.0 9.0 ns
tPHL11 Propagation Delay - LEA, LEB to ERRA, ERRB 5.0 12.0 ns
tPLH11 Propagation Delay - LEA, LEB to ERRA, ERRB 5.0 12.0 ns
tPZH1 Output Enable Time - GBA or GAB to An, Bn 3.5 9.5 ns
8
Notes:
* For devices procured with a total ionizing dose tolerance guarantee, the post-irradiation performance is guaranteed at 25×C per MIL-STD-883 Method 1019, Condition
A up to the maximum TID level procured.
1. All specifications valid for radiation >1E5 rads(Si) per MIL-STD-883, Method 1019.
2. Verified by functional test.
tPZL1 Output Enable Time - GBA or GAB to An, Bn 3.5 9.5 ns
tPZH2 Output Enable Time - GBA or GAB to BP AR or AP AR 3.5 9.5 ns
tPZL2 Output Enable Time - GBA or GAB to BP AR or AP AR 3.5 9.5 ns
tPHZ1 Output Disable Time - GBA or GAB to An, Bn 2.0 6.0 ns
tPLZ1 Output Disable Time - GBA or GAB to An, Bn 2.0 6.0 ns
tPHZ2 Output Disable Time - GBA or GAB to BPAR, to
APAR 2.0 6.0 ns
tPLZ2 Output Disable Time - GBA or GAB to BPAR, to
APAR 2.0 6.0 ns
tSSetup Time, High or Low, An, Bn, APAR, BPAR to
LEA, LEB 1.0 ns
tHHold Time, High or Low, An, B n, APAR, BPAR to
LEA, LEB 1.5 ns
tW2Pulse Width for LEA, LEB 4.0 ns
fMAX2Maximum clock frequency 80 MHz
Test Load or Equivalent1
VDD
40pF 100ohms
VDD
100ohms
Notes
1. Equivalent test circuit means that DUT performance will be correlated and remai n guaranteed to the applicable test circuit, above, whenever a test platform
change necessitates a deviation from the applicable test circuit.
9
AC TIMING DIAGRAMS
An, APAR
(Bn, BPAR)
Bn, BPAR
(An, APAR)
VIM
VOM
VOH
VOL
INPUT
OUTPUT
tPLH1,2 tPHL1,2
VIM
VOM
VOM
+3.0V
0V
Note:
1. VIM = 1.5V, VOM = VDD/2
2. SEL = 3.0V = H
Figure 1. Propagation Delay, An to Bn, Bn to An, APAR to BPAR, BPAR to APAR
Figure 2. Propagation Delay, An to BPAR, or Bn to APAR (with Even Parity Mode Shown)
An
(Bn) ODD PAR ITY ODD PARITY
EVEN PARITY
VIM VIM
tPHL3 tPLH3 VOH
VOL
INPUT
OUTPUT
BPAR
(APAR) VOM
VOM
+3.0V
0V
Note:
1. VIM = 1.5V, VOM = VDD/2
2. SEL = ODD/EVEN = VSS = L
3. LEA (LEB) = 3.0V = H
10
An
(Bn) EVEN PARITY EVEN PARITYODD PARITY
VIM VIM
tPHL4 tPLH4
VOM
VOH
VOL
INPUT
OUTPUT
ERRA
(ERRB) VOM
+
3
.
0
V
0V
Note:
1. VIM = 1.5V, VOM = VDD/2
2. APAR (BPAR) = ODD/EVEN = VSS = L
3. LEA (LEB) = 3.0V = H
Figure 4. Pr opagation Delay, ODD/EVEN to ERRA or ODD/EVEN to ERRB
Figure 3. Propagation Delay, An to ERRA or Bn to ERRB (with Even Parity Mode Shown)
Note:
1. VIM = 1.5V, VOM = VDD/2
2. APAR (BPAR) = VSS = L
An
(Bn) ODD PARITY
ODD/EVEN VIM VIM
VOM
VOH
INPUT
OUTPUT
tPLH5
INPUT
ERRA
(ERRB) VOM
VOL
tPHL5
+3.0V
+3.0V
0V
0V
11
An
(Bn)
BPAR
(APAR)
EVEN PARITY
ODD/EVEN VIM VIM
VOM
VOH
INPUT
OUTPUT
tPLH6
INPUT
VOM
VOM
VOL
tPHL6
+3.0V
+3.0V
0V
0V
Figure 5. Propagation Delay, ODD/EVEN to APAR or ODD/EVEN to BPAR (with Even Parity Mode Shown)
Note:
1. VIM = 1.5V, VOM = VDD/2
2. SEL = APAR (BPAR) = VSS = L
Figure 6. Pr opagation Delay, APAR to ERRA or BPAR to ERRB
(With Even Parity Mode Shown with Even Data Parity. Odd Parity Mode would cause Inverted Output.)
Note:
1. VIM = 1.5V, VOM = VDD/2
2. ODD/EVEN = VSS = L
An
(Bn) EVEN PARITY
VIM VIM
VOM
VOH
INPUT
OUTPUT
tPLH7 tPHL7
INPUT
APAR
(BPAR)
VOM
ERRA
(ERRB) VOM
VOL
+3.0V
0V
+3.0V
0V
12
An
(Bn) EVEN PARITY
VIM
VOM
VOH
INPUT
OUTPUT
tPLH8
INPUT
BPAR
(APAR)
SEL
VOL
VOM
VIM
tPHL8
+3.0V
0V 0V
+3.0V
0V
+3.0V
Figure 7. Pr opagation Delay, SEL to BPAR or SEL to APAR
(With Odd Parity Mode Sho w n with Even Data Parity. Even Parity Mode would cause Inverted Output.)
Note:
1. VIM = 1.5V, VOM = VDD/2
2. ODD/EVEN = 3.0V = H
3. APAR (BPAR) = VSS = L
Figure 8. Propagation Delay, LEA to BPAR or LEB to APAR, LEA to Bn or LEB to An
Note:
1. VIM = 1.5V, VOM = VDD/2
2. SEL = 3.0V = H
VIM
VOM
VOH
INPUT
OUTPUT
tPLH9,10
LEA
(LEB)
tPHL9,10
VIM
Bn, BPAR
(An, APA R ) VOM
VOL
APAR, An
(BP AR ,Bn ) INPUT
+3.0V
0V
+3.0V
0V
13
Note:
1. VIM = 1.5V, VOM = VDD/2
2. APAR (BPAR) = ODD/EVEN = 3.0V = H
Figure 9. Propagation Delay, LEA to ERRA or LEB to ERRB (with Odd Parity Mode Shown)
Figure 10. 3-State Output Enable Time to High Level and Output Disable Time from High Level
Note:
1. VIM = 1.5V, VOM = VDD/2
INPUT
An, APAR
(Bn, BPAR)
VIM VIM
VOM
0.8VDD-0.2V OUTPUT
VOH
VOM
tPHZ1,2
tPZH1,2
GBA
(GAB)
VOM+0.2V
+3.0V
0V
VIM
VOM
VOH
INPUT
OUTPUT
tPLH11
INPUT
LEA
(LEB)
tPHL11
ODD PARITY ODD PARITY
VIM
EVEN PARITY
ERRA
(ERRB) VOL
VOM
An
(Bn)
+3.0V
+3.0V
0V
0V
14
Note:
1. VIM = 1.5V, VOM = VDD/2
Figure 11. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
INPUT
An, APAR
(Bn, BPAR)
VIM VIM
VOM
GBA
(GAB)
OUTPUT
VOM
VOL
tPLZ1,2
tPZL1,2
VOM - 0.2V 0.2VDD+0.2V
+3.0V
0V
Note:
1. VIM = 1.5V, VOM = VDD/2
Figure 12. Data Setup and Hold Times, Pulse Width High
LEA , LEB tw
VALID
VIM VIM VIM INPUT
tH
tS
APAR, An
BPAR ,Bn VIM INPUT
+
3
.0
V
0V
+3.0V
0
V
15
Packaging
Figure 13. 28-pin Ceramic Flatpack
NOTE:
1. Seal ring is connected to VSS.
2. Units are in inches.
3. All exposed metalized areas must be gold plated 100 to 225 microinches thick and all bottom side expo sed
metalized areas must be gold plated to 60 microinches thick nominal. Both sides shall be over electroplated
nickel undercoating 10 0 to 350 microinches per MIL-PRF-38535.
16
ORDERING INFORMATION
UT54ACTS899: SMD
5962 * 06240 ** * * *
Lead Finish: (Notes 1 & 2)
(A) = Solder
(C) = Gold
(X)= Factory Option (Gold or Solder)
Case Outline:
(X) = 28-Lead BB Ceramic Flatpack
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Device Types:
(01) = 9-bit latchable Transceiver with Parity Generator/Checker
Drawing Number: 06240
Total Dose: (Note 3)
(R) = 1E5 rads(Si)
Federal Stock Class Designator: No Options
Notes:
1. Lead finish (A, C, or X) must be specified.
2. If an "X" is specified when ordering, then the part marking will match the lead finish and will be either "A" (solder) or "C" (gold).
3. Total dose radiation must be specifi ed when ordering . QML-Q and QM L-V are not available withou t radiation hardening. For prototyping inquiries, contact f ac-
tory.
17
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