TLC1225I, TLC1225M SELF-CALIBRATING 12-BIT-PLUS-SIGN ANALOG-TO-DIGITAL CONVERTERS SLAS029B - AUGUST 1990 - REVISED DECEMBER 1993 * * * * * * * * * * * Advanced LinCMOS Technology Self Calibration Eliminates Expensive Trimming at Factory and Offset Adjustment in the Field 12-Bit-Plus-Sign Resolution 12-Bit Linearity 12-s Conversion Period at fclock = 2 MHz Compatible With All Microprocessors Single 5-V and 5-V Supply Operation True Differential Analog Voltage Inputs With - Vref to Vref Differential Input Range For Single 5-V Supply, Input Common-Mode Voltage Range is 0 V to 5 V For 5-V Supplies, Input Common-Mode Voltage Range is - 5 V to 5 V Unipolar or Bipolar Operation 2s-Complement Output Low Power 85 mW Max on TLC1225I 87.5 mW Max on TLC1225M J OR NW PACKAGE (TOP VIEW) ANLG VCC - IN - IN + ANLG GND REF ANLG VCC + TIE HIGH CLK IN WR CS RD DGTL GND READY OUT INT 1 28 2 27 3 26 4 25 5 24 6 23 7 22 8 21 9 20 10 19 11 18 12 17 13 16 14 15 DGTL VCC D12 D11 D10 D9 D8 D7 D6 D5/D15 D4/D14 D3/D13 D2/D12 D1/D11 D0/D10 I/O Bus FK OR FN PACKAGE (TOP VIEW) ANLG GND IN+ IN- ANLG VCC - DGTL VCC D12 D11 * * description DGTL GND READY OUT INT D0/D10 D1/D11 D2/D12 D3/D13 4 3 2 1 28 27 26 The TLC1225I and TLC1225M converters are 5 25 D10 REF manufactured with Texas Instruments highly 24 D9 ANLG VCC+ 6 efficient Advanced LinCMOS technology. The 23 D8 TIE HIGH 7 TLC1225I and TLC1225M CMOS analog-to8 22 D7 CLK IN digital converters (ADCs) can be operated with a 9 21 D6 WR single 5-V supply or with 5-V supplies. The 20 D5/D15 CS 10 differential input range is - Vref to Vref in both 11 19 D4/D14 RD supply configurations. The common-mode input 12 13 14 15 16 17 18 range is ANLG VCC - to ANLG VCC +. For single 5-V supply operation, grounding IN - corresponds to standard unipolar conversion. For 5-V supply operation, grounding IN - corresponds to standard bipolar conversion. Conversion is performed via the successive-approximation method. The TLC1225x outputs the converted data in a parallel word and interfaces directly to a 16-bit data bus. Negative numbers are given in the 2s-complement data format. All digital signals are fully TTL and CMOS compatible. This converter uses a self-calibration technique by which seven of the internal capacitors in the capacitive array of the A/D conversion circuitry can be automatically calibrated. The internal capacitors are calibrated during a nonconversion capacitor-calibrate cycle in which all seven of the internal capacitors are calibrated at the same time. A conversion period requires only 24 clock cycles. Self calibration requires 300 clock cycles. The calibration or conversion cycle can be initiated at any time by issuing the proper command word to the data bus. The self-calibrating technique eliminates the need for expensive trimming of thin-film resistors at the factory and provides excellent performance at low cost. The conversion period is the reciprocal of the conversion rate and includes the access, sample, setup, and A/D conversion times. Advanced LinCMOS is a trademark of Texas Instruments Incorporated. Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 1 TLC1225I, TLC1225M SELF-CALIBRATING 12-BIT-PLUS-SIGN ANALOG-TO-DIGITAL CONVERTERS SLAS029B - AUGUST 1990 - REVISED DECEMBER 1993 description (continued) The TLC1225I is characterized for operation from - 40C to 85C. The TLC1225M is characterized over the full military temperature range of - 55C to 125C. AVAILABLE OPTIONS PACKAGED DEVICES TA CERAMIC CHIP CARRIER (FK) PLASTIC CHIP CARRIER (FN) - 40C to 85C CERAMIC DIP (J) PLASTIC DIP (NW) TLC1225IFN - 55C to 125C TLC225INW TLC1225MFK TLC1225MJ functional block diagram Microprocessor 8-Bit Calibration DAC ANLG VCC - 13-Bit Capacitor DAC and S/H IN + 8 8 8-Bit Switch Control 8-Bit SAR Register 1 Comp 13-Bit Capacitor DAC and S/H IN - REF 13 Register 2 AUL 8 8-Word RAM 8-Bit Calibration DAC Address Counter 1 13 13 Address Counter 2 Clocks 5-V - 10-V Translator 6 13-Bit Switch Control Input Data Latches 13-Bit SAR 13-Bit Calibration Control Logic 13-Bit Data Latch 13 6 I/O BUS 13 MUX 13 Program Counter TIE HIGH INT CS WR RD READY OUT 2 Control ROM POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 8-Bit Data Path TLC1225I, TLC1225M SELF-CALIBRATING 12-BIT-PLUS-SIGN ANALOG-TO-DIGITAL CONVERTERS SLAS029B - AUGUST 1990 - REVISED DECEMBER 1993 detailed description calibration of comparator offset The following actions are performed to calibrate the comparator offset: 1. The IN+ and IN - inputs are internally shorted together so that the converter input is zero. A coarse comparator offset calibration is performed by storing the offset voltages of the interconnecting comparator stages on the coupling capacitors that connect these stages (see Figure 1). The storage of offset voltages is accomplished by closing all switches and then opening switches A and A', then switches B and B', and then C and C'. This process continues until all interconnecting stages of the comparator are calibrated. After this action, some of the comparator offset remains uncalibrated. GND B A A' GND GND C B' GND C' GND GND Figure 1. Comparator Offset Null 2. An A/D conversion is done on the remaining offset with the 8-bit calibration digital-to-analog converters (DACs) and 8-bit successive-approximation register (SAR), and the result is stored in the RAM. calibration of the ADC capacitive capacitor array The following actions are performed to calibrate capacitors in the 13-bit DACs that comprise the ADC's capacitive array: 1. IN+ and IN - are internally disconnected from the 13-bit DACs. 2. The most significant bit (MSB) capacitor is tied to REF, while the rest of the array capacitors are tied to GND. The A/D conversion result for the remaining comparator offset, obtained in step 2 above, is retrieved from the RAM and is input to the 8-bit DACs. 3. Step 1 of the calibration of comparator offset sequence is performed. The 8-bit DAC input is returned to zero, and the remaining comparator offset is then subtracted; thus, the comparator offset is completely corrected. 4. The MSB capacitor is tied to GND, while the rest of the array capacitors (Cx), are tied to REF. An MSB capacitor voltage error (see Figure 2) on the comparator output occurs if the MSB capacitor does not equal the sum of the other capacitors in the capacitive array. This error voltage is converted to an 8-bit word from which a capacitor error is computed and stored in the RAM. 5. The capacitor voltage error for the next most significant capacitor is calibrated by keeping the MSB capacitor grounded and then performing the above steps 1 - 4 while using the next most significant capacitor instead of the MSB capacitor. The seven most significant capacitors are calibrated in this manner. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 3 TLC1225I, TLC1225M SELF-CALIBRATING 12-BIT-PLUS-SIGN ANALOG-TO-DIGITAL CONVERTERS SLAS029B - AUGUST 1990 - REVISED DECEMBER 1993 Vref (step 3) GND (step 4) CMSB + CX MSB-Capacitor Voltage Error (step 4) CX CMSB - GND (step 3) Vref (step 4) Figure 2. Capacitor Array Null analog-to-digital conversion The following steps are performed in the analog-to-digital conversion process: * * * Step 1 of the calibration of comparator offset sequence is performed. The A/D conversion result for the remaining comparator offset, obtained in step 2 of the calibration of comparator offset, is retrieved from the RAM and is input to the 8-bit DACs. The comparator offset is completely corrected. IN+ and IN - are sampled into the 13-bit capacitive arrays. The 13-bit analog-to-digital conversion is performed. As the successive-approximation conversion proceeds successively through the seven most significant capacitors, the error for each of these capacitors is recovered from the RAM and accumulated in a register. This register controls the 8-bit DACs so the total accumulated error for these capacitors is subtracted out during the conversion process. absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage (ANLG VCC + and DGTL VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 V Supply voltage, ANLG VCC - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 7.5 V Differential supply voltage, ANLG VCC + - ANLG VCC - . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V Clock input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Control input voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to VCC + 0.3 V Analog input (IN +, IN -) voltage range, VI + and VI - . . . . . . . . . ANLG VCC - - 0.3 V to ANLG VCC + + 0.3 V Reference voltage range, Vref . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to ANLG VCC + + 0.3 V Voltage range, TIE HIGH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to ANLG VCC + + 0.3 V Output voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 0.3 V to DGTL VCC + 0.3 V Input current (per pin) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 mA Input current (per package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Continued total dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Dissipation Rating Table Operating free-air temperature range, TA: TLC1225I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 40C to 85C TLC1225M . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 55C to 125C Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . - 65C to 150C Case temperature for 60 seconds: FK or FN package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: NW package . . . . . . . . . . . . . . . . 260C Lead temperature 1,6 mm (1/16 inch) from the case for 60 seconds: J package . . . . . . . . . . . . . . . . . . 300C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: All analog voltages are referred to ANLG GND, and all digital voltages are referred to DGTL GND. 4 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC1225I, TLC1225M SELF-CALIBRATING 12-BIT-PLUS-SIGN ANALOG-TO-DIGITAL CONVERTERS SLAS029B - AUGUST 1990 - REVISED DECEMBER 1993 DISSIPATION RATING TABLE PACKAGE TA 25C POWER RATING DERATING FACTOR TA = 70C POWER RATING TA = 85C POWER RATING TA = 125C POWER RATING FK 1375 mW 11.0 mW/C 880mW 715 mW 275 mW FN 1400 mW 11.2 mW/C 896 mW 728 mW 280 mW J 1375 mW 11.0 mW/C 880 mW 715 mW 275 mW N 1150 mW 9.2 mW/C 736 mW 598 mW -- recommended operating conditions Supply voltage MIN MAX ANLG VCC + 4.5 5.5 ANLG VCC - - 5.5 DGTL VCC 4.5 ANLG GND All digital inputs except CLK IN 2 Low-level input voltage, g , VIL (ANLG VCC = DGTL VCC = 4.75 to 5.25 V) All digital inputs except CLK IN 0.8 CLK IN 1.4 V 3.5 Analog input voltage, VI+, VI - ANLG VCC - - 0.05 V 5.5 High-level input voltage, g g , VIH (ANLG VCC = DGTL VCC = 4.75 to 5.25 V) CLK IN UNIT ANLG VCC + 0.05 V High-level input voltage, TIE HIGH, VIH ANLG VCC = DGTL VCC = 5 V Clock input frequency, fclock ANLG VCC = DGTL VCC = 5 V 0.3 2.6 Clock duty cycle ANLG VCC = DGTL VCC = 5 V 40% 60% Pulse duration, CS and WR low, tw ANLG VCC = DGTL VCC = 5 V 15 ns Setup time, I/O bus in before WR or CS, tsu ANLG VCC = DGTL VCC = 5 V 60 ns Hold time, I/O bus in after WR or CS, th ANLG VCC = DGTL VCC = 5 V 50 Operating free-air free air temperature, temperature TA 2 V V ns TLC1225I - 40 85 TLC1225M - 55 125 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 MHz C 5 TLC1225I, TLC1225M SELF-CALIBRATING 12-BIT-PLUS-SIGN ANALOG-TO-DIGITAL CONVERTERS SLAS029B - AUGUST 1990 - REVISED DECEMBER 1993 electrical characteristics over recommended operating free-air temperature range, ANLG VCC+ = DGTL VCC = Vref = 5 V, ANLG VCC- = -5 V or ANLG GND (unless otherwise noted) (see Note 2) PARAMETER TEST CONDITIONS DGTL VCC = 4 4.75 75 V IO = - 1.8 mA IO = - 50 A DGTL VCC = 4.75 V,, See Note 3 IO = 3.2 mA,, VOH High level output voltage High-level VOL Low level output voltage Low-level rref Input resistance, REF IIH IIL High-level input current IOZ High impedance state output leakage current High-impedance-state VO = 0 VO = 5 V IO Output current VO = 0 VO = 5 V DGTL ICC Supply current from DGTL VCC fclock = 2 MHz, CS high ANLG ICC + Supply current from ANLG VCC + fclock MHz l k = 2 MHz, CS high ANLG ICC - Supply current from ANLG VCC - TLC1225I TLC1225M MIN 0.4 0.45 1 TLC1225I TLC1225M UNIT V 4.5 VI = 5 V VI = 0 Low-level input current MAX 2.4 V 10 M 5 A -5 A -3 3 -6 A mA 8 6 9 8.5 mA mA fclock = 2 MHz, CS high -3 mA NOTES: 2. The input voltage range is defined as: VI + = - 5.05 V to 5.05 V, VI - = - 5.05 V to 5.05 V, and | VI + - VI - | 5.05 V when ANLG VCC - = - 5 V. The input voltage range is defined as: VI + = - 0.05 V to 5.05 V, VI - = - 0.05 V to 5.05 V, and | VI + - VI - | 5.05 V when ANLG VCC - = ANLG GND. 3. IO = 4 mA for READY OUT, INT, and D12. 6 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC1225I, TLC1225M SELF-CALIBRATING 12-BIT-PLUS-SIGN ANALOG-TO-DIGITAL CONVERTERS SLAS029B - AUGUST 1990 - REVISED DECEMBER 1993 electrical characteristics over recommended operating free-air temperature range, ANLG VCC+ = DGTL VCC = Vref = 5 V, ANLG VCC- = -5 V or ANLG GND, fclock = 2 MHz (unless otherwise noted) (see Note 2) PARAMETER EL ED TEST CONDITIONS MIN TYP Differential linearity Zero error MAX 0.012% Integral linearity error - 5 V < ((IN + - IN -)) < 5 V,, VCC+ = 5 V, VCC - = - 5 V -1 1 0 < (IN ( + - IN -)) < 5.05 V,, VCC+ = 5 V, VCC - = 0 -1 1 LSB 1.5 TLC1225I 1 TLC1225M 2 Unadjusted positive and negative full-scale error Temperature coefficient of gain Temperature coefficient of offset point Zero error Positive and negative g full-scale error UNIT FSR LSB LSB 15 ppm/C 1.5 ppm/C 0.75 ANLG VCC + = 5 V 5%, ANLG VCC - = - 5 V 5%, 5% DGTL VCC = 5 V 5% 0.75 0 75 kSVS Supply voltage sensitivity CMRR Common-mode rejection ratio IN - = IN + = - 5 V to 5 V 65 dB Common-mode rejection j ((maximum code change g from code 0000000000000) IN - = IN + = - 5 V to 5 V 2 LSB tconv Conversion period (1/fclock l k) (see Notes 4 and 5) fclock 2 6 MHz l k = 2.6 24 clock cycles ta Access time ((delay y from falling g edge g of CS RD to data output) CL = 100 pF,, fclock = 2.6 MHz 95 ns tdi dis Disable time,, output (delay ( y from rising g edge g of RD to high-impedance state) RL = 2 k,, CL = 100 pF,, fclock = 2.6 MHz 90 ns Delay time, control signal edge to READY OUT fclock = 2.6 MHz fclock = 2.6 MHz Linearity error td1(READY) td2(READY) Delay time, control signal edge to READY OUT LSB 0.25 100 ns 100 ns td(INT) Delay time, RD or WR to reset of INT fclock = 2.6 MHz 100 ns All typical values are at TA = 25C. FSR is full-scale range: 0.012% FSR linearity error is equivalent to 1 LSB = 1.22 mV. No missing codes NOTES: 2. The input voltage range is defined as: VI + = - 5.05 V to 5.05 V, VI - = - 5.05 V to 5.05 V, and | VI + - VI - | 5.05 V when ANLG VCC - = - 5 V. The input voltage range is defined as: VI + = - 0.05 V to 5.05 V, VI - = - 0.05 V to 5.05 V, and | VI + - VI - | 5.05 V when ANLG VCC - = ANLG GND. 4. If INT and RD go low within the same fclock period, INT is not reset until WR is brought low. If INT and RD do not go low within the same fclock period, INT is reset. 5. The conversion period is the reciprocal of the conversion rate and includes the access, sample, setup, and A/D conversion times. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 7 TLC1225I, TLC1225M SELF-CALIBRATING 12-BIT-PLUS-SIGN ANALOG-TO-DIGITAL CONVERTERS SLAS029B - AUGUST 1990 - REVISED DECEMBER 1993 PARAMETER MEASUREMENT INFORMATION Input Sampling Conversion 0 3 10 24 50% CS tconv WR 50% 50% 50% RD 50% td(INT) 50% INT td2(READY) td2(READY) td1(READY) td1(READY) READY 50% 50% 50% 50% th tdis tsu I/O Bus ta 10% 10% In Command to Calibrate 7 Capacitors and Offset (requires 300 clock cycles) 10% In Command to Initiate Conversion Figure 3. Timing Diagram 8 POST OFFICE BOX 655303 10% Out * DALLAS, TEXAS 75265 TLC1225I, TLC1225M SELF-CALIBRATING 12-BIT-PLUS-SIGN ANALOG-TO-DIGITAL CONVERTERS SLAS029B - AUGUST 1990 - REVISED DECEMBER 1993 PARAMETER MEASUREMENT INFORMATION DGTL VCC Data Output RD CL VCC RD GND 50% 90% 10% tdis RL VOH Data Output GND 90% DGTL VCC VCC RD GND RL RD Data Output CL 50% 90% 10% tdis VCC Data Output VOL 10% Figure 4. Load Circuits and Waveforms APPLICATION INFORMATION unipolar and bipolar operation For single-ended signal input, the IN+ input is connected to the analog source and the IN- input is connected to ANLG GND. In the unipolar configuration, the ADC uses a single 5-V supply and the analog input voltage range is 0 V to 5 V. Data bit D12 always remains low. In the bipolar configuration, the ADC uses 5-V supplies and the analog input voltage range is - 5 V to 5 V. Data bit D12 indicates the sign of the input signal. In both configurations, the 13-bit data format is extended sign with 2s-complement, right-justified data. power-up sequence Calibration is not automatic on power up. Calibration is initiated by writing control words to the six least significant bits of the data bus. Vref must have fully settled before calibration is initiated. If addressed or initiated, conversion can begin after the first clock cycle; however, full A/D conversion accuracy is not established until after internal capacitor calibration. conversion period start sequence The writing of the conversion command word to the six least significant bits of the data bus when either CS or WR goes high initiates the conversion sequence. analog sampling sequence Sampling of the input signal occurs during clock cycles 3 through 10 of the conversion sequence. completed A/D conversion When INT goes low, conversion is complete and the A/D result can be read. A new conversion period can begin immediately. The A/D conversion is complete at the end of clock cycle 24 of the conversion period. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 9 TLC1225I, TLC1225M SELF-CALIBRATING 12-BIT-PLUS-SIGN ANALOG-TO-DIGITAL CONVERTERS SLAS029B - AUGUST 1990 - REVISED DECEMBER 1993 APPLICATION INFORMATION aborting a conversion period in process and beginning a new conversion If a conversion period is initiated while a conversion sequence is in process, the ongoing conversion is aborted and a new conversion period begins. reading the conversion result When both CS and RD go low, all 13 bits of conversion data are output to the I/O bus. The format of the output is extended sign with 2s-complement, right-justified data. The sign bit D12 is low if VI + - VI - is positive and high if VI + - VI - is negative. general reset INT When reading the conversion data, the falling edge of the first low-going combination of CS and RD reset INT. The falling edge of the low-going combination of CS and WR also reset INT. ready out For high-speed microprocessors, READY OUT allows the TLC1225 to insert a wait state in the microprocessor's read or write cycle. reference voltage (Vref) This voltage defines the range for | VI + - VI - |. When | VI + - VI - | equals Vref, the highest conversion data value results. When | VI + - VI - | equals 0, the conversion data value is zero. For a given input, the conversion data changes ratiometrically with changes in Vref. Calibration should be performed with the same value of Vref that is used during conversion. TIE HIGH TIE HIGH is a digital input and should be tied high. calibration and conversion period considerations Calibration of the internal capacitors and A/D conversion are two separate actions. Each action is independently initiated. A calibration command should be initiated prior to subsequent conversions; it is not necessary to recalibrate before each conversion. Capacitor calibration is expected to last indefinitely as long as the clock signal and power are not interrupted. The offset calibration may drift with temperature changes. The temperature coefficient of the offset point is shown in the electrical characteristics table. Periodic calibration is recommended. Calibration and conversion commands require 300 and 24 clock cycles, respectively. The calibrate and conversion commands are initiated by writing control words on the six least significant bits of the data bus. These control words are written into the IC when either CS or WR goes high. The initiation of these commands is illustrated in Figure 3. The bit patterns for the commands are shown in Table 1. Table 1. Conversion Commands I/O BUS COMMAND CS + WR Conversion Calibrate D15 D13 D12 D11 D10 H L X X X L 24 L X L L L L 300 Calibration is lost when the clock is stopped. 10 REQUIRED NUMBER OF CLOCK CYCLES D14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 TLC1225I, TLC1225M SELF-CALIBRATING 12-BIT-PLUS-SIGN ANALOG-TO-DIGITAL CONVERTERS SLAS029B - AUGUST 1990 - REVISED DECEMBER 1993 APPLICATION INFORMATION analog inputs differential inputs provide common-mode rejection The differential inputs reduce common-mode noise. Common-mode noise is noise common to both IN + and IN- inputs, such as 60-Hz noise. There is no time interval between the sampling of the IN + and IN -, so these inputs are truly differential. No conversion errors result from a time interval between the sampling of the IN + and IN- inputs. input bypass capacitors Input bypass capacitors can be used for noise filtering; however, the charge on these bypass capacitors is depleted during the input sampling sequence when the internal sampling capacitors are charged. The charging of the bypass capacitors through the differential source resistances must keep pace with the charge depletion of the bypass capacitors during the input sampling sequence. Higher source resistances reduce the amount of charging current for the bypass capacitors. Also fast, successive conversion has the greatest charge depletion effect on the bypass capacitors. The above phenomenon becomes more significant as source resistances and the conversion rate (i.e., higher clock frequency and conversion initiation rate) increase. In addition, if the above phenomenon prevents the bypass capacitors from fully charging between conversions, voltage drops across the source resistances result due to the ongoing bypass capacitor charging currents. The voltage drops cause a conversion error. Also, the voltage drops increase with higher | VI + - VI - | values, higher source resistances, and lower charge on the bypass capacitors (i.e., faster conversion rate). For low-source-resistance applications (Rsource < 100 ), a 0.001-F bypass capacitor at the inputs prevents pickup due to the series lead inductance of a long wire. A 100- resistor can be placed between the capacitor and the output of an operational amplifier to isolate the capacitor from the operational amplifier. input leads The input leads should be kept as short as possible since the coupling of noise and digital clock signals to the the inputs can cause errors. power supply considerations Noise spikes on the VCC lines can cause conversion error. Low-inductance tantalum capacitors (> 1 F) with short leads should be used to bypass ANLG VCC and DGTL VCC. A separate regulator for the TLC1225 and other analog circuitry greatly reduces digital noise on the supply line. A ferrite bead or equivalent inductance can be used between the analog and digital ground planes if the digital ground noise is excessive. POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 11 TLC1225I, TLC1225M SELF-CALIBRATING 12-BIT-PLUS-SIGN ANALOG-TO-DIGITAL CONVERTERS SLAS029B - AUGUST 1990 - REVISED DECEMBER 1993 APPLICATION INFORMATION (4095) 0 1111 1111 1111 (4094) 0 1111 1111 1110 Positive Full-Scale Transition Output Code Zero Transition (2) 0 0000 0000 0010 (1) 0 0000 0000 0001 (0) 0 0000 0000 0000 LSB 1 1111 1111 1111 (- 1) - Vref + Vref 1 1111 1111 1110 (- 2) CODE TRANSITION (DECIMAL) Negative Full-Scale Transition - 4096 to - 4095 - 1 to 0 0 to 1 4094 to 4095 LSB = Vref / 4096 1 0000 0000 0001 (- 4095) 1 0000 0000 0000 (- 4096) Analog Input Voltage [VIN(+) - VIN(-)] ANALOG INPUT VOLTAGE (LSB) - 4095.5 - 0.5 0.5 4094.5 Figure 5. Transfer Characteristic 3 TIE HIGH IN + 7 DGTL VCC 28 Signal In 2 IN - ANLG VCC + (see Note A) 0.1 F (see Notes B and C) 4 + 0.1 F (see Note B) + 10 F - (see Note B) 1 REF ANLG VCC - 0.1 F (see Note B) ANLG GND Signal GND 12 DGTL GND Power GND NOTES: A. The analog input must have some current return path to ANLG GND. B. Bypass capacitor leads must be as short as possible. C. For high-accuracy applications, use a larger capacitor to reduce reference noise. Figure 6. Analog Considerations 12 POST OFFICE BOX 655303 10 F - (see Note B) 6 TLC1225 5 0.1 F (see Note B) * DALLAS, TEXAS 75265 TLC1225I, TLC1225M SELF-CALIBRATING 12-BIT-PLUS-SIGN ANALOG-TO-DIGITAL CONVERTERS SLAS029B - AUGUST 1990 - REVISED DECEMBER 1993 APPLICATION INFORMATION 5V 15 V Op Amp 1 k + IN914 3 - IN + ANLG VCC + IN914 6 + - 10 F TLC1225 - 15 V 2 IN - Figure 7. Input Protection 5V 4 k XDR VXDR 3 (see Note B) 500- Zero Adjust 2 IN + ANLG VCC + 0.1 F IN - (see Note A) DGTL VCC 500 6 0.1 F REF - 10 F 28 TLC1225 TIE HIGH + 10 F + 3.9 k - 7 1/2 LM358A + 5 - + - 1 F 1-k Full-Scale Adjust 8.2 k NOTES: A. VI = 0.15 x ANLG VCC+ B. 15% of ANLG VCC VXDR 85% of ANLG VCC Figure 8. Operating With Ratiometric Transducers POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 13 TLC1225I, TLC1225M SELF-CALIBRATING 12-BIT-PLUS-SIGN ANALOG-TO-DIGITAL CONVERTERS SLAS029B - AUGUST 1990 - REVISED DECEMBER 1993 14 POST OFFICE BOX 655303 * DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI's standard warranty. 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