TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
Copyright 1993, Texas Instruments Incorporated
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
•Advanced LinCMOS Technology
•Self Calibration Eliminates Expensive
Trimming at Factory and Offset Adjustment
in the Field
•12-Bit-Plus-Sign Resolution
•12-Bit Linearity
•12-µs Conversion Period at fclock = 2 MHz†
•Compatible With All Microprocessors
•Single 5-V and ±5-V Supply Operation
•True Differential Analog Voltage Inputs
With –Vref to Vref Differential Input Range
•For Single 5-V Supply, Input
Common-Mode Voltage Range is 0 V to 5 V
•For ±5-V Supplies, Input Common-Mode
Voltage Range is –5 V to 5 V
•Unipolar or Bipolar Operation
•2s-Complement Output
•Low Power
85 mW Max on TLC1225I
87.5 mW Max on TLC1225M
description
The TLC1225I and TLC1225M converters are
manufactured with Texas Instruments highly
efficient Advanced LinCMOS technology. The
TLC1225I and TLC1225M CMOS analog-to-
digital converters (ADCs) can be operated with a
single 5-V supply or with ±5-V supplies. The
differential input range is –Vref to Vref in both
supply configurations. The common-mode input
range is ANLG VCC– to ANLG VCC+. For single
5-V supply operation, grounding IN– corresponds
to standard unipolar conversion. For ±5-V supply
operation, grounding IN– corresponds to
standard bipolar conversion. Conversion is
performed via the successive-approximation
method. The TLC1225x outputs the converted data in a parallel word and interfaces directly to a 16-bit data bus.
Negative numbers are given in the 2s-complement data format. All digital signals are fully TTL and CMOS
compatible.
This converter uses a self-calibration technique by which seven of the internal capacitors in the capacitive array
of the A/D conversion circuitry can be automatically calibrated. The internal capacitors are calibrated during a
nonconversion capacitor-calibrate cycle in which all seven of the internal capacitors are calibrated at the same
time. A conversion period requires only 24 clock cycles. Self calibration requires 300 clock cycles. The
calibration or conversion cycle can be initiated at any time by issuing the proper command word to the data bus.
The self-calibrating technique eliminates the need for expensive trimming of thin-film resistors at the factory and
provides excellent performance at low cost.
Advanced LinCMOS is a trademark of Texas Instruments Incorporated.
†The conversion period is the reciprocal of the conversion rate and includes the access, sample, setup, and A/D conversion times.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ANLG VCC–
IN–
IN+
ANLG GND
REF
ANLG VCC+
TIE HIGH
CLK IN
WR
CS
RD
DGTL GND
READY OUT
INT
DGTL VCC
D12
D11
D10
D9
D8
D7
D6
D5/D15
D4/D14
D3/D13
D2/D12
D1/D11
D0/D10
I/O
Bus
321
13 14
5
6
7
8
9
10
11
D10
D9
D8
D7
D6
D5/D15
D4/D14
REF
ANLG VCC+
TIE HIGH
CLK IN
WR
CS
RD
4
15 16 17 18
READY OUT
INT
D0/D10
D1/D11
D2/D12
D3/D13
ANLG GND
IN+
IN–
ANLG V
28 27 2625
24
23
22
21
20
19
12
DGTL GND
DGTL V
D12
D11
CC –
CC
FK OR FN PACKAGE
(TOP VIEW)
J OR NW PACKAGE
(TOP VIEW)
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
2POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
The TLC1225I is characterized for operation from –40°C to 85°C. The TLC1225M is characterized over the
full military temperature range of –55°C to 125°C.
AVAILABLE OPTIONS
PACKAGED DEVICES
TACERAMIC CHIP CARRIER
(FK) PLASTIC CHIP CARRIER
(FN) CERAMIC DIP
(J) PLASTIC DIP
(NW)
–40°C to 85°C TLC1225IFN TLC225INW
–55°C to 125°C TLC1225MFK TLC1225MJ
functional block diagram
READY OUT
RD
WR
CS
INT
TIE HIGH
I/O BUS
REF
IN –
IN +
ANLG VCC –
Microprocessor
Path
Data
8-Bit
Input Data Latches
Clocks
2
Address
Counter
1
Counter
Address
RAM
8-Word
AUL
Register 2
Register 1
8-Bit SAR
Control
8-Bit Switch
Counter
Program
ROM
Control
MUX
13
6
13
13
6
8
8
8
DAC
Calibration
8-Bit
DAC
Calibration
8-Bit
Comp
13
13
13
13-Bit Data Latch
Control Logic
13-Bit Calibration
13-Bit SAR
13-Bit Switch Control
5-V–10-V Translator
13-Bit
Capacitor DAC
and S/H
and S/H
Capacitor DAC
13-Bit
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description
calibration of comparator offset
The following actions are performed to calibrate the comparator offset:
1. The IN+ and IN– inputs are internally shorted together so that the converter input is zero. A coarse
comparator offset calibration is performed by storing the offset voltages of the interconnecting
comparator stages on the coupling capacitors that connect these stages (see Figure 1). The storage of
offset voltages is accomplished by closing all switches and then opening switches A and A’, then
switches B and B’, and then C and C’. This process continues until all interconnecting stages of the
comparator are calibrated. After this action, some of the comparator offset remains uncalibrated.
C’
C
GND
GND
B’A’
B
GND
GND
A
GND
GND
Figure 1. Comparator Offset Null
2. An A/D conversion is done on the remaining offset with the 8-bit calibration digital-to-analog converters
(DACs) and 8-bit successive-approximation register (SAR), and the result is stored in the RAM.
calibration of the ADC capacitive capacitor array
The following actions are performed to calibrate capacitors in the 13-bit DACs that comprise the ADC’s
capacitive array:
1. IN+ and IN– are internally disconnected from the 13-bit DACs.
2. The most significant bit (MSB) capacitor is tied to REF, while the rest of the array capacitors are tied to
GND. The A/D conversion result for the remaining comparator offset, obtained in step 2 above, is
retrieved from the RAM and is input to the 8-bit DACs.
3. Step 1 of the calibration of comparator offset sequence is performed. The 8-bit DAC input is returned to
zero, and the remaining comparator offset is then subtracted; thus, the comparator offset is completely
corrected.
4. The MSB capacitor is tied to GND, while the rest of the array capacitors (Cx), are tied to REF. An MSB
capacitor voltage error (see Figure 2) on the comparator output occurs if the MSB capacitor does not
equal the sum of the other capacitors in the capacitive array. This error voltage is converted to an 8-bit
word from which a capacitor error is computed and stored in the RAM.
5. The capacitor voltage error for the next most significant capacitor is calibrated by keeping the MSB
capacitor grounded and then performing the above steps 1–4 while using the next most significant
capacitor instead of the MSB capacitor. The seven most significant capacitors are calibrated in this
manner.
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
4POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Vref (step 4)
GND (step 3)
GND (step 4)
Vref (step 3)
MSB-Capacitor
Voltage Error
(step 4)
CXCMSB –
CX
CMSB +
Figure 2. Capacitor Array Null
analog-to-digital conversion
The following steps are performed in the analog-to-digital conversion process:
•Step 1 of the calibration of comparator offset sequence is performed. The A/D conversion result for the
remaining comparator offset, obtained in step 2 of the calibration of comparator offset, is retrieved from
the RAM and is input to the 8-bit DACs. The comparator offset is completely corrected.
•IN+ and IN– are sampled into the 13-bit capacitive arrays.
•The 13-bit analog-to-digital conversion is performed. As the successive-approximation conversion
proceeds successively through the seven most significant capacitors, the error for each of these
capacitors is recovered from the RAM and accumulated in a register. This register controls the 8-bit
DACs so the total accumulated error for these capacitors is subtracted out during the conversion
process.
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)†
Supply voltage (ANLG VCC+ and DGTL VCC) (see Note 1) 7.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Supply voltage, ANLG VCC– –7.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential supply voltage, ANLG VCC+ – ANLG VCC– 15 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock input voltage range –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control input voltage range –0.3 V to VCC + 0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog input (IN+, IN–) voltage range, VI+ and VI– ANLG VCC– –0.3 V to ANLG VCC+ +0.3 V. . . . . . . . .
Reference voltage range, Vref –0.3 V to ANLG VCC+ +0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range, TIE HIGH –0.3 V to ANLG VCC+ +0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range –0.3 V to DGTL VCC +0.3 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current (per pin) ±5 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input current (per package) ±20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continued total dissipation See Dissipation Rating Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operating free-air temperature range, TA: TLC1225I –40°C to 85°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
TLC1225M –55°C to 125°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range –65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Case temperature for 60 seconds: FK or FN package 260°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 10 seconds: NW package 260°C. . . . . . . . . . . . . . . .
Lead temperature 1,6 mm (1/16 inch) from the case for 60 seconds: J package 300°C. . . . . . . . . . . . . . . . . .
†Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only , and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may af fect device reliability.
NOTE 1: All analog voltages are referred to ANLG GND, and all digital voltages are referred to DGTL GND.
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DISSIPATION RATING TABLE
PACKAGE TA ≤ 25°C
POWER RATING DERATING
FACTOR TA = 70°C
POWER RATING TA = 85°C
POWER RATING TA = 125°C
POWER RATING
FK 1375 mW 11.0 mW/°C 880mW 715 mW 275 mW
FN 1400 mW 11.2 mW/°C 896 mW 728 mW 280 mW
J 1375 mW 11.0 mW/°C 880 mW 715 mW 275 mW
N 1150 mW 9.2 mW/°C 736 mW 598 mW —
recommended operating conditions
MIN MAX UNIT
ANLG VCC+ 4.5 5.5
Supply voltage ANLG VCC– –5.5 ANLG GND V
DGTL VCC 4.5 5.5
High-level input voltage, V
IH
All digital inputs except CLK IN 2
V
gg,
IH
(ANLG VCC = DGTL VCC = 4.75 to 5.25 V) CLK IN 3.5
V
Low-level input voltage, V
IL
All digital inputs except CLK IN 0.8
V
g, IL
(ANLG VCC = DGTL VCC = 4.75 to 5.25 V) CLK IN 1.4
V
Analog input voltage, VI+, VI– ANLG VCC– – 0.05 ANLG VCC+ 0.05 V
High-level input voltage, TIE HIGH, VIH ANLG VCC = DGTL VCC = 5 V 2 V
Clock input frequency, fclock ANLG VCC = DGTL VCC = 5 V 0.3 2.6 MHz
Clock duty cycle ANLG VCC = DGTL VCC = 5 V 40% 60%
Pulse duration, CS and WR low, twANLG VCC = DGTL VCC = 5 V 15 ns
Setup time, I/O bus in before WR↑or CS↑, tsu ANLG VCC = DGTL VCC = 5 V 60 ns
Hold time, I/O bus in after WR↑ or CS↑, thANLG VCC = DGTL VCC = 5 V 50 ns
O
p
erating free air tem
p
erature TA
TLC1225I –40 85 °
C
Operating
free
-
air
temperat
u
re
,
T
ATLC1225M –55 125
°C
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
6POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
ANLG VCC+ = DGTL VCC = Vref = 5 V, ANLG VCC– = –5 V or ANLG GND (unless otherwise noted)
(see Note 2)
PARAMETER TEST CONDITIONS MIN MAX UNIT
VOH
High level out
p
ut voltage
DGTL VCC = 4 75 V
IO = –1.8 mA 2.4
V
V
OH
High
-
le
v
el
o
u
tp
u
t
v
oltage
DGTL
V
CC =
4
.
75
V
IO = –50 µA4.5
V
VOL
Low level out
p
ut voltage
TLC1225I DGTL V
CC
= 4.75 V, I
O
= 3.2 mA, 0.4
V
V
OL
Lo
w-
le
v
el
o
u
tp
u
t
v
oltage
TLC1225M
CC ,
See Note 3
O,
0.45
V
rref Input resistance, REF 1 10 MΩ
IIH High-level input current VI = 5 V 5 µA
IIL Low-level input current VI = 0 –5 µA
IOZ
High im
p
edance state out
p
ut leakage current
VO = 0 –3
µA
I
OZ
High
-
impedance
-
state
o
u
tp
u
t
leakage
c
u
rrent
VO = 5 V 3 µ
A
IO
Out
p
ut current
VO = 0 –6
mA
I
O
O
u
tp
u
t
c
u
rrent
VO = 5 V 8
mA
DGTL ICC Supply current from DGTL VCC fclock = 2 MHz, CS high 6 mA
ANLG ICC
Su
pp
ly current from ANLG VCC
TLC1225I
flk
= 2 MHz
CS high
9
mA
ANLG
I
CC+
S
u
ppl
y
c
u
rrent
from
ANLG
V
CC+ TLC1225M
f
clock =
2
MH
z,
CS
hi
g
h
8.5
mA
ANLG ICC– Supply current from ANLG VCC– fclock = 2 MHz, CS high –3 mA
NOTES: 2. The input voltage range is defined as: VI+ = –5.05 V to 5.05 V, VI– = –5.05 V to 5.05 V, and | VI+ – VI– | ≤ 5.05 V when ANLG
VCC– = –5 V . The input voltage range is defined as: VI+ = –0.05 V to 5.05 V , VI– = –0.05 V to 5.05 V , and | VI+ – VI– | ≤ 5.05 V when
ANLG VCC– = ANLG GND.
3. IO = 4 mA for READY OUT, INT, and D12.
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
electrical characteristics over recommended operating free-air temperature range,
ANLG VCC+ = DGTL VCC = Vref = 5 V, ANLG VCC– = –5 V or ANLG GND, fclock = 2 MHz (unless
otherwise noted) (see Note 2)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
ELIntegral linearity error ±0.012% FSR‡
–5 V < (IN+ – IN–) < 5 V,
≥1
§
ED
Differential linearity
(),
VCC+ = 5 V, VCC– = – 5 V
≥
–
1
LSB§
E
D
Differential
linearit
y0 < (IN+ – IN–) < 5.05 V,
≥1
LSB§
(),
VCC+ = 5 V, VCC– = 0
≥
–
1
Zero error
TLC1225I ±1.5
LSB
Zero
error
TLC1225M ±1
LSB
Unadjusted positive and negative full-scale error ±2 LSB
Temperature coefficient of gain 15 ppm/°C
Temperature coefficient of of fset point 1.5 ppm/°C
Zero error ±0.75
kSVS
Su
pp
ly voltage sensitivity
Positive and negative ANLG VCC+ = 5 V ±5%,
ANLG VCC 5V±5%
±075
LSB
k
SVS
S
u
ppl
y v
oltage
sensiti
v
it
y
g
full-scale error
ANLG
V
CC– = –
5
V
±5%
,
DGTL VCC
=
5V±5%
±0
.
75
LSB
Linearity error
DGTL
VCC
=
5
V
±5%
±0.25
CMRR Common-mode rejection ratio IN– = IN+ = –5 V to 5 V 65 dB
Common-mode rejection (maximum code change
IN =IN+= 5Vto5V
2
LSB
j( g
from code 0000000000000)
IN
– =
IN
+ = –
5
V
to
5
V
2
LSB
t
Conversion
p
eriod (1/f lk
) (see Notes 4 and 5)
flk
=26MHz
clock
t
conv
Con
v
ersion
period
(1/f
clock
)
(see
Notes
4
and
5)
f
clock =
2
.
6
MH
z
cycles
t
Access time (delay from falling edge of C
L
= 100 pF,
ns
t
a
(y gg
CS ⋅ RD to data output)
L,
fclock = 2.6 MHz
ns
tdi
Disable time, output (delay from rising edge of RD to R
L
= 2 kΩ,C
L
= 100 pF,
ns
t
dis
,(y gg
high-impedance state)
L,L,
fclock = 2.6 MHz
ns
td1(READY) Delay time, control signal edge to READY OUT fclock = 2.6 MHz 100 ns
td2(READY) Delay time, control signal edge to READY OUT fclock = 2.6 MHz 100 ns
td(INT) Delay time, RD or WR to reset of INT fclock = 2.6 MHz 100 ns
†All typical values are at TA = 25°C.
‡FSR is full-scale range: 0.012% FSR linearity error is equivalent to 1 LSB = 1.22 mV.
§No missing codes
NOTES: 2. The input voltage range is defined as: VI+ = –5.05 V to 5.05 V, VI– = –5.05 V to 5.05 V, and | VI+ – VI– | ≤ 5.05 V when ANLG
VCC– = –5 V . The input voltage range is defined as: VI+ = –0.05 V to 5.05 V , VI– = –0.05 V to 5.05 V , and | VI+ – VI– | ≤ 5.05 V when
ANLG VCC– = ANLG GND.
4. If INT and RD go low within the same fclock period, INT is not reset until WR is brought low . If INT and RD do not go low within the
same fclock period, INT is reset.
5. The conversion period is the reciprocal of the conversion rate and includes the access, sample, setup, and A/D conversion times.
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
8POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
I/O Bus
READY
RD
INT
WR
CS
tconv
td(INT)
td1(READY)
td2(READY)
th
tsu
In In Out
241030
Conversion
Input Sampling
td1(READY)
td2(READY)
ta
tdis
Command to Calibrate
7 Capacitors and Offset
(requires 300 clock cycles)
Command to
Initiate Conversion
10%
50% 50%
50% 50%
50% 50%
10%
50% 50%
10%10%
50%
50%
Figure 3. Timing Diagram
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
VOL
VCC
CL
RL
Data Output
DGTL
VCC
RD
RD
VCC
DGTL
Data Output
RL
CL90%
Data Output 10%
90%
10%
50%
tdis
VCC
RD
GND
GND
Data Output
VOH
GND
RD
VCC
tdis
50% 10%
90%
Figure 4. Load Circuits and Waveforms
APPLICATION INFORMATION
unipolar and bipolar operation
For single-ended signal input, the IN+ input is connected to the analog source and the IN– input is connected
to ANLG GND. In the unipolar configuration, the ADC uses a single 5-V supply and the analog input voltage
range is 0 V to 5 V. Data bit D12 always remains low . In the bipolar configuration, the ADC uses ±5-V supplies
and the analog input voltage range is –5 V to 5 V. Data bit D12 indicates the sign of the input signal. In both
configurations, the 13-bit data format is extended sign with 2s-complement, right-justified data.
power-up sequence
Calibration is not automatic on power up. Calibration is initiated by writing control words to the six least significant
bits of the data bus. Vref must have fully settled before calibration is initiated. If addressed or initiated, conversion
can begin after the first clock cycle; however , full A/D conversion accuracy is not established until after internal
capacitor calibration.
conversion period start sequence
The writing of the conversion command word to the six least significant bits of the data bus when either CS or
WR goes high initiates the conversion sequence.
analog sampling sequence
Sampling of the input signal occurs during clock cycles 3 through 10 of the conversion sequence.
completed A/D conversion
When INT goes low , conversion is complete and the A/D result can be read. A new conversion period can begin
immediately. The A/D conversion is complete at the end of clock cycle 24 of the conversion period.
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
aborting a conversion period in process and beginning a new conversion
If a conversion period is initiated while a conversion sequence is in process, the ongoing conversion is aborted
and a new conversion period begins.
reading the conversion result
When both CS and RD go low , all 13 bits of conversion data are output to the I/O bus. The format of the output
is extended sign with 2s-complement, right-justified data. The sign bit D12 is low if VI+ – VI– is positive and high
if VI+ – VI– is negative.
general
reset INT
When reading the conversion data, the falling edge of the first low-going combination of CS and RD reset INT.
The falling edge of the low-going combination of CS and WR also reset INT.
ready out
For high-speed microprocessors, READY OUT allows the TLC1225 to insert a wait state in the microprocessor’s
read or write cycle.
reference voltage (Vref)
This voltage defines the range for | VI+ – VI– |. When | VI+ – VI– | equals Vref, the highest conversion data value
results. When | VI+ – VI– | equals 0, the conversion data value is zero. For a given input, the conversion data
changes ratiometrically with changes in V ref. Calibration should be performed with the same value of Vref that
is used during conversion.
TIE HIGH
TIE HIGH is a digital input and should be tied high.
calibration and conversion period considerations
Calibration of the internal capacitors and A/D conversion are two separate actions. Each action is independently
initiated. A calibration command should be initiated prior to subsequent conversions; it is not necessary to
recalibrate before each conversion. Capacitor calibration is expected to last indefinitely as long as the clock
signal and power are not interrupted. The offset calibration may drift with temperature changes. The
temperature coefficient of the of fset point is shown in the electrical characteristics table. Periodic calibration is
recommended. Calibration and conversion commands require 300 and 24 clock cycles, respectively.
The calibrate and conversion commands are initiated by writing control words on the six least significant bits
of the data bus. These control words are written into the IC when either CS or WR goes high. The initiation of
these commands is illustrated in Figure 3. The bit patterns for the commands are shown in Table 1.
Table 1. Conversion Commands
COMMAND
CS +WR
I/O BUS REQUIRED NUMBER
COMMAND
CS
+
WR
D15 D14 D13 D12 D11 D10
REQUIRED
NUMBER
OF CLOCK CYCLES
Conversion ↑H L X X X L 24
Calibrate†↑L X L L L L 300
†Calibration is lost when the clock is stopped.
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
analog inputs
differential inputs provide common-mode rejection
The differential inputs reduce common-mode noise. Common-mode noise is noise common to both IN+ and
IN– inputs, such as 60-Hz noise. There is no time interval between the sampling of the IN+ and IN–, so these
inputs are truly differential. No conversion errors result from a time interval between the sampling of the IN+ and
IN– inputs.
input bypass capacitors
Input bypass capacitors can be used for noise filtering; however, the charge on these bypass capacitors is
depleted during the input sampling sequence when the internal sampling capacitors are charged. The charging
of the bypass capacitors through the differential source resistances must keep pace with the charge depletion
of the bypass capacitors during the input sampling sequence. Higher source resistances reduce the amount
of charging current for the bypass capacitors. Also fast, successive conversion has the greatest charge
depletion effect on the bypass capacitors. The above phenomenon becomes more significant as source
resistances and the conversion rate (i.e., higher clock frequency and conversion initiation rate) increase.
In addition, if the above phenomenon prevents the bypass capacitors from fully charging between conversions,
voltage drops across the source resistances result due to the ongoing bypass capacitor charging currents. The
voltage drops cause a conversion error . Also, the voltage drops increase with higher | VI+ – VI– | values, higher
source resistances, and lower charge on the bypass capacitors (i.e., faster conversion rate).
For low-source-resistance applications (Rsource < 100 Ω), a 0.001-µF bypass capacitor at the inputs prevents
pickup due to the series lead inductance of a long wire. A 100-Ω resistor can be placed between the capacitor
and the output of an operational amplifier to isolate the capacitor from the operational amplifier.
input leads
The input leads should be kept as short as possible since the coupling of noise and digital clock signals to the
the inputs can cause errors.
power supply considerations
Noise spikes on the VCC lines can cause conversion error. Low-inductance tantalum capacitors (> 1 µF) with
short leads should be used to bypass ANLG VCC and DGTL VCC. A separate regulator for the TLC1225 and other
analog circuitry greatly reduces digital noise on the supply line. A ferrite bead or equivalent inductance can be
used between the analog and digital ground planes if the digital ground noise is excessive.
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
LSB = Vref ÷ 4096
4094.5
– 0.5
– 4095.5
(LSB)
INPUT VOLTAGE
ANALOG
4094 to 4095
0 to 1
– 1 to 0
– 4096 to – 4095
(DECIMAL)
TRANSITION
CODE
(4095) 0 1111 1111 111 1
(4094) 0 1111 1111 1110
(2) 0 0000 0000 0010
(1) 0 0000 0000 0001
(0) 0 0000 0000 0000
– Vref
Analog Input Voltage [VIN(+) – VIN(–)]
1 0000 0000 0000 (– 4096)
1 0000 0000 0001 (– 4095)
+ Vref
1 1111 1111 1110 (– 2)
1 1111 1111 1111 (– 1)
LSB
Positive
Full-Scale
Transition
Zero Transition
†
†
Negative
Full-Scale
Transition
Output Code
0.5
Figure 5. Transfer Characteristic
ANLG VCC–
ANLG VCC+
DGTL VCC
TIE HIGH
DGTL GND
ANLG GND
REF
IN–
IN+
Power GND
Signal GND
(see Note A)
Signal In
+
–
10 µF
–
+
0.1 µF
0.1 µF10 µF
0.1 µF
0.1 µF
(see Note B)
(see Notes B and C)
(see Note B)
(see Note B) (see Note B)
(see Note B)
5
3
2
4
12
1
7
28
6
TLC1225
NOTES: A. The analog input must have some current return path to ANLG GND.
B. Bypass capacitor leads must be as short as possible.
C. For high-accuracy applications, use a larger capacitor to reduce reference noise.
Figure 6. Analog Considerations
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
5 V
TLC1225
IN–
ANLG VCC +
IN+
– 15 V
Amp
Op
15 V
–
+1 kΩ
IN914
IN914
10 µF
–
+
3
2
6
Figure 7. Input Protection
TLC1225
REF
TIE HIGH
DGTL VCC
ANLG VCC +
IN– (see Note A)
IN+
VXDR
XDR (see Note B)
4 kΩ
Zero Adjust
500-Ω
5 V
3.9 kΩ
8.2 kΩ
Adjust
Full-Scale
1-kΩ
–
+
–
+
1/2 LM358A
+
–
10 µF
–
+
0.1 µF
500 Ω0.1 µF 10 µF
1 µF
3
2
6
7
5
28
NOTES: A. VI = 0.15 × ANLG VCC+
B. 15% of ANLG VCC ≤ VXDR ≤ 85% of ANLG VCC
Figure 8. Operating With Ratiometric Transducers
TLC1225I, TLC1225M
SELF-CALIBRATING 12-BIT-PLUS-SIGN
ANALOG-TO-DIGITAL CONVERTERS
SLAS029B – AUGUST 1990 – REVISED DECEMBER 1993
14 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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