CY2308
3.3V Zero Delay Buffer
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document Number: 38-07146 Rev. *H Revised March 12, 2009
Features
■
Zero input-output propagation delay, adjustable by capacitive
load on FBK input
■
Multiple configurations, see Available CY2308 Configurations
on page 3
■
Multiple low skew outputs
■
T wo banks of four outputs, three-stateable by two select input s
■
10 MHz to 133 MHz operating range
■
75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)
■
Space saving 16-pi n 150 mil SOIC package or 16-pin TSSOP
■
3.3V opera tion
■
Industrial temperature availab le
Functional Description
The CY2308 is a 3.3V Zero Delay Buffer designed to distribute
high speed clocks in PC, workstation, datacom, telecom, and
other high performance applications.
The part has an on-chip PLL that locks to an input clock
presented on the REF pin . The PLL feedback is driven into the
FBK pin and obtained from one of the outputs. The
input-to-output skew is less than 350 ps and output-to-output
skew is less than 200 ps.
The CY2308 has two banks of four outputs each that is controlled
by the select inputs as shown in the table Select Input Decoding
on page 2. If all output clocks are not required, Bank B is
three-stated. The input clo ck is directl y applied to the output fo r
chip and system testing purposes by the select inputs.
The CY2308 PLL enters a p ower down state when there are no
rising edges on the REF input. In this mode, all outputs are
three-stated and the PLL is turned off resulting in less than 50 μA
of current draw. T he PLL shuts down in two addition al cases a s
shown in the table Select Input Decoding on page 2.
Multiple CY2308 devices accept the same input clock and
distribute it in a system. In this case, the skew between the
outputs of two devices is less than 700 ps.
The CY2308 is available in five different configurations as shown
in the table Available CY2308 Configurations on page 3. The
CY2308–1 is the base part where the output frequencies eq ual
the reference if there is no counter in the feedback path. The
CY2308–1H is the hig h drive version of the –1 and rise and fall
times on this device are much faster.
The CY2308–2 enables the user to obtain 2X and 1X frequencies
on each output bank. The exact configuration and output
frequencies depend on the output that drives the fee dback pin.
The CY2308–3 enables the user to obtain 4X and 2X frequencies
on the outputs.
The CY2308–4 enables the user to obtain 2X clocks on all
outputs. Thus, the part is extremely versatile and is used in a
variety of applications.
The CY2308–5H is a high drive version with REF/2 on both
banks.
REF
CLKA1
CLKA2
CLKA3
CLKA4
FBK
PLL
MUX
Select Input
Decoding
S2
S1 CLKB1
CLKB2
CLKB3
CLKB4
/2
Extra Divider (–2, –3)
/2
Extra Divider (–3, –4)
Extra D ivider (–5H)
/2
Logic Block Diagram
[+] Feedback
CY2308
Document Number: 38-0714 6 Rev. *H Page 2 of 15
Pinouts
Figure 1. Pin Diagram - 16 Pin SOIC (Top view)
Table 1. Pin Definitions - 16 Pin SOIC
Pin Signal Description
1REF
[1]
Input reference frequency, 5V tolerant input
2CLKA1
[2]
Clock output, Bank A
3CLKA2
[2]
Clock output, Bank A
4V
DD
3.3V supply
5 GND Ground
6CLKB1
[2]
Clock output, Bank B
7CLKB2
[2]
Clock output, Bank B
8S2
[3]
Select input, bit 2
9S1
[3]
Select input, bit 1
10 CLKB3
[2]
Clock output, Bank B
11 CLKB4
[2]
Clock output, Bank B
12 GND Ground
13 V
DD
3.3V supply
14 CLKA3
[2]
Clock output, Bank A
15 CLKA4
[2]
Clock output, Bank A
16 FBK PLL feedback input
Select Input Deco ding
S2 S1 CLOCK A1–A4 CLOCK B1–B4 Output Source PLL Shutdown
0 0 Tri-State Tri-State PLL Y
0 1 Driven Tri-State PLL N
10 Driven
[4]
Driven
[4]
Reference Y
1 1 Driven Driven PLL N
9
16
FBK
CLKA4
CLKA3
V
DD
GND
CLKB4
CLKB3
S1
1
2
3
4
5
6
7
8
10
11
12
13
14
15
REF
CLKA1
CLKA2
V
DD
GND
CLKB1
CLKB2
S2
Notes
1. Weak pull down.
2. Weak pull down on all outputs.
3. Weak pull ups on these inputs.
4. Outputs inverted on 2308–2 and 2308–3 in bypass mode, S2 = 1 and S1 = 0.
[+] Feedback
CY2308
Document Number: 38-0714 6 Rev. *H Page 3 of 15
Zero Delay and Skew Control
To close the feedback loop of the CY2308, the FBK pin is driven
from any of the eight available output pins. The output driving the
FBK pin drives a total load of 7 pF plus any additional load that
it drives. The relative loading of this output to the remaining
outputs adjusts the input-output delay. This is shown in the
Figure 2.
For applications requiring zero input-output delay, all outputs
including the one providing feedback is equally loaded.
If input-output delay adjustments are required, use the Zero
Delay and Skew Control graph to calculate loading differences
between the feedback output and remaining outputs.
For zero output-output skew, outputs are loaded equally. For
further information on using CY2308, refer to the application note
“CY2308: Zero Delay Buffer.”
Available CY2308 Configurations
Device Feedback From Bank A Frequency Bank B Frequency
CY2308–1 Bank A or Bank B Reference Reference
CY2308–1H Bank A or Bank B Reference Reference
CY2308–2 Bank A Reference Reference/2
CY2308–2 Bank B 2 X Reference Reference
CY2308–3 Bank A 2 X Reference Reference or Reference
[5]
CY2308–3 Bank B 4 X Reference 2 X Reference
CY2308–4 Bank A or Bank B 2 X Reference 2 X Reference
CY2308–5H Bank A or Bank B Reference /2 Reference /2
Figure 2. REF. Input to CLKA/CLKB Delay Ve rsus Difference in Loading between FBK Pin an d CLKA/CLKB Pins
Note
5. Output phase is indeterminant (0° or 180° from input clock). If phase integrity is required, use the CY2308–2.
[+] Feedback
CY2308
Document Number: 38-0714 6 Rev. *H Page 4 of 15
Maximum Ratings
Supply Voltage to Ground Potential................–0.5V to +7.0V
DC Input Voltage (Except Ref) ..............–0.5V to V
DD
+ 0.5V
DC Input Voltage REF ............... ............................–0.5 to 7V
Storage Temperature.................................. –65°C to +150°C
Junction Temperature.................................................. 150°C
Static Discharge Voltage
(MIL-STD-883, Method 3015)....................................>2000V
Operating Conditions for Commercial Temperature Devices
Parameter Description Min Max Unit
V
DD
Supply Voltage 3.0 3.6 V
T
A
Operating Temperature (Ambient Temperature) 0 70 °C
C
L
Load Capacitance, below 100 MHz – 30 pF
Load Capacitance, from 100 MHz to 133 MHz – 15 pF
C
IN
Input Capacitance
[6]
–7pF
t
PU
Power up time for all V
DD
s to reach minimum specified voltage
(power ramps must be monotonic) 0.05 50 ms
Electrical Characteristics for Commercial Temperature Devices
Parameter Description Test Conditions Min Max Unit
V
IL
Input LOW Voltage – 0.8 V
V
IH
Input HIGH Voltage 2.0 – V
I
IL
Input LOW Current V
IN
= 0V – 50.0 μA
I
IH
Input HIGH Current V
IN
= V
DD
–100.0μA
V
OL
Output LOW Voltage
[7]
I
OL
= 8 mA (–1, –2, –3, –4)
I
OL
= 12 mA (–1H, –5H) –0.4V
V
OH
Output HIGH Voltage
[7]
I
OH
= –8 mA (–1, –2, –3, –4)
I
OH
= –12 mA (–1H, –5H) 2.4 – V
I
DD
(PD mode) Power Down Supply Current REF = 0 MHz – 12.0 μA
I
DD
Supply Current Unloaded outputs, 100 MHz REF,
Select inputs at V
DD
or GND – 45.0 mA
– 70.0
(–1H,–5H) mA
Unloaded outputs, 66 MHz REF
(–1, –2, –3, –4) – 32.0 mA
Unloaded outputs, 33 MHz REF
(–1, –2, –3, –4) – 18.0 mA
Switching Characteristics for Commercial Temperature Devices
Parameter
[8]
Name Test Conditions Min Typ. Max Unit
t
1
Output Frequency 30 pF load, All devices 10 – 100 MHz
t
1
Output Frequency 20 pF load, –1H, –5H devices
[9]
10 – 133.3 MHz
t
1
Output Frequency 15 pF load, –1, –2, –3, –4 device s 10 – 133.3 MHz
t
PD
Duty Cycle
[7, 8]
= t
2
÷ t
1
(–1, –2, –3, –4, –1H, –5H) Measured at 1.4V , F
OUT
= 66.66 MHz
30 pF load 40.0 50.0 60.0 %
t
PD
Duty Cycle
[7, 8]
= t
2
÷ t
1
(–1, –2, –3, –4, –1H, –5H) Measured at 1.4V, F
OUT
< 50 MHz
15 pF load 45.0 50.0 55.0 %
Notes
6. Applies to both Ref Clock and FBK.
7. Parameter is guaranteed by design and characterization. Not 100% tested in production.
8. All parameters are specified with loaded outputs.
9. CY2308–5H has maximum input frequency of 133.33 MHz and maximum output of 66.67 MHz.
[+] Feedback
CY2308
Document Number: 38-0714 6 Rev. *H Page 5 of 15
t
3
Rise Time
[7, 8]
(–1, –2, –3, –4) Measured between 0.8V and 2.0V,
30 pF load – – 2.20 ns
t
3
Rise Time
[7, 8]
(–1, –2, –3, –4) Measured between 0.8V and 2.0V,
15 pF load – – 1.50 ns
t
3
Rise Time
[7, 8]
(–1H, –5H) Measured between 0.8V and 2.0V,
30 pF load – – 1.50 ns
t
4
Fall Time
[7, 8]
(–1, –2, –3, –4) Measured between 0.8V and 2.0V,
30 pF load – – 2.20 ns
t
4
Fall Time
[7, 8]
(–1, –2, –3, –4) Measured between 0.8V and 2.0V,
15 pF load – – 1.50 ns
t
4
Fall Time
[7, 8]
(–1H, –5H) Measured between 0.8V and 2.0V,
30 pF load – – 1.25 ns
t
5
Output to Output Skew on
same Bank
(–1, –2, –3, –4)
[7, 8]
All outputs equally loaded – – 200 ps
Output to O utput Skew (–1H ,
–5H) All outputs equally loaded – – 200 ps
Output Bank A to Output
Bank B Skew (–1, –4, –5H) All outputs equally loaded – – 200 ps
Output Bank A to Output
Bank B Skew (–2, –3) All outputs equally loaded – – 400 ps
t
6
Delay, REF Rising Edge to
FBK Rising Edge
[7, 8]
Measured at V
DD
/2 – 0 ±250 ps
t
7
Device to Device Skew
[7, 8]
Measured at V
DD
/2 on the FBK pins
of devices – 0 700 ps
t
8
Output Slew Rate
[7, 8]
Measured between 0.8V and 2.0V on
–1H, –5H device using Test Circuit 2 1– V/ns
t
J
Cycle to Cycle Jitter
[7, 8]
(–1, –1H, –4, –5H) Measured at 66.67 MHz, loaded
outputs,
15 pF load
– 75 200 ps
Measured at 66.67 MHz, loaded
outputs,
30 pF load
– – 200 ps
Measured at 133.3 MHz, loaded
outputs,
15 pF load
– – 100 ps
t
J
Cycle to Cycle Jitter
[7, 8]
(–2, –3) Measured at 66.67 MHz, loaded
outputs
30 pF load
– – 400 ps
Measured at 66.67 MHz, loaded
outputs
15 pF load
– – 400 ps
t
LOCK
PLL Lock Time
[7, 8]
Stable power supply, valid clocks
presented on REF and FBK pins ––1.0ms
Switching Characteristics for Commercial Temperature Devices
(continued)
Parameter
[8]
Name Test Conditions Min Typ. Max Unit
[+] Feedback
CY2308
Document Number: 38-0714 6 Rev. *H Page 6 of 15
Operating Conditions for Industrial Temperature Devices
Parameter Description Min Max Unit
V
DD
Supply Voltage 3.0 3.6 V
T
A
Operating Temperature (Ambient Temperature) –40 85 °C
C
L
Load Capacitance, below 100 MHz – 30 pF
Load Capacitance, from 100 MHz to 133 MHz – 15 pF
C
IN
Input Capacit ance
[6]
–7pF
t
PU
Power up time for all V
DD
s to reach minimum specified voltage (power
ramps must be monotonic) 0.05 50 ms
Electrical Characteristics for Industrial Temperature Devices
Parameter Description Test Conditions Min Max Unit
V
IL
Input LOW Vo ltage – 0.8 V
V
IH
Input HIGH Voltage 2.0 – V
I
IL
Input LOW Current V
IN
= 0V – 50.0 μA
I
IH
Input HIGH Current V
IN
= V
DD
–100.0μA
V
OL
Output LOW Voltage
[7, 8]
I
OL
= 8 mA (–1, –2, –3, –4)
I
OL
= 12 mA (–1H, –5H) –0.4V
V
OH
Output HIGH Voltage
[7, 8]
I
OH
= –8 mA (–1, –2, –3, –4)
I
OH
= –12 mA (–1H, –5H) 2.4 – V
I
DD
(PD mode) Power Down Supply Current REF = 0 MHz – 25.0 μA
I
DD
Supply Current Unloaded outputs, 100 MHz, Select
inputs at V
DD
or GND – 45.0 mA
– 70(–1H,–5H) mA
Unloaded outputs, 66 MHz REF (–1,
–2, –3, –4) – 35.0 mA
Unloaded outputs, 66 MHz REF (–1,
–2, –3, –4) – 20.0 mA
Switching Characteristics for Industrial Temperature Devices
Parameter
[8]
Name Test Conditions Min Typ Max Unit
t
1
Output Freque ncy 30 pF load, All devices 10 – 100 MHz
t
1
Output Freque ncy 20 pF load, –1H, –5H devices
[9]
10 – 133.3 MHz
t
1
Output Freque ncy 15 pF load, –1, –2, –3, –4 devices 10 – 133.3 MHz
t
PD
Duty Cycle
[7, 8]
= t
2
÷ t
1
(–1, –2, –3, –4, –1H, –5H) Measured at 1.4V, F
OUT
= 66.66 MHz
30 pF load 40.0 50.0 60.0 %
t
PD
Duty Cycle
[7, 8]
= t
2
÷ t
1
(–1, –2, –3, –4, –1H, –5H) Measured at 1.4V, F
OUT
< 50 MHz
15 pF load 45.0 50.0 55.0 %
t
3
Rise Time
[7, 8]
(–1, –2, –3, –4) Measured between 0.8V and 2.0V,
30 pF load – – 2.50 ns
t
3
Rise Time
[7, 8]
(–1, –2, –3, –4) Measured between 0.8V and 2.0V,
15 pF load – – 1.50 ns
t
3
Rise Time
[7, 8]
(–1H, –5H) Measured between 0.8V and 2.0V,
30 pF load – – 1.50 ns
t
4
Fall Time
[7, 8]
(–1, –2, –3, –4) Measured between 0.8V and 2.0V,
30 pF load – – 2.50 ns
t
4
Fall Time
[7, 8]
(–1, –2, –3, –4) Measured between 0.8V and 2.0V,
15 pF load – – 1.50 ns
[+] Feedback
CY2308
Document Number: 38-0714 6 Rev. *H Page 7 of 15
t
4
Fall Time
[7, 8]
(–1H, –5H) Measured between 0.8V and 2.0V,
30 pF load – – 1.25 ns
t
5
Output to Output Skew on
same Bank (–1, –2, –3, –4)
[7, 8]
All outputs equally loaded – – 200 ps
Output to Output Skew
(–1H, –5H) All outputs equally loaded – – 200 ps
Output Bank A to Output Bank
B Skew (–1, –4, –5H) All outputs equally loaded – – 200 ps
Output Bank A to Output Bank
B Skew (–2, –3) All outputs equally loaded – – 400 ps
t
6
Delay, REF Rising Edge to
FBK Rising Edge
[78]
Measured at V
DD
/2 – 0 ±250 ps
t
7
Device to Device Skew
[7, 8]
Measured at V
DD
/2 on the FBK pins of
devices –0700ps
t
8
Output Slew R ate
[7, 8]
Measured between 0.8V and 2.0V on
–1H, –5H device using Test Circuit 2 1– –V/ns
t
J
Cycle to Cycle Jitter
[7, 8]
(–1, –1H, –4, –5H) Measured at 66.67 MHz, loaded
outputs, 15 pF load –75200ps
Measured at 66.67 MHz, loaded
outputs, 30 pF load ––200ps
Measured at 133.3 MHz, loaded
outputs, 15 pF load ––100ps
t
J
Cycle to Cycle Jitter
[7, 8]
(–2, –3) Measured at 66.67 MHz, loaded
outputs
30 pF load
––400ps
Measured at 66.67 MHz, loaded
outputs
15 pF load
––400ps
t
LOCK
PLL Lock Time
[7, 8]
Stable power supply, valid clocks
presented on REF and FBK pins ––1.0ms
Switching Characteristics for Industrial Temperature Devices
(continued)
Parameter
[8]
Name Test Conditions Min Typ Max Unit
Switching Waveforms
t
1
t
2
1.4V 1.4V 1.4V
Figure 3. Duty Cycle Timing
[+] Feedback
CY2308
Document Number: 38-0714 6 Rev. *H Page 8 of 15
Switching Waveforms
(continued)
1.4V
t
5
OUTPUT
OUTPUT 1.4V
Figure 5. Output-Output Skew
V
DD
/2
t
6
INPUT
FBK
V
DD
/2
Figure 6. Input-Output Propagation Delay
V
DD
/2
V
DD
/2
t
7
FBK, Device 1
FBK, Device 2
Figure 7. Device-Device Skew
[+] Feedback
CY2308
Document Number: 38-0714 6 Rev. *H Page 9 of 15
Typic al Duty Cycle
[10]
and I
DD
Trends
[11]
for CY2308–1,2,3,4
Notes
10.Duty cycle is taken from typical chip measured at 1.4V.
11. I
DD
data is calculated from I
DD
= I
CORE
+ nCVf, where I
CORE
is the unloaded current.
(n = number of outputs; C = Capacitance load per output (F); V = Voltage Supply (V); f = frequency (Hz).
Dut y Cy cle Vs VDD
(for 30 pF Loads over Frequency - 3. 3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3 3.13.23.33.43.53.6
VDD (V)
Duty C ycle (%)
33 MHz
66 MHz
100 MHz
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
Duty Cycle (% )
33 MHz
66 MHz
100 MHz
133 MHz
Duty Cycle Vs Frequency
(for 30 pF Loads over Temperature - 3.3V)
40
42
44
46
48
50
52
54
56
58
60
20 40 60 80 100 120 140
Fre quency (MHz)
D uty Cy cl e (%)
-40C
0C
25C
70C
85C
Dut y C yc le Vs F requen cy
(for 15 pF Loads over Tem perature - 3.3V )
40
42
44
46
48
50
52
54
56
58
60
20 40 60 80 100 120 140
Frequency (MHz)
Duty Cycle (%)
-40C
0C
25C
70C
85C
IDD vs Number of Loaded Outputs
(for 30 pF Loads over Frequency - 3.3V, 25C)
0
20
40
60
80
10 0
12 0
14 0
02468
N umb er o f Lo ad ed Out put s
33 MHz
66 MHz
100 MHz
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
0
20
40
60
80
100
120
140
02468
N umb er o f Lo ad ed Out put s
33 MHz
66 MHz
100 MHz
[+] Feedback
CY2308
Document Number: 38-0714 6 Rev. *H Page 10 of 15
Typical Duty Cycle
[10]
and I
DD
Trends
[11]
for CY2308–1H, 5H
Duty Cycl e Vs VDD
(for 30 pF Loads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V )
D u ty Cycle (%)
33 MHz
66 MHz
100 MHz
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
Duty Cycle (% )
33 MHz
66 MHz
100 MHz
133 MHz
Duty Cycle Vs Fr equ ency
(for 30 pF Loads over Tem perature - 3.3V)
40
42
44
46
48
50
52
54
56
58
60
20 40 60 80 100 120 140
Fre quency (MHz)
Duty Cycle (%)
-40C
0C
25C
70C
85C
Duty Cycle Vs VDD
(for 15 pF Loads over Frequency - 3.3V, 25C)
40
42
44
46
48
50
52
54
56
58
60
3 3.1 3.2 3.3 3.4 3.5 3.6
VDD (V)
Duty Cycle (% )
33 MHz
66 MHz
100 MHz
133 MHz
Duty Cycl e Vs Freq uency
(for 15 pF Loads over Temperature - 3.3V)
40
42
44
46
48
50
52
54
56
58
60
20 40 60 80 100 120 140
Fre quency (MHz)
Du ty Cy cl e (%)
-40C
0C
25C
70C
85C
IDD vs Number of Loaded Outputs
(for 30 pF Loads over F requency - 3.3V, 25C)
0
20
40
60
80
100
120
140
02468
Number of Loaded Outputs
33 MHz
66 MHz
1 00 MHz
IDD vs Number of Loaded Outputs
(for 15 pF Loads over Frequency - 3.3V, 25C)
0
20
40
60
80
100
120
140
02468
Number of Loaded Outputs
33 MHz
66 MHz
1 00 MHz
[+] Feedback
CY2308
Document Number: 38-0714 6 Rev. *H Page 11 of 15
Test Circuits
Ordering Information
Ordering Code Package Type Operating Range
CY2308SC–1
[12]
16-pin 150 mil SOIC Commercial
CY2308SC–1T
[12]
16-pin 150 mil SOIC - Tape and Reel Commercial
CY2308SI–1
[12]
16-pin 150 mil SOIC Industrial
CY2308SI–1T
[12]
16-pin 150 mil SOIC - Tape and Reel Industrial
CY2308SC–1H
[12]
16-pin 150 mil SOIC Commercial
CY2308SC–1HT
[12]
16-pin 150 mil SOIC - Tape and Reel Commercial
CY2308SI–1H
[12]
16-pin 150 mil SOIC Industrial
CY2308SI–1HT
[12]
16-pin 150 mil SOIC - Tape and Reel Industrial
CY2308ZC–1H
[12]
16-pin 4.4mm TSSOP Commercial
CY2308ZC–1HT
[12]
16-pin 4.4mm TSSOP - Tape and Reel Commercial
CY2308ZI–1H
[12]
16-pin 4.4mm TSSOP Industrial
CY2308ZI–1HT
[12]
16-pin 4.4mm TSSOP - Tape and Reel Industrial
CY2308SC–2
[12]
16-pin 150 mil SOIC Commercial
CY2308SC–2T
[12]
16-pin 150 mil SOIC - Tape and Reel Commercial
CY2308SI–2
[12]
16-pin 150 mil SOIC Industrial
CY2308SI–2T
[12]
16-pin 150 mil SOIC - Tape and Reel Industrial
CY2308SC–3
[12]
16-pin 150 mil SOIC Commercial
CY2308SC–3T
[12]
16-pin 150 mil SOIC - Tape and Reel Commercial
CY2308SC–4
[12]
16-pin 150 mil SOIC Commercial
CY2308SC–4T
[12]
16-pin 150 mil SOIC - Tape and Reel Commercial
0.1 μF
V
DD
0.1 μF
V
DD
CLK
OUT
C
LOAD
Outputs
GND
GND
Test Circuit 1
V
DD
0.1 μF
V
DD
CLK
out
10 pF
Outputs
GND
GND
1 KΩ
1 KΩ
0.1 μF
Test Circuit for t
8
, Output slew rate on –1H, –5 deviceTest Circuit for all parameters except t
8
Test Circuit 2
Note
12.Not recommended for new designs.
[+] Feedback
CY2308
Document Number: 38-0714 6 Rev. *H Page 12 of 15
Pb-Free
CY2308SXC–1 16-pin 150 mil SOIC Commercial
CY2308SXC–1T 16-pin 150 mil SOIC - Tape and Reel Commercial
CY2308SXI–1 16-pin 150 mil SOIC Industrial
CY2308SXI–1T 16-pin 150 mil SOIC - Tape and Reel Industrial
CY2308SXC–1H 16-pin 150 mil SOIC Commercial
CY2308SXC–1HT 16-pin 150 mil SOIC - Tape and Reel Commercial
CY2308SXI–1H 16-pin 150 mil SOIC Industrial
CY2308SXI–1HT 16-pin 150 mil SOIC - Tape and Reel Industrial
CY2308ZXC–1H 16-pin 4.4mm TSSOP Commercial
CY2308ZXC–1HT 16-pin 4.4mm TSSOP - Tape and Reel Commercial
CY2308ZXI–1H 16-pin 4.4mm TSSOP Industrial
CY2308ZXI–1HT 16-pin 4.4mm TSSOP - Tape and Reel Industrial
CY2308SXC–2 16-pin 150 mil SOIC Commercial
CY2308SXC–2T 16-pin 150 mil SOIC - Tape and Reel Commercial
CY2308SXI–2 16-pin 150 mil SOIC Industrial
CY2308SXI–2T 16-pin 150 mil SOIC - Tape and Reel Industrial
CY2308SXC–3 16-pin 150 mil SOIC Commercial
CY2308SXC–3T 16-pin 150 mil SOIC - Tape and Reel Commercial
CY2308SXI–3 16-pin 150 mil SOIC Industrial
CY2308SXI–3T 16-pin 150 mil SOIC -Tape and Reel Industrial
CY2308SXC–4 16-pin 150 mil SOIC Commercial
CY2308SXC–4T 16-pin 150 mil SOIC - Tape and Reel Commercial
CY2308SXI–4 16-pin 150 mil SOIC Industrial
CY2308SXI–4T 16-pin 150 mil SOIC - Tape and Reel Industrial
CY2308SXC–5H
]
16-pin 150 mil SOIC Commercial
CY2308SXC–5HT 16-pin 150 mil SOIC - Tape and Reel Commercial
CY2308SXI–5H 16-pin 150 mil SOIC Industrial
CY2308SXI–5HT 16-pin 150 mil SOIC - Tape and Reel Industrial
Ordering Information
(continued)
Ordering Code Package Type Operating Range
[+] Feedback
CY2308
Document Number: 38-0714 6 Rev. *H Page 13 of 15
Package Drawings and Dimensions
PIN 1 ID
0°~8°
16 Lead (150 Mil) SOIC
18
916
SEATING PLANE
0.230[5.842]
0.244[6.197]
0.157[3.987]
0.150[3.810]
0.386[9.804]
0.393[9.982]
0.050[1.270]
BSC
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
DIMENSIONS IN INCHES[MM] MIN.
MAX.
0.016[0.406]
0.010[0.254] X 45°
0.004[0.102]
REFERENCE JEDEC MS-012
PART #
S16.15 STANDARD PKG.
SZ16.15 LEAD FREE PKG.
PACKAGE WEIGHT 0.15gms
51-85068-*B
Figure 7. 16-Pin (150 Mil) SOIC S16.15
4.90[0.193]
1.10[0.043] MAX.
0.65[0.025]
0.20[0.008]
0.05[0.002]
16
PIN1ID
6.50[0.256]
SEATING
PLANE
1
0.076[0.003]
6.25[0.246]
4.50[0.177]
4.30[0.169]
BSC.
5.10[0.200]
0.15[0.006]
0.19[0.007]
0.30[0.012]
0.09[[0.003]
BSC
0.25[0.010]
0°-8°
0.70[0.027]
0.50[0.020]
0.95[0.037]
0.85[0.033]
PLANE
GAUGE
DIMENSIONS IN MM[INCHES] MIN.
MAX.
REFERENCE JEDEC MO-153
PACKAGE WEIGHT 0.05 gms
PART #
Z16.173 STANDARD PKG.
ZZ16.173 LEAD FREE PKG.
51-85091-*A
Figure 8. 16-Pin TSSOP 4.40 mm Body Z16.173
[+] Feedback
CY2308
Document Number: 38-0714 6 Rev. *H Page 14 of 15
Document History Page
Document Title: CY2308 3.3V Zero Delay Buffer
Document Number: 38-07146
Rev. ECN Orig. of
Change Submission
Date Description of Change
** 110255 SZV 12/17/01 Changed from Specification number: 38-00528 to 38-07146
*A 118722 RGL 10/31/02 Added Note 1 in page 2.
*B 121832 RBI 12/14/02 Power up requirements added to Operating Conditions Information
*C 235854 RGL 06/24/04 Added Pb-Free D evices
*D 310594 RGL 02/09/05 Removed obsolete parts in the ordering information table
Specifie d typical value for cycle-to-cycle jitter
*E 1344343 KVM/VED 08/20/07 Brought the Ordering Information Table up to date: removed three obsolete parts
and added two parts
Changed titles to tables that are specific to commercial and industrial temperature
ranges
*F 2568575 AESA 09/19/08 Updated template. Added Note “Not recommended for new designs.”
Changed IDD (PD mode) from 12.0 to 25.0 μA for Comme rci al and Industrial
Temperature Devices
Deleted Duty Cycle parameters for F
out
< 50 MHz
Removed CY2308SI-4, CY2308SI-4T and CY2308SC-5HT.
*G 2632364 KVM 01/08/09 Corrected TSSOP package size (from 150 mil to 4.4 mm) in Ordering Information
table
*H 2673353 KVM/PYRS 03/13/09 Reverted IDD (PD mode) and Du ty Cycle paramete rs back to the values in
revision *E:
Changed IDD (PD mode) from 25 to 12 μA for commercial temperature devices
Added Duty Cycle parameters for F
out
< 50 MHz for commercial and industrial
devices.
[+] Feedback
Document Number: 38-07146 Rev. *H Revised March 12, 2009 Page 15 of 15
All products and c ompany names mentioned in th is document m ay be the trademarks of their respective holders.
CY2308
© Cypress Semicondu ctor Cor porati on, 2001- 2009. The in formatio n contai ned herei n is subject to change witho ut notice. Cy press Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress prod uc ts are not war ran ted no r inte nded to be used for
medical, lif e supp or t, l ife saving, critical contr o l or safety applicat io ns, unless pursuant to an exp re ss wr i tten agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be ex pected to result in significa nt injury to the us er . The inclusion of Cypress p roducts in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent prot ectio n (Unit ed States and fore ign),
United States copyright laws and interna ti on al tr eaty provisions. Cyp ress he reby gr ants to licensee a per son al, non- exclu sive , non- tran sferabl e lic ense to cop y, use, modify, create derivative wor ks of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of lice nsee product to be used on ly in conjunction w ith a Cypress
integrated circui t as specified in the applicab le agreement. Any reproduction, m odification, tra nslation, compilati on, or represent ation of thi s Source Code except as specifi ed above is pro hibited with out
the express written permiss i on of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liabi lit y arisin g ou t of the a ppli cati on or use of an y produ ct or ci rcui t descri bed herein . Cypr ess does n ot auth ori ze its p roducts fo r use as critical componen ts in life-su ppor t systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support syst ems application im plies that the manuf acturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC psoc.cypress.com
Clocks & Buffers clocks.cypress.com
Wireless wireless.cypress.com
Memories memory.cypress.com
Image Sensors image.cypress.com
PSoC Solutions
General psoc.cypress.com/solutions
Low Power/Low Voltage psoc.cypress.com/low-power
Precision Analog psoc.cypress.com/precision-analog
LCD Drive psoc.cypress.com/lcd-drive
CAN 2.0b psoc.cypress.com/can
USB psoc.cypress.com/usb
[+] Feedback