DM74LS47NX - Fairchild Semiconductor

October 1988

Revised March 2000

DM74LS47 BCD to 7-Segment Decoder/Driver with Open-Collect or Ou tputs

DM74LS47

BCD to 7-Segment Decoder/Driver with

Open-Collector Outputs

General Descript ion

The DM74LS47 accepts four lines of BCD (8421) input

data, gener ates their compl ements interna lly and d ecodes

the data with seven AND/OR gates having open-collector

output s to drive in dica tor segm ents dir ectly. Each segme nt

output is guaranteed to sink 24 mA in the ON (LOW) state

and withstand 15V in the OFF (HIGH) state with a maxi-

mum leakage current of 2 50 µA. Auxiliary inputs provided

blanking, lamp test and cascadable zero-suppression func-

tions.

Features

■Open-col lect or outp uts

■Drive indicator segments directly

■Cascadable zero-suppression capability

■Lamp test inpu t

Ordering Code:

Devices also available in Tape and R eel. Speci fy by appending the s uffix let t er “X” to the orderin g c ode.

Logic Symbol

VCC = Pin 16

GND = Pin 8

Connection Diagram

Pin Descriptions

Note 1: OC—Open C ollector

Order Number Package Number Package Description

DM74LS47M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

DM74LS47N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Pin Names Description

A0–A3 BCD Inputs

RBI Ripple Blanking Input (Active LOW)

LT Lamp Test Input (Active LOW)

BI/RBO Blanking Input (Active LOW) or

Ripple Blanking Output (Active LOW)

a –g Segment Outputs (Active LOW) (Note 1)

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DM74LS47

Truth Table

Note 2: BI/RBO is wire -AND lo gic serving as blank ing inpu t (BI) and/ or ripple-bla nk ing out put (RB O). T he blan k ing out (BI) m ust be open or he ld at a H I GH

level when output functions 0 through 15 are desired, and ripple-blanking input (RBI) must be open or at a HIGH level if blanking or a decimal 0 is not

desired. X = input may b e HIGH or LOW.

Note 3: When a LOW level is applied to the blanking input (forced condition) all segment outputs go to a HIGH level regardless of the state of any other input

condition.

Note 4: W hen ripple -blan king inpu t (RBI) a nd in puts A0 , A1 , A2 a nd A 3 are L OW le vel, with t he l amp tes t i nput at HIGH lev el, all s egm ent out put s go to a

HIGH lev el and th e ripple-b lanking out put (RBO ) goes to a LO W lev el (resp onse con dit ion).

Note 5: When the blanking input/ripple-blanking output (BI/RBO) is OPEN or held at a HIGH lev el, and a LOW level is applied to lamp tes t inp ut , all seg m ent

outputs go to a LOW level.

Functional Description

The DM74LS47 decodes the input data in the pattern indi-

cated in the Truth Table and the segment identification

illustration. If the input data is decimal zero, a LOW signal

applied to the RBI blanks the display and causes a multi-

digit display. For example, by grounding the RBI of the

high est o rde r d eco der an d co nne cting i ts BI/RBO to RBI of

the next lowest order decoder, etc., leading zeros will be

suppressed. Similarly, by grounding RBI of the lowest order

decoder and connecting its BI/RBO to RBI of the next high-

est order decoder, etc., trailing zeros will be suppressed.

Leading and trailing zeros can be suppressed simulta-

neously by using external gates, i.e.: by driving RBI of a

intermediate decoder from an OR gate whose inputs are

BI/RBO of the next highes t and lowest ord er decoders . BI/

RBO also serves as an unconditional blanking input. The

internal NAND gate that generates the RBO signal has a

resistive pu ll-up, as opposed to a tot em pole, and thus B I/

RBO can be for ced LOW by extern al means, usin g wired-

collector logic. A LOW signal th us applied to BI/RBO tu rns

off all segme nt outputs. Thi s blanki ng feature can be used

to contro l display in tensity by varying the duty cycle o f the

blanking signal. A LOW signal applied to LT turns on all

segment outputs, provided that BI/RBO is not forced LOW.

Decimal Inputs Outputs

or Note

Function LT RBI A3 A2 A1 A0 BI/RBO a b c d e f g

0 HHLLLL H LLLLLLH(Note 2)

1 H X L L L H H H L L H H H H (Note 2)

2HXLLHLHLLHLLHL

3 HXLLHHHLLLLHHL

4HXLHLLHHLLHHLL

5 HXLHLHHLHLLHLL

6 HXLHHL H HHLLLLL

7 HXLHHHHLLLHHHH

8 HXHLLL H LLLLLLL

9 HXHLLH H LLLHHLL

10 H X H L H L H H H H L L H L

11 HXHLHH H HHLLHHL

12 H X H H L L H H L H H H L L

13 HXHHLHHLHHLHLL

14 HXHHHL H HHHLLLL

15 HXHHHH H HHHHHHH

BI XXXXXX L HHHHHHH(Note 3)

RBI HL L L L L L HHHHHHH(Note 4)

LT LXXXXX H LLLLLLL(Note 5)

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DM74LS47

Logic Diagram

Numerical Designations—Resultant Displays

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Absolute Maximum Ratings(Not e 6) Note 6: Th e “Absolute Max imum Ratin gs” are those v alues beyon d which

the saf ety of the device cannot be guarante ed. The device s hould not be

operated at these limits. The parametric values defined in the Electrical

Characteristics tables are not guaranteed at the abso lute maximu m rati n gs.

The “Re comme nded Operat ing Co ndition s” table will define the cond itions

for actu al device operation.

Recommended Operating Conditions

Note 7: OFF-State at a–g.

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted)

Note 8: All typic als are at VCC = 5V, TA = 25°C.

Note 9: Not more than one output should be shorted at a time, and the duration should not exceed one second.

Switching Characteri stics

at VCC = +5.0V, TA = +25°C

Note 10: LT = HIGH, A0–A3 = LOW

Supply Voltage 7V

Input Vo l tag e 7V

Operating Free Air Temperature Range 0°C to +70°C

Storage Temperature Range −65°C to +150°C

Symbol Parameter Min Nom Max Units

VCC Supply Voltage 4.75 5 5.25 V

VIH HIGH Level Input Voltage 2 V

VIL LOW Level Input Voltage 0.8 V

IOH HIGH Level Output Current −250 µA

a − g @ 15V = VOH (Note 7)

IOH HIGH Level Output Current BI /RBO −50 µA

IOL LOW Level Output Current 24 mA

TAFree Air Operating Temperature 0 70 °C

Symbol Parameter Conditions Min Typ Max Units

(Note 8)

VIInput Clamp Voltage VCC = Min, II = −18 mA −1.5 V

VOH HIGH Level VCC = Min, I OH = Max, 2.7 3.4 V

Output Voltage VIL = Max, BI /RBO

IOFF Output HIGH Current Segment Outputs VCC = 5.5V, VO = 15V a − g 250 µA

VOL LOW Level VCC = Min, IOL = Max, 0.35 0.5

Output Voltage VIH = Min, a − g

IOL = 3.2 mA, BI /RBO 0.5 V

IOL = 12 mA, a –g 0.25 0.4

IOL = 1.6 mA, BI /RBO 0.4

IIInput Current @ Max VCC = Max, VI = 7V 100 µA

Input Voltage VCC = Max, VI = 10V

IIH HIGH Level Input Curre nt VCC = Ma x, VI = 2.7V 20 µA

IIL LOW Level Input Current VCC = Max, VI = 0.4V −0.4 mA

IOS Short Circuit VCC = Max (Note 9), mA

Output Current IOS at BI/RBO −0.3 −2.0

ICC Supply Curr ent VCC = Max 13 mA

RL = 665Ω

Symbol Parameter Conditions CL = 15 pF Units

Min Max

tPLH Propagation Delay 100 ns

tPHL An to a –g 100

tPLH Propagation Delay 100 ns

tPHL RBI to a –g (Note 10) 100

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DM74LS47

Physical Dim ensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow

Package Number M16A

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DM74LS47 BCD to 7-Segment Decoder/Driver with Open-Collector Outputs

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

Package Number N16E

Fairchild does no t assume any responsibility for use of any circuitry de scribed, no circuit patent licenses are imp lied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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