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a
AD7841
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 www.analog.com
Octal 14-Bit, Parallel Input,
Voltage-Output DAC
FUNCTIONAL BLOCK DIAGRAM
DAC
REG
A
INPUT
REG
A
DAC E
AD7841
DB13
DB0
WR
CS
A0
A1
A2
LDAC
RR
RR
R
R
RR
RR
RR
RR
RR
DAC
REG
B
INPUT
REG
B
DAC
REG
C
INPUT
REG
C
DAC
REG
D
INPUT
REG
D
DAC
REG
E
INPUT
REG
E
DAC
REG
F
INPUT
REG
F
DAC
REG
G
INPUT
REG
G
DAC
REG
H
INPUT
REG
H
14
DAC D
DAC C
DAC F
DAC B
DAC A
DAC G
DAC H
V
CC
V
SS
V
DD
V
REF
(+)
AB
V
REF
(–)
AB
DUTGND
CD
DUTGND
AB
V
OUT
A
V
OUT
B
V
OUT
C
V
OUT
D
V
OUT
E
V
OUT
F
V
OUT
G
V
OUT
H
DUTGND
GH
DUTGND
EF
V
REF
(–)
CDEF
V
REF
(+)
CDEF
V
REF
(–)
GH
V
REF
(+)
GH
GND CLR
ADDRESS
DECODE
14 14
14 14 14
14 14 14
14 14 14
14 14 14
14 14 14
14 14 14
14 14 14
FEATURES
Eight 14-Bit DACs in One Package
Voltage Outputs
Offset Adjust for Each DAC Pair
Reference Range of 5 V
Maximum Output Voltage Range of 10 V
15 V 10% Operation
Clear Function to User-Defined Voltage
44-Lead MQFP Package
APPLICATIONS
Automatic Test Equipment
Process Control
General Purpose Instrumentation
GENERAL DESCRIPTION
The AD7841 contains eight 14-bit DACs on one monolithic
chip. It has output voltages with a full-scale range of ±10 V
from reference voltages of ±5 V.
The AD7841 accepts 14-bit parallel loaded data from the exter-
nal bus into one of the input registers under the control of the
WR, CS, and DAC channel address pins, A0–A2.
The DAC outputs are updated on reception of new data into
the DAC registers. All the outputs may be updated simulta-
neously by taking the LDAC input low.
Each DAC output is buffered with a gain-of-two amplifier into
which an external DAC offset voltage can be inserted via the
DUTGNDx pins.
The AD7841 is available in a 44-lead MQFP package.
REV. B
Fax: 781/461-3113
© 1999-2011 Analog Devices, Inc. All rights reserved.
–2–
AD7841–SPECIFICATIONS
(VCC = 5 V 5%; VDD = 15 V10%; VSS = –15 V10%; GND = DUTGND =
0 V; RL = 5 k and CL = 50 pF to GND, TA1 = TMIN to TMAX, unless otherwise noted)
Parameter A B Unit Test Conditions/Comments
ACCURACY
Resolution 14 14 Bits
Relative Accuracy ±4±2 LSB max
Differential Nonlinearity –0.9/2 ±1 LSB max Guaranteed Monotonic Over Temperature for All
Grades
Zero-Scale Error ±8±8 LSB max V
REF
(+) = +5 V, V
REF
(–) = –5 V. Typically within
±2 LSB
Full-Scale Error ±8±8 LSB max V
REF
(+) = +5 V, V
REF
(–) = –5 V. Typically within
±2 LSB
Gain Error ±2±2 LSB typ V
REF
(+) = +5 V, V
REF
(–) = –5 V
Gain Temperature Coefficient
2
0.5 0.5 ppm FSR/°C typ
10 10 ppm FSR/°C max
DC Crosstalk
2
120 120 µV max See Terminology. Typically 75 µV
REFERENCE INPUTS
2
DC Input Impedance 100 100 MΩ typ
Input Current ±1±1µA max Per Input. Typically ±0.03 µA
V
REF
(+) Range 0/5 0/5 V min/max
V
REF
(–) Range –5/0 –5/0 V min/max
[V
REF
(+) – V
REF
(–)] 2/10 2/10 V min/max For Specified Performance. Can Go as Low as 0 V,
but Performance Not Guaranteed
DUTGND INPUTS
2
DC Input Impedance 60 60 kΩ typ
Max Input Current ±0.3 ±0.3 mA typ Per Input
Input Range
3
–2/+2 –2/+2 V min/max
OUTPUT CHARACTERISTICS
2
Output Voltage Swing V
SS
+ 2.5 V to V
SS
+ 2.5 V to V typ V
OUT
= 2 × (V
REF
(–) + [V
REF
(+) – V
REF
(–)] × D)
V
DD
– 2.5 V V
DD
– 2.5 V – V
DUTGND
Short Circuit Current 15 15 mA max
Resistive Load 5 5 kΩ min To 0 V
Capacitive Load 50 50 pF max To 0 V
DC Output Impedance 0.5 0.5 Ω max
DIGITAL INPUTS
2
V
INH
, Input High Voltage 2.4 2.4 V min
V
INL
, Input Low Voltage 0.8 0.8 V max
I
INH
, Input Current Total for All Pins
@ 25°C±1±1µA max
T
MIN
to T
MAX
±10 ±10 µA max
C
IN
, Input Capacitance 10 10 pF max
POWER REQUIREMENTS
4
V
CC
4.75/+5.25 4.75/+5.25 V min/max For Specified Performance
V
DD
15 V ± 10% 15 V ± 10% V min/max For Specified Performance
V
SS
–15 V ± 10% –15 V ± 10% V min/max For Specified Performance
Power Supply Sensitivity
2
∆Full Scale/∆V
DD
90 90 dB typ
∆Full Scale/∆V
SS
90 90 dB typ
I
CC
0.5 0.5 mA max V
INH
= V
CC
, V
INL
= GND. Dynamic Current
I
DD
10 10 mA max Outputs Unloaded. Typically 8 mA
I
SS
10 10 mA max Outputs Unloaded. Typically 8 mA
NOTES
1
Temperature range for A and B Versions: –40°C to +85°C.
2
Guaranteed by characterization. Not production tested.
3
See DUTGND Voltage Range section.
4
The AD7841 is functional with power supplies of ±12 V ±10% with reduced output range. Output amplifier requires 2.5 V of head room at the bottom and top ends
of the transfer for function. At 12 V supplies it is recommended to restrict the reference range to ±4 V.
Specifications subject to change without notice.
REV. B
–3–
AD7841
(These characteristics are included for Design Guidance and are not subject
to production testing.)
AC PERFORMANCE CHARACTERISTICS
A & B
Parameter Versions Unit Test Conditions/Comments
DYNAMIC PERFORMANCE
Output Voltage Settling Time 31 µs typ Full-Scale Change to ±1/2 LSB. DAC Latch Contents Alternately
Loaded with All 0s and All 1s
Slew Rate 0.7 V/µs typ
Digital-to-Analog Glitch Impulse 230 nV-s typ Measured with V
REF
(+) = +5 V, V
REF
(–) = –5 V. DAC Latch
Alternately Loaded with 1FFF Hex and 2000 Hex. Not Dependent
on Load Conditions
Channel-to-Channel Isolation 99 dB typ See Terminology
DAC-to-DAC Crosstalk 40 nV-s typ See Terminology
Digital Crosstalk 0.2 nV-s typ Feedthrough to DAC Output Under Test Due to Change in Digital
Input Code to Another Converter
Digital Feedthrough 0.1 nV-s typ Effect of Input Bus Activity on DAC Output Under Test
Output Noise Spectral Density
@ 1 kHz 200 nV/√Hz
typ All 1s Loaded to DAC. V
REF
(+) = V
REF
(–) = 0 V
Specifications subject to change without notice.
TIMING SPECIFICATIONS
1, 2
Parameter Limit at T
MIN,
T
MAX
Unit Description
t
1
15 ns min Address to WR Setup Time
t
2
0 ns min Address to WR Hold Time
t
3
50 ns min CS Pulsewidth Low
t
4
50 ns min WR Pulsewidth Low
t
5
0 ns min CS to WR Setup Time
t
6
0 ns min WR to CS Hold Time
t
7
20 ns min Data Setup Time
t
8
0 ns min Data Hold Time
t
9
31 µs typ Settling Time
t
10
300 ns max CLR Pulse Activation Time
t
11
50 ns min LDAC Pulsewidth Low
NOTES
1
All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2
Rise and fall times should be no longer than 50 ns.
Specifications subject to change without notice.
t
1
t
2
t
5
t
6
t
3
t
4
t
7
t
8
t
9
t
10
t
11
LDAC
CLR
WR
CS
A0, A1, A2
DATA
V
OUT
V
OUT
Figure 1. Timing Diagram
(VCC = 5 V 5%; VDD = 15 V 10%; VSS = –15 V 10%; GND = DUTGND = 0 V)
REV. B
AD7841
–4–
ABSOLUTE MAXIMUM RATINGS
1, 2
(T
A
= 25°C unless otherwise noted)
V
CC
to GND
3
. . . . . . . . . . . . . . –0.3 V, +7 V or V
DD
+ 0.3 V
(Whichever Is Lower)
V
DD
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V, +17 V
V
SS
to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, –17 V
Digital Inputs to GND . . . . . . . . . . . . . . –0.3 V, V
CC
+ 0.3 V
V
REF
(+) to V
REF
(–) . . . . . . . . . . . . . . . . . . . . . –0.3 V, +18 V
V
REF
(+) to GND . . . . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
V
REF
(–) to GND . . . . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
DUTGND to GND . . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
V
OUT
(A–H) to GND . . . . . . . . . . . . V
SS
– 0.3 V, V
DD
+ 0.3 V
Operating Temperature Range
Industrial (A Version) . . . . . . . . . . . . . . . –40°C to +85°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150°C
MQFP Package
Power Dissipation . . . . . . . . . . . . . . . . . (T
J
Max – T
A
)/θ
JA
θ
JA
Thermal Impedance . . . . . . . . . . . . . . . . . . . . . 95°C/W
NOTES
1
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2
Transient currents of up to 100 mA will not cause SCR latch-up.
3
V
CC
must not exceed V
DD
by more than 0.3 V. If it is possible for this to happen
during power supply sequencing, the following diode protection scheme will ensure
protection.
PIN CONFIGURATION
3
4
5
6
7
1
2
10
11
8
9
40 39 3841424344 36 35 3437
PIN 1
IDENTIFIER
TOP VIEW
(Not to Scale)
12 13 14 15 16 17 18 19 20 21 22
29
30
31
32
33
27
28
25
26
23
24
DUTGND_GH
V
OUT
H
V
REF
(–)GH
V
REF
(+)GH
CLR
DB13
DB12
AD7841
DUTGND_AB
V
OUT
A
V
REF
(–)AB
V
REF
(+)AB
V
DD
V
SS
LDAC
A2
A1
A0
CS
DB11
DB10
DB9
DB8
DB4
V
OUT
B
V
OUT
C
DUTGND_CD
V
OUT
D
V
DD
V
OUT
E
DUTGND_EF
V
OUT
F
V
OUT
G
DB7
DB5
DB6
DB2
WR
V
CC
GND
DB0
DB1
DB3
V
REF
(–)CDEF
V
REF
(+)CDEF
V
DD
V
CC
AD7841
HP5082-2811
V
DD
V
CC
IN4148
REV. B
Lead Temperature ............................JEDEC Industry Standard
Soldering ......................................................................J-STD-020
ESD .................................................................................. >4000 V
AD7841
–5–
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic Description
1 DUTGND_AB Device Sense Ground for DACs A and B. V
OUT
A and V
OUT
B are referenced to the voltage
applied to this pin.
2, 44, 43, V
OUT
A..V
OUT
H DAC Outputs.
41, 37, 35,
34, 32
3, 4 V
REF
(–)AB, V
REF
(+)AB Reference Inputs for DACs A and B. These reference voltages are referred to GND.
5, 38 V
DD
Positive Analog Power Supply; +15 V ± 10% for specified performance.
6V
SS
Negative Analog Power Supply; –15 V ± 10% for specified performance.
7LDAC Load DAC Logic Input (active low). When this logic input is taken low the contents of the
registers are transferred to their respective DAC registers. LDAC can be tied permanently
low enabling the outputs to be updated on the rising edge of WR.
8, 9, 10 A2, A1, A0 Address inputs. A0, A1 and A2 are decoded to select one of the eight input registers for a
data transfer.
11 CS Level-Triggered Chip Select Input (active low). The device is selected when this input is low.
12 WR Level-Triggered Write Input (active low), used in conjunction with CS to write data to the
AD7841 data registers. Data is latched into the selected input register on the rising edge
of WR.
13 V
CC
Logic Power Supply; 5 V ± 5%.
14 GND Ground.
15–28 DB0 . . DB12 Parallel Data Inputs. The AD7841 can accept a straight 14-bit parallel word on DB0 to
DB13 where DB13 is the MSB and DB0 is the LSB.
29 CLR Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog
outputs are switched to the externally set potential on the relevant DUTGND pin. The con-
tents of input registers and DAC registers A to H are not affected when the CLR pin is taken
low. When CLR is brought back high, the DAC outputs revert to their original outputs as
determined by the data in their DAC registers.
30, 31 V
REF
(+)GH, V
REF
(–)GH Reference Inputs for DACs G and H. These reference voltages are referred to GND.
33 DUTGND_GH Device Sense Ground for DACs G and H. V
OUT
G and V
OUT
H are referenced to the voltage
applied to this pin.
36 DUTGND_EF Device Sense Ground for DACs E and F. V
OUT
E and V
OUT
F are referenced to the voltage
applied to this pin.
39 V
REF
(+)CDEF Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND.
40 V
REF
(–)CDEF Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND.
42 DUTGND_CD Device Sense Ground for DACs C and D. V
OUT
C and V
OUT
D are referenced to the voltage
applied to this pin.
REV. B
AD7841
–6–
TERMINOLOGY
Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the max-
imum deviation from a straight line passing through the endpoints
of the DAC transfer function. It is measured after adjusting for
zero-scale error and full-scale error and is expressed in Least
Significant Bits.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
DC Crosstalk
Although the common input reference voltage signals are inter-
nally buffered, small IR drops in the individual DAC reference
inputs across the die can mean that an update to one channel
can produce a dc output change in one or another of the chan-
nel outputs.
The eight DAC outputs are buffered by op amps that share
common V
DD
and V
SS
power supplies. If the dc load current
changes in one channel (due to an update), this can result in a
further dc change in one or another of the channel outputs. This
effect is most obvious at high load currents and reduces as the
load currents are reduced. With high impedance loads the effect
is virtually impossible to measure.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
This is the amount of charge injected into the analog output
when the inputs change state. It is specified as the area of the
glitch in nV-secs. It is measured with V
REF
(+) = +5 V and
V
REF
(–) = –5 V and the digital inputs toggled between 1FFFH
and 2000H.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input that appears at the out-
put of another DAC. It is expressed in dBs.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is defined as the glitch impulse that
appears at the output of one converter due to both the digital
change and subsequent analog O/P change at another converter.
It is specified in nV-secs.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the digital crosstalk and is specified in nV-secs.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device’s digital inputs can be capacitively coupled both
across and through the device to show up as noise on the V
OUT
pins. This noise is digital feedthrough.
DC Output Impedance
This is the effective output source resistance. It is dominated by
package lead resistance.
Full-Scale Error
This is the error in DAC output voltage when all 1s are loaded
into the DAC latch. Ideally the output voltage, with all 1s loaded
into the DAC latch, should be 2 V
REF
(+) – 1 LSB.
Zero-Scale Error
Zero-scale error is the error in the DAC output voltage when all
0s are loaded into the DAC latch. Ideally the output voltage,
with all 0s in the DAC latch should be equal to 2 V
REF
(–). Zero-
scale error is mainly due to offsets in the output amplifier.
Gain Error
Gain Error is defined as (Full-Scale Error) – (Zero-Scale Error).
GENERAL DESCRIPTION
DAC Architecture—General
Each channel consists of a straight 14-bit R-2R voltage-mode
DAC. The full-scale output voltage range is equal to twice the
reference span of V
REF
(+) – V
REF
(–). The DAC coding is straight
binary; all 0s produces an output of 2 V
REF
(–); all 1s produces
an output of 2 V
REF
(+) – 1 LSB.
The analog output voltage of each DAC channel reflects the
contents of its own DAC register. Data is transferred from
the external bus to the input register of each DAC on a per
channel basis.
Bringing the CLR line low switches all the signal outputs, V
OUT
A
to V
OUT
H, to the voltage level on the relevant DUTGND pin.
When the CLR signal is brought back high, the output voltages
from the DACs will reflect the data stored in the relevant
DAC registers.
Data Loading to the AD7841
Data is loaded into the AD7841 in straight parallel 14-bit wide
words.
The DAC output voltages, V
OUT
A – V
OUT
H are updated to
reflect new data in the DAC registers.
The actual input register being written to is determined by the
logic levels present on the device’s address lines, as shown in
Table I.
Table I. Address Line Truth Table
A2 A1 A0 DAC Selected
0 0 0 INPUT REG A (DAC A)
0 0 1 INPUT REG B (DAC B)
0 1 0 INPUT REG C (DAC C)
0 1 1 INPUT REG D (DAC D)
1 0 0 INPUT REG E (DAC E)
1 0 1 INPUT REG F (DAC F)
1 1 0 INPUT REG G (DAC G)
1 1 1 INPUT REG H (DAC H)
REV. B
AD7841
–7–
Typical Performance Characteristics–
INL ERROR – LSBs
CODE
2
–2
02048
1
0
4096 12288 16384
–1
6144 8192 10240 14336
V
DD
= +15V
V
SS
= –15V
V
REF
(+) = +5V
V
REF
(–) = –5V
T
A
= 25C
TPC 1. Typical INL Plot
DNL ERROR – LSBs
1
–1
–0.5
0.5
0
TEMPERATURE – C
–40 100–200 20406080
V
DD
= +15V
V
SS
= –15V
V
REF
(+) = +5V
V
REF
(+) = –5V
TPC 4. Typical DNL Error vs.
Temperature
0.6
0.5
0.4
0.3
0.1
Volts
0.2
0
–0.1
–0.2
0 500
1
000
1
500
2
000
2
500 3000 3500
4
000
4
500 5000
TPC 7. Typical Digital-to-Analog
Glitch Impulse
CODE
1
–1
0 2048
0.75
0.25
0
0.5
4096 6144 8192
DNL ERROR – LSBs
–0.25
–0.5
–0.75
10240 12288 14336 16384
V
DD
= +15V
V
SS
= –15V
V
REF
(+) = +5V
V
REF
(–) = –5V
T
A
= 25C
TPC 2. Typical DNL Plot
ERROR – LSBs
TEMPERATURE – C
4
2
–4
0
–2
–40 –20 100
0 20406080
V
DD
= +15V
V
SS
= –15V
V
REF(+)
= +5V
V
REF(–)
= –5V
FULL-SCALE ERROR
ZERO-SCALE ERROR
TPC 5. Zero-Scale and Full-Scale
Error vs. Temperature
V
OUT
– Volts
10.19
10.17
10.16
10.18
SETTLING TIME –
s
27 3328 29 30 31 32
TPC 8. Settling Time (+)
INL ERROR – LSBs
TEMPERATURE – C
4
2
–1
0
–2
–40 –20 1000 20406080
V
DD
= +15V
V
SS
= –15V
V
REF
(+) = +5V
V
REF
(–) = –5V
TPC 3. Typical INL Error vs.
Temperature
TEMPERATURE – C
–40 100–200 20406080
6
–1
I
CC
– mA
1
5
3
4
2
0
V
CC
= +5V
V
DD
= +15V
V
SS
= –15V
DIGITAL INPUTS @ SUPPLIES
DIGITAL INPUTS @
THRESHOLDS
TPC 6. I
CC
vs. Temperature
10
8
6
4
–40 –20 0 20 40 60
I
DD
/I
SS
– mA
TEMPERATURE – °C
80 100
I
SS
I
DD
V
DD
= +15V
V
SS
= –15V
V
CC
= +5V
TPC 9. I
DD
, I
SS
vs. Temperature
REV. B
AD7841
–8–
Unipolar Configuration
Figure 2 shows the AD7841 in the unipolar binary circuit
configuration. The V
REF
(+) input of the DAC is driven by the
AD586, a 5 V reference. V
REF
(–) is tied to ground. Table II
gives the code table for unipolar operation of the AD7841.
Other suitable references include the REF02, a precision 5 V
reference, and the REF195, a low dropout, micropower preci-
sion 5 V reference.
AD7841*
V
DD
V
CC
V
REF
(+) V
OUT
DUTGND
GND
V
SS
V
REF
(–)
SIGNAL
GND
–15V
V
OUT
(0 TO +10V)
+5V+15V
AD586
R1
10k
2
6
5
4
8
C1
1F
SIGNAL
GND
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 2. Unipolar 10 V Operation
Offset and gain may be adjusted in Figure 2 as follows: To
adjust offset, disconnect the V
REF
(–) input from 0 V, load the
DAC with all 0s and adjust the V
REF
(–) voltage until V
OUT
= 0 V.
For gain adjustment, the AD7841 should be loaded with all 1s
and R1 adjusted until V
OUT
= 2 V
REF
(+) – 1 LSB = 10 V(16383/
16384) = 9.99939 V.
Many circuits will not require these offset and gain adjustments.
In these circuits R1 can be omitted. Pin 5 of the AD586 may be
left open circuit and Pin 2 (V
REF
(–)) of the AD7841 tied to 0 V.
Table II. Code Table for Unipolar Operation
Binary Number in DAC Register Analog Output
MSB LSB (V
OUT
)
11 1111 1111 1111 2 V
REF
(16383/16384) V
10 0000 0000 0000 2 V
REF
(8192/16384) V
01 1111 1111 1111 2 V
REF
(8191/16384) V
00 0000 0000 0001 2 V
REF
(1/16384) V
00 0000 0000 0000 0 V
NOTES
V= V
REF
(+); V
REF
(–) = 0 V for unipolar operation.
For V
REF
(+) = 5 V, 1 LSB = 10 V/2
14
= 10 V/16384 = 610 µV.
Bipolar Configuration
Figure 3 shows the AD7841 set up for ±10 V operation. The
AD588 provides precision ±5 V tracking outputs that are fed to
the V
REF
(+) and V
REF
(–) inputs of the AD7841. The code table
for bipolar operation of the AD7841 is shown in Table III.
In Figure 3, full-scale and bipolar zero adjustments are provided
by varying the gain and balance on the AD588. R2 varies the
gain on the AD588 while R3 adjusts the offset of both the +5 V
and –5 V outputs together with respect to ground.
For bipolar-zero adjustment, the DAC is loaded with
1000...0000 and R3 is adjusted until V
OUT
= 0 V. Full scale
is adjusted by loading the DAC with all 1s and adjusting R2
until V
OUT
= 10(8191/8192) V = 9.99878 V.
When bipolar-zero and full-scale adjustment are not needed, R2
and R3 can be omitted. Pin 12 on the AD588 should be con-
nected to Pin 11 and Pin 5 should be left floating.
AD7841*
VDD VCC
VREF(+)
VOUT
DUTGND
GND
VSS
VREF(–)
SIGNAL
GND
–15V
VOUT
(–10V TO +10V)
+5V+15V
*ADDITIONAL PINS OMITTED FOR CLARITY
R1
39k
C1
1F
R2
100k
R3
100k
AD588
46
2
3
1
14
15
16
7
9
5
10
11
12 8 13
Figure 3. Bipolar
±
10 V Operation
Table III. Code Table for Bipolar Operation
Binary Number in DAC
Register Analog Output
MSB LSB (V
OUT
)
11 1111 1111 1111 2[V
REF
(–) + V
REF
(16383/16384)] V
10 0000 0000 0001 2[V
REF
(–) + V
REF
(8193/16384)] V
10 0000 0000 0000 2[V
REF
(–) + V
REF
(8192/16384)] V
01 1111 1111 1111 2[V
REF
(–) + V
REF
(8191/16384)] V
00 0000 0000 0001 2[V
REF
(–) + V
REF
(1/16384)] V
00 0000 0000 0000 2[V
REF
(–)] V
NOTES
V
REF
= (V
REF
(+) – V
REF
(–)).
For V
REF
(+) = +5 V, and V
REF
(–) = –5 V, V
REF
= 10 V, 1 LSB = 2 V
REF
V/2
14
=
20 V/16384 = 1.22 mV.
CONTROLLED POWER-ON OF THE OUTPUT STAGE
A block diagram of the output stage of the AD7841 is shown in
Figure 4. It is capable of driving a load of 5 kΩ in parallel with
50 pF. G
1
to G
6
are transmission gates used to control the
power on voltage present at V
OUT
. On power up G
1
and G
2
are
also used in conjunction with the CLR input to set V
OUT
to the
user defined voltage present at the DUTGND pin. When CLR
is taken back high, the DAC outputs reflect the data in the
DAC registers.
G
1
G
2
G
4
G
3
G
6
G
5
DUTGND
V
OUT
R
R = 60k
14k
DAC
Figure 4. Block Diagram of AD7841 Output Stage
REV. B
AD7841
–9–
Power-On with CLR Low
The output stage of the AD7841 has been designed to allow
output stability during power-on. If CLR is kept low during
power-on, then just after power is applied to the AD7841, the
situation is as depicted in Figure 5. G
1
, G
4
and G
6
are open
while G
2
, G
3
and G
5
are closed.
G
1
G
2
G
4
G
3
G
6
G
5
DUTGND
V
OUT
R
R
14k
DAC
Figure 5. Output Stage with V
DD
< 7 V or V
SS
> –3 V;
CLR
Low
V
OUT
is kept within a few hundred millivolts of DUTGND via
G
5
and a 14 kΩ resistor. This thin-film resistor is connected in
parallel with the gain resistors of the output amplifier. The
output amplifier is connected as a unity gain buffer via G
3
, and
the DUTGND voltage is applied to the buffer input via G
2
. The
amplifier’s output is thus at the same voltage as the DUTGND
pin. The output stage remains configured as in Figure 5 until
the voltage at V
DD
exceeds 7 V and V
SS
is more negative than
–3 V. By now the output amplifier has enough headroom to
handle signals at its input and has also had time to settle. The
internal power-on circuitry opens G
3
and G
5
and closes G
4
and
G
6
. This situation is shown in Figure 6. Now the output ampli-
fier is configured in its noise gain configuration via G
4
and G
6
.
The DUTGND voltage is still connected to the noninverting
input via G
2
and this voltage appears at V
OUT
.
G1
G2G4
G3
G6
G5
DUTGND
VOUT
R
R
14k
DAC
Figure 6. Output Stage with V
DD
> 7 V and V
SS
< –3 V;
CLR
Low
V
OUT
has been disconnected from the DUTGND pin by the
opening of G
5
, but will track the voltage present at DUTGND
via the configuration shown in Figure 6.
When CLR is taken back high, the output stage is configured as
shown in Figure 7. The internal control logic closes G
1
and
opens G
2
. The output amr})fier is connected in a noninverting
gain-of-two configuration. The voltage that appears on the V
OUT
pins is determined by the data present in the DAC registers.
G
1
G
2
G
4
G
3
G
6
G
5
DUTGND
V
OUT
R
R
14k
DAC
Figure 7. Output Stage After
CLR
Is Taken High
Power-On with CLR High
If CLR is high on the application of power to the device, the
output stages of the AD7841 are configured as in Figure 8 while
V
DD
is less than 7 V and V
SS
is more positive than –3 V. G
1
is
closed and G
2
is open, thereby connecting the output of the
DAC to the input of its output amplifier. G
3
and G
5
are closed
while G
4
and G
6
are open, thus connecting the output amplifier as
a unity gain buffer. V
OUT
is connected to DUTGND via G
5
through a 14 kΩ resistor until V
DD
exceeds 7 V and V
SS
is more
negative than –3 V.
G
1
G
2
G
4
G
3
G
6
G
5
DUTGND
V
OUT
R
R
14k
DAC
Figure 8. Output Stage Powering Up with
CLR
High
While V
DD
< 7 V or V
SS
> –3 V
When the difference between the supply voltages reaches 10 V,
the internal power-on circuitry opens G
3
and G
5
and closes G
4
and G
6
configuring the output stage as shown in Figure 9.
G1
G2G4
G3
G6
G5
DUTGND
VOUT
R
R
14k
DAC
Figure 9. Output Stage Powering Up with
CLR
High
When V
DD
> 7 V and V
SS
< –3 V
REV. B
AD7841
–10–
DUTGND Voltage Range
During power-on, the V
OUT
pins of the AD7841 are connected
to the relevant DUTGND pins via G
5
and the 14 kΩ thin-film
resistor. The DUTGND potential must obey the max ratings at
all times. Thus, the voltage at DUTGND must always be within
the range V
SS
– 0.3 V, V
DD
+ 0.3 V. However, in order that the
voltages at the V
OUT
pins of the AD7841 stay within ±2 V of the
relevant DUTGND potential during power-on, the voltage
applied to DUTGND should also be kept within the range
GND – 2 V, GND + 2 V.
Once the AD7841 has powered on and the on-chip amplifiers
have settled, any voltage that is now applied to the DUTGND
pin is subtracted from the DAC output, which has been gained
up by a factor of two. Thus, for specified operation, the maximum
voltage that can be applied to the DUTGND pin increases to the
maximum allowable 2 V
REF
(+) voltage, and the minimum volt-
age that can be applied to DUTGND is the minimum 2 V
REF
(–)
voltage. After the AD7841 has fully powered on, the outputs
can track any DUTGND voltage within this minimum/maxi-
mum range.
Power Supply Sequencing
When operating the AD7841, it is important that ground be
connected at all times to avoid high current states. The recom-
mended power-up sequence is V
DD
/V
SS
followed by V
CC
. If V
CC
can exceed V
DD
on power-up, the diode scheme shown in the
absolute maximum ratings section will ensure protection. The
reference inputs and digital inputs should be powered up last.
Should the references exceed V
DD
/V
SS
on power-up, current
limiting resistors should be inserted in series with the reference
inputs to limit the current to 20 mA. Logic inputs should not be
applied before V
CC
. Current limiting resistors (470 Ω) in series
with the logic inputs should be inserted if these inputs come up
before V
CC
.
MICROPROCESSOR INTERFACING
Interfacing the AD7841—16-Bit Interface
The AD7841 can be interfaced to a variety of 16-bit micro-
controllers or DSP processors. Figure 10 shows the AD7841
interfaced to a generic 16-bit microcontroller/DSP processor.
The lower address lines from the processor are connected to A0,
A1 and A2 on the AD7841 as shown. The upper address lines
are decoded to provide a chip select signal or an LDAC signal
for the AD7841. The fast interface timing of the AD7841 allows
direct interface to a wide variety of microcontrollers and DSPs
as shown in Figure 10.
AD7841
CONTROLLER/
DSP PROCESSOR*
ADDRESS
DECODE
D13
D0
DATA
BUS
UPPER BITS OF
ADDRESS BUS
A2
A1
A0
R/W
*ADDITIONAL PINS OMITTED FOR CLARITY
D13
D0
CS
LDAC
A2
A1
A0
WR
Figure 10. Parallel Interface
APPLICATIONS
Power Supply Bypassing and Grounding
In any circuit where accuracy is important, careful consideration
of the power supply and ground return layout helps to ensure
the rated performance. The printed circuit board on which the
AD7841 is mounted should be designed such that the analog
and digital sections are separated and confined to certain areas
of the board. This facilitates the use of ground planes that can
be easily separated. A minimum etch technique is generally best
for ground planes as it gives the best shielding. Digital and ana-
log ground planes should be joined at only one place. The GND
pin of the AD7841 should be connected to the AGND of the
system. If the AD7841 is in a system where multiple devices
require an AGND-to-DGND connection, the connection should
be made at one point only, a star ground point that should be
established as close as possible to the AD7841.
Digital lines running under the device should be avoided as
these will couple noise onto the die. The analog ground plane
should be allowed to run under the AD7841 to avoid noise
coupling. The power supply lines of the AD7841 should use as
large a trace as possible to provide low impedance paths and
reduce the effects of glitches on the power supply line. Fast
switching signals like clocks should be shielded with digital
ground to avoid radiating noise to other parts of the board and
should never be run near the analog inputs.
Avoid crossover of digital and analog signals. Traces on opposite
sides of the board should run at right angles to each other. This
reduces the effects of feedthrough through the board. A micro-
strip technique is by far the best but not always possible with a
double sided board. In this technique, the component side of
the board is dedicated to ground plane while signal traces are
placed on the solder side.
REV. B
AD7841
–11–
The AD7841 should have ample supply bypassing located as
close to the package as possible, ideally right up against the
device. Figure 11 shows the recommended capacitor values of
10 µF in parallel with 0.1 µF on each of the supplies. The 10 µF
capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low Effective Series Resistance (ESR) and Effective
Series Inductance (ESI), such as the common ceramic types,
which provide a low impedance path to ground at high frequen-
cies to handle transient currents due to internal logic switching.
10F0.1F10F 0.1F
10F0.1F
V
CC
V
DD
V
SS
AD7841
Figure 11. Recommended Decoupling Scheme for AD7841
Automated Test Equipment
The AD7841 is particularly suited for use in an automated test
environment. Figure 12 shows the AD7841 providing the neces-
sary voltages for the pin driver and the window comparator in a
typical ATE pin electronics configuration. AD588s are used to
provide reference voltages for the AD7841. In the configuration
shown, the AD588s are configured so that the voltage at Pin 1 is
5 V greater than the voltage at Pin 9 and the voltage at Pin 15 is
5 V less than the voltage at Pin 9.
AD7841*
V
REF
(+)AB
V
OUT
B
DUTGND_GH
V
OUT
G
V
OUT
H
GND
DUTGND_AB
*ADDITIONAL PINS OMITTED FOR CLARITY
V
OUT
A
V
REF
(–)AB
V
REF
(+)GH
V
REF
(–)GH
TO TESTER
WINDOW
COMPARATOR
V
OUT
DEVICE
GND
DEVICE
GND
–15V
+15V
PIN
DRIVER
AD588
0.1F
V
OFFSET
+15V –15V
4
6
8
13
216
3
1
15
14
9
AD588
+15V –15V
4
6
9
13
7
216
3
1
15
14
8
10
11
12
1F
DEVICE
GND
10
11
12
7
1F
Figure 12. ATE Application
One of the AD588s is used as a reference for DACs A and B.
These DACs are used to provide high and low levels for the pin
driver. The pin driver may have an associated offset. This can
be nulled by applying an offset voltage to Pin 9 of the AD588.
First, the code 1000...0000 is loaded into the DACA latch
and the pin driver output is set to the DACA output. The
V
OFFSET
voltage is adjusted until 0 V appears between the pin
driver output and DUTGND. This causes both V
REF
(+) and
V
REF
(–) to be offset with respect to GND by an amount equal to
V
OFFSET
. However, the output of the pin driver will vary from
–10 V to +10 V with respect to DUTGND as the DAC input
code varies from 000...000 to 111...111. The V
OFFSET
voltage is also applied to the DUTGND pins. When a clear is
performed on the AD7841, the output of the pin driver will be
0 V with respect to DUTGND.
The other AD588 is used to provide a reference voltage for
DACs G and H. These provide the reference voltages for the
window comparator shown in the diagram. Note that Pin 9 of
this AD588 is connected to Device GND. This causes V
REF
(+)GH
and V
REF
(–)GH to be referenced to Device GND. As DAC G
and DAC H input codes vary from 000...000 to 111...111,
V
OUT
G and V
OUT
H vary from –10 V to +10 V with respect to
Device GND. Device GND is also connected to DUTGND.
When the AD7841 is cleared, V
OUT
G and V
OUT
H are cleared to
0 V with respect to Device GND.
Programmable Reference Generation for the AD7841 in an
ATE Application
The AD7841 is particularly suited for use in an automated test
environment. The reference input for the AD7841 octal 14-bit
DAC requires three differential references for the eight DACs.
Programmable references may be a requirement in some ATE
applications as the offset and gain errors at the output of a DAC
can be adjusted by varying the voltages on the reference pins of
the DAC. To trim offset errors, the DAC is loaded with the
digital code 000...000 and the voltage on the V
REF
(–) pin is
adjusted until the desired negative output voltage is obtained.
To trim out gain errors, first the offset error is trimmed. Then
the DAC is loaded with the code 111...111 and the voltage
on the V
REF
(+) pin is adjusted until the desired full-scale voltage
minus one LSB is obtained.
It is not uncommon in ATE design, to have other circuitry at
the output of the AD7841 that can have offset and gain errors of
up to say ±300 mV. These offset and gain errors can be easily
removed by adjusting the reference voltages of the AD7841.
The AD7841 uses nominal reference values of ±5 V to achieve
an output span of ±10 V. Since the AD7841 has a gain of two
from the reference inputs to the DAC output, adjusting the
reference voltages by ±150 mV will adjust the DAC offset and
gain by ±300 mV.
There are a number of suitable 8- and 10-bit DACs available
that would be suitable to drive the reference inputs of the AD7841,
such as the AD7804, a quad 10-bit digital-to-analog converter
with serial load capabilities. The voltage output from this DAC
is in the form of V
BIAS
±
V
SWING
and rail-to-rail operation is
achievable. The voltage reference for this DAC can be inter-
nally generated or provided externally. This DAC also contains
an 8-bit SUB DAC which can be used to shift the complete trans-
fer function of each DAC around the V
BIAS
point. This can be
used as a fine trim on the output voltage. In this application two
AD7804s are required to provide programmable reference capabil-
ity for all eight DACs. One AD7804 is used to drive the V
REF
(+)
pins and the second package used to drive the V
REF
(–) pins.
Another suitable DAC for providing programmable reference
capability is the AD8803. This is an octal 8-bit TRIMDAC
®
and provides independent control of both the top and bottom
ends of the TRIMDAC. This is helpful in maximizing the reso-
lution of devices with a limited allowable voltage control range.
TRIMDAC is a registered trademark of Analog Devices, Inc.
REV. B
AD7841
–12–
GND
V
DD
8/10-BIT
DAC
GND
V
DD
8/10-BIT
DAC
LOGIC LEVEL
SHIFT
+5V
5V
SCLK
D IN
FSIN/CS
SCLK
D IN
FSIN/CS
0V TO +5V
0V TO 5V
V
REF
(+)AB
A0, A1, A2
V
OUT
A
V
OUT
A
V
OUT
B
V
OUT
B
V
REF
()AB
AD7841*
GND
DATA BUS
ADDR
DECODER
ADDR BUS
SDATA
SCLK
DATA BUS
CONTROLLER
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 13. Programmable Reference Generation for the AD7841
The AD8803 has an output voltage range of GND to V
DD
(0 V
to 5 V). To trim the V
REF
(+) input, the appropriate trim range
on the AD8803 DAC can be set using the V
REFL
and V
REFH
pins
allowing 8 bits of resolution between the two points. This will
allow the V
REF
(+) pin to be adjusted to remove gain errors.
To trim the V
REF
(–) voltage, some method of providing a trim
voltage in the required negative voltage range is required. Neither
the AD7804 or the AD8803 can provide this range in normal
operation as their output range is 0 V to 5 V. There are two
methods of producing this negative voltage. One method is to
provide a positive output voltage and then to level shift that ana-
log voltage to the required negative range. Alternatively these
DACs can be operated with supplies of 0 V and –5 V, with the
V
DD
pin connected to 0 V and the GND pin connected to –5 V.
Now these can be used to provide the negative reference volt-
ages for the V
REF
(–) inputs on the AD7841. However, the digital
signals driving the DACs need to be level-shifted from the 0 V
to +5 V range to the –5 V to 0 V range. Figure 13 shows a
typical application circuit to provide programmable reference
capabilities for the AD7841.
REV. B
AD7841
Rev. B | Page 13 of 13
OUTLINE DIMENSIONS
COM PLI ANT TO JE DE C S TANDARDS MO-112-AA-1
041807-A
14.15
13.90 SQ
13.65
0.45
0.30
2.45
MAX
1.03
0.88
0.73
TOP VIEW
(PINS DOWN)
12
44
1
22
23
34
33
11
0.25 MIN
2.20
2.00
1.80
7°
0°
VIEW A
ROTATE D 90° CCW
0.23
0.11
10.20
10.00 SQ
9.80
0.80 BSC
LEAD PITCH LEAD WIDT H
0.10
COPLANARITY
VIEW A
SEATING
PLANE
1.95 REF
PIN 1
Figure 14. 44-Lead Metric Quad Flat Package [MQFP]
(S-44-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Linearity Error (LSBs) DNL (LSBs) Temperature Range Package Description
Package
Option
AD7841ASZ ±4 −0.9/+2 −40°C to +85°C 44-Lead Metric Quad Flat Package [MQFP] S-44-2
AD7841ASZ-REEL ±4 −0.9/+2 −40°C to +85°C 44-Lead Metric Quad Flat Package [MQFP] S-44-2
AD7841BSZ ±2 ±1 −40°C to +85°C 44-Lead Metric Quad Flat Package [MQFP] S-44-2
AD7841BSZ-REEL ±2 ±1 −40°C to +85°C 44-Lead Metric Quad Flat Package [MQFP] S-44-2
EVAL-AD7841EBZ Evaluation Board
1 Z = RoHS Compliant Part.
REVISION HISTORY
1/11—Rev. A to Rev. B
Changes to Absolute Maximum Ratings, Lead Temperature ...... 4
Updated Outline Dimensions ........................................................ 13
Moved and Changes to Ordering Guide ...................................... 13
©1999-2011 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09645-0-1/11(B)
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Authorized Distributor
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