Data Sheet XE88LC01 Data Acquisition Microcontroller XE88LC01 Sensing Machine 16 + 10 bit Data Acquisition Ultra Low-Power Microcontroller General Description Key product Features The XE88LC01 is an ultra low-power microcontroller unit (MCU) associated with a versatile analog-to-digital converter (ADC) including a programmable offset and gain pre-amplifier (PGA) . * * * * * XE88LC01 is available with on chip Multiple-Time-Programmable (MTP) Flash program memory and ROM. Applications * * * * * Internet connected appliances Portable, battery operated instruments Piezoresistive bridge sensors HVAC control Motor control Low-power, high resolution ZoomingADC Low-voltage low-power controller operation * * * * * * 0.5 to 1000 gain with offset cancellation up to 16 bits ADC up to 13 input multiplexer 2 MIPS at 2.4 V to 5.5 V supply voltage 300 A at 1 MIPS, 2.4 V to 5.5 V supply 22 kByte (8 kInstruction) MTP, 520 Byte RAM RC and crystal oscillators 5 reset, 18 interrupt, 8 event sources 100 years MTP Flash retention at 55C Ordering Information Reference XE88LC01MI000 XE88LC01MI027 XE88LC01MI032 XE88LC01RI000 XE88LC01RI027 Memory type Temperature MTP Flash MTP Flash MTP Flash ROM ROM Cool Solutions for Wireless Connectivity XEMICS SA, email: info@xemics.com web: www.xemics.com -40C to 85C -40C to 85C -40C to 85C -40C to 125C -40C to 125C Package die LQFP44 PLL-44L die LQFP44 Cool Solutions for Wireless Connectivity XEMICS SA, email: info@xemics.com web: www.xemics.com Data Sheet XE88LC01 Data Acquisition Microcontroller 1 Detailed Pin Description 1 4 5 production lot identification 6 7 40 8 38 36 34 32 XEMICS 3 42 XE88LC01MI 2 N9K1444 9920 packaging date 31 30 29 28 27 26 9 24 10 12 Figure 1.1: device type 25 14 16 18 22 20 Pinout of the XE88LC01 in LQFP44 package Pin Table 1.1: 3 Position in TQFP44 Function name 1 2 3 4 5 6 7 8 9 10 11 PA(5) PA(6) PA(7) PC(0) PC(1) PC(2) PC(3) PC(4) PC(5) PC(6) PC(7) 12 PB(0) Second function name Type Input Input Input Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output Input/Output testout Input/Output/Analog 13 PB(1) Input/Output/Analog 14 PB(2) Input/Output/Analog 15 PB(3) SOU Input/Output/Analog 16 PB(4) SCL Input/Output/Analog 17 PB(5) SIN Input/Output/Analog 18 PB(6) Tx Input/Output/Analog 19 PB(7) Rx Input/Output/Analog 20 VPP/TEST Vhigh Special 21 AC_R(3) Analog 22 23 24 25 26 AC_R(2) AC_A(7) AC_A(6) AC_A(5) AC_A(4) Analog Analog Analog Analog Analog Description Input of Port A Input of Port A Input of Port A Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output of Port C Input-Output-Analog of Port B/ Data output for test and MTP programing/ PWM output Input-Output-Analog of Port B/ PWM output Input-Output-Analog of Port B Input-Output-Analog of Port B, Output pin of USRT Input-Output-Analog of Port B/ Clock pin of USRT Input-Output-Analog of Port B/ Data input or input-output pin of USRT Input-Output-Analog of Port B/ Emission pin of UART Input-Output-Analog of Port B/ Reception pin of UART Test mode/High voltage for MTP programing Highest potential node for 2nd reference of ADC Lowest potential node for 2nd reference of ADC ADC input node ADC input node ADC input node ADC input node Pin-out of the XE88LC01 in LQFP44 (see Table "IO pins performances" on page 18 for drive capabilities of the pins) D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller Pin Table 1.1: 4 Position in TQFP44 Function name 27 28 29 30 31 32 33 34 35 36 37 AC_A(3) AC_A(2) AC_A(1) AC_A(0) AC_R(1) AC_R(0) VSS Vbat Vreg RESET Vmult 38 OscIn ck_cr Analog/Input 39 OscOut ptck Analog/Input 40 PA(0) testin Input 41 PA(1) testck Input 42 PA(2) Input 43 PA(3) Input 44 PA(4) Input Second function name Type Analog Analog Analog Analog Analog Analog Power Power Analog Input Analog Description ADC input node ADC input node ADC input node ADC input node Highest potential node for 1st reference of ADC Lowest potential node for 1st reference of ADC Negative power supply, connected to substrate Positive power supply Regulated supply Reset pin (active high) Pad for optional voltage multiplier capacitor Connection to Xtal/ CoolRISC clock for test and MTP programing Connection to Xtal/ Peripheral clock for test and MTP programing Input of Port A/ Data input for test and MTP programing/ Counter A input Input of Port A/ Data clock for test and MTP programing/ Counter B input Input of Port A/ Counter C input/ Counter capture input Input of Port A/ Counter D input/ Counter capture input Input of Port A Pin-out of the XE88LC01 in LQFP44 (see Table "IO pins performances" on page 18 for drive capabilities of the pins) D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 2 Absolute maximum ratings Stresses beyond these listed in this chapter may cause permanent damage to the device. No functional operation is implied at or beyond these conditions. Exposure to these conditions for an extended period may affect the device reliability. Table 2.1: Parameter Valeue VBAT with respect to VSS Input voltage on any input pin Storage temperature Storage temperature for programmed MTP devices -0.3V to 6.0V VSS-0.3V to VBAT+0.3V -55C to 125C -40C to 85C Absolute maximum ratings These devices are ESD sensitive. Although these devices feature proprietary ESD protection structures, permanent damage may occur on devices subjected to high energy electrostatic discharges. Proper ESD precautions have to be taken to avoid performance degradation or loss of functionality. 5 D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 3 Electrical Characteristics All specification are -40C to 85C unless otherwise noted. ROM operates up to 125C. Operation conditions Power supply Operating speed Instruction cycle Current requirement Current requirement MTP Flash memory ROM version MTP version 2.4 V to 5.5 V any instruction CPU running at 1 MIPS CPU running at 32 kHz on Xtal, RC off CPU halt, timer on Xtal, RC off CPU halt, timer on Xtal, RC ready CPU halt, Xtal off timer on RC at 100 kHz CPU halt, ADC 16 bits at 4 kHz CPU halt, ADC 12 bits at 4 kHz, PGA gain 100 CPU at 1 MIPS, ADC 12 bits at 4 kHz CPU at 1 MIPS, ADC 12 bits at 4 kHz, PGA gain 10 CPU at 1 MIPS, ADC 12 bits at 4 kHz, PGA gain 100 CPU at 1 MIPS, ADC 12 bits at 4 kHz, PGA gain 1000 Voltage level detection Prog. voltage Erase time Write/Erase cycles Data retention min typ max Unit Remarks 5.5 5.5 2 V V MHz ns 7 310 uA 1 10 uA 1 1 uA 1 1.7 uA 1 1.4 uA 1 190 uA 4,6 460 uA 4,6 670 uA 3,4,6 790 uA 3,4,6 940 uA 3,4,6 1100 uA 3,4,6 2.4 2.4 0.032 500 10.3 0.2 10 10 100 15 10.8 1 uA V s 100 years years 8 5 85C, 2 55C, 2 Table 3.1: Specifications and current requirement of the XE88LC01 Note: 1) Power supply: 2.4 V - 5.5 V, temperature is 27C. 2) < 10 erase cycles. 3) Output not loaded. 4) Current requirement can be divided by a factor of 2 or 4 by reducing the speed accordingly. 5) More cycles possible during development, with restraint retention 6) Power supply: 3.0V, at 27C; see chapter Power Consumption on page 30 for variation of current with voltage and clock speed variation 7) With 2 MHz clock, all instructions are using exactly 1 clock cycle 8) Longer erase time may degrade retention 6 D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 4 CPU The XE88LC01 CPU is a low power RISC core. It has 16 internal registers for efficient implementation of the C compiler. Its instruction set is made of 35 generic instructions, all coded on 22 bits, with 8 addressing modes. All instructions are executed in one clock cycle, including conditional jumps and 8x8 multiplication. A complete tool suite for development is available from XEMICS, including programmer, Ccompiler, assembler, simulator, linker, all integrated in a modern and efficient graphical user interface. 7 D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 5 Memory organisation The CPU uses a Harvard architecture, so that memory is organised in two separated fields: program memory and data memory. As both memory are separated, the central processing unit can read/write data at the same time it loads an instruction. Peripherals and system control registers are mapped on data memory space. Program memory is fitted onto one page. Data is made of several 256 bytes pages. Program memory 8k instructions MTP or 6k instructions ROM Data address bus Program address bus 0h1FFF / 01hBFF RAM 512 Bytes 0h0080 CPU Peripherals Instruction pipeline 0h0000 CPU registers 22 bits wide Figure 5.1: 0h027F 0h0010 LP RAM 0h0000 8 bits wide Memory organization 5.1 Program memory The program memory is implemented as Multiple Time Programmable (MTP) Flash memory. The power consumption of MTP memory is linear with the access frequency (no significant static current). Size of the MTP Flash memory is 8192 x 22 bits (= 22 kBytes) Size of the ROM memory is 6144 x 22 bits (= 17 kBytes) Table 5.1: 8 block size address MTP ROM 8192 x 22 6144 x 22 H0000 - H1FFF H0000 - H1BFF Program addresses for MTP or ROM memory D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 5.2 Data memory The data memory is implemented as static Random-Access Memory (RAM). The RAM size is 512 x 8 bits plus 8 low power RAM bytes that require very low current when addressed. Programs using the low-power RAM instead of RAM will use even less current. Table 5.2: 6 block size address LP RAM RAM 8x8 512 x 8 H0000 - H0007 H0080 - H027F RAM addresses Registers list Left column include register name and address. Right columns include bit name, access (r: read, r0: always 0 when read, w: write, c: cleared by writing any value, c1: cleared by writing 1), and reset status (0 or 1) and signal. Empty bits are reserved for future use and should not be written, neither should their read value be used for any purpose as it may change without notice. 6.1 Peripherals mapping Table 6.1: 9 block size address LP RAM System control Port A Port B Port C Reserved MTP Event Interrupts control reserved UART Counters Zooming ADC Reserved Reserved Other (VLD) RAM1 RAM2 RAM3 8x8 16x8 8x8 8x8 4x8 4x8 4x8 4x8 8x8 8x8 8x8 8x8 8x8 12x8 8x8 H0000-H0007 H0010-H001F H0020-H0027 H0028-H002F H0030-H0033 H0034-H0037 H0038-H003B H003C-H003F H0040-H0047 H0048-H004F H0050-H0057 H0058-H005F H0060-H0067 H0068-H0073 H0074-H007B 4x8 H007C-H007F 128x8 256x8 128x8 H0080 - H00FF H0100 - H01FF H0200 - H027F Page Page 0 Page 1 Page 2 Peripherals addresses D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 6.2 Resets The reset source name is simplified in the following registers description. Name mapping is in the next table. reset source name in this document resetsystem resetSynch resetPOR resetCold resetPad resetPconf resetSleep Table 6.2: 6.3 global cold pconf sleep Reset signal name mapping Low power RAM Low power RAM is a small additionnal RAM area with extremely low power requirement. Name Address 7 6 5 4 3 2 1 0 h0000 rw rw rw rw rw rw rw rw h0001 rw rw rw rw rw rw rw rw h0002 rw rw rw rw rw rw rw rw h0003 rw rw rw rw rw rw rw rw h0004 rw rw rw rw rw rw rw rw h0005 rw rw rw rw rw rw rw rw h0006 rw rw rw rw rw rw rw rw h0007 rw rw rw rw rw rw rw rw Table 6.3: 10 Low power RAM D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 6.4 System, oscillators, prescaler and watchdog Name Address RegSysCtrl h0010, type 1 RegSysReset h0011, type 1 RegSysClock h0012, type 1 7 SleepEn 6 5 EnRes-PConf EnBus-Error 4 3 2 1 ResPad-Deb rc, 0 cold ResPad rc, 0 cold EnResWD rw, 0 por rw, 0 cold rw, 0 cold rw, 0 cold Sleep w, 0 cold ResPor r, 0 ResBus-Error rc, 0 cold ResWD rc, 0 cold ResPortA rc, 0 cold CpuSel ExtClk EnExtClk BiasRC ColdXtal ColdRC EnableXtal EnableRC rw, 0 sleep r, 0 cold rw, 0 cold rw, 1 cold r, 1 sleep r, 1 sleep rw, 0 sleep rw, 1 sleep RCOnPA0 DebFast OutputCkXtal OutputCkCPU rw, 0 sleep rw, 0 sleep rw, 0 sleep rw, 0 sleep RegSysMisc h0013, type 1 RegSysWD WatchDog(3) WatchDog(2) WatchDog(1) WatchDog(0) special special special special h0014 ResPre ClearLowPrescal (*) w, 0 cold RegSysPre0 h0015 RegSysRCTrim1 h001B RegSysRCTrim2 h001C Table 6.4: 6.5 0 RCFreqRange RCFreqCoarse(3) RCFreqCoarse(2) RCFreqCoarse(1) RCFreqCoarse(0) rw, 0 cold rw, 0 cold rw, 0 cold rw, 0 cold rw, 0 cold RCFreqFine(5) RCFreqFine(4) RCFreqFine(3) RCFreqFine(2) RCFreqFine(1) RCFreqFine(0) rw, 1 cold rw, 0 cold rw, 0 cold rw, 0 cold rw, 0 cold rw, 0 cold System control registers PortA Name Address 7 6 5 4 3 2 1 0 RegPAIn PAIn(7) RegPAIn(6) PAIn(5) PAIn(4) PAIn(3) PAIn(2) PAIn(1) PAIn(0) RegPADebounce r PADeb(7) r PADeb(6) r PADeb(5) r PADeb(4) r PADeb(3) r PADeb(2) r PADeb(1) r PADeb(0) rw, 0 pconf PAEdge(7) rw, 0 pconf PAEdge(6) rw, 0 pconf PAEdge(5) rw, 0 pconf PAEdge(4) rw, 0 pconf PAEdge(3) rw, 0 pconf PAEdge(2) rw, 0 pconf PAEdge(1) rw, 0 pconf PAEdge(0) h0020 h0021 RegPAEdge h0022 RegPAPullup h0023, type 1 RegPARes0 h0024 RegPARes1 h0025 Table 6.5: 11 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global PAPullUp(7) PAPullUp(6) PAPullUp(5) PAPullUp(4) PAPullUp(3) PAPullUp(2) PAPullUp(1) PAPullUp(0) rw, 0 pconf PARes0(7) rw, 0 pconf PARes0(6) rw, 0 pconf PARes0(5) rw, 0 pconf PARes0(4) rw, 0 pconf PARes0(3) rw, 0 pconf PARes0(2) rw, 0 pconf PARes0(1) rw, 0 pconf PARes0(0) rw, 0 global PARes1(7) rw, 0 global PARes1(6) rw, 0 global PARes1(5) rw, 0 global PARes1(4) rw, 0 global PARes1(3) rw, 0 global PARes1(2) rw, 0 global PARes1(1) rw, 0 global PARes1(0) rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global Port A registers D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 6.6 PortB Name Address RegPBOut h0028 RegPBIn h0029 RegPBDir h002A RegPBOpen h002B RegPBPullup h002C 7 6 5 4 1 0 PBOut(7) PBOut(6) PBOut(5) PBOut(4) PBOut(3) PBOut(2) PBOut(1) PBOut(0) rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf PBIn(7) PBIn(6) PBIn(5) PBIn(4) PBIn(3) PBIn(2) PBIn(1) PBIn(0) r r r r r r r r PBDir(7) PBDir(6) PBDir(5) PBDir(4) PBDir(3) PBDir(2) PBDir(1) PBDir(0) rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf PBOpen(7) PBOpen(6) PBOpen(5) PBOpen(4) PBOpen(3) PBOpen(2) PBOpen(1) PBOpen(0) rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf PBPullUp(7) PBPullUp(6) PBPullUp(5) PBPullUp(4) PBPullUp(3) PBPullUp(2) PBPullUp(1) PBPullUp(0) rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf h002D 6.7 2 rw, 0 pconf RegPBAna Table 6.6: 3 rw, 0 pconf rw, 0 pconf rw, 0 pconf PBAna(3) PBAna(2) PBAna(1) rw, 0 pconf PBAna(0) rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf Port B registers PortC Name Address RegPCOut h0030 RegPCIn h0031 RegPCDir h0032 Table 6.7: 6.8 7 6 5 4 3 2 1 0 PCOut(7) rw, 0 pconf PCOut(6) rw, 0 pconf PCOut(5) rw, 0 pconf PCOut(4) rw, 0 pconf PCOut(3) rw, 0 pconf PCOut(2) rw, 0 pconf PCOut(1) rw, 0 pconf PCOut(0) rw, 0 pconf PCIn(7) PCIn(6) PCIn(5) PCIn(4) PCIn(3) PCIn(2) PCIn(1) PCIn(0) r r r r r r r r PCDir(7) PCDir(6) PCDir) PCDir(4) PCDir(3) PCDir(2) PCDir(1) PCDir(0) rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf Port C registers MTP Name Address 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw special special special special special special special special special special special special special special special special RegEEP h0038 RegEEP1 h0039 RegEEP2 h003A RegEEP3 h003B Table 6.8: 12 MTP control registers D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 6.9 Events Name Address RegEvn h003C RegEvnEn h003D RegEvnPriority h003E 7 6 5 4 3 2 EvnCntA EvnCntC EvnPre1 EvnPA(1) EvnCntB EvnCntD EvnPre2 EvnPA(0) rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global EvnEnCntA rw, 0 global EvnEnCntC rw, 0 global EvnEnPre1 rw, 0 global EvnEnPA(1) rw, 0 global EvnEnCntB rw, 0 global EvnEnCntD rw, 0 global EvnEnPre2 rw, 0 global EvnEnPA(0) rw, 0 global EvnPriority(7) EvnPriority(6) EvnPriority(5) EvnPriority(4) EvnPriority(3) EvnPriority(2) EvnPriority(1) EvnPriority(0) r,1 global r,1 global r,1 global r,1 global r,1 global r,1 global h003F 6.10 r,1 global r,1 global EvnHigh r, 0 global EvnLow r, 0 global 1 0 IrqUartTx rc1, 0 global IrqUartRx rc1, 0 global Events control registers Interrupts Name Address RegIrqHig h0040 7 6 IrqAc rc1, 0 global IrqPre1 rc1, 0 global RegIrqMid h0041 RegIrqLow h0042 RegIrqEnHig h0043 RegIrqEnLow RegIrqPriority h0046 4 3 IrqCntA rc1, 0 global IrqCntC rc1, 0 global IrqPA(5) IrqPA(4) IrqPre2 IrqVld IrqPA(1) IrqPA(0) rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global IrqPA(6) IrqCntB IrqCntD IrqPA(3) IrqPA(2) rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global IrqEnAc IrqEnPre1 IrqEnCntA IrqEnCntC IrqEnUartTx IrqEnUartRx rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global IrqEnPA(5) IrqEnPA(4) IrqEnPre2 IrqEnVld IrqEnPA(1) IrqEnPA(0) rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global IrqEnPA(7) IrqEnPA(6) IrqEnCntB IrqEnCntD IrqEnPA(3) IrqEnPA(2) rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global IrqPriority(7) IrqPriority(6) IrqPriority(5) IrqPriority(4) IrqPriority(3) IrqPriority(2) IrqPriority(1) IrqPriority(0) r, 1 global r, 1 global r, 1 global r, 1 global r, 1 global r, 1 global r, 1 global r, 1 global IrqHig IrqMid IrqLow r, 0 global r, 0 global r, 0 global 2 1 0 RegIrqIrq h0047 Table 6.10: 6.11 2 IrqPA(7) h0044 h0045 5 rc1, 0 global RegIrqEnMid Interrupts control registers USRT Name Address 7 6 5 4 3 RegUsrtSin UsrtSin h0048 rw, 1 global UsrtScl RegUsrtScl h0049 rw, 1 global RegUsrtCtrl UsrtWaitS0 h004A r, 0 global RegUsrtData UsrtEnWaitS0 UsrtEnable rw, 0 global rw, 0 global r RegUsrtEdgeScl UsrtEdgeScl h004E Table 6.11: UsrtEnWaitCond1 rw, 0 global UsrtData h004D 13 0 rc1, 0 global RegEvnEvn Table 6.9: 1 r, 0 global USRT control registers D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 6.12 UART Name Address RegUartCtrl h0050 7 RegUartTx h0052 5 4 3 2 UartEnRx UartEnTx UartXRx UartXTx UartBR(2) UartBR(1) UartBR(0) rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 1 global rw, 0 global rw, 1 global SelXtal UartWakeup UartRCSel(2) UartRCSel(1) UartRCSel(0) UartPM UartPE UartWL rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 1 global UartTx(7) UartTx(6) UartTx(5) UartTx(4) UartTx(3) UartTx(2) UartTx(1) UartTx(0) rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global UartTxBusy UartTxFull RegUartTxSta UartRx(7) UartRx(6) r r h0054 RegUartRxSta UartRx(5) Table 6.12: UartRx(3) UartRx(2) r, 0 global UartRx(1) UartRx(0) r r r r r r UartRxPErr UartRxFErr UartRxOErr UartRxBusy UartRxFull r r r c r r UART control registers Counters Name Address 7 6 5 4 3 2 1 0 RegCntA CounterA(7) rw CounterA(6) rw CounterA(5) rw CounterA(4) rw CounterA(3) rw CounterA(2) rw CounterA(1) rw CounterA(0) rw RegCntB CounterB(7) CounterB(6) CounterB(5) CounterB(4) CounterB(3) CounterB(2) CounterB(1) CounterB(0) rw rw rw rw rw rw rw rw RegCntC CounterC(7) CounterC(6) CounterC(5) CounterC(4) CounterC(3) CounterC(2) CounterC(1) CounterC(0) rw rw rw rw rw rw rw rw RegCntD CounterD(7) CounterD(6) CounterD(5) CounterD(4) CounterD(3) CounterD(2) CounterD(1) CounterD(0) rw rw rw rw rw rw rw rw RegCntCtrlCk CntDSel(1) CntDSel(0) CntCSel(1) CntCSel(0) CntBSel(1) CntBSel(0) CntASel(1) CntASel(0) rw rw rw rw h0058 h0059 h005A h005B h005C RegCntConfig1 h005D RegCntConfig2 h005E CntDDownUp CntCDownUp CntBDownUp CntADownUp rw rw rw rw CapSel(1) CapSel(0) CapFunc(1) CapFunc(0) rw, 0 global rw, 0 global rw, 0 global rw, 0 global RegCntOn h005F Table 6.13: 14 UartRx(4) r, 0 global UartRxSErr h0055 6.13 0 UartEcho h0053 RegUartRx 1 rw, 0 global RegUartCmd h0051 6 rw rw rw rw CascadeCD CascadeAB CntPWM1 CntPWM0 rw rw rw, 0 global rw, 0 global PWM1Size(1) PWM1Size(0) PWM0Size(1) PWM0Size(0) rw rw rw rw CntDEnable CntCEnable CntBEnable CntAEnable rw, 0 global rw, 0 global rw, 0 global rw, 0 global Counters control registers D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 6.14 Acquisition chain Name Address RegAcOutLsb h0060 RegAcOutMsb h0061 RegAcCfg0 h0062 RegAcCfg1 h0063 7 6 5 4 3 2 1 0 AdcOutL(7) AdcOutL(6) AdcOutL(5) AdcOutL(4) AdcOutL(3) AdcOutL(2) AdcOutL(1) AdcOutL(0) r r r r r r r r AdcOutM(7) AdcOutM(6) AdcOutM(5) AdcOutM(4) AdcOutM(3) AdcOutM(2) AdcOutM(1) AdcOutM(0) r r r r r r r r Start NelConv(1) NelConv(0) OSR(2) OSR(1) OSR(0) Cont r0w, 0 global rw, 0 global rw, 0 global rw, 1 global RegAcCfg2 h0064 RegAcCfg3 h0065 Table 6.14: 6.15 rw, 1 global rw, 0 global Enable(3) Enable(2) Enable(1) Enable(0) rw, 1 global rw, 1 global rw, 1 global rw, 0 global rw, 0 global rw, 0 global rw, 1 global Fin(1) Fin(0) Pga2Gain(1) Pga2Gain(0) Pga2Off(3) Pga2Off(2) Pga2Off(1) Pga2Off(0) rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global Pga1Gain rw, 0 global Pga3Gain(6) rw, 0 global Pga3Gain(5) rw, 0 global Pga3Gain(4) rw, 0 global Pga3Gain(3) rw, 1 global Pga3Gain(2) rw, 1 global Pga3Gain(1) rw, 0 global Pga3Gain(0) rw, 0 global RegAcCfg4 RegAcCfg5 rw, 0 global IbAmpPga(0) rw, 0 global h0066 h0067 rw, 1 global IbAmpPga(1) IbAmpADC(1) IbAmpAdc(0) Pga3Off(6) Pga3Off(5) Pga3Off(4) Pga3Off(3) Pga3Off(2) Pga3Off(1) Pga3Off(0) rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global Busy Def AMux(4) AMux(3) AMux(2) AMux(1) AMux(0) VMux r, 0 global wr0 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global 4 3 2 1 0 Enable Fin(1) Fin(0) VldMult rw, 0 global VldTune(2) rw, 0 global VldTune(1) rw, 0 global VldTune(0) rw, 0 cold VldIrq rw, 0 cold VldValid rw, 0 cold VldEn r, 0 global r, 0 global rw, 0 global Acquisition chain control registers Vmult and Vld registers Name Address 7 6 5 RegVmultCfg0 h007C RegVldCtrl h007E rw, 0 cold RegVldStat h007F Table 6.15: 15 Vmult and Vld control registers D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 7 Peripherals The XE88LC01 includes usual microcontroller peripherals and some other blocks more specific to low-voltage or mixed-signal operation. They are 3 parallel ports, one input port (A), one IO and analog port (B) with analog switching capabilities and one general purpose IO port (C). A watchdog is available, connected to a prescaler. Four 8-bit counters, with capture, PWM and chaining capabilities are available. The UART can handle transmission speeds as high as 115kbaud. Low-power low-voltage blocks include a voltage level detector, two oscillators (one internal 0.1-2 MHz RC oscillator and a 32 kHz crystal oscillator) and a specific regulation scheme that largely uncouples current requirement from external power supply (usual CMOS ASICs require much more current at 5.5 V than they need at 2.4 V. This is not the case for the XE88LC01). Analog blocks (ZoomingADC (acquisition path)) are defined below. All these blocks operate on 2.4 - 5.5 V power supply range. 7.1 Counters * * * * * 4 8-bit counters Daisy chain on 16 bits PWM on 8-16 bits Capture - compare on 16 bits Events and interrupts generation * Interrupt generated with 1 second period for ultra low power hibernation mode * 2 seconds watchdog * * * * * * * * * * full duplex operation with buffered receiver and transmitter. Internal baudrate generator with programmable baudrate (300 - 115000 bauds). 7 or 8 bits word length. even, odd, or no-parity bit generation and detection 1 stop bit error receive detection : Start, Parity, Frame and Overrun receiver echo mode 2 interrupts (receive full and transmit empty) enable receive and/or transmit invert pad Rx and/or Tx 7.2 Prescaler 7.3 Watchdog 7.4 UART 16 D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 7.5 Xtal clock The Xtal Oscillator operates with an external crystal of 32'768 Hz. symbol description f_clk32k st_x32k duty_clk32k nominal frequency oscillator start-up time duty cycle on the digital output relative frequency deviation from nominal, for a crystal with CL=8.2 pF and temperature between -40 and +85C fstab_1 min typ 30 32768 1 50 -100 max unit comments 2 70 Hz s % for full precision +300 ppm not included: crystal frequency tolerance and aging crystal frequency - temperature dependence Table 7.1: Xtal oscillator specifications. Note: Board layout recommendations for safer crystal oscillation and lower current consumption: Keep lines xtal_in and xtal_out short and insert a VSS line between them. Connect package of the crystal to VSS. No noisy or digital lines near xtal_in and xtal_out. Insert guards at VSS where needed. 7.6 RC oscillator The RC Oscillator is always turned on at power-on reset and can be turned off after the optional Xtal oscillator has been started. The RC oscillator has two frequency ranges: sub-MHz (100KHz to 1MHz) and above-MHz (1MHz to max MCU frequency). Inside a range, the frequency can be tuned by software for coarse and fine adjustment. Note: No external component is required for the RC oscillator. The RC oscillator can be in 3 modes. In mode 1(RC on), the RC oscillator and its bias are on. In mode 2 (RC ready), the RC oscillator is off and the bias is on. In mode 3 (RC off), the RC oscillator and the bias are off. RC ready mode is a compromise between power consumption and start-up time. Figure 7.1: 17 RC frequencies programming example for low range (typical values) D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller symbol description min typ max unit Fst frequency at start-up 50 80 110 kHz range range selection 1 10 multiplies Fst mult[3:0] coarse tuning range 1 16 4 bits, multiplies Fst * range fine tuning range 0.65 tune[5:0] 1.4 Tst start-up time 30 Ost overshoot at start-up Twu wakeup time overshoot at wakeup jit jitter rms Table 7.2: 6 bits, multiplies Fst * range * mult 1.5 fine tuning step Owu comments 3 2 % 50 s bias current is off (RC off) 50 % bias current is off (RC off) 5 s bias current is on (RC ready) 50 % bias current is on (RC ready) o 2 /oo RC specifications 7.7 Parallel IO ports * * * sym 8 bit input port A with interrupt, reset and event generation. 8 bit input-output-analog port B with analog switching capabilities. 8 bit input-output port C. description condition Port A: low threshold limit Port A: high threshold limit output drop when sinking 1 mA output drop when sourcing 1 mA Port A: low threshold limit Port A: high threshold limit output drop when sinking 1 mA output drop when sinking 8 mA output drop when sourcing 1 mA output drop when sourcing 8 mA Port A: low threshold limit Port A: high threshold limit output drop when sinking 1 mA output drop when sinking 8 mA output drop when sourcing 1 mA output drop when sourcing 8 mA pull-up, pull-down resistor Table 7.3: 18 min typ Vbat = 1.2 V max 0.4 0.4 1 1.5 Vbat = 2.4 V 0.4 0.4 2 3 Vbat = 5.0 V 0.4 50 0.4 150 unit Comments V V V V V V V V V V V V V V V V kohm IO pins performances D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 7.8 Voltage level detector * * Can be switched off, on or simultaneously with CPU activities Generates an interrupt if power supply is below a pre-determined level The Voltage Level Detector monitors the state of the system battery. It returns a logical high value (an interrupt) in the status register if the supplied voltage drops below the user defined level. symbol description min typ max unit Note 1 Vth Threshold voltage comments trimming values: 1.53 1.44 1.36 1.29 1.22 1.16 1.11 1.06 3.06 2.88 2.72 2.57 2.44 2.33 2.22 2.13 V VldRange 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 VldTune 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 TEOM duration of measurement 2.0 2.5 ms Note 2 TPW Minimum pulse width detected 875 1350 us Note 2 Table 7.4: Voltage level detector operation Note: 1) Absolute precision of the threshold voltage is 10%. 2) This timing is respected in case the internal RC or crystal oscillators are selected. Refer to the clock block documentation in case the external clock is used. 19 D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 8 ZoomingADC The fully differential acquisition chain is formed of a programmable gain (0.5 - 1000) and offset amplifier and a programmable speed and resolution ADC (example: 12 bits at 4 kHz, 16 bits at 1 kHz). It can handle inputs with very low full scale signal and large offsets. reference selection AC_R(0) AC_R(1) AC_R(2) AC_R(3) AC_A(0) AC_A(1) AC_A(2) AC_A(3) AC_A(4) AC_A(5) AC_A(6) AC_A(7) ADC gain1 gain2 offset2 mode gain3 offset3 output code input selection Figure 8.1: Acquisition channel block diagram Input selection is made from 1 of 4 differential pairs or 1 of seven single signal versus AC_A(0). Reference is chosen from the 2 differential references. Acquisition path offset can be suppressed by inverting input polarity. The gain of each amplifier is programmed individually. Each amplifier is powered on and off on command to minimize the total current requirement. All blocks can be set to low frequency operation and lower their current requirement by a factor 2 or 4. The ADC can run continuously (end of conversion signalled by an interrupt, event or by pooling the ready bit), or it can be started on request. 8.1 PGA 1 symbol description min GD1 GD_preci GD_TC fs Zin1 Zin1p PGA1 Signal Gain Precision on gain settings Temperature dependency of gain settings input sampling frequency Input impedance Input impedance for gain 1 1 -5 -5 VN1 Input referred noise typ 150 1500 28.6 max unit Comments 10 +5 +5 512 % ppm/C kHz k k nV/ sqrt(Hz) GD1 = 1 or 10 1 1 2 Table 8.1: PGA1 Performances Note: 1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs = 128 kHz. 2) Input referred rms noise is 205 uV per input sample with gain = 1, 20.5 uV with gain = 10. This corresponds to 28.6 nV/sqrt(Hz) for fs = 512 kHz and gain = 10. 20 D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 8.2 PGA2 sym description min GD2 GDoff2 GDoff2_step GD_preci GD_TC fs Zin2 PGA2 Signal Gain PGA2 Offset Gain GDoff2(code+1) - GDoff2(code) Precision on gain settings Temperature dependency of gain settings Input sampling frequency Input impedance 1 -1 0.18 -5 -5 VN2 Input referred noise typ 0.2 max unit Comments 10 1 0.22 +5 +5 512 FS % ppm/C kHz k nV/ sqrt(Hz) GD2 = 1, 2, 5 or 10 150 47.5 valid for GD2 and GDoff2 1 2 Table 8.2: PGA2 Performances Note: 1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs = 128 kHz. 2) Input referred rms noise is 340 uV per input sample with gain = 1, 34 uV with gain = 10.This corresponds to 47.5 nV/sqrt(Hz) for fs = 512 kHz and gain = 10. 8.3 PGA3 sym description min GD3 GDoff3 GD3_step GDoff3_step GD_preci GD_TC fs PGA3 Signal Gain PGA3 Offset Gain GD3(code+1) - GD3(code) GDoff2(code+1) - GDoff2(code) Precision on gain settings Temperature dependency of gain settings Input sampling frequency 0 -5 0.075 0.075 -5 -5 Zin3 Input impedance 150 VN3 Input referred noise typ 0.08 0.08 51.0 max unit 10 5 0.085 0.085 +5 +5 512 FS % ppm/C kHz Comments valid for GD3 and GDoff3 k 1 nV/ sqrt(Hz) 2 Table 8.3: PGA3 Performances Note: 1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequency for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs = 128 kHz. 2) Input referred rms noise is 365 uV per imput sample with gain = 1, 36.5 uV with gain = 10. This corresponds to 51.0 nV/sqrt(Hz) for fs = 512 kHz. 21 D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 8.4 Analog to digital converter (ADC) The whole analog to digital conversion sequence is basically made of an initialisation, a set of Nelconv elementary incremental conversions and finally a termination phase(NumCONV is set by 2 bits on RegACCfg0). The result is a mean of the results of the elementary conversions. 1 2 input sample smax 1 2 smax START 1st elementary conversion 2nd elementary conversion conversion index 1 2 Figure 8.2: 1 2 elementary conversion smax elementary conversion NumConv-1 END NumConv Conversion sequence. smax is the oversampling rate. Note: NumCONV elementary conversions are performed, each elementary conversion being made of smax input samples. NumCONV = 2NELCONV smax = 8*2OSR During the elementary conversions, the operation of the converter is the same as in a sigma delta modulator. During one conversion sequence, the elementary conversions are alternatively performed with direct and crossed PGA-ADC differential inputs, so that when two elementary conversions or more are performed, the offset of the converter is cancelled. Some additional clock cycles (NINIT+NEND) clock cycles are used to initiate and terminate the conversion properly. 8.5 ADC performances sym description min VINR Resol NResol DNL INL fs smax Input range Resolution Numerical resolution Differential non-linearity Integral non-linearity sampling frequency Oversampling Ratio Number of elementary conversions in incremental mode Number of periods for incremental conversion initialization Number of periods for incremental conversion termination -0.5 6 NUMCONV Ninit Nend typ max unit Comments -0.1 -3 10 8 0.5 16 16 0.1 2 512 1024 Vref bits bits LSB LSB kHz - 3 LSB at 16 bits 2, LSB at 16 bits 1 8 - 1 5 - 5 - 1 Table 8.4: ADC Performances Note: Note: 1) Only powers of 2 2) INL is defined as the deviation of the DC transfer curve from the best fit straight line. This specifi- 22 D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller cation holds over 100% of the full scale. 3) NResol is the maximal readable resolution of the digital filter. 8.6 resolution conditions input frequency. convertion time. output frequency. oversampling per convertion = 8 1 conversion (no offset rejection) oversampling per convertion = 16 1 conversion (no offset rejection) oversampling per convertion = 64 1 conversion (no offset rejection) oversampling per convertion = 64 2 convertions (offset rejection) oversampling per convertion = 256 1 convertion (no offset rejection) oversampling per convertion = 256 2 convertions (offset rejection) oversampling per convertion = 1024 8 convertions (offset rejection) 6 8 12 13 16 16 16 Table 8.5: 512 kHz 40 us 25 kHz 512 kHz 50 us 20 kHz 512 kHz 150 us 6.7 kHz 512 kHz 275 us 3.6 kHz 512 kHz 500 us 2 kHz 512 kHz 1 ms 1 kHz 512 kHz 16.5 ms 60 Hz ADC performances examples 8.7 Linearity To quantify linearity errors, Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) were measured for the ADC alone and for gains of 1, 5, 10, 20, 100, 1000, and a resolution of 12 bits and 16 bits. INL is defined as the deviation (in LSB) of the DC transfer curve of each individual code from the best-fit straight line. This specification holds over the full scale. DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code transitions for successive codes. INL and DNL are specified after gain and offset errors have been removed. 8.8 Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) for 12-bit resolution 12 bits - ADC converter (No PGA; ADC only) (version v5a) 12 bits - ADC converter (No PGA; ADC only) (version v5a) Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples 0.50 Differential Non-Linearity (DNL) [LSB] Integral Non-Linearity (INL) [LSB] 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 0 500 1000 1500 2000 2500 VIN [mV] 23 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 -1.0 Figure 8.3: 0.40 0 500 1000 1500 2000 2500 VIN [mV] NO GAIN (ONLY ADC), 12 bit ADC setting D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 12 bits - ADC converter (GDtot = 1) (version v5a) 12 bits - ADC converter (GDtot = 1) (version v5a) Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples 0.50 1.5 1.0 0.5 INL 0.0 -0.5 -1.0 -1.5 Differential Non-Linearity (DNL) [LSB] Integral Non-Linearity (INL) [LSB] 2.0 -2.0 0.40 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 0 500 1000 1500 2000 2500 0 500 1000 VIN [mV] Figure 8.4: 12 bits - ADC converter (GDtot = 5) (version v5a) 12 bits - ADC c onve rte r (GDtot = 5) (ve rsion v5a ) Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples Differential Non-Linearity (DNL) [LSB] Integral Non-Linearity (INL) [LSB] 0.5 0.0 -0.5 -1.0 0.40 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 0 100 200 300 400 0 500 100 200 Figure 8.5: 300 400 500 VIN [mV] VIN [mV] GAIN=5, 12 bit ADC setting 12 bits - ADC converter (GDtot = 10) (version v5a) 12 bits - ADC converter (GDtot = 10) (version v5a) Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples 0.50 Differential Non-Linearity (DNL) [LSB] 2.0 Integral Non-Linearity (INL) [LSB] 2500 0.50 -1.5 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 0.40 0.30 0.20 0.10 0.00 -0.10 -0.20 -0.30 -0.40 -0.50 -2.0 0 50 100 150 200 250 VIN [mV] 24 2000 GAIN=1, 12 bit ADC setting 1.0 Figure 8.6: 1500 VIN [mV] 0 50 100 150 200 250 VIN [mV] GAIN=10, 12 bit ADC setting D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 12 bits - ADC converter (GDtot = 20) (version v5a) 12 bits - ADC converter (GDtot = 20) (version v5a) Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples 0.60 Differential Non-Linearity (DNL) [LSB] Integral Non-Linearity (INL) [LSB] 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 0.40 0.20 0.00 -0.20 -0.40 -0.60 -0.80 -0.8 0 20 40 60 80 100 0 120 20 40 60 Figure 8.7: Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples 1.00 Differential Non-Linearity (DNL) [LSB] Integral Non-Linearity (INL) [LSB] 4.0 3.0 2.0 1.0 0.0 -1.0 -2.0 -3.0 -4.0 0.50 0.00 -0.50 -1.00 -1.50 0 5 10 15 20 25 0 5 10 VIN [mV] Figure 8.8: 15 20 25 VIN [mV] GAIN=100, 12 bit ADC setting 12 bits - ADC converter (GDtot = 1000) (version v5a) 12 bits - ADC converter (GDtot = 1000) (version v5a) Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples 6.0 2.0 Differential Non-Linearity (DNL) [LSB] Integral Non-Linearity (INL) [LSB] 120 12 bits - ADC converter (GDtot = 100) (version v5a) Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples 4.0 2.0 0.0 -2.0 -4.0 -6.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 5 10 15 20 25 10*VIN [mV] 25 100 GAIN=20, 12 bit ADC setting 12 bits - ADC converter (GDtot = 100) (version v5a) Figure 8.9: 80 VIN [mV] VIN [mV] 0 5 10 15 20 25 10*V IN [mV] GAIN=1000, 12 bit ADC setting D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 8.9 Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) for 16-bit resolution 16 bits - ADC converter (No PGA; ADC only) (ve rsion v5a ) 16 bits - ADC c onve rter (No PGA; ADC only) (ve rsion v5a ) Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples 0.10 Differential Non-Linearity (DNL) [LSB] Integral Non-Linearity (INL) [LSB] 3 2 1 0 -1 -2 -3 0.05 0.00 -0.05 -0.10 -0.15 0 500 1000 1500 2000 2500 0 500 VIN [mV] 16 bits - ADC converter (GDtot = 1) (version v5a) 16 bits - ADC converter (GDtot = 1) (version v5a) Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples 0.10 20.0 0.08 15.0 10.0 5.0 0.0 -5.0 -10.0 -15.0 -20.0 -25.0 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 500 1000 1500 2000 -0.08 2500 0 500 1000 VIN [mV] Figure 8.11: 1500 2000 2500 VIN [mV] GAIN=1, 16 bit ADC setting 16 bits - ADC converter (GDtot = 5) (version v5a) 16 bits - ADC converter (GDtot = 5) (version v5a) Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples 0.15 Differential Non-Linearity (DNL) [LSB] 10.0 Integral Non-Linearity (INL) [LSB] 2500 -0.10 0 5.0 0.0 -5.0 -10.0 -15.0 -20.0 0.10 0.05 0.00 -0.05 -0.10 -0.15 0 100 200 300 400 500 VIN [mV] 26 2000 NO GAIN (ONLY ADC), 16 bit ADC setting 25.0 Figure 8.12: 1500 VIN [mV] Differential Non-Linearity (DNL) [LSB] Integral Non-Linearity (INL) [LSB] Figure 8.10: 1000 0 100 200 300 400 500 VIN [mV] GAIN=5, 16 bit ADC setting D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 16 bits - ADC converter (GDtot = 10) (version v5a) 16 bits - ADC converter (GDtot = 10) (version v5a) Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples 0.25 Differential Non-Linearity (DNL) [LSB] Integral Non-Linearity (INL) [LSB] 30 20 10 0 -10 -20 -30 0 50 100 150 200 0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 250 0 VIN [mV] Figure 8.13: 250 Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples 0.6 Differential Non-Linearity (DNL) [LSB] 8 6 4 2 0 -2 -4 -6 -8 0.4 0.2 0.0 -0.2 -0.4 -0.6 -10 0 20 40 60 80 100 0 120 20 40 Figure 8.14: 60 80 100 120 VIN [mV] VIN [mV] GAIN=20, 16 bit ADC setting 16 bits - ADC converter (GDtot = 100) (version v5a) 16 bits - ADC converter (GDtot = 100) (version v5a) Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples 40 0.8 Differential Non-Linearity (DNL) [LSB] Integral Non-Linearity (INL) [LSB] 200 16 bits - ADC converter (GDtot = 20) (version v5a) 10 30 20 10 0 -10 -20 -30 -40 0 5 10 15 20 25 VIN [mV] 27 150 GAIN=10, 16 bit ADC setting Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples Figure 8.15: 100 VIN [mV] 16 bits - ADC converter (GDtot = 20) (version v5a) Integral Non-Linearity (INL) [LSB] 50 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 5 10 15 20 25 VIN [mV] GAIN=100, 16 bit ADC setting D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 16 bits - ADC converter (GDtot = 1000) (version v5a) 16 bits - ADC converter (GDtot = 1000) (version v5a) Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2 fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V N sweep = 1201; average on 4 samples 2.0 Differential Non-Linearity (DNL) [LSB] Integral Non-Linearity (INL) [LSB] 80 60 40 20 0 -20 -40 -60 -80 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 5 10 15 20 25 0 10*VIN [mV] Figure 8.16: 5 10 15 20 25 10*VIN [mV] GAIN=1000, 16 bit ADC setting The gain settings of each PGA stage for the plots of above figure are those of the table below. Table 8.6: Table 8.7: PGA Gain GDTOT (V/V) PGA1 Gain GD1 (V/V) PGA2 Gain GD2 (V/V) PGA3 Gain GD3 (V/V) 1 5 10 20 100 1000 1 1 10 10 10 10 bypassed 5 bypassed 2 10 10 bypassed bypassed bypassed bypassed bypassed 10 Individual PGA gains for INL & DNL measurements 8.10 Noise Ideally, a constant input voltage VIN should result in a constant output code. However, because of circuit noise, the output code may vary for a fixed input voltage. The figure shows the distribution for the ADC alone (PGA1, 2, and 3 bypassed) and of several configurations of the PGAs. Quantization noise is dominant in this case of ADC only, and, thus, the ADC thermal noise is negligible. One has to considere two points when computing final noise of the acquisition chain: * this is a type of amplifier (switched-cap with constant capacitive load) that maintains its output noise when changing the gain. Therefore input refered noise is lowered when the gain of an amplifier is increased. * the ADC is oversampled, and the number of samples taken lowers the thermal noise Total input refered noise can be computed using the following equation: 2 2 2 V n, out1 Vn, out2 V n, out3 ---------------- -------------------------------- ----------------------------------------------------- gain1 + gain1 gain2 + gain1 gain2 gain3 2 ----------------------------------------------------------------------------------------------------------------------------------------------V n, in = numconv smax 28 D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller Where Vn,outx is the rms output noise of amplifier x. Amplifier Symbol Typical output noise per over-sample Unit PGA1 Vn,out1 205 uVrms PGA2 Vn,out2 340 uVrms PGA3 Vn,out3 365 uVrms Typical output noise of ZoomingADC preamplifiers ADC only Figure 8.17: PGA1: 1 PGA2: 10 PGA3: off PGA1: off PGA2: 1 PGA3: 10 PGA1: 10 PGA2: 10 PGA3: off PGA1: 1 PGA2: 10 PGA3: 10 Noise measured at the output of the ZoomingADC As one can see on the figures above, increase the gain of the first amplifier lowers the output noise for constant global gain. It also lowers sensitivity to temperature drift as offset is better compensated on first amplifier. 8.11 Gain Error and Offset Error Gain error is defined as the amount of deviation between the ideal transfer function and the measured transfer function (with the offset error removed). The left figure shows gain error vs. temperature for different PGA gains. The curves are expressed in % of Full-Scale Range (FSR) normalized to 25C. 29 D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller Offset error is defined as the output code error for a zero volt input (ideally, output code = 0). The measured offset errors vs. temperature curves for different PGA gains are depicted in the right figure below. The output offset error, expressed in (LSB), is normalized to 25C. Output Offset Error [LSB] Gain Error [% of FSR] 0.2 0.1 0.0 -0.1 1 5 20 100 -0.2 -0.3 -0.4 100 1 5 20 100 80 60 40 20 0 -20 -40 -50 -25 0 25 50 75 100 -50 -25 Temperature [C] Figure 8.18: 0 25 50 75 100 Temperature [C] Gain and offset error vs temperature for several gains, normalized to 25C, offset cancellation disabled. When the offset cancellation is enabled, the offset remains below the LSB in all temperature situations. 8.12 Power Consumption Left figure below plots the variation of quiescent current consumption with supply voltage VDD, as well as the distribution between the 3 PGA stages and the ADC. As shown in the right figure, quiescent current consumption is not greatly affected by sampling frequency. It can be seen that the quiescent current varies by about 20% between 100kHz and 2MHz. Quiescent current consumption vs. temperature is shown in the second set of figures, showing a relative increase of nearly 40% between -45 and +85C. 800 800 Quiescent Current - IQ [ A] Quiescent Current - IQ [ A] 700 PGA1, 2 & 3 600 500 PGA1 & 2 only 400 PGA1 only 300 200 750 Sampling Frequency fS : 500kHz 700 250kHz 62.5kHz 650 600 550 No PGAs, ADC only 500 100 2.5 3.0 3.5 4.0 4.5 5.0 2.5 5.5 Supply Voltage - VDDA [V] Figure 8.19: 30 3.5 4.0 4.5 5.0 5.5 Supply Voltage - VDDA [V] Quiescent current versus supply voltage for different gains and clock speed (not using the PGA and ADC low power modes) Supply ADC PGA1 PGA2 PGA3 TOTAL Unit VDD = 5V 250 165 130 175 720 A VDD = 3V 190 150 120 160 620 A Table 8.8: 3.0 Typical quiescent current distributions in acquisition chain (n = 16 bits, fS = 500kHz) D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 20 Relative Quiescent Current Change IQ / IQ,25C [%] Quiescent Current - IQ [ A] 900 850 800 750 700 650 600 550 500 15 10 5 0 -5 -10 -15 -20 -25 -50 -25 0 25 50 75 100 125 -50 -25 0 25 Temperature [C] Figure 8.20: 75 100 125 3000 3500 Absolute and (b) relative change in quiescent current consumption vs. temperature Relative Quiescent Current Change IQ / IQ,2MHz [%] 850 Quiescent Current - IQ [ A] 50 Temperature [C] 800 750 700 650 600 550 500 15 10 5 0 -5 -10 -15 -20 0 500 1000 1500 2000 2500 3000 Frequency - fRC [kHz] Figure 8.21: 3500 0 500 1000 1500 2000 2500 Frequency - fRC [kHz] Absolute and (b) relative change in quiescent current consumption vs. clock speed 8.13 Power Supply Rejection Ratio Figure below shows power supply rejection ratio (PSRR) at 3V and 5V supply voltage, and for various PGA gains. PSRR is defined as the ratio (in dB) of voltage supply change (in V) to the change in the converter output (in V). PSRR depends on both PGA gain and supply voltage VDD. 31 D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 105 100 VDD=3V VDD=5V PSRR [dB] 95 90 85 80 75 70 65 60 1 5 10 20 100 PGA Gain [V/V] Figure 8.22: Power supply rejection ratio (PSRR) Supply VDD = 5V GAIN = 1 GAIN =5 GAIN = 10 GAIN = 20 GAIN =100 Unit 79 78 100 99 97 dB VDD = 3V 72 79 90 90 86 dB Table 8.9: PSRR (n = 16 bits, VIN = VREF = 2.5V, fS = 500kHz) 8.14 Frequency Response The incremental ADC of the XE88LC01 is an over-sampled converter with two main blocks: an analog modulator and a low-pass digital filter. The main function of the digital filter is to remove the quantization noise introduced by the modulator. As shown below, this filter determines the frequency response of the transfer function between the output of the ADC and the analog input VIN. Notice that the frequency axes are normalized to one elementary conversion period OSR/fS. The plots below also show that the frequency response changes with the number of elementary conversions NELCONV performed. In particular, notches appear for NELCONV 2. These notches occur at: f NOTCH (i ) = i fS OSR N ELCONV (Hz)for i = 1,2,..., ( N ELCONV - 1) and are repeated every fS/OSR. Information on the location of these notches is particularly useful when specific frequencies must be filtered out by the acquisition system. For example, consider a 5Hz-bandwidth, 16-bit sensing system where 50Hz line rejection is needed. Using the above equation and the plots below, we set the 4th notch for NELCONV = 4 to 50Hz, i.e. 1.25fS/OSR = 50Hz. The sampling frequency is then calculated as fS = 20.48kHz for OSR = 512. Notice that this choice yields also good attenuation of 50Hz harmonics. 32 D0202-60 1.2 1 Normalized Magnitude [-] Normalized Magnitude [-] Data Sheet XE88LC01 Data Acquisition Microcontroller NELCONV = 1 0.8 0.6 0.4 0.2 0 1.2 1 NELCONV = 2 0.8 0.6 0.4 0.2 0 0 1 2 3 4 0 1.2 1 NELCONV = 4 0.8 0.6 0.4 0.2 0 0 1 2 3 Normalized Frequency - f *(OSR/fS) [-] Figure 8.23: 33 1 2 3 4 Normalized Frequency - f *(OSR/fS) [-] Normalized Magnitude [-] Normalized Magnitude [-] Normalized Frequency - f *(OSR/fS) [-] 4 1.2 NELCONV = 8 1 0.8 0.6 0.4 0.2 0 0 1 2 3 4 Normalized Frequency - f *(OSR/fS) [-] Frequency response: normalized magnitude vs. frequency for different NELCONV D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 9 Physical description 9.1 LQFP44 package Figure 9.1: LQFP44 package, size in mm. 9.2 PLL-44L package Figure 9.2: 34 PLL-44L package, D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 9.3 Die form pin 1 XE88LC01 in die: 4.1 x 4.6 mm2 Figure 9.3: 9.3.1 Bonding pads location Coordinates start with a point near to the bottom left border (with respect to above picture). X is horizontal, Y is vertical. Pad size is 85 x 85 um. Symbol Pad X um Y um Symbol Pad X um Y um 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 PA(4) PA(5) NC PA(6) PA(7) PC(0) PC(1) PC(2) PC(3) NC PC(4) PC(5) PC(6) PC(7) PB(0) PB(1) PB(2) PB(3) PB(4) NC PB(5) PB(6) PB(7) TEST NC AC_R(3) 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 52.6 398.5 533.5 668.5 798.5 933.5 1063.5 1198.5 1328.5 1463.5 1934.1 2394.1 2854.1 4075.5 3795.5 3515.5 3235.5 2955.5 2675.5 2395.5 2115.5 1835.5 1555.5 1275.5 995.5 715.5 435.5 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 47.6 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 AC_R(2) AC_A(7) NC AC_A(6) AC_A(5) AC_A(4) AC_A(3) AC_A(2) NC AC_A(1) AC_A(0) AC_R(1) AC_R(0) Vss Vbat NC Vreg RESET Vmult OscIn NC OscOut PA(0) PA(1) PA(2) PA(3) 3314.1 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3958.4 3597.6 3332.6 3067.6 2802.6 2537.0 2007.6 1742.6 1477.6 1212.6 947.6 682.6 417.6 47.6 522.4 807.4 1092.4 1377.4 1662.4 1947.4 2232.4 2517.4 2802.4 3087.4 3372.4 3657.4 3942.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 4453.4 Table 9.1: 35 Bonding pads location. Do not connect pads named NC. Connect Vss pad and substrate to Vss. D0202-60 Data Sheet XE88LC01 Data Acquisition Microcontroller 10 Contacting XEMICS You will find more information about the XE88LC01 and other XEMICS products, as well as the addresses of our representatives and distributors for your region on http://www.xemics.com. XEMICS 2002 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. XEMICS PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF XEMICS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER'S OWN RISK. Should a customer purchase or use XEMICS products for any such unauthorized application, the customer shall indemnify and hold Xemics and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could arise. 36 D0202-60