Cool Solutions for Wireless Connectivity
XEMICS SA, email: info@xemics.com web: www.xemics.com
XE88LC01 Sensing Machine
16 + 10 bit Data Acquisition
Ultra Low-Power Microcontroller
General Description
The XE88LC01 is an ultra low-power microcontroller unit
(MCU) associated with a versatile analog-to-digital con-
verter (ADC) including a programmable offset and gain
pre-amplifier (PGA) .
XE88LC01 is available with on chip Multiple-Time-Pro-
grammable (MTP) Flash program memory and ROM.
Applications
• Internet connected appliances
• Portable, battery operated instruments
• Piezoresistive bridge sensors
•HVACcontrol
• Motor control
Key product Features
• Low-power, high resolution ZoomingADC
• 0.5 to 1000 gain with offset cancellation
• upto16bitsADC
• upto13inputmultiplexer
• Low-voltage low-power controller operation
• 2 MIPS at 2.4 V to 5.5 V supply voltage
• 300 µA at 1 MIPS, 2.4 V to 5.5 V supply
• 22 kByte (8 kInstruction) MTP, 520 Byte RAM
• RC and crystal oscillators
• 5 reset, 18 interrupt, 8 event sources
• 100 years MTP Flash retention at 55°C
Ordering Information
Reference Memory type Temperature Package
XE88LC01MI000 MTP Flash -40°C to 85°C die
XE88LC01MI027 MTP Flash -40°C to 85°C LQFP44
XE88LC01MI032 MTP Flash -40°C to 85°C PLL-44L
XE88LC01RI000 ROM -40°C to 125°C die
XE88LC01RI027 ROM -40°C to 125°C LQFP44
Data Sheet XE88LC01
Data Acquisition Microcontroller
Cool Solutions for Wireless Connectivity
XEMICS SA, email: info@xemics.com web: www.xemics.com
3D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
1 Detailed Pin Description
Pin
Description
Position
in
TQFP44
Function
name Second function
name Type
1 PA(5) Input Input of Port A
2 PA(6) Input Input of Port A
3 PA(7) Input Input of Port A
4 PC(0) Input/Output Input-Output of Port C
5 PC(1) Input/Output Input-Output of Port C
6 PC(2) Input/Output Input-Output of Port C
7 PC(3) Input/Output Input-Output of Port C
8 PC(4) Input/Output Input-Output of Port C
9 PC(5) Input/Output Input-Output of Port C
10 PC(6) Input/Output Input-Output of Port C
11 PC(7) Input/Output Input-Output of Port C
12 PB(0) testout Input/Output/Analog Input-Output-Analog of Port B/
Data output for test and MTP programing/
PWM output
13 PB(1) Input/Output/Analog Input-Output-Analog of Port B/
PWM output
14 PB(2) Input/Output/Analog Input-Output-Analog of Port B
15 PB(3) SOU Input/Output/Analog Input-Output-Analog of Port B,
Output pin of USRT
16 PB(4) SCL Input/Output/Analog Input-Output-Analog of Port B/
Clock pin of USRT
17 PB(5) SIN Input/Output/Analog Input-Output-Analog of Port B/
Data input or input-output pin of USRT
18 PB(6) Tx Input/Output/Analog Input-Output-Analog of Port B/
Emission pin of UART
19 PB(7) Rx Input/Output/Analog Input-Output-Analog of Port B/
Reception pin of UART
20 VPP/TEST Vhigh Special Test mode/High voltage for MTP programing
21 AC_R(3) Analog Highest potential node for 2nd reference of
ADC
22 AC_R(2) Analog Lowest potential node for 2nd reference of ADC
23 AC_A(7) Analog ADC input node
24 AC_A(6) Analog ADC input node
25 AC_A(5) Analog ADC input node
26 AC_A(4) Analog ADC input node
Table 1.1: Pin-out of the XE88LC01 in LQFP44
(see Table “IO pins performances” on page 18 for drive capabilities of the pins)
Figure 1.1: Pinout of the XE88LC01 in LQFP44 package
1
2
3
4
5
6
7
8
10
12 14 16 18 20 22
24
26
28
30
XEMICS
XE88LC01MI
N9K1444
9920
device type
production
packaging date
lot identification
42
32
34363840
25
27
29
31
9
4D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
27 AC_A(3) Analog ADC input node
28 AC_A(2) Analog ADC input node
29 AC_A(1) Analog ADC input node
30 AC_A(0) Analog ADC input node
31 AC_R(1) Analog Highest potential node for 1st reference of ADC
32 AC_R(0) Analog Lowest potential node for 1st reference of ADC
33 VSS Power Negative power supply, connected to substrate
34 Vbat Power Positive power supply
35 Vreg Analog Regulated supply
36 RESET Input Reset pin (active high)
37 Vmult Analog Pad for optional voltage multiplier capacitor
38 OscIn ck_cr Analog/Input Connection to Xtal/
CoolRISC clock for test and MTP programing
39 OscOut ptck Analog/Input Connection to Xtal/
Peripheral clock for test and MTP programing
40 PA(0) testin Input Input of Port A/
Data input for test and MTP programing/
Counter A input
41 PA(1) testck Input Input of Port A/
Data clock for test and MTP programing/
Counter B input
42 PA(2) Input Input of Port A/
Counter C input/ Counter capture input
43 PA(3) Input Input of Port A/
Counter D input/ Counter capture input
44 PA(4) Input Input of Port A
Pin
Description
Position
in
TQFP44
Function
name Second function
name Type
Table 1.1: Pin-out of the XE88LC01 in LQFP44
(see Table “IO pins performances” on page 18 for drive capabilities of the pins)
5D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
2 Absolute maximum ratings
Stresses beyond these listed in this chapter may cause permanent damage to the device. No
functional operation is implied at or beyond these conditions. Exposure to these conditions for
an extended period may affect the device reliability.
These devices are ESD sensitive. Although these devices feature proprietary ESD protection
structures, permanent damage may occur on devices subjected to high energy electrostatic
discharges. Proper ESD precautions have to be taken to avoid performance degradation or
loss of functionality.
Parameter Valéue
VBAT with respect to VSS -0.3V to 6.0V
Input voltage on any input pin VSS-0.3V to VBAT+0.3V
Storage temperature -55°Cto125°C
Storage temperature for programmed MTP devices -40°Cto85°C
Table 2.1: Absolute maximum ratings
6D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
3 Electrical Characteristics
All specification are -40°C to 85°C unless otherwise noted. ROM operates up to 125°C.
Note: 1) Power supply: 2.4 V - 5.5 V, temperature is 27°C.
2) < 10 erase cycles.
3) Output not loaded.
4) Current requirement can be divided by a factor of 2 or 4 by reducing the speed accordingly.
5) More cycles possible during development, with restraint retention
6) Power supply: 3.0V, at 27°C; see chapter Power Consumption on page 30 for variation of current
with voltage and clock speed variation
7) With 2 MHz clock, all instructions are using exactly 1 clock cycle
8) Longer erase time may degrade retention
Operation conditions min typ max Unit Remarks
Power supply ROM version 2.4 5.5 V
MTP version 2.4 5.5 V
Operating speed 2.4 V to 5.5 V 0.032 2 MHz
Instruction cycle any instruction 500 ns 7
Current requirement
CPU running
at 1 MIPS 310 uA 1
CPU running
at 32 kHz
on Xtal,
RC off
10 uA 1
CPU halt,
timer on Xtal,
RC off 1uA 1
CPU halt,
timer on Xtal,
RC ready 1.7 uA 1
CPU halt,
Xtal off
timer on RC
at 100 kHz
1.4 uA 1
Current requirement
CPU halt,
ADC 16 bits
at 4 kHz 190 uA 4,6
CPU halt,
ADC 12 bits
at 4 kHz,
PGA gain 100
460 uA 4,6
CPU at 1 MIPS,
ADC 12 bits
at 4 kHz 670 uA 3,4,6
CPU at 1 MIPS,
ADC12bitsat4kHz,
PGA gain 10 790 uA 3,4,6
CPU at 1 MIPS,
ADC12bitsat4kHz,
PGA gain 100 940 uA 3,4,6
CPU at 1 MIPS,
ADC12bitsat4kHz,
PGA gain 1000 1100 uA 3,4,6
Voltage level detection 15 uA
MTP Flash
memory
Prog. voltage 10.3 10.8 V
Erase time 0.2 1 s 8
Write/Erase cycles 10 100 5
Data retention 10 years 85°C, 2
100 years 55°C, 2
Table 3.1: Specifications and current requirement of the XE88LC01
7D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
4CPU
The XE88LC01 CPU is a low power RISC core. It has 16 internal registers for efficient imple-
mentation of the C compiler. Its instruction set is made of 35 generic instructions, all coded on
22 bits, with 8 addressing modes. All instructions are executed in one clock cycle, including
conditional jumps and 8x8 multiplication.
A complete tool suite for development is available from XEMICS, including programmer, C-
compiler, assembler, simulator, linker, all integrated in a modern and efficient graphical user
interface.
8D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
5 Memory organisation
The CPU uses a Harvard architecture, so that memory is organised in two separated fields:
program memory and data memory. As both memory are separated, the central processing
unit canread/write data at the same time it loadsan instruction. Peripheralsand system control
registers are mapped on data memory space.
Program memory is fitted onto one page. Data is made of several 256 bytes pages.
5.1 Program memory
The program memory is implemented as Multiple Time Programmable (MTP) Flash memory.
The power consumption of MTP memory is linear with the access frequency (no significant
static current).
Size of the MTP Flash memory is 8192 x 22 bits (= 22 kBytes)
Size of the ROM memory is 6144 x 22 bits (= 17 kBytes)
block size address
MTP 8192 x 22 H0000 - H1FFF
ROM 6144 x 22 H0000 - H1BFF
Table 5.1: Program addresses for MTP or ROM memory
Figure 5.1: Memory organization
CPU
Program
memory
LP RAM
Peripherals
RAM
Program address bus
Data address bus
22 bits wide 8 bits wide
CPU
registers
Instruction
pipeline
8k instructions MTP
512 Bytes
0h0000
0h1FFF / 01hBFF
0h0000
0h0010
0h0080
0h027F
or
6k instructions ROM
9D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
5.2 Data memory
The data memory is implemented as static Random-Access Memory (RAM). The RAM size is
512 x 8 bits plus 8 low power RAM bytes that require very low current when addressed. Pro-
grams using the low-power RAM instead of RAM will use even less current.
6 Registers list
Left column include register name and address.
Right columns include bit name, access (r: read, r0: always 0 when read, w: write, c: cleared
by writing any value, c1: cleared by writing 1), and reset status (0 or 1) and signal. Empty bits
are reserved for future use and should not be written, neither should their read value be used
for any purpose as it may change without notice.
6.1 Peripherals mapping
block size address
LP RAM 8 x 8 H0000 - H0007
RAM 512 x 8 H0080 - H027F
Table 5.2: RAM addresses
block size address Page
LP RAM 8x8 H0000-H0007
Page 0
System control 16x8 H0010-H001F
Port A 8x8 H0020-H0027
Port B 8x8 H0028-H002F
Port C 4x8 H0030-H0033
Reserved 4x8 H0034-H0037
MTP 4x8 H0038-H003B
Event 4x8 H003C-H003F
Interrupts control 8x8 H0040-H0047
reserved 8x8 H0048-H004F
UART 8x8 H0050-H0057
Counters 8x8 H0058-H005F
Zooming ADC 8x8 H0060-H0067
Reserved 12x8 H0068-H0073
Reserved 8x8 H0074-H007B
Other
(VLD) 4x8 H007C-H007F
RAM1 128x8 H0080 - H00FF
RAM2 256x8 H0100 - H01FF Page 1
RAM3 128x8 H0200 - H027F Page 2
Table 6.1: Peripherals addresses
10 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
6.2 Resets The reset source name is simplified in the following registers description. Name mapping is in
the next table.
6.3 Low power RAM
Low power RAM is a small additionnal RAM area with extremely low power requirement.
reset source name in this
document
resetsystem global
resetSynch
resetPOR coldresetCold
resetPad
resetPconf pconf
resetSleep sleep
Table 6.2: Reset signal name mapping
Name 7 6 5 4 3 2 1 0
Address
h0000 rw rw rw rw rw rw rw rw
h0001 rw rw rw rw rw rw rw rw
h0002 rw rw rw rw rw rw rw rw
h0003 rw rw rw rw rw rw rw rw
h0004 rw rw rw rw rw rw rw rw
h0005 rw rw rw rw rw rw rw rw
h0006 rw rw rw rw rw rw rw rw
h0007 rw rw rw rw rw rw rw rw
Table 6.3: Low power RAM
11 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
6.4 System, oscillators, prescaler and watchdog
6.5 PortA
Name 7 6 5 4 3 2 1 0
Address
RegSysCtrl SleepEn EnRes-PConf EnBus-Error EnResWD
h0010, type 1 rw, 0 por rw, 0 cold rw, 0 cold rw, 0 cold
RegSysReset Sleep ResPor ResBus-Error ResWD ResPortA ResPad-Deb ResPad
h0011, type 1 w,0cold r,0 rc,0cold rc,0cold rc,0cold rc,0cold rc,0cold
RegSysClock CpuSel ExtClk EnExtClk BiasRC ColdXtal ColdRC EnableXtal EnableRC
h0012, type 1 rw,0sleep r,0cold rw,0cold rw,1cold r,1sleep r,1sleep rw,0sleep rw,1sleep
RegSysMisc RCOnPA0 DebFast Output-
CkXtal Output-
CkCPU
h0013, type 1 rw, 0 sleep rw, 0 sleep rw, 0 sleep rw, 0 sleep
RegSysWD WatchDog(3) WatchDog(2) WatchDog(1) WatchDog(0)
h0014 special special special special
RegSysPre0 ResPre
ClearLow-
Prescal (*)
h0015 w, 0 cold
RegSysRCTrim1 RCFreq-
Range RCFreq-
Coarse(3) RCFreq-
Coarse(2) RCFreq-
Coarse(1) RCFreq-
Coarse(0)
h001B rw,0cold rw,0cold rw,0cold rw,0cold rw,0cold
RegSysRCTrim2 RCFreq-
Fine(5) RCFreq-
Fine(4) RCFreq-
Fine(3) RCFreq-
Fine(2) RCFreq-
Fine(1) RCFreq-
Fine(0)
h001C rw,1cold rw,0cold rw,0cold rw,0cold rw,0cold rw,0cold
Table 6.4: System control registers
Name 7 6 5 4 3 2 1 0
Address
RegPAIn PAIn(7) RegPAIn(6) PAIn(5) PAIn(4) PAIn(3) PAIn(2) PAIn(1) PAIn(0)
h0020 rrrrrrrr
RegPADebounce PADeb(7) PADeb(6) PADeb(5) PADeb(4) PADeb(3) PADeb(2) PADeb(1) PADeb(0)
h0021 rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf
RegPAEdge PAEdge(7) PAEdge(6) PAEdge(5) PAEdge(4) PAEdge(3) PAEdge(2) PAEdge(1) PAEdge(0)
h0022 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global
RegPAPullup PAPullUp(7) PAPullUp(6) PAPullUp(5) PAPullUp(4) PAPullUp(3) PAPullUp(2) PAPullUp(1) PAPullUp(0)
h0023, type 1 rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf
RegPARes0 PARes0(7) PARes0(6) PARes0(5) PARes0(4) PARes0(3) PARes0(2) PARes0(1) PARes0(0)
h0024 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global
RegPARes1 PARes1(7) PARes1(6) PARes1(5) PARes1(4) PARes1(3) PARes1(2) PARes1(1) PARes1(0)
h0025 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global
Table 6.5: Port A registers
12 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
6.6 PortB
6.7 PortC
6.8 MTP
Name 7 6 5 4 3 2 1 0
Address
RegPBOut PBOut(7) PBOut(6) PBOut(5) PBOut(4) PBOut(3) PBOut(2) PBOut(1) PBOut(0)
h0028 rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf
RegPBIn PBIn(7) PBIn(6) PBIn(5) PBIn(4) PBIn(3) PBIn(2) PBIn(1) PBIn(0)
h0029 rrrrrrrr
RegPBDir PBDir(7) PBDir(6) PBDir(5) PBDir(4) PBDir(3) PBDir(2) PBDir(1) PBDir(0)
h002A rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf
RegPBOpen PBOpen(7) PBOpen(6) PBOpen(5) PBOpen(4) PBOpen(3) PBOpen(2) PBOpen(1) PBOpen(0)
h002B rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf
RegPBPullup PBPullUp(7) PBPullUp(6) PBPullUp(5) PBPullUp(4) PBPullUp(3) PBPullUp(2) PBPullUp(1) PBPullUp(0)
h002C rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf
RegPBAna PBAna(3) PBAna(2) PBAna(1) PBAna(0)
h002D rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf
Table 6.6: Port B registers
Name 7 6 5 4 3 2 1 0
Address
RegPCOut PCOut(7) PCOut(6) PCOut(5) PCOut(4) PCOut(3) PCOut(2) PCOut(1) PCOut(0)
h0030 rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf
RegPCIn PCIn(7) PCIn(6) PCIn(5) PCIn(4) PCIn(3) PCIn(2) PCIn(1) PCIn(0)
h0031 rrrrrrrr
RegPCDir PCDir(7) PCDir(6) PCDir) PCDir(4) PCDir(3) PCDir(2) PCDir(1) PCDir(0)
h0032 rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf rw, 0 pconf
Table 6.7: Port C registers
Name 7 6 5 4 3 2 1 0
Address
RegEEP
h0038 rw rw rw rw rw rw rw rw
RegEEP1
h0039 rw rw rw rw rw rw rw rw
RegEEP2
h003A special special special special special special special special
RegEEP3
h003B special special special special special special special special
Table 6.8: MTP control registers
13 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
6.9 Events
6.10 Interrupts
6.11 USRT
Name 7 6 5 4 3 2 1 0
Address
RegEvn EvnCntA EvnCntC EvnPre1 EvnPA(1) EvnCntB EvnCntD EvnPre2 EvnPA(0)
h003C rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global
RegEvnEn EvnEnCntA EvnEnCntC EvnEnPre1 EvnEnPA(1) EvnEnCntB EvnEnCntD EvnEnPre2 EvnEnPA(0)
h003D rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global
RegEvnPriority EvnPriority(7) EvnPriority(6) EvnPriority(5) EvnPriority(4) EvnPriority(3) EvnPriority(2) EvnPriority(1) EvnPriority(0)
h003E r,1 global r,1 global r,1 global r,1 global r,1 global r,1 global r,1 global r,1 global
RegEvnEvn EvnHigh EvnLow
h003F r, 0 global r, 0 global
Table 6.9: Events control registers
Name 7 6 5 4 3 2 1 0
Address
RegIrqHig IrqAc IrqPre1 IrqCntA IrqCntC IrqUartTx IrqUartRx
h0040 rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global
RegIrqMid IrqPA(5) IrqPA(4) IrqPre2 IrqVld IrqPA(1) IrqPA(0)
h0041 rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global
RegIrqLow IrqPA(7) IrqPA(6) IrqCntB IrqCntD IrqPA(3) IrqPA(2)
h0042 rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global rc1, 0 global
RegIrqEnHig IrqEnAc IrqEnPre1 IrqEnCntA IrqEnCntC IrqEnUartTx IrqEnUartRx
h0043 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global
RegIrqEnMid IrqEnPA(5) IrqEnPA(4) IrqEnPre2 IrqEnVld IrqEnPA(1) IrqEnPA(0)
h0044 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global
RegIrqEnLow IrqEnPA(7) IrqEnPA(6) IrqEnCntB IrqEnCntD IrqEnPA(3) IrqEnPA(2)
h0045 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global
RegIrqPriority IrqPriority(7) IrqPriority(6) IrqPriority(5) IrqPriority(4) IrqPriority(3) IrqPriority(2) IrqPriority(1) IrqPriority(0)
h0046 r, 1 global r, 1 global r, 1 global r, 1 global r, 1 global r, 1 global r, 1 global r, 1 global
RegIrqIrq IrqHig IrqMid IrqLow
h0047 r, 0 global r, 0 global r, 0 global
Table 6.10: Interrupts control registers
Name 7 6 5 4 3 2 1 0
Address
RegUsrtSin UsrtSin
h0048 rw, 1 global
RegUsrtScl UsrtScl
h0049 rw, 1 global
RegUsrtCtrl UsrtWaitS0 UsrtEnWait-
Cond1 UsrtEnWaitS0 UsrtEnable
h004A r, 0 global rw, 0 global rw, 0 global rw, 0 global
RegUsrtData UsrtData
h004D r
RegUsrtEdgeScl UsrtEdgeScl
h004E r, 0 global
Table 6.11: USRT control registers
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Data Sheet XE88LC01
Data Acquisition Microcontroller
6.12 UART
6.13 Counters
Name 7 6 5 4 3 2 1 0
Address
RegUartCtrl UartEcho UartEnRx UartEnTx UartXRx UartXTx UartBR(2) UartBR(1) UartBR(0)
h0050 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 1 global rw, 0 global rw, 1 global
RegUartCmd SelXtal UartWakeup UartRCSel(2) UartRCSel(1) UartRCSel(0) UartPM UartPE UartWL
h0051 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 1 global
RegUartTx UartTx(7) UartTx(6) UartTx(5) UartTx(4) UartTx(3) UartTx(2) UartTx(1) UartTx(0)
h0052 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global
RegUartTxSta UartTxBusy UartTxFull
h0053 r, 0 global r, 0 global
RegUartRx UartRx(7) UartRx(6) UartRx(5) UartRx(4) UartRx(3) UartRx(2) UartRx(1) UartRx(0)
h0054 rrrrrrrr
RegUartRxSta UartRxSErr UartRxPErr UartRxFErr UartRxOErr UartRxBusy UartRxFull
h0055 rrrcrr
Table 6.12: UART control registers
Name 7 6 5 4 3 2 1 0
Address
RegCntA CounterA(7) CounterA(6) CounterA(5) CounterA(4) CounterA(3) CounterA(2) CounterA(1) CounterA(0)
h0058 rw rw rw rw rw rw rw rw
RegCntB CounterB(7) CounterB(6) CounterB(5) CounterB(4) CounterB(3) CounterB(2) CounterB(1) CounterB(0)
h0059 rw rw rw rw rw rw rw rw
RegCntC CounterC(7) CounterC(6) CounterC(5) CounterC(4) CounterC(3) CounterC(2) CounterC(1) CounterC(0)
h005A rw rw rw rw rw rw rw rw
RegCntD CounterD(7) CounterD(6) CounterD(5) CounterD(4) CounterD(3) CounterD(2) CounterD(1) CounterD(0)
h005B rw rw rw rw rw rw rw rw
RegCntCtrlCk CntDSel(1) CntDSel(0) CntCSel(1) CntCSel(0) CntBSel(1) CntBSel(0) CntASel(1) CntASel(0)
h005C rw rw rw rw rw rw rw rw
RegCntConfig1 CntDDownUp CntCDownUp CntBDownUp CntADownUp CascadeCD CascadeAB CntPWM1 CntPWM0
h005D rw rw rw rw rw rw rw, 0 global rw, 0 global
RegCntConfig2 CapSel(1) CapSel(0) CapFunc(1) CapFunc(0) PWM1Size(1) PWM1Size(0) PWM0Size(1) PWM0Size(0)
h005E rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw rw rw rw
RegCntOn CntDEnable CntCEnable CntBEnable CntAEnable
h005F rw, 0 global rw, 0 global rw, 0 global rw, 0 global
Table 6.13: Counters control registers
15 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
6.14 Acquisition chain
6.15 Vmult and Vld registers
Name 7 6 5 4 3 2 1 0
Address
RegAcOutLsb AdcOutL(7) AdcOutL(6) AdcOutL(5) AdcOutL(4) AdcOutL(3) AdcOutL(2) AdcOutL(1) AdcOutL(0)
h0060 rrrrrrrr
RegAcOutMsb AdcOutM(7) AdcOutM(6) AdcOutM(5) AdcOutM(4) AdcOutM(3) AdcOutM(2) AdcOutM(1) AdcOutM(0)
h0061 rrrrrrrr
RegAcCfg0 Start NelConv(1) NelConv(0) OSR(2) OSR(1) OSR(0) Cont
h0062 r0w, 0 global rw, 0 global rw, 1 global rw, 0 global rw, 1 global rw, 0 global rw, 0 global
RegAcCfg1 IbAmpADC(1) IbAmpAdc(0) IbAmpPga(1) IbAmpPga(0) Enable(3) Enable(2) Enable(1) Enable(0)
h0063 rw, 1 global rw, 1 global rw, 1 global rw, 1 global rw, 0 global rw, 0 global rw, 0 global rw, 1 global
RegAcCfg2 Fin(1) Fin(0) Pga2Gain(1) Pga2Gain(0) Pga2Off(3) Pga2Off(2) Pga2Off(1) Pga2Off(0)
h0064 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global
RegAcCfg3 Pga1Gain Pga3Gain(6) Pga3Gain(5) Pga3Gain(4) Pga3Gain(3) Pga3Gain(2) Pga3Gain(1) Pga3Gain(0)
h0065 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 1 global rw, 1 global rw, 0 global rw, 0 global
RegAcCfg4 Pga3Off(6) Pga3Off(5) Pga3Off(4) Pga3Off(3) Pga3Off(2) Pga3Off(1) Pga3Off(0)
h0066 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global
RegAcCfg5 Busy Def AMux(4) AMux(3) AMux(2) AMux(1) AMux(0) VMux
h0067 r, 0 global wr0 rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global
Table 6.14: Acquisition chain control registers
Name 7 6 5 4 3 2 1 0
Address
RegVmultCfg0 Enable Fin(1) Fin(0)
h007C rw, 0 global rw, 0 global rw, 0 global
RegVldCtrl VldMult VldTune(2) VldTune(1) VldTune(0)
h007E rw,0cold rw,0cold rw,0cold rw,0cold
RegVldStat VldIrq VldValid VldEn
h007F r, 0 global r, 0 global rw, 0 global
Table 6.15: Vmult and Vld control registers
16 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
7 Peripherals
The XE88LC01 includes usual microcontroller peripherals and some other blocks more spe-
cific to low-voltage or mixed-signal operation. They are 3 parallel ports, one input port (A), one
IO and analog port (B) with analog switching capabilities and one general purposeIO port (C).
A watchdog is available, connected toa prescaler. Four 8-bit counters, with capture, PWM and
chaining capabilities are available. The UART can handle transmission speeds as high as
115kbaud.
Low-power low-voltage blocks include a voltage level detector, two oscillators (one internal
0.1-2 MHz RC oscillator and a 32 kHz crystal oscillator) and a specific regulation scheme that
largely uncouples current requirement from external power supply (usual CMOS ASICs re-
quire much more current at 5.5 V than they need at 2.4 V. This is not the case for the
XE88LC01).
Analog blocks (ZoomingADC (acquisition path)) are defined below. All these blocks operate
on 2.4 - 5.5 V power supply range.
7.1 Counters • 4 8-bit counters
• Daisy chain on 16 bits
• PWM on 8-16 bits
• Capture - compare on 16 bits
• Events and interrupts generation
7.2 Prescaler • Interrupt generated with 1 second period for ultra low power hibernation mode
7.3 Watchdog • 2 seconds watchdog
7.4 UART • full duplex operation with buffered receiver and transmitter.
• Internal baudrate generator with programmable baudrate (300 - 115000 bauds).
• 7 or 8 bits word length.
• even, odd, or no-parity bit generation and detection
•1stopbit
• error receive detection : Start, Parity, Frame and Overrun
• receiver echo mode
• 2 interrupts (receive full and transmit empty)
• enable receive and/or transmit
• invert pad Rx and/or Tx
17 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
7.5 Xtal clock
The Xtal Oscillator operates with an external crystal of 32’768 Hz.
Note: Board layout recommendations for safer crystal oscillation and lower current consumption:
Keep lines xtal_in and xtal_out short and insert a VSS line between them.
Connect package of the crystal to VSS.
No noisy or digital lines near xtal_in and xtal_out.
Insert guards at VSS where needed.
7.6 RC oscillator
The RC Oscillator is always turned on at power-on reset and can be turned off after the option-
al Xtal oscillator has been started. The RC oscillator has two frequency ranges: sub-MHz
(100KHz to 1MHz) and above-MHz (1MHz to max MCU frequency). Inside a range, the fre-
quency can be tuned by software for coarse and fine adjustment.
Note: No external component is required for the RC oscillator.
The RC oscillator can be in 3 modes. In mode 1(RC on), the RC oscillator and its bias are on.
In mode 2 (RC ready), the RC oscillator is off and the bias is on. In mode 3 (RC off), the RC
oscillator and the bias are off. RC ready mode is a compromise between power consumption
and start-up time.
symbol description min typ max unit comments
f_clk32k nominal frequency 32768 Hz
st_x32k oscillator start-up time 1 2 s for full precision
duty_clk32k duty cycle on the digital output 30 50 70 %
fstab_1
relative frequency deviation from
nominal, for a crystal with CL=8.2 pF
and temperature between -40° and
+85°C
-100 +300 ppm not included:
crystal frequency tolerance and aging
crystal frequency - temperature dependence
Table 7.1: Xtal oscillator specifications.
Figure 7.1: RC frequencies programming example for low range (typical values)
18 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
7.7 Parallel IO ports
• 8 bit input port A with interrupt, reset and event generation.
• 8 bit input-output-analog port B with analog switching capabilities.
• 8 bit input-output port C.
symbol description min typ max unit comments
Fst frequency at start-up 50 80 110 kHz
range range selection 1 10 multiplies Fst
mult[3:0] coarse tuning range 1 16 4 bits, multiplies Fst *range
tune[5:0] fine tuning range 0.65 1.5 6 bits, multiplies Fst * range * mult
fine tuning step 1.4 2 %
Tst start-up time 30 50 µs bias current is off (RC off)
Ost overshoot at start-up 50 % bias current is off (RC off)
Twu wakeup time 3 5 µs bias current is on (RC ready)
Owu overshoot at wakeup 50 % bias current is on (RC ready)
jit jitter rms 2 o/oo
Table 7.2: RC specifications
sym description condition min typ max unit Comments
Port A: low threshold limit
Vbat =
1.2 V
V
Port A: high threshold limit V
output drop when sinking 1 mA 0.4 V
output drop when sourcing 1 mA 0.4 V
Port A: low threshold limit
Vbat =
2.4 V
1V
Port A: high threshold limit 1.5 V
output drop when sinking 1 mA V
output drop when sinking 8 mA 0.4 V
output drop when sourcing 1 mA V
output drop when sourcing 8 mA 0.4 V
Port A: low threshold limit
Vbat =
5.0 V
2V
Port A: high threshold limit 3 V
output drop when sinking 1 mA V
output drop when sinking 8 mA 0.4 V
output drop when sourcing 1 mA V
output drop when sourcing 8 mA 0.4 V
pull-up, pull-down resistor 50 150 kohm
Table 7.3: IO pins performances
19 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
7.8 Voltage level detector
• Can be switched off, on or simultaneously with CPU activities
• Generates an interrupt if power supply is below a pre-determined level
The Voltage Level Detector monitors the state of the system battery. It returns a logical high
value (an interrupt) in the status register if the supplied voltage drops below the user defined
level.
Note: 1) Absolute precision of the threshold voltage is ±10%.
2) This timing is respected in case the internal RC or crystal oscillators are selected. Refer to the clock
block documentation in case the external clock is used.
symbol description min typ max unit comments
Vth Threshold voltage
Note 1
V
trimming values:
VldRange VldTune
1.53 0 000
1.44 0 001
1.36 0 010
1.29 0 011
1.22 0 100
1.16 0 101
1.11 0 110
1.06 0 111
3.06 1 000
2.88 1 001
2.72 1 010
2.57 1 011
2.44 1 100
2.33 1 101
2.22 1 110
2.13 1 111
TEOM duration of measurement 2.0 2.5 ms Note 2
TPW Minimum pulse width detected 875 1350 us Note 2
Table 7.4: Voltage level detector operation
20 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
8 ZoomingADC
The fully differential acquisition chain is formed of a programmable gain (0.5 - 1000) and offset
amplifier and a programmable speed and resolution ADC (example: 12 bits at 4 kHz, 16 bits
at 1 kHz). It can handle inputs with very low full scale signal and large offsets.
Input selection is made from 1 of 4 differentialpairs or 1 of sevensingle signal versus AC_A(0).
Referenceischosenfromthe2differentialreferences.Acquisitionpathoffsetcanbesup-
pressed by inverting input polarity.
The gain of each amplifier is programmed individually. Each amplifier is powered on and off on
command to minimize the total current requirement. All blocks can be set to low frequency op-
eration and lower their current requirement by a factor 2 or 4.
The ADCcan run continuously (endof conversion signalled by an interrupt, event orby pooling
the ready bit), or it can be started on request.
8.1 PGA 1
Note: 1) Measuredwith block connected to inputs through AMUX block. Normalized input samplingfrequen-
cy for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs
= 128 kHz.
2) Input referred rms noise is 205 uV per input sample with gain = 1, 20.5 uV with gain = 10. This cor-
responds to 28.6 nV/sqrt(Hz) for fs = 512 kHz and gain = 10.
symbol description min typ max unit Comments
GD1 PGA1 Signal Gain 1 10 - GD1 = 1 or 10
GD_preci Precision on gain settings -5 +5 %
GD_TC Temperature dependency of gain settings -5 +5 ppm/°C
fs input sampling frequency 512 kHz
Zin1 Input impedance 150 kΩ1
Zin1p Input impedance for gain 1 1500 kΩ1
VN1 Input referred noise 28.6 nV/
sqrt(Hz) 2
Table 8.1: PGA1 Performances
Figure 8.1: Acquisition channel block diagram
gain1 offset2
gain2 offset3
gain3 mode output
code
input selection
ADC
AC_A(0)
AC_A(1)
AC_A(2)
AC_A(3)
AC_A(4)
AC_A(5)
AC_A(6)
AC_A(7)
AC_R(0)
AC_R(1)
AC_R(2)
AC_R(3)
reference selection
21 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
8.2 PGA2
Note: 1) Measuredwith block connected to inputs through AMUX block. Normalized input samplingfrequen-
cy for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs
= 128 kHz.
2) Input referred rms noise is 340 uV per input sample with gain = 1, 34 uV with gain = 10.This corre-
spondsto47.5nV/sqrt(Hz)forfs=512kHzandgain=10.
8.3 PGA3
Note: 1) Measuredwith block connected to inputs through AMUX block. Normalized input samplingfrequen-
cy for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs
= 128 kHz.
2) Input referred rms noise is 365 uV per imput sample with gain = 1, 36.5 uV with gain = 10. This cor-
responds to 51.0 nV/sqrt(Hz) for fs = 512 kHz.
sym description min typ max unit Comments
GD2 PGA2 Signal Gain 1 10 - GD2 = 1, 2, 5 or 10
GDoff2 PGA2 Offset Gain -1 1 FS
GDoff2_step GDoff2(code+1) – GDoff2(code) 0.18 0.2 0.22 -
GD_preci Precision on gain settings -5 +5 % valid for GD2 and GDoff2
GD_TC Temperature dependency of gain settings -5 +5 ppm/°C
fs Input sampling frequency 512 kHz
Zin2 Input impedance 150 kΩ1
VN2 Input referred noise 47.5 nV/
sqrt(Hz) 2
Table 8.2: PGA2 Performances
sym description min typ max unit Comments
GD3 PGA3 Signal Gain 0 10 -
GDoff3 PGA3 Offset Gain -5 5 FS
GD3_step GD3(code+1) - GD3(code) 0.075 0.08 0.085 -
GDoff3_step GDoff2(code+1) – GDoff2(code) 0.075 0.08 0.085 -
GD_preci Precision on gain settings -5 +5 % valid for GD3 and GDoff3
GD_TC Temperature dependency of gain settings -5 +5 ppm/°C
fs Input sampling frequency 512 kHz
Zin3 Input impedance 150 kΩ1
VN3 Input referred noise 51.0 nV/
sqrt(Hz) 2
Table 8.3: PGA3 Performances
22 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
8.4 Analog to digital converter (ADC)
The whole analog to digital conversion sequence is basically made of an initialisation, a set of
Nelconv elementary incremental conversions and finally a termination phase(NumCONV is set
by 2 bits on RegACCfg0). The result is a mean of the results of the elementary conversions.
Some additional clock cycles (NINIT+NEND)clockcyclesareusedtoinitiateandterminatethe
conversion properly.
8.5 ADC performances
Note: 1) Only powers of 2
Note: 2) INL is defined as the deviation of the DC transfer curve from the best fit straight line. This specifi-
sym description min typ max unit Comments
VINR Input range -0.5 0.5 Vref
Resol Resolution 6 16 bits
NResol Numerical resolution 16 bits 3
DNL Differential non-linearity -0.1 0.1 LSB LSB at 16 bits
INL Integral non-linearity -3 2 LSB 2, LSB at 16 bits
fs sampling frequency 10 512 kHz
smax Oversampling Ratio 8 1024 - 1
NUMCONV Number of elementary conversions in
incremental mode 18-1
Ninit Number of periods for incremental conversion
initialization 5-
Nend Number of periods for incremental conversion
termination 5-
Table 8.4: ADC Performances
Note: NumCONV elementary conversions are performed, each elementary conversion being made of
smax input samples.
NumCONV =2
NELCONV
smax = 8*2OSR
During the elementary conversions, the operation of the converter is the same as in a sigma
delta modulator. During one conversion sequence, the elementary conversions are alterna-
tively performed with direct and crossed PGA-ADC differential inputs, so that when two ele-
mentary conversions or more are performed, the offset of the converter is cancelled.
Figure 8.2: Conversion sequence. smax is the oversampling rate.
START END
1st elementary
conversion 2nd elementary
conversion elementary
conversion elementary
conversion
conversion
index 12N
umConv-1 NumConv
input 12 smax12 smax 12 smax
sample
23 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
cation holds over 100% of the full scale.
3) NResol is the maximal readable resolution of the digital filter.
8.6
8.7 Linearity
To quantify linearity errors, Integral Non-Linearity (INL) and Differential Non-Linearity (DNL)
were measured for the ADC alone and for gains of 1, 5, 10, 20, 100, 1000, and a resolution of
12 bits and 16 bits.
INL is defined as the deviation (in LSB) of the DC transfer curve of each individual code from
the best-fit straight line. This specification holds over the full scale.
DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code tran-
sitions for successive codes. INL and DNL are specified after gain and offset errors have been
removed.
8.8 Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) for 12-bit reso-
lution
resolution conditions input frequency. convertion time. output frequency.
6oversampling per convertion = 8
1 conversion (no offset rejection) 512 kHz 40 us 25 kHz
8oversampling per convertion = 16
1 conversion (no offset rejection) 512 kHz 50 us 20 kHz
12 oversampling per convertion = 64
1 conversion (no offset rejection) 512 kHz 150 us 6.7 kHz
13 oversampling per convertion = 64
2 convertions (offset rejection) 512 kHz 275 us 3.6 kHz
16 oversampling per convertion = 256
1 convertion (no offset rejection) 512 kHz 500 us 2 kHz
16 oversampling per convertion = 256
2 convertions (offset rejection) 512 kHz 1 ms 1 kHz
16 oversampling per convertion = 1024
8 convertions (offset rejection) 512 kHz 16.5 ms 60 Hz
Table 8.5: ADC performances examples
12 bits - ADC converter (No PGA; ADC only) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
1.0
0 500 1000 1500 2000 2500
V
IN
[mV]
Integral Non-Linearity
(INL) [LSB]
Figure 8.3: NO GAIN (ONLY ADC), 12 bit ADC setting
12 bits - ADC converter (No PGA; ADC only) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-0.30
-0.20
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0 500 1000 1500 2000 2500
V
IN
[mV]
DifferentialNon-Linearity
(DNL) [LSB]
24 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
Figure 8.4: GAIN=1, 12 bit ADC setting
12 bits - ADC converter (GDtot = 1) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0 500 1000 1500 2000 2500
V
IN
[mV]
Integral Non-Linearity
(INL) [LSB]
INL
12 bits - ADC converter (GDtot = 1) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-0.30
-0.20
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0 500 1000 1500 2000 2500
V
IN
[mV]
Differential Non-Linearity
(DNL) [LSB]
Figure 8.5: GAIN=5, 12 bit ADC setting
12 bits - ADC converter (GDtot = 5) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-1.5
-1.0
-0.5
0.0
0.5
1.0
0 100 200 300 400 500
V
IN
[mV]
Integral Non-Linearity
(INL) [LSB]
12 bits- ADC converter(GDtot= 5) (versionv5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4
fRC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-0.30
-0.20
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0 100 200 300 400 500
V
IN
[mV]
Differential Non-Linearity
(DNL) [LSB]
Figure 8.6: GAIN=10, 12 bit ADC setting
12 bits - ADC converter (GDtot = 10) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0 50 100 150 200 250
V
IN
[mV]
Integral Non-Linearity
(INL) [LSB]
12 bits - ADC converter (GDtot = 10) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-0.50
-0.40
-0.30
-0.20
-0.10
0.00
0.10
0.20
0.30
0.40
0.50
0 50 100 150 200 250
V
IN
[mV]
Differential Non-Linearity
(DNL) [LSB]
25 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
Figure 8.7: GAIN=20, 12 bit ADC setting
12 bits - ADC converter (GDtot = 20) (version v5a)
Vbat =Vref = 5.0V; fs = 500kHz; OSR= 32; NELCONV = 4
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
0 20 40 60 80 100 120
V
IN
[mV]
Integral Non-Linearity
(INL) [LSB]
12 bits - ADC converter (GDtot = 20) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-0.80
-0.60
-0.40
-0.20
0.00
0.20
0.40
0.60
0 20406080100120
V
IN
[mV]
Differential Non-Linearity
(DNL) [LSB]
Figure 8.8: GAIN=100, 12 bit ADC setting
12 bits - ADC converter (GDtot = 100) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4samples
-4.0
-3.0
-2.0
-1.0
0.0
1.0
2.0
3.0
4.0
0 5 10 15 20 25
V
IN
[mV]
Integral Non-Linearity
(INL) [LSB]
12 bits - ADC converter (GDtot = 100) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-1.50
-1.00
-0.50
0.00
0.50
1.00
0 5 10 15 20 25
V
IN
[mV]
Differential Non-Linearity
(DNL) [LSB]
Figure 8.9: GAIN=1000, 12 bit ADC setting
12 bits - ADC converter (GDtot = 1000) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4samples
-6.0
-4.0
-2.0
0.0
2.0
4.0
6.0
0 5 10 15 20 25
10*V
IN
[mV]
Integral Non-Linearity
(INL) [LSB]
12 bits - ADC converter (GDtot = 1000) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0 5 10 15 20 25
10*V
IN
[mV]
DifferentialNon-Linearity
(DNL) [LSB]
26 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
8.9 Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) for 16-bit reso-
lution
Figure 8.10: NO GAIN (ONLY ADC), 16 bit ADC setting
16 bits- ADC converter (No PGA; ADC only) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-3
-2
-1
0
1
2
3
0 500 1000 1500 2000 2500
V
IN
[mV]
Integral Non-Linearity
(INL) [LSB]
16bits- ADC converter(No PGA;ADC only) (versionv5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-0.15
-0.10
-0.05
0.00
0.05
0.10
0 500 1000 1500 2000 2500
V
IN
[mV]
Differential Non-Linearity
(DNL) [LSB]
Figure 8.11: GAIN=1, 16 bit ADC setting
16 bits - ADC converter (GDtot = 1) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-25.0
-20.0
-15.0
-10.0
-5.0
0.0
5.0
10.0
15.0
20.0
25.0
0 500 1000 1500 2000 2500
V
IN
[mV]
Integral Non-Linearity
(INL) [LSB]
16 bits - ADC converter (GDtot = 1) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-0.10
-0.08
-0.06
-0.04
-0.02
0.00
0.02
0.04
0.06
0.08
0.10
0 500 1000 1500 2000 2500
V
IN
[mV]
Differential Non-Linearity
(DNL) [LSB]
Figure 8.12: GAIN=5, 16 bit ADC setting
16 bits - ADC converter (GDtot = 5) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-20.0
-15.0
-10.0
-5.0
0.0
5.0
10.0
0 100 200 300 400 500
V
IN
[mV]
Integral Non-Linearity
(INL) [LSB]
16 bits - ADC converter (GDtot = 5) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0 100 200 300 400 500
V
IN
[mV]
Differential Non-Linearity
(DNL) [LSB]
27 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
Figure 8.13: GAIN=10, 16 bit ADC setting
16 bits - ADC converter (GDtot = 10) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-30
-20
-10
0
10
20
30
0 50 100 150 200 250
V
IN
[mV]
Integral Non-Linearity
(INL) [LSB]
16 bits - ADC converter (GDtot = 10) (version v5a)
Vbat=Vref=5.0V;fs=500kHz;OSR=512;NELCONV=2
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-0.25
-0.20
-0.15
-0.10
-0.05
0.00
0.05
0.10
0.15
0.20
0.25
0 50 100 150 200 250
V
IN
[mV]
Differential Non-Linearity
(DNL) [LSB]
Figure 8.14: GAIN=20, 16 bit ADC setting
16 bits - ADC converter (GDtot = 20) (versionv5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-10
-8
-6
-4
-2
0
2
4
6
8
10
0 20 40 60 80 100 120
V
IN
[mV]
Integral Non-Linearity
(INL) [LSB]
16 bits - ADC converter (GDtot = 20) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0 20406080100120
V
IN
[mV]
Differential Non-Linearity
(DNL) [LSB]
Figure 8.15: GAIN=100, 16 bit ADC setting
16 bits - ADC converter (GDtot = 100) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512;NELCONV = 2
f
RC
= 2MHz; IB_AMP(1:0) = 11;Vinn=0V
N sweep = 1201; average on 4 samples
-40
-30
-20
-10
0
10
20
30
40
0 5 10 15 20 25
VIN [mV]
Integral Non-Linearity
(INL) [LSB]
16 bits - ADC converter (GDtot = 100) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-1.0
-0.8
-0.6
-0.4
-0.2
0.0
0.2
0.4
0.6
0.8
0 5 10 15 20 25
V
IN
[mV]
Differential Non-Linearity
(DNL) [LSB]
28 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
The gain settings of each PGA stage for the plots of above figure are those of the table below.
8.10 Noise
Ideally, a constant input voltage VIN should result in a constant output code. However, because
of circuit noise, the output code may vary for a fixed input voltage. The figure shows the distri-
bution for the ADC alone (PGA1, 2, and 3 bypassed) and of several configurations of the
PGAs. Quantization noise is dominant in this case of ADC only, and, thus, the ADC thermal
noise is negligible.
One has to considere two points when computing final noise of the acquisition chain:
• this is a type of amplifier (switched-cap with constant capacitive load) that maintains its output
noise when changing the gain. Therefore input refered noise is lowered when the gain of an
amplifier is increased.
• the ADC is oversampled, and the number of samples taken lowers the thermal noise
Total input refered noise can be computed using the following equation:
PGA Gain
GDTOT
(V/V)
PGA1 Gain
GD1
(V/V)
PGA2 Gain
GD2
(V/V)
PGA3 Gain
GD3
(V/V)
1 1 bypassed bypassed
515bypassed
10 10 bypassed bypassed
20 10 2 bypassed
100 10 10 bypassed
1000 10 10 10
Table 8.6: Individual PGA gains for INL & DNL measurements
Table 8.7:
Figure 8.16: GAIN=1000, 16 bit ADC setting
16 bits - ADC converter (GDtot = 1000) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-80
-60
-40
-20
0
20
40
60
80
0 5 10 15 20 25
10*VIN [mV]
Integral Non-Linearity
(INL) [LSB]
16 bits - ADC converter (GDtot = 1000) (version v5a)
Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2
f
RC
= 2MHz; IB_AMP(1:0) = 11; Vinn=0V
N sweep = 1201; average on 4 samples
-2.0
-1.5
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
0 5 10 15 20 25
10*V
IN
[mV]
Differential Non-Linearity
(DNL) [LSB]
V2nin,
Vnout1,
gain1
-----------------
2Vnout2,
gain1gain2⋅
----------------------------------
2Vnout3,
gain1gain2gain3⋅⋅
------------------------------------------------------
2
++
numconv smax⋅
------------------------------------------------------------------------------------------------------------------------------------------------
=
29 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
Where Vn,outx is the rms output noise of amplifier x.
As one can see on the figures above, increase the gain of the first amplifier lowers the output
noise for constant global gain. It also lowers sensitivity to temperature drift as offset is better
compensated on first amplifier.
8.11 Gain Error and Offset Error
Gain error is defined as the amount of deviation between the ideal transfer function and the
measured transfer function (with the offset error removed). The left figure shows gain error vs.
temperature for different PGA gains. The curves are expressed in % of Full-Scale Range
(FSR)normalizedto25°C.
Amplifier Symbol Typical output noise per
over-sample Unit
PGA1 Vn,out1 205 uVrms
PGA2 Vn,out2 340 uVrms
PGA3 Vn,out3 365 uVrms
Typical output noise of ZoomingADC preamplifiers
Figure 8.17: Noise measured at the output of the ZoomingADC
ADC only
PGA1: off
PGA2: 1
PGA3: 10
PGA1: 1
PGA2: 10
PGA3: 10
PGA1: 1
PGA2: 10
PGA3: off
PGA1: 10
PGA2: 10
PGA3: off
30 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
Offset error is defined as the output code error for a zero volt input (ideally, output code = 0).
The measured offset errors vs. temperature curves for different PGA gains are depicted in the
right figure below. The output offset error, expressed in (LSB), is normalized to 25°C.
8.12 Power Consumption
Left figure below plots the variation of quiescent current consumption with supply voltage VDD,
as well as thedistributionbetween the 3 PGAstagesand the ADC. As shown in the right figure,
quiescent current consumption is not greatly affected by sampling frequency. It can be seen
that the quiescent current varies by about 20% between 100kHz and 2MHz. Quiescent current
consumption vs. temperature is shown in the secondset of figures, showing a relative increase
of nearly 40% between -45 and +85°C.
Supply ADC PGA1 PGA2 PGA3 TOTAL Unit
VDD =5V 250 165 130 175 720 µA
VDD =3V 190 150 120 160 620 µA
Table 8.8: Typical quiescent current distributions in acquisition chain (n = 16 bits, fS= 500kHz)
Figure 8.18: Gain and offset error vs temperature for several gains, normalized to 25°C, offset cancellation
disabled. When the offset cancellation is enabled, the offset remains below the LSB in all
temperature situations.
-0.4
-0.3
-0.2
-0.1
0.0
0.1
0.2
-50 -25 0 25 50 75 100
Temperature [°C]
Gain Error [% of FSR]
1
5
20
100
-40
-20
0
20
40
60
80
100
-50 -25 0 25 50 75 100
Temperature [°C]
Output Offset Error [LSB]
1
5
20
100
Figure 8.19: Quiescent current versus supply voltage for different gains and clock speed (not using the PGA and
ADC low power modes)
100
200
300
400
500
600
700
800
2.5 3.0 3.5 4.0 4.5 5.0 5.5
SupplyVoltage - V
DDA
[V]
QuiescentCurrent-I
Q
[µ
µ
µ
µA]
No PGAs,ADC only
PGA1 only
PGA1 & 2 only
PGA1, 2 & 3
500
550
600
650
700
750
800
2.5 3.0 3.5 4.0 4.5 5.0 5.5
SupplyVoltage - V
DDA
[V]
QuiescentCurrent-I
Q
[µ
µ
µ
µA]
500kHz
250kHz
62.5kHz
Sampling Frequency f
S
:
31 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
8.13 Power Supply Rejection Ratio
Figure below shows power supply rejection ratio (PSRR) at 3V and 5V supply voltage, and for
various PGA gains. PSRR is defined as the ratio (in dB) of voltage supply change (in V) to the
change in the converter output (in V). PSRR depends on both PGA gain and supply voltage
VDD.
Figure 8.20: Absolute and (b) relative change in quiescent current consumption vs. temperature
500
550
600
650
700
750
800
850
900
-50 -25 0 25 50 75 100 125
Temperature [°C]
Quiescent Current - I
Q
[µ
µ
µ
µA]
-25
-20
-15
-10
-5
0
5
10
15
20
-50-25 0 255075100125
Temperature [°C]
Relative Quiescent Current Change
I
Q
/I
Q,25°C
[%]
Figure 8.21: Absolute and (b) relative change in quiescent current consumption vs. clock speed
500
550
600
650
700
750
800
850
0 500 1000 1500 2000 2500 3000 3500
Frequency - f
RC
[kHz]
Quiescent Current - I
Q
[µ
µ
µ
µA]
-20
-15
-10
-5
0
5
10
15
0 500 1000 1500 2000 2500 3000 3500
Frequency - f
RC
[kHz]
Relative Quiescent Current Change
∆
∆
∆
∆I
Q
/I
Q,2MHz
[%]
32 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
8.14 Frequency Response
The incremental ADC of the XE88LC01 is an over-sampled converter with two main blocks:
an analog modulator and a low-pass digital filter. The main function of the digital filter is to re-
move the quantization noise introduced by the modulator. As shown below, this filter deter-
mines the frequency response of the transfer function between the output of the ADC and the
analog input VIN. Notice that the frequency axes are normalized to one elementary conversion
period OSR/fS. The plots below also show that the frequency response changes with the
number of elementary conversions NELCONV performed. In particular, notches appear for
NELCONV ≥2. These notches occur at:
(Hz)for
and are repeated every fS/OSR.
Information on the location of these notches is particularly useful when specific frequencies
must be filtered out by the acquisition system. For example, consider a 5Hz-bandwidth, 16-bit
sensing system where 50Hz line rejection is needed. Using the above equation and the plots
below, we set the 4th notch for NELCONV = 4 to 50Hz, i.e. 1.25⋅fS/OSR = 50Hz. The sampling
frequency is then calculated as fS= 20.48kHz for OSR = 512. Notice that this choice yields
also good attenuation of 50Hz harmonics.
Supply GAIN = 1 GAIN =5 GAIN = 10 GAIN = 20 GAIN =100 Unit
VDD =5V 79 78 100 99 97 dB
VDD =3V 72 79 90 90 86 dB
Table 8.9: PSRR (n = 16 bits, VIN =V
REF =2.5V,f
S= 500kHz)
Figure 8.22: Power supply rejection ratio (PSRR)
60
65
70
75
80
85
90
95
100
105
1 5 10 20 100
PGA Gain [V/V]
PSRR [dB]
VDD=3V
VDD=5V
ELCONV
S
NOTCH NOSR fi
if ⋅
⋅
=)( )1(,...,2,1 −= ELCONV
Ni
33 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
Figure 8.23: Frequency response: normalized magnitude vs. frequency for different NELCONV
0
0.2
0.4
0.6
0.8
1
1.2
01234
Normalized Frequency - f *(OSR/f
S
)[-]
Normalized Magnitude [-]
N
ELCONV
=4
0
0.2
0.4
0.6
0.8
1
1.2
01234
Normalized Frequency - f *(OSR/f
S
)[-]
Normalized Magnitude [-]
N
ELCONV
=8
0
0.2
0.4
0.6
0.8
1
1.2
01234
Normalized Frequency - f *(OSR/f
S
) [-]
Normalized Magnitude [-]
N
ELCONV
=2
0
0.2
0.4
0.6
0.8
1
1.2
01234
Normalized Frequency - f *(OSR/f
S
) [-]
Normalized Magnitude [-]
N
ELCONV
=1
34 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
9 Physical description
9.1 LQFP44 package
9.2 PLL-44L package
Figure 9.1: LQFP44 package, size in mm.
Figure 9.2: PLL-44L package,
35 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
9.3 Die form
9.3.1 Bonding pads location
Coordinates start with a point near to the bottom left border (with respect to above picture). X
is horizontal, Y is vertical.
Padsizeis85x85um.
Symbol Pad X Y Symbol Pad X Y
um um um um
1 PA(4) 52.6 4075.5 27 AC_R(2) 3314.1 47.6
2 PA(5) 52.6 3795.5 28 AC_A(7) 3958.4 522.4
3 NC 52.6 3515.5 29 NC 3958.4 807.4
4 PA(6) 52.6 3235.5 30 AC_A(6) 3958.4 1092.4
5 PA(7) 52.6 2955.5 31 AC_A(5) 3958.4 1377.4
6 PC(0) 52.6 2675.5 32 AC_A(4) 3958.4 1662.4
7 PC(1) 52.6 2395.5 33 AC_A(3) 3958.4 1947.4
8 PC(2) 52.6 2115.5 34 AC_A(2) 3958.4 2232.4
9 PC(3) 52.6 1835.5 35 NC 3958.4 2517.4
10 NC 52.6 1555.5 36 AC_A(1) 3958.4 2802.4
11 PC(4) 52.6 1275.5 37 AC_A(0) 3958.4 3087.4
12 PC(5) 52.6 995.5 38 AC_R(1) 3958.4 3372.4
13 PC(6) 52.6 715.5 39 AC_R(0) 3958.4 3657.4
14 PC(7) 52.6 435.5 40 Vss 3958.4 3942.4
15 PB(0) 398.5 47.6 41 Vbat 3597.6 4453.4
16 PB(1) 533.5 47.6 42 NC 3332.6 4453.4
17 PB(2) 668.5 47.6 43 Vreg 3067.6 4453.4
18 PB(3) 798.5 47.6 44 RESET 2802.6 4453.4
19 PB(4) 933.5 47.6 45 Vmult 2537.0 4453.4
20 NC 1063.5 47.6 46 OscIn 2007.6 4453.4
21 PB(5) 1198.5 47.6 47 NC 1742.6 4453.4
22 PB(6) 1328.5 47.6 48 OscOut 1477.6 4453.4
23 PB(7) 1463.5 47.6 49 PA(0) 1212.6 4453.4
24 TEST 1934.1 47.6 50 PA(1) 947.6 4453.4
25 NC 2394.1 47.6 51 PA(2) 682.6 4453.4
26 AC_R(3) 2854.1 47.6 52 PA(3) 417.6 4453.4
Table 9.1: Bonding pads location. Do not connect pads named NC. Connect Vss pad and substrate to Vss.
Figure 9.3: XE88LC01 in die: 4.1 x 4.6 mm2
pin 1
36 D0202-60
Data Sheet XE88LC01
Data Acquisition Microcontroller
10 Contacting XEMICS
You will find more information about the XE88LC01 and other XEMICS products, as well as
the addresses of our representatives and distributors for your region on http://www.xemics.com.
XEMICS 2002
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The
information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent or other industrial or intellectual property rights.
XEMICS PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR
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