High Performance ISM Band OOK/FSK Transmitter IC ADF7901 FEATURES GENERAL DESCRIPTION Single-chip, low power UHF transmitter 369.5 MHz to 395.9 MHz frequency operation using fractional-N PLL and fully integrated VCO 3.0 V supply voltage Data rates up to 50 kbps supported Low current consumption 26 mA at 12 dBm output at 384 MHz Power-down mode (<1 A) 24-lead TSSOP The ADF7901 is a low power OOK/FSK UHF transmitter designed for use in RF remote control devices. It is capable of frequency shift keying (FSK) modulation on eight different channels, selectable by three external control lines. OOK modulation is performed by modulating the PA control line. The on-chip VCO operates at 2x the output frequency. The division by 2 at the output of the VCO reduces the amount of PA feedthrough. As a result, OOK modulation depths of greater than 50 dB are easily achievable. The FSK_ADJ and ASK_ADJ resistors can be adjusted in the system to optimize output power for each modulation scheme. An additional 1.5 dB of output power is provided for the lower bank of channels to adjust for antenna performance. The CE line allows the transmitter to be powered down completely. In this mode, the leakage current is typically 0.1 A. FUNCTIONAL BLOCK DIAGRAM CREG2 OSC1 PA_EN OSC2 CVCO VDD VCO RFOUT PA R=1 RFGND PDF CHARGE PUMP LDO REGULATOR 1 FRACTIONAL N TXDATA LDO REGULATOR 2 - FSK CHANNEL SELECT CE DGND FSK1 FSK2 FSK3 CREG1 CREG2 RSET OOK_SEL RSET_FSK RSET_OOK 05349-001 DVDD Figure 1. Rev. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006 Analog Devices, Inc. All rights reserved. ADF7901 TABLE OF CONTENTS Features .............................................................................................. 1 Channel Frequencies.....................................................................9 General Description ......................................................................... 1 Layout Guidelines....................................................................... 10 Functional Block Diagram .............................................................. 1 Decoupling.............................................................................. 10 Specifications..................................................................................... 3 Regulator Stability .................................................................. 10 Absolute Maximum Ratings............................................................ 5 Grounding............................................................................... 10 ESD Caution.................................................................................. 5 Supply ...................................................................................... 10 Pin Configuration and Function Descriptions............................. 6 Digital Lines............................................................................ 10 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 11 Circuit Description........................................................................... 9 Ordering Guide .......................................................................... 11 Loop Filter ..................................................................................... 9 REVISION HISTORY 3/06--Rev. 0 to Rev. A Added Crystal ESR Parameter ........................................................ 4 Change to Figure 8 ......................................................................... 10 Updated Outline Dimensions ....................................................... 11 Changes to Ordering Guide .......................................................... 11 3/05--Revision 0: Initial Version Rev. A | Page 2 of 12 ADF7901 SPECIFICATIONS VDD =3.0 V; GND = 0 V; TA = TMIN to TMAX, unless otherwise noted. Typical specifications, TA = 25C. 1 Table 1. Parameter RF CHARACTERISTICS Output Frequency Ranges Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 Channel 7 Channel 8 Channel 9 Phase Frequency Detector Frequency TRANSMISSION PARAMETERS Transmit Rate FSK OOK Frequency Shift Keying FSK Separation 2 On/Off Keying Modulation Depth 3 Output Power Min/Max Range 4 fOUT 384 MHz fOUT > 384 MHz Occupied 20 dB BW OOK at 1 kbps FSK (PA Off/On) at10 Hz 5 LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH/IINL, Input Current CIN, Input Capacitance POWER SUPPLIES Voltage Supply DVDD Transmit Current Consumption 369.5 MHz to 376.9 MHz at 12 dBm 384 MHz at +12 dBm 388.3 MHz to 395.9 MHz at 10.5 dBm 384 MHz at 5 dBm Power-Down Mode Low Power Sleep Mode 6 Min 10 7 Typ Max Unit Comments/Conditions 369.5 371.1 375.3 376.9 384.0 388.3 391.5 394.3 395.9 9.8304 MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz 50 50 kbps kbps -34.8 +34.8 kHz kHz Data = 1 Data = 0 83 dB Output power = 12 dBm 15 12 10.5 dBm dBm dBm 28 26 461.9 461.9 kHz kHz 0.2 x VDD 1 10 V V A pF 2.124 3.0 V 26 26 21 17 mA mA mA mA 0.2 Rev. A| Page 3 of 12 1 A ADF7901 Parameter PHASE-LOCKED LOOP VCO Gain Spurious3, 7 Integer Boundary Reference Harmonics3 Second Harmonic VDD = 3.0 V Third Harmonic VDD = 3.0 V All Other Harmonics REFERENCE INPUT Crystal Reference Crystal ESR 8 POWER AMPLIFIER PA Output Impedance TIMING INFORMATION Crystal Oscillator to PLL Lock3 PA Enable to PA Ready-PLL Settle 9 TEMPERATURE RANGE (TA) Min Typ Max 30 Unit Comments/Conditions MHz/V At 384 MHz 100 kHz loop BW -45 -70 -23 -23 dBc dBc -24 -14 -21 -11 -18 dBc dBc dBc 80 MHz 9.8304 97 + 6.4 pF 2 100 0 At 384 MHz 3 250 50 ms s C 1 Operating temperature range is 0C to 50C. 2 Frequency Deviation = 58 x (9.8304 MHz)/214. Error in the crystal is reflected in variation in the desired deviation. 3 Not production tested; based on characterization. 4 The output power can be varied in both ASK/FSK mode by altering the relevant external resistor. 5 Measured using spectrum analyzer, 1 MHz span, 100 kHz RBW, maximum hold enabled. 6 Maximum power-down current specification applies for the OSC2 pin grounded. 7 Measured >461.9 kHz away from channel. 8 Maximum recommended crystal ESR. The crystal oscillator works with crystals with higher ESR, but this results in longer power-up times. 9 This specification refers to the time taken for the PLL to regain lock after the PA has been enabled. The PA is should only be enabled after the PLL has settled to the correct frequency. Rev. A | Page 4 of 12 ADF7901 ABSOLUTE MAXIMUM RATINGS TA = 25C, unless otherwise noted. 1 Table 2. Parameter VDD to GND 2 RFVDD to GND Digital I/O Voltage to GND Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP JA Thermal Impedance Lead Temperature, Soldering Vapor Phase (60 sec) Infrared (15 sec) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Value -0.3 V to +4.0 V -0.3 V to +4.0 V -0.3 V to VDD + 0.3 V 0C to 50C -65C to +125C 125C 150.4C/W 235C 240C 1 This device is a high performance, RF-integrated circuit with an ESD rating of <1 kV. It is ESD sensitive. Take proper precautions for handling and assembly. 2 GND = RFGND = DGND = 0 V. ESD CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. Rev. A| Page 5 of 12 ADF7901 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS DVDD 1 24 CREG2 CREG1 2 23 RSET CPOUT 3 22 PA_EN TxDATA 4 DGND 5 NC 6 DGND 7 OSC1 8 17 CVCO OSC2 9 16 OOK_SEL 10 15 RSET_OOK FSK1 11 14 CE FSK2 12 13 FSK3 21 DVDD TOP VIEW (Not to Scale) 20 RFOUT 19 RFGND 18 VCOIN RSET_FSK 05349-002 ADF7901 Figure 2. Pin Configuration Table 3. Pin Function Descriptions Pin No. 1 Mnemonic DVDD 2 CREG1 3 CPOUT 4 5 6 7 8 TxDATA DGND NC DGND OSC1 9 OSC2 10 11 12 13 14 15 OOK_SEL FSK1 FSK2 FSK3 CE RSET_OOK 16 RSET_FSK 17 CVCO 18 VCOIN 19 20 RFGND RFOUT Function Positive Supply for the Digital Circuitry. This must be 3.0 V. Decoupling capacitors to the analog ground plane should be placed as close as possible to this pin. A 2.2 F capacitor should be added at CREG1 to reduce regulator noise and improve stability. A reduced capacitor improves regulator power-on time but can cause higher spurious. Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. Digital FSK data to be transmitted is inputted on this pin. Ground for Digital Section. No Connect. Ground for Digital Section. The reference crystal should be connected between this pin and the OSC2 pin. The necessary crystal load capacitor should be tied between this pin and ground. The reference crystal should be connected between this pin and the OSC1 pin. The necessary crystal load capacitor should be tied between this pin and ground. A TCXO or external square wave can also be connected to this pin, with OSC1 left floating. A DC-blocking capacitor (4.7 nF is adequate) should be placed between the TCXO output and OSC2 pin. When not using an external regulator, a 1 M resistor can be tied between the OSC2 pin and ground to meet the power-down current specification of 1 A. A high on this pin selects operation in OOK mode at 384 MHz when CE is high. FSK Channel Select Pin. This represents the LSB of the channel select pins. FSK Channel Select Pin. FSK Channel Select Pin. Bringing CE low puts the ADF7901 into power-down, drawing <1 A of current. The value of this resistor sets the output power for data = 1 in OOK mode. A resistor of 3.6 k provides the maximum output power. Increasing the resistor reduces the power and the current consumption. A lower resistor value than 3.6 k can be used to increase the power to a maximum of 14 dBm. The PA does not operate efficiently in this mode. The value of this resistor sets the output power in FSK mode. A resistor of 3.6 k provides maximum output power. Increasing the resistor reduces the power and the current consumption. A resistor value lower than 3.6 k can be used to increase the power to a maximum of 14 dBm. The PA does not operate efficiently in this mode. A 22 nF capacitor should be tied between the CVCO and CREG2 pins. This line should run underneath the ADF7901. The capacitor is necessary to ensure stable VCO operation. The tuning voltage on this pin determines the output frequency of the voltage controlled oscillator (VCO). The higher the tuning voltage the higher the output frequency. The output of the loop filter is connected here. Ground for Output Stage of Transmitter. The modulated signal is available at this pin. Output power levels are from -5 dBm to +12 dBm. The output should be impedance matched using suitable components to the desired load. Rev. A | Page 6 of 12 ADF7901 Pin No. 21 Mnemonic DVDD 22 PA_EN 23 24 RSET CREG2 Function Voltage Supply for VCO and PA Section. It should be supplied with 3.0 V. Decoupling capacitors to the ground plane should be placed as close as possible to this pin. This pin is used to enable the power amplifier. It should be modulated with the OOK data in OOK mode. In FSK mode, it should be enabled when the PLL is locked. External Resistor. Sets charge pump current and some internal bias currents. Use 3.6 k as default. A 2.2 F capacitor should be added at CREG2 to reduce regulator noise and improve stability. A reduced capacitor improves regulator power-on time but can cause higher spurs. Rev. A| Page 7 of 12 ADF7901 TYPICAL PERFORMANCE CHARACTERISTICS Ref 15dBm Avg Log 10 dB/ OUTPUT POWER (dBm) 16 Mkr1 10.00kHz Noise -89.55dB/Hz Atten 30dB 1R 12 RBW 300.0000000Hz 8 PAvg 1 W1 S2 S3 FS AA 4 2 3 4 5 6 RSET 7 8 9 10 Center 395.948 29MHz #Res BW 300Hz Span 50kHz Sweep 2.118 s (601 pts) VBW 300Hz 05349-006 0 05349-004 (f): f<50k Swp Figure 5. Phase Noise at Channel 9 Figure 3. Output Power vs. RSET FSK, Upper FSK Channels, Measured into 50 Ref 15dBm Peak Log 10 4R dB/ 2 35 4 30 Mkr4 1.59GHz -21.30dB Atten 30dB 1 Marker Trace Type 1 (1) Freq 2 (1) Freq 3 (1) Freq 4 (1) Freq X Axis 400MHz 800MHz 1.19GHz 1.59GHz Amplitude -25.56dB -13.89dB -34.53dB -21.30dB IDD (mA) 3 25 20 15 5 6 7 8 OUTPUT POWER (dBm) 9 10 Figure 4. Current Consumption vs. Output Power, Upper FSK Channels, Measured into 50 Rev. A | Page 8 of 12 Center 5.50GHz #Res BW 1MHz VBW 1MHz Span 10.5GHz Sweep 17.52 ms (601 pts) Figure 6. Harmonic Levels--Up to Fourth Harmonic, Measured at Channel 9 into 50 05349-007 4 05349-005 LgAv 10 ADF7901 CIRCUIT DESCRIPTION Table 4. Frequency (MHz) 369.5 371.1 375.3 376.9 384.0 388.3 391.5 394.3 395.9 FSK3 0 0 0 0 Don't care 1 1 1 1 FSK2 0 0 1 1 Don't care 0 0 1 1 FSK1 0 1 0 0 Don't care 0 1 0 1 OOK_SEL 0 0 0 0 1 CHANNEL FREQUENCIES The nine channel frequencies listed in Table 4 are obtainable from a single 9.8304 MHz crystal reference by changing the value of the N and F numbers in the fractional PLL, using control lines FSK1, FSK2, and FSK3. The channel frequency is given by FCHANNEL = FREF x (N + F) 0 0 0 0 LOOP FILTER The loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the VCO to the desired frequency. It also attenuates spurious levels generated by the PLL. The recommended loop filter design for this circuit is 297 kHz. This is based on the trade-off between attenuation of beat note spurs and the need to minimize chirp when the PA is turned on. However, the VCO is tuned to operate over a frequency range of 344 MHz to 401 MHz (typically). Therefore, any channel frequency within this range can be obtained if the required reference frequency is used. The N and F numbers for each channel are listed in Table 5, together with the corresponding channel frequencies for 9.8304 MHz and, for example purposes, frequencies for 10 MHz. With the 10 MHz reference, the two largest N settings give channel frequencies above the maximum VCO output frequency and are therefore invalid. Frequency deviation is also dependent on reference frequency. The relationship is given by FDEV = 58 x (9.8304 MHz)/214 Therefore, the frequency deviation is 34.8 kHz when the 9.8304 MHz reference is used and 35.4 kHz when the 10 MHz reference is used. R2 = 6.2k CHARGE PUMP OUT VCO C1 = 33pF C2 = 390pF C3 = 10pF 05349-008 R1 = 3k Figure 7. Improved spurious performance in FSK mode can be achieved by using a narrower loop bandwidth. For a data rate of 20 kbps, a loop bandwidth of roughly 50 kHz would be suitable. The following components give a loop bandwidth of 51.1 kHz: C1 = 680 pF C2 = 15 nF C3 = 180 pF Table 5. N 37 37 38 38 39 39 39 40 40 R1 = 510 R2 = 6.2 k ADIsimPLL is a free software tool offered by Analog Devices for assistance in designing with ADI's frequency synthesizers and ISM band transmitters. To select the correct loop filter components for use with the ADF7901, open a project for the ADF7012 device. Then, enter the desired output carrier frequency and loop bandwidth, and use the 870 A charge pump current setting. ADIsimPLL can be downloaded from www.analog.com. Rev. A| Page 9 of 12 F 2406/4096 3073/4096 727/4096 1374/4096 256/4096 2048/4096 3381/4096 452/4096 1118/4096 Channel Frequency (MHz) 9.8304 MHz Ref 10 MHz Ref 369.5 375.9 371.1 377.5 375.3 381.8 376.9 383.4 384.0 390.6 388.3 395 391.5 398.3 394.3 N/A 395.9 N/A ADF7901 22nF 2.2F 2.2F MATCHING RFOUT TO 50 CVCO CREG2 DVDD CREG1 RSET 27nH 5TH-ORDER, LOW-PASS FILTER 3.6k 22nH 5.6pF 1.5pF 22nH RFOUT VCOIN CPOUT ANTENNA 3pF VCOIN 8pF 3pF ADF7901 36nH MATCHING 50 TO ANTENNA RSET_FSK 3.6k RSET_OOK 3.6k FSK1 FSK2 OSC2 FSK3 OOK_SEL 9.8304MHz OSC1 PA_EN CE 33pF 33pF GND NOTES 1. DECOUPLING CAPACITORS HAVE BEEN OMITTED FOR CLARITY. 05349-003 TxDATA Figure 8. Applications Diagram for the ADF7901 in a Remote Control System LAYOUT GUIDELINES Grounding The layout of the board is crucial to ensuring low levels of spurious and harmonics. Emphasis should be placed on grounding once the decoupling capacitors have been added. The PA stage switches currents of 15 mA in maximum power mode. This causes changes in the ground resulting in large return currents that can radiate to other parts of the board. The shortest and least obstructed ground from RFGND back to the ground of the battery should be ensured. A 4-layer board helps, as well as flooding the top layer. The ground paths should not have any vias and should be wide tracks. Decoupling Decoupling capacitors (high frequency 22 pF, low frequency 100 nF) should be placed as close as possible to the supply pins on the part. Low size 0402 and 0603 components are recommended for the high frequency rejection on the supply. Regulator Stability A minimum of 1 F is needed on both CREG1 and CREG2 to ensure stability. An additional 22 pF capacitor can be added to reject higher frequency noise. Because many of the internal blocks run off the regulator, it is critical to reduce its noise. Low size 0402 and 0603 components are recommended for the high frequency rejection on the supply. Supply The supply tracks can be routed through vias, because they act as free inductors and make layout easier on a 2-layer board (see the Decoupling section). Tracks should be wide. Digital Lines Digital lines should contain a large resistor in series. This impedance blocks signals of many frequencies, including harmonics and the carrier frequency. Long control lines can act as antennae. It can be useful to add capacitance to ground. There is some capacitance to ground provided by the lines and at the input of the digital pins. Rev. A | Page 10 of 12 ADF7901 OUTLINE DIMENSIONS 7.90 7.80 7.70 24 13 4.50 4.40 4.30 6.40 BSC 1 12 PIN 1 0.65 BSC 0.15 0.05 0.30 0.19 1.20 MAX SEATING PLANE 0.20 0.09 8 0 0.75 0.60 0.45 0.10 COPLANARITY COMPLIANT TO JEDEC STANDARDS MO-153AD Figure 9. 24-Lead Thin Shrink Small Outline Package [TSSOP] (RU-24) Dimensions shown in millimeters ORDERING GUIDE Model ADF7901BRU ADF7901BRU-REEL ADF7901BRU-REEL7 ADF7901BRUZ 1 ADF7901BRUZ-RL1 ADF7901BRUZ-RL71 EVAL-ADF7901EB 1 Temperature Range 0C to 50C 0C to 50C 0C to 50C 0C to 50C 0C to 50C 0C to 50C Package Description 24-Lead Thin Shrink Small Outline Package (TSSOP) 24-Lead Thin Shrink Small Outline Package (TSSOP) 24-Lead Thin Shrink Small Outline Package (TSSOP) 24-Lead Thin Shrink Small Outline Package (TSSOP) 24-Lead Thin Shrink Small Outline Package (TSSOP) 24-Lead Thin Shrink Small Outline Package (TSSOP) Evaluation Board Z = Pb-free part. Rev. A| Page 11 of 12 Package Option RU-24 RU-24 RU-24 RU-24 RU-24 RU-24 ADF7901 NOTES (c)2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05349-0-3/06(A) Rev. A | Page 12 of 12