CY25811/12/14
Spread Spectrum Clock Generator
Cypress Semiconductor Corporation • 198 Champion Court • San Jose
,
CA 95134-1709 • 408-943-2600
Document Number: 38-07112 Rev. *G Revised October 22, 2008
Features
■
4 to 32 MHz input frequency range
■
4 to 128 MHz output frequency range
■
Accepts clock, cryst al, and resonator input s
■
1x, 2x, and 4x frequency multiplicatio n:
❐
CY25811: 1x; CY25812: 2x; CY25814: 4x
■
Center and down spread modulatio n
■
Low power dissipation:
❐
3.3V = 52 mW - typ at 6 MHz
❐
3.3V = 60 mW - typ at12 MHz
❐
3.3V = 72 mW - typ at 24 MHz
■
Low cycle to cycle jitter:
❐
8 MHz = 480 ps-max
❐
16 MHz = 400 ps-max
❐
32 MHz = 450 ps-max
■
Available in 8-pin SOIC and TSSOP packages
■
Commercial and industrial temperature ranges
Applications
■
Printers and MFPs
■
LCD panels
■
Digital copiers
■
PDAs
■
CD-ROM, VCD, and DVD
■
Networking, LAN, and WAN
■
Scanners
■
Modems
■
Embedded digital systems
Benefits
■
Peak EMI reduction by 8 to 16 dB
■
Fast time to market
■
Cost reduction
S1 S0
FRSEL
300K
VDD
VSS
XIN
XOUT
SSCLK
8pF
REFERENCE
DIVIDER
PD and
CP LF
VCO
VCO
COUNTE
R
COUNTER
and
MUX
INPUT
DECODER
LOGIC
1
7
8
25
MODULATION
CONTROL
3 46
8pF
Logic Block Diagram
[+] Feedback
CY25811/12/14
Document Number: 38-07112 Rev. *G Page 2 of 13
Pinouts
Figure 1. Pin Diagram - 8 Pin SOIC/TSSOP
Table 1. Pin Definition - 8 Pin SOIC/TSSOP
Functional Description
The CY25811/12/14 products are Spread Spectrum Clock
Generator (SSCG) ICs used for the purpose of reducing electro-
magnetic interference (EMI) found in today’s high speed digital
electronic systems.
The devices use a Cypress proprietary phase-locked loop (PLL)
and Spread Spectrum Clock (SSC) technology to synthesize and
modulate the frequency of the input clock. By frequency
modulating the clock, the measured EMI at the fundamental and
harmonic frequencies is greatly reduced.
This reduction in radiated energy significantly reduces the cost
of complying with regulatory agency requirements and improves
time to market without degrading system performance.
The input frequency range is 4 to 32 MHz and accepts clock,
crystal and ceramic resonator inputs. The output clock can be
selected to produce 1x, 2x, or 4x multiplication of the input
frequency with Spread Spectrum Frequency Modulation.
The use of 2x or 4x frequency multiplication eliminates the need
for higher order crystals and enables the user to generate up to
128 MHz S pread S pectrum Clock (SSC) by using only first order
crystals. This reduces the cost while improving the system clock
accuracy, performance, and complexity.
The user selects Center Spread or Down Spread frequency
modulation based on four discrete valu es of Spread % for each
Spread mode with the option of a Non Spread mode for system
test and verification purposes.
The CY2581 1/12/14 products are available in an 8 pin SOIC -150
mil package with a commercia l operating temperature rang e of
0 to 70°C and Industrial Temperature range of –40 to 85°C. Refer
to CY25568 for multiple clock output options such as modulated
and unmodulated clock outputs or Power-down function. For
Automotive applications, refer to CY25811/12/14SE data sheets.
Input Frequency Range and Selection
The CY25811/12/14 inpu t freq uen cy range is 4 to 3 2 MHz. This
range is divided into three segments and controlled by a 3-Level
FRSEL pin as given in Table 2.
1
2
3
4
8
7
6
5
XIN/CLKIN
VSS
S1
S0
XOUT
VDD
FRSE L
SSCLK
CY25811
CY25812
CY25814
Pin No. Name Type Description
1Xin/CLK Cryst al, ceramic resonator or clock input pin
2VSS Power supply ground.
3S1 Digital Spread% control pin. 3-Level input (H-M-L). Default = M.
4S0 Digital Spread% control pin. 3-Level input (H-M-L). Default = M.
5 SSCLK Spread Spectrum output clock.
6 FRSEL Input frequency range selection digital control input. 3-Level input (H-M-L). Default = M.
7VDD Positive power supply.
8XOUT Crystal or ceramic resonator output pin.
Table 2. Input Frequency Selection
FRSEL Input Frequency Range
0 4.0 to 8.0 MHz
1 8.0 to 16.0 MHz
M 16.0 to 32.0 MHz
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CY25811/12/14
Document Number: 38-07112 Rev. *G Page 3 of 13
Spread Percentage Selection
The CY25811/12/14 SSCG products provide Center-Spread, Down-Spread, and No-Spread functions. The amount of Spread
percentage is selected using 3-Level. S0 and S1 digital inputs and Spread percent values are given in Table 3.
3-Level Digital Inputs
S0, S1, and FRSEL digital inputs are designed to sense 3
different logic levels designated as High “1”, Low “0”, and Middle
“M”. With this 3-Level digital input logic, the 3-Level Logic detects
nine different logic states.
S0, S1, and FRSEL pins include an on chip 20K (10K and 10K)
resistor divider. No external application resistors are needed to
implement the 3-Level logi c levels as shown here:
Logic Level “0”: 3–Level logic pin connected to GND.
Logic Level “M”: 3–Level logic pin left floating (no connection).
Logic Level “1”: 3–Level logic pin connected to V
DD
.
Figure 2 illustrates how to implement 3–Level Logic.
Figure 2. 3–Level Logic
Modulation Rate
SSCGs use frequency modulation (FM) to distribute energy over
a specific band of frequ encies. The maximum frequency of the
clock (fmax), and minimum frequency of the clock (fmin)
determine this band of frequencies. The time required to
transition from fmin to fmax and back to fmin is the period of the
Modulation Rate. The Modulation Rate of SSCG clocks are
generally referred to in terms of frequency, or:
fmod = 1/Tmod.
The input clock frequency , fin, and the internal divider determine
the Modulation Rate.
In CY25811/2/4 devices, the (Spread Spectrum) modulation
Rate, fmod, is given by the following formula:
fmod = fin/DR
Here fmod is the Modulation Rate, fin is the Input Frequency , and
DR is the Divider Ratio as given in Table 4. Note that Input
Frequency Range is set by FRSEL.
Table 3. Spread Percent Selection
XIN
(MHz) FRSEL S1 = 0
S0 = 0 S1 = 0
S0 = M S1 = 0
S0 = 1 S1 = M
S0 = 0 S1 = 1
S0 = 1 S1 = 1
S0 = 0 S1 = M
S0 = 1 S1 = 1
S0 = M S1 = M
S0 = M
Center
(%) Center
(%) Center
(%) Center
(%) Down
(%) Down
(%) Down
(%) Down
(%) No Spread
4-5 0 ±1.4 ± 1.2 ± 0.6 ± 0.5 –3.0 –2.2 –1.9 –0.7 0
5-6 0 ±1.3 ± 1.1 ± 0.5 ± 0.4 –2.7 –1.9 –1.7 –0.6 0
6-7 0 ±1.2 ± 0.9 ± 0.5 ± 0.4 –2.5 –1.8 –1.5 –0.6 0
7-8 0 ±1.1 ± 0.9 ± 0.4 ± 0.3 –2.3 –1.7 –1.4 –0.5 0
8-10 1 ±1.4 ±1.2 ± 0.6 ± 0.5 –3.0 –2.2 –1.9 –0.7 0
10-12 1 ±1.3 ±1.1 ± 0.5 ± 0.4 –2.7 –1.9 –1.7 –0.6 0
12-14 1 ±1.2 ± 0.9 ± 0.5 ± 0.4 –2.5 –1.8 –1.5 –0.6 0
14-16 1 ±1.1 ± 0.9 ± 0.4 ± 0.3 –2.3 –1.7 –1.4 –0.5 0
16-20 M ±1.4 ±1.2 ± 0.6 ± 0.5 –3.0 –2.2 –1.9 –0.7 0
20-24 M ±1.3 ±1.1 ± 0.5 ± 0.4 –2.7 –1.9 –1.7 –0.6 0
24-28 M ±1.2 ± 0.9 ± 0.5 ± 0.4 –2.5 –1.8 –1.5 –0.6 0
28-32 M ±1.1 ± 0.9 ± 0.4 ± 0.3 –2.3 –1.7 –1.4 –0.5 0
LOGIC
MIDDLE (M) LOGIC
HIGH (H)
S0, S1
and
FRSEL
to VDD
S0, S1
and
FRSEL
UNCONNECTED
S0, S1
and
FRSEL
to VSS
VSS
LOGIC
LOW (0)
Table 4. Modulation Rate Divider Ratios
FRSEL Input Frequency Range
(MHz) Divider Ratio
(DR)
0 4 to 8 128
1 8 to 16 256
M 16 to 32 512
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CY25811/12/14
Document Number: 38-07112 Rev. *G Page 4 of 13
Input and Output Frequency Selection
The relationship between input frequency and output frequency in device selection and FRSEL setting is given in Table 5. As shown,
the input frequency range is selected b y FRSEL and is the same for CY25811, CY25812, and C Y25814. Th e selection of CY25811
(1x), CY25812 (2x), or CY25814 (4x) determines the frequency multiplication at the output (SSCLK, Pin 5) with respect to input
frequency (XIN, Pin-1).
Table 5. Input and Output Fre quen cy Selection
Input Frequency Range
(MHz) FRSEL Product Multiplication Output Freq uency Range
(MHz)
4 to 8 0 CY25811 1x 4 to 8
8 to 16 1 CY25811 1x 8 to 16
16 to 32 M CY25811 1x 16 to 32
4 to 8 0 CY25812 2x 8 to 16
8 to 16 1 CY25812 2x 16 to 32
16 to 32 M CY25812 2x 32 to 64
4 to 8 0 CY25814 4x 16 to 32
8 to 16 1 CY25814 4x 32 to 64
16 to 32 M CY25814 4x 64 to 128
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CY25811/12/14
Document Number: 38-07112 Rev. *G Page 5 of 13
Absolute Maximum Conditions
(both Commercial and Industrial Grades)
[1,2]
Parameter Description Condition Min Max Unit
V
DD
Supply Voltage –0.5 4.6 V
V
IN
Input Voltage Relative to V
SS
–0.5 V
DD
+ 0.5 VDC
T
S
Temperature, Storage Non Functional –65 150 °C
T
A1
Temperature, Operating Ambie nt Functional, C-Grade 0 70 °C
T
A2
Temperature, Operating Ambie nt Functional, I-Grade –40 85 °C
T
J
Temperature, Junction Functional – 150 °C
ESD
HBM
ESD Protection (Human Body Model) MIL-STD-883, Meth od 3015 2000 – V
UL-94 Flammability Rating @1 /8 in. V–0
MSL Moisture Sensitivity Level 1
DC Electrical Specifications
(Commercial Grade)
Parameter Description Condition Min Max Unit
V
DD
3.3 Operating Voltage 3.3 ± 10% 3.97 3.63 V
V
IL
Input Low Voltage S0, S1 and FRSEL Inputs 0 0.15V
DD
V
V
IM
Input Middle Voltage S0, S1 and FRSEL Inputs 0.40V
DD
0.60V
DD
V
V
IH
Input High Voltage S0, S1 and FRSEL Inputs 0.85V
DD
V
DD
V
V
OL1
Output Low Voltage I
OL
= 4 ma, SSCLK Output – 0.4 V
V
OL2
Output Low Voltage I
OL
= 10 ma, SSCLK Output – 1.2 V
V
OH1
Output High Voltage I
OH
= 4 ma, SSCLK Output 2.4 – V
V
OH2
Output High Voltage I
OH
= 6 ma, SSCLK Output 2.0 – V
C
IN1
Input Pin Capacitance XIN (Pin 1) and XOUT (Pin 8) 3.5 9.0 pF
C
IN2
Input Pin Capacitance All Digital Inputs 2.8 6.0 pF
C
L
Output Load Capacitor SSCLK Output – 15 pF
I
DD1
Dynamic Supply Current Fin = 12 MHz, no load – 28 mA
I
DD2
Dynamic Supply Current Fin = 24 MHz, no load – 33 mA
I
DD3
Dynamic Supply Current Fin = 32 MHz, no load – 40 mA
Notes
1. Operation at any Absolute Maximum Rating is not implied.
2. Single Power Supply: The voltage on any input or I/O pin cannot exceed the powe r pi n during power up.
[+] Feedback
CY25811/12/14
Document Number: 38-07112 Rev. *G Page 6 of 13
AC Electrical Specifications
(Commercial Gra de)
Parameter Description Condition Min Max Unit
F
IN
Input Frequency Range Clock, Crystal, or Ceramic Resonator Input 4 32 MHz
T
R1
Clock Rise Time SSCLK, CY25811 an d CY25812 2.0 5.0 ns
T
F1
Clock Fall Time SSCLK, CY25811 and CY25812 1.6 4.4 ns
T
R2
Clock Rise Time SSCLK, only CY25814 when FRSEL = M 1.0 2.2 ns
T
F2
Clock Fall Time SSCLK, only CY25814 when FRSEL = M 0.8 2.2 ns
T
DCIN
Input Clock Duty Cycle XIN 40 60 %
T
DCOUT
Output Clock Duty Cycle SSCLK 40 60 %
T
CCJ1
Cycle to Cycle Jitter, Spread on Fin = 4 MHz, Fout = 4 MHz, CY25811 – 800 ps
T
CCJ2
Cycle to Cycle Jitter, Spread on Fin = 8 MHZ, Fout = 8 MHz, CY25811 – 480 ps
T
CCJ3
Cycle to Cycle Jitter, Spread on Fin = 8 MHz, Fout = 16 MHz, CY25812 – 400 ps
T
CCJ4
Cycle to Cycle Jitter, Spread on Fin = 16 MHz, Fout = 32 MHz, CY25812 – 450 ps
T
CCJ5
Cycle to Cycle Jitter, Spread on Fin = 16 MHz, Fout = 64 MHz, CY25814 – 550 ps
T
CCJ6
Cycle to Cycle Jitter, Spread on Fin = 32 MHz, Fout = 128 MHz, CY258 14 – 380 ps
T
SU
PLL Lock Time Fom V
DD
3.0V to valid SSCLK – 3 ms
DC Electrical Specifications
(Industrial Grade)
Parameter Description Condition Min Max Unit
V
DD
3.3 Operating Voltage 3.3 ± 5% 3.135 3.465 V
V
IL
Input Low Voltage S0, S1 and FRSEL Inputs 0 0.13V
DD
V
V
IM
Input Middle Voltage S0, S1 and FRSEL Inputs 0.40V
DD
0.60V
DD
V
V
IH
Input High Voltage S0, S1 and FRSEL Inputs 0.85V
DD
V
DD
V
V
OL1
Output Low Voltage I
OL
= 4 ma, SSCLK Output – 0.4 V
V
OL2
Output Low Voltage I
OL
= 10 ma, SSCLK Output – 1.2 V
V
OH1
Output High Voltage I
OH
= 4 ma, SSCLK Output 2.4 – V
V
OH2
Output High Voltage I
OH
= 6 ma, SSCLK Output 2.0 – V
C
IN1
Input Pin Capacitance XIN (Pin 1) and XOUT (Pin 8) 3.5 9.0 pF
C
IN2
Input Pin Capacitance All Digital Inputs 2.8 6.0 pF
C
L
Output Load Capacitor SSCLK Output – 15 pF
I
DD1
Dynamic Supply Current Fin = 12 MHz, no load – 28 mA
I
DD2
Dynamic Supply Current Fin = 24 MHz, no load – 33 mA
I
DD3
Dynamic Supply Current Fin = 32 MHz, no load – 41 mA
AC Electrical Specifications
(Industrial Grade)
Parameter Description Condition Min Max Unit
F
IN
Input Frequency Range Clock, Crystal or Ceramic Resonator Input 4 32 MHz
T
R1
Clock Rise Time SSCLK, CY25811, and CY25812 2.0 5.0 ns
T
F1
Clock Fall Time SSCLK, CY25811, and CY25812 1.6 4.4 ns
T
R2
Clock Rise Time SSCLK, only CY25814 when FRSEL = M 1.0 2.2 ns
T
F2
Clock Fall Time SSCLK, only CY25814 when FRSEL = M 0.8 2.2 ns
T
DCIN
Input Clock Duty Cycle XIN 40 60 %
T
DCOUT
Output Clock Duty Cycle SSCLK 40 60 %
T
CCJ1
Cycle to Cycle Jitter, Spread on Fin = 6MHz, CY25811/12/14 – 650 ps
[+] Feedback
CY25811/12/14
Document Number: 38-07112 Rev. *G Page 7 of 13
Characteristic Curves
The following curves demonstrate the characteristic behavior of CY258 11/12/14 whe n tested over a number of environmental and
application specific parameters. These are typical perfo rmance curve s and are n ot meant to replace any parameter specified in DC
and AC Specification tables.
Figure 3. Characteristic Curves
.
T
CCJ2
Cycle-to-Cycle Jitter, Spread on Fin = 12MHZ, CY25811/12/14 – 630 ps
T
CCJ3
Cycle-to-Cycle Jitter, Spread on Fin = 24MHz, CY25811/12/1 4 – 520 ps
T
SU
PLL Lock Time From V
DD
3.0V to valid SSCLK – 4 ms
AC Electrical Specifications
(Industrial Grade) (continue d)
Parameter Description Condition Min Max Unit
0
100
200
300
400
500
600
4 8 12 16 20 24 28 32
Input Frequency (MH z)
CCJ (ps)
1.75
2
2.25
2.5
2.75
-40 -25 -10 5 20 35 50 65 80 95 110 125
Temp (C)
BW %
6.0 MH z
32.0 MH z
1.8
1.9
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7
VDD (volts)
BW (%)
4.0 M Hz
8.0 M Hz
10
12
14
16
18
20
22
24
26
28
30
4 4.5 5 5.5 6 6.5 7 7.5 8
Frequency (MHz), no load, normalized to FRSEL = 0, (4 - 8 MHz).
IDD (mA)
FRSEL = 0
4 - 8 MHz
FRSEL = 1
8 - 16 MH z
FRSEL = M
16 - 32 MH z
Jitter vs. Input Frequency (No Load) Bandwidth % vs. Temperature
IDD vs. Frequency (FRSEL = 0, 1, M) Bandwidth % vs. VDD
[+] Feedback
CY25811/12/14
Document Number: 38-07112 Rev. *G Page 8 of 13
SSCG Profiles
CY25811/12/14 SSCG products use a non-linear “optimized” frequency profile as shown In Figure 4. The use of Cypress proprietary
“optimized” frequency profile maintains flat energy distribution over the fundamental and higher order harmonics. This results in
additional EMI reduction in el ectronic systems.
Figure 4. Spread Spectrum Profiles (Frequency versus Time)
Xin = 6.0 MHz SSCLK1 = 6.0 MHz
S1, S0 = 0
FRSEL = 0 P/N = CY25811
Xin = 24.0 MHz SSCLK1 = 24.0 MHz
S1, S0 = 0
FRSEL = M P/N = CY25811
Xin = 12.0 MHz SSCLK1 = 48.0 MHz
S1, S0 = 0
FRSEL = 1 P/N = CY25814
Xin = 24.0 MHz SSCLK1 = 96.0 MHz
S1, S0 = 0
FRSEL = M P/N = CY25814
[+] Feedback
CY25811/12/14
Document Number: 38-07112 Rev. *G Page 10 of 13
Package Drawing and Dimensions
Figure 5. 8-Pin (150-Mil) SOIC S8 (51-85066)
Ordering Information
Part Number Package Type Product Flow
Pb-Free Devices
CY25811SXC 8-pin SOIC Commercial, 0° to 70°C
CY25811SXCT 8-pin SOIC – Tape and Reel Commercial, 0° to 70°C
CY25811SXI 8-pin SOIC Industrial, –40° to 85°C
CY25811SXIT 8-pin SOIC – Tape and Reel Industrial, –40° to 85°C
CY25811ZXC 8-pin TSSOP Commercial, 0° to 70°C
CY25811ZXCT 8-pin TSSOP – Tape and Reel Commercial, 0° to 70°C
CY25812SXC 8-pin SOIC Commercial, 0° to 70°C
CY25812SXCT 8-pin SOIC – Tape and Reel Commercial, 0° to 70°C
CY25812SXI 8-pin SOIC Industrial, –40° to 85°C
CY25812SXIT 8-pin SOIC – Tape and Reel Industrial, –40° to 85°C
CY25812ZXC 8-pin TSSOP Commercial, 0° to 70°C
CY25812ZXCT 8-pin TSSOP – Tape and Reel Commercial, 0° to 70°C
CY25814SXC 8-pin SOIC Commercial, 0° to 70°C
CY25814SXCT 8-pin SOIC – Tape and Reel Commercial, 0° to 70°C
CY25814SXI 8-pin SOIC Industrial, –40° to 85°C
CY25814SXIT 8-pin SOIC – Tape and Reel Industrial, –40° to 85°C
CY25814ZXC 8-pin TSSOP Commercial, 0° to 70°C
CY25814ZXCT 8-pin TSSOP – Tape and Reel Commercial, 0° to 70°C
SEATING PLANE
PIN1ID
0.230[5.842]
0.244[6.197]
0.157[3.987]
0.150[3.810]
0.189[4.800]
0.196[4.978]
0.050[1.270]
BSC
0.061[1.549]
0.068[1.727]
0.004[0.102]
0.0098[0.249]
0.0138[0.350]
0.0192[0.487]
0.016[0.406]
0.035[0.889]
0.0075[0.190]
0.0098[0.249]
1. DIMENSIONS IN INCHES[MM] MIN.
MAX.
0°~8°
0.016[0.406]
0.010[0.254] X 45°
2. PIN 1 ID IS OPTIONAL,
ROUND ON SINGLE LEADFRAME
RECTANGULAR ON MATRIX LEADFRAME
0.004[0.102]
14
58
3. REFERENCE JEDEC MS-012
PART #
S08.15 STANDARD PKG.
SZ08.15 LEAD FREE PKG.
4. PACKAGE WEIGHT 0.07gms
51-85066-*C
[+] Feedback
CY25811/12/14
Document Number: 38-07112 Rev. *G Page 11 of 13
Figure 6. 8-Pin Thin Shrunk Small Outline Package (4.40 MM Body) Z8 (51-85093)
8
PIN1ID
SEATING
PLANE
1
BSC.
BSC
0°-8°
PLANE
GAUGE
2.90[0.114]
1.10[0.043] MAX.
0.65[0.025]
0.20[0.008]
0.05[0.002]
6.50[0.256]
0.076[0.003]
6.25[0.246]
4.50[0.177]
4.30[0.169]
3.10[0.122]
0.15[0.006]
0.19[0.007]
0.30[0.012]
0.09[[0.003]
0.25[0.010]
0.70[0.027]
0.50[0.020]
0.95[0.037]
0.85[0.033]
DIMENSIONS IN MM[INCHES] MIN.
MAX.
51-85093-*A
[+] Feedback
CY25811/12/14
Document Number: 38-07112 Rev. *G Page 12 of 13
Document History Page
Document Title: CY2581 1/12/14 Spread Spectrum Clock Generator
Document Number: 38-07112
Rev. ECN NO. Submis-
sion Date Orig. of
Change Description o f Change
** 107516 06/14/02 NDP Converted from IMI to Cypress
*A 108002 06/29/02 NDP Deleted Junction Temp. in Absolute Maximum Ratings
*B 121578 01/29/03 RGL Converted from Word to FrameMaker
Added 8-pin TSSOP package in Commercial Temp. only
Added an Industrial Temperature Range to all existing 8-pin SOIC packages
*C 125550 05/14/03 RGL Changed IDD values from 19.6/22/27.2 to 25/30/35 in Commercial Grade DC Specs
table
Changed IDD values from 24/26. 5/33 to 26/32/37 in Industrial grade DC Specs table
Changed T
CCJ1/2
values from 675/260 to 800/450 in Commercial grade AC Specs table
Changed T
CCJ1
value from 350 to 650 in Industrial grade AC Specs table
*D 131941 12/24/03 RGL Removed automotive in the Applications section
Changed the Output Clock Duty Cycle (T
DCOUT
) from min. 45 and max. 55 to 40 and
60% respectively for both industrial and commercial grade
Changed the min. Input Low Voltage (V
IL
) from 0.15V
DD
to 0.13V
DD
Removed preliminary from the industrial AC/DC Electrical Specifications table
*E 231057 See ECN RGL Added Pb Free Devices
*F 1499165 See ECN KVM Updated Ordering Information table
Corrected jitter values in features section on page 1
Changed:VDD from ±5% to ±10%, CIN1 min from 6 to 3.5 pF, CIN2 min from 3.5 to 2.8
pF, TF1 min from 2 to 1.6 ns, and TF2 min from 1.0 to 0.8 ns.
Commercial grade: IDD1 max from 25 to 28 mA, IDD2 max from 30 to 33 mA, IDD3
max from 35 to 40 mA, TCCJ2 from 450 to 480 ps, TCCJ4 from 380 to 450 ps, and
TCCJ5 from 380 to 550 ps
Industrial grade: IDD1 max from 26 to 28 mA, IDD2 max from 32 to 33 mA, IDD3 max
from 37 to 41 mA, TCCJ2 from 400 to 630 ps,and TCCJ3 from 400 to 520 ps
*G 2592288 10 /23/08 CXQ/PYRS Removed Pb package devices from Ordering Table
[+] Feedback
Document Number: 38-07112 Rev. *G Revised October 22, 2008 Page 13 of 13
All products and company names mentioned in this document may be the trademarks o f t heir respect i ve holders.
CY25811/12/14(s)
© Cypress Semicondu ctor Corpor ation, 2004-200 8. The informati on cont ained herein is subject to change witho ut notice. Cypr ess Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress produc ts are n ot war ran t ed nor int e nded to be used for
medical, life supp or t, l if e savi n g, cr it ical control or safety applications, unless pursuant to an express wr itten agreement with Cypress. Furth er m ore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failur e may reasonably be expected to result in significant injury to the user. The inclusion of Cypress product s in life-support syst ems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and interna tion al trea ty provisi ons. Cyp ress he reby gr ant s t o license e a per sonal , non- exclus ive, no n-tran sferab le lic ense to cop y, use, modify, create derivative works of ,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of lice nsee product to be used on ly in conjunction wit h a Cypress
integrated circui t as specified in the applicab le agreement. Any r eproduction, m odification, transl ation, compilatio n, or represent ation of this S ource Code exce pt as specified above is prohib ited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNE SS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liabil ity ar ising ou t of t he app licati on or us e of an y product or circ uit de scrib ed herei n. Cypr ess does n ot auth orize it s product s for use a s critical componen ts in life-suppo rt systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the m anufacturer
assumes all risk of such use and in doing so indemnifies Cypr ess against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
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Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at cypress.com/sales.
Products
PSoC psoc.cypress.com
Clocks & Buffers clocks.cypress.com
Wireless wireless.cypress.com
Memories memory.cypress.com
Image Sensors image.cypress.com
PSoC Solutions
General psoc.cypress.com/solutions
Low Power/Low Voltage psoc.cypress.com/low-power
Precision Analog psoc.cypress.com/precision-analog
LCD Drive psoc.cypress.com/lcd-drive
CAN 2.0b psoc.cypress.com/can
USB psoc.cypress.com/usb
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