PRELIMINARY fax id: 5420 CY7CAG0A/CY7C462A CY7C464A/CY7C466A 7 CYPRESS "Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs Features High-speed, low-power, first-in first-out (FIFO) memories BK x 9 FIFO (CY7C460A) 16K x 9 FIFO (CY7C462A) 32K x 9 FIFO (CY7C464A) 64K x 9 FIFO (CY7C466A) 10 ns access times, 20 ns read/write cycle times High-speed 50 MHz read/write independent of depth/width Low operating power lec= 60 mA _ Isp =2mA Asynchronous read/write Empty and Full flags Half Full fiag (in standalone mode) Retransmit (in standalone mode) TTL-compatibie Width and Depth Expansion Capability 5V + 10% suppiy PLCC, LCC, 300-mil and 600-mil DIP packaging Three-state outputs Pin compatible density upgrade to CY7C42X/46X family * Pin compatible and functionally equivalent to IDT7205, 1DT7206, [DT7207, IDT7208 . . Functional Description The CY7C4A6GO0A, CY7C462A, CY7C464A, and CY7C466A are respectively, 8K, 16K, 32K, and 64K words by 9-bit wide first-in-first-out (FIFO) memories. Each FIFO memory is orga- nized such that the data is read in the same sequential order that it was written. Full and Empty flags are provided to prevent overrun and underrun. Three additional pins are also provided to facilitate unlimited expansion in width, depth. or both. The depth expansion technique steers the control signals from one device to another by passing tokens. The read and write operations may be asynchronous: each can occur at a rate of up to 50 MHz. The write operation occurs when the write (W) signal is LOW. Read occurs when read (R) goes LOW. The nine data outputs go to the high-impedance state when Ri is HIGH. A Half Full (AF) output flag is provided that is valid in the standalone (single device) and width expansion configurations. In the depth ex- pansion configuration, this pin provides the expansion out (XO} infor- mation that is used to tell the next FIFO that it will be activated. In the standalone and width expansion configurations, a LOW on the retransmit (RT) input causes the FIFOs to retransmit the data. Read enable (R) and write enable (W) must both be HIGH dur- ing a retransmit cycle, and then R is used to access the data. The CY7C460A. CY7C462A, CY7C464A, and CY7C466A are fabricated using Cypresss advanced 0.5 RAM3 CMOS tech- nology. Input ESD protection is greater than 2000V and latch-up is prevented by careful layout and the use of guard rings. Logic BlockDiagram aeranpurs Pin Configurations DIP. {Do-D s) PLCC/LCC Top View Top View TOOT s WRITE 2 We) CONTROL | 2 DUAL PORT RAM ARRAY write PANY" akx READ POINTER by) 18k x9 POINTER 32K x9 64K x9 e 9 o TitTTi tt THREE STATEN Joee 22 BUFFERS J} 14 15 1617 181920 DATAOUTPUTS PPESE SE {Qu 8) 6 RESET xe MA Ca460A-2 : READ LOGIC dae FLAT i Fe CONTROL | 7 | roo EF FF EXPANSION ~ XI 105K | _____ ROE CA60A-1 For the most recent information, visit the Cypress web site at www.cypress.com 2-365CY7C460A/CY7C462A CYPRESS PRELIMINARY CY7C464A/CY7C466A Setection Guide 7C460A-10 7CAGOA-15 7C460A-25 7C462A-10 7C462A-15 7C462A-25 7C464A-10 7C464A-15 7C464A-25 7C466A-10 7CA466A-15 7C466A-25 Frequency (MHz) 50 40 28.5 Maximum Access Time (ns) 10 15 25 Maximum Ratings Output Current, into Outputs (LOW)... cesses 20 mA eee wiested) useful life may be impaired. For user guide- (par MIL STD bas. Meteod 3018) Te ee >2001V Storage Temperature... -65C to +150C Latch-Up Current... ccc tees eeeeen sees 2200 MA POWOT APDIGU. rrsec re teemnnn 55C to+125 Operating Range Supply Voltage to Ground Potential............... ~0.5V to +7.0V | Ambient DC Voltage Applied to Outputs Range Temperature Voc in High Z State o....ccceccccsessssescesesessneasecses ~0.5V to +7.0V Commercial C to + 70C 5V + 10% DC Input Voltage oo... cece ecesesceteseenenstenseee ~0.5V to +7.0V Industrial -40C to +85C 5V + 10% Power Dissipation ............ cece scectesecneceneceresereesenaeee 1.0W Military") -55C to +125C 5V + 10% Electrical Characteristics Over the Operating Rangel! 7TC460A/462A/4640/466A (-10,-15,-25) Parameter Description Test Conditions Min. Max. Unit Vou Output HIGH Voltage Voc = Min., lon = -2.0 mA 2.4 Vv Vor Output LOW Voltage Voc = Min., lo. = 8.0 mA 0.4 v Vie Input HIGH Voltage 2.2 Veco v Vir Input LOW Voltage -0.5 0.8 Vv hx Input Leakage Current GND <Vi< Voc -10 +10 HA loz Output Leakage Current | A> Viy, GND < Vo< Voc -10 +10 uA lec Operating Current Veco = Max., 60 mA lout = O mA, Freg=20MHz Isp Standby Current All Inputs = Voc-.2V, Freq=OMHz 2 mA Capacitance"! Parameter Description Test Conditions Max. Unit Cin input Capacitance Ta = 25C, f= 1 MHz, 10 pF Cour Output Capacitance Voc = 4.5V 12 pF Notes: 1. T, is the instant on case temperature. 2. See the last page of this specitication for Group A subgroup testing information. 3. For test purposes, not more than one output at a time should be shorted. Short circuit test duration should not exceed 1 second. 4. Tested initially and after any design or process changes that may affect these parameters. 2-366CYPRE 59 PRELIMINARY AC Test Loads and Waveforms Ri5002 5v rs | 5V Ri500 CY7C460A/CY7C462A CY7C464A/CY7C466A ALL INPUT PULSES ir | Ra 30 pF R2 5 pF I 333Q, I ; 3330 INCLUDING+> > INCLUDING i> JIG AND ~ CABDA~4 JIG AND ~ ~ $460A-8 CAB0A-6 SCOPE a) SCOPE (b) Equivalent to: THEVENIN EQUIVALENT 200Q OUTPUT o_ws-__0 2 Switching Characteristics Over the Operating Rangel *l _ 7C4G0A-10 7CA60A-15 7C4G0A-25 - 7C462A-10 7C462A-15 7C462A-25 7C464A-10 7C464A-15 7C464A-25 7C466A-10 TC466A-15 7C466A-25 Parameter Description Min. Max. Min. Max. Min. Max. Unit tac Read Cycle Time 20 25 35 ns ta Access Time 10 15 25 ns tar Read Recovery Time 10 10 10 ns ter Read Pulse Width 10 15 25 ns tizR Read LOW to Low Z 3 3 3 ns | tov! Data Valid After Read HIGH 3 3 3 ns tuzr' Read HIGH to High Z 15 15 18 ns two Write Cycle Time 20 | 25 35 ns tpw Write Pulse Width 10 / 15 25 ns tuwz Write HIGH to Low Z 5 5 5 ns twa Write Recovery Time 10 10 10 ns tsp Data Set-Up Time 3 9 9 ns tup Data Hold Time 0 0 ns twrsc MR Cycle Time 20 25 35 ns tpmA MRA Pulse Width 10 15 25 ns tau MR Recovery Time 10 10 10 ns tepw Read HIGH toMRHIGH =| 10 15 25 ns twew Write HIGH to MR HIGH ' 40 15 25 ns tare Retransmit Cycle Time 20 25 35 ns teat Retransmit Pulse Width 10 15 25 ns terr Retransmit Recovery Time 10 10} 10 ns tere MR to EF LOW 20 | 26 35 ns tHeH MIR to HF HIGH 20 25 35 ns trey MIR to FF HIGH 20 ; 25 35 ns tree Read LOW to EF LOW i 10 15 25 ns taer Read HIGH to FF HIGH 10 15 25 ns twer Write HIGH to EF HIGH 10 15 25 ns twer Write LOW to FF LOW 10 15 25 ns twHe | Write LOW to HF LOW 10 15 35 ns | 2-367a: CY7C460A/CY7C462A PRELIMINARY CYPRESS CY7C464A/CY7C466A Switching Characteristics Over the Operating Range!*5l (continued) 7C460A-10 7C460A-15 7CAGOA-25 7C462A-10 7C462A-15 7C462A-25 7C464A-10 7C464A-15 7C4G4A-25 7C466A-10 7C466A-15 7CAG6A-25 Parameter Description Min. Max. Min. Max. Min. Max. Unit taye Read HIGH to HF HIGH 10 15 35 ns trac Effective Read from Write 10 15 25 ns HIGH {RPE Effective Read Pulse Width 10 15 26 ns After EF HIGH twar Effective Write from Read 10 15 25 ns HIGH twee Effective Write Pulse 10 15 25 ns Width After FF HIGH txoL Expansion Out LOW 10 15 25 ns Delay from Clock , i txoH Expansion Out HIGH 10 15 | 25 ns Delay from Clock | | Notes: 5. Test conditions assume signal transmission time of 5 ns ar less, timing reference levels of 1.6V and output loading of the specified ig, Ao, and 30-pF load capacitance, as in part (a) of AC Test Load, unless otherwise specif 6. tuz@ and toy use Capacitance loading as in part (b) of AC Test Load. 2-368CY7C460A/CY7C462A PRELIMINARY CY7C464A/CY7C466A CYPRESS Switching Waveforms! Asynchronous Read and Write tow twa CCOCt~CSCSN tsp et tip tsp ee tho Do-D 8 DATA VALID DATA VALID ca60A-7 ea Master Reset tuasc (9! tema MR RW {8} EF AF tery >} FE 2ORRIOCKR RRR casoa-a Half Full Flag HALF FULL HALF FULL+1 HALF FULL Ww => taHE f< A bt, ro twHe HAF a C460A~9 Notes: 7. AHIGH-ta-LOW transition of aithar the write or read strobe causes a HIGH-to-LOW transition of the responding flag. Correspondingly, a LOW-to-HIGH strobe transition causes a LOW-to-HIGH flag transition. 8. Wand Fi = Vj, around the rising edge of MR. 9. tusrc = tema t tM 2-369prs: CY7C460A/CY7C462A PRELIMINARY CY7C464A/CY7C466A Switching Waveforms! (continued) Last Write to First ReadFull Flag ADDITIONAL R LAST WRITE FIRST READ READS FIRST WRITE \F LS Went br Py / LS atte etlare be a C4B0A-10 Last READ to First WRITE Empty Flag ADDITIONAL LAST READ FIRST WRITE WRITES FIRST READ WwW ' oo TT / \_/ tREF > tWer ta, DATA OUT 4 VALID X) { VALID) (x) CA4G0A-11 Retransmit!'""! lato jt pay __> FURT yf AW \ tatr x / rem tere 1 h taTR CABDA~12 Notes: 10. targ = tear +tarn- 44. EF, HF and FF may change state during retransmit as a result of the offset of the read and write pointers, but flags will De valid at tprc, except for the CY7C46x-20 (Military). whose flags will be valid after tare + 10 ns. 2-370aay: CY7C460A/CY7C462A PRELIMINARY CYPRESS CY7CAG4A/CY7C466A Switching Waveforms! (continued) Full Flag and Write Data Flow-Through Mode R Yt x m twar + twee W AAMAAAAAAAAAMA A i ter WEF . > tHo DATAIN DATA VALID pe ta f# tsp | a oavacut {XXK_ ara vale XXX C4604-1 Empty Flag and Read Data Flow-Through Mode DATA IN Y " fT NF ee tac F AAA , _f \ be ther = wer ta > towz DATA OUT XXXKXA_PATA vaio XXX) EF C460A-14 2-371CY7C460A/CY7C462A PRELIMINARY CY7C464A/CY7C466A CYPRESS Switching Waveforms"! (continued) Expansion TimingDiagrams xo | Do~D g x hi< taR txou ee Qo Qg mmreaiemmnd Note: 12, Expansion out of device 1 (X0,) is connected fo expansion in of device 2 (XI,). Architecture Resetting the FIFO Upon power up, the FIFO must be reset with a master reset (MR) cycle. This causes the FIFO to enter the empty condition signified by the Empty flag (EF) being LOW, and both the Half Full (AF), and Full flags (FF) being HIGH. Read (R) and write (W) must be HIGH trpy/t wey before and tRMR after the rising edge of WA for a valid reset cycle. if reading from the FIFO after a reset cycle is attempted, the outputs will all be in the high-impedance state. Writing Data to the FIFO The availability of at least one empty location is indicated by a HIGH FF. The falling edge of W initiates a write cycle. Data appearing at the inputs (DgDg) tgp before and typ after the rising edge of W will be stored sequentially in the FIFO. The EF LOW-to-HIGH transition occurs twer after the first LOW-to-HIGH transition of W for an empty FIFO. HF goes LOW twue alter the falling edge of W following the FIFO actu- ally being half full. Therefore, the AF is active once the FIFO is filled to half its capacity plus one word. AF will remain LOW while less than one half of total memory is available for writing. The LOW-to-HIGH transition of HF occurs tar after the rising edge of R when the FIFO goes from half fuil +1 to half full. AF is available in standalone and width expansion modes. FF goes LOW twee after the falling edge of W, during the cycle in which the last available location is filled. Internal logic pre- vents overrunning a full FIFO. Writes to a full FIFO are ignored and the write pointer is not incremented. FF goes HIGH tage after a read from a full FIFO, Reading Data from the FIFO The falling edge of R initiates a read cycle if the EF is not LOW. Data outputs (Q9-Qg) are in a high-impedance condition be- tween read operations (HR HIGH), when the FIFO is empty, or when the FIFO is not the active device in the depth expansion mode. When one word is in the FIFO, the falling edge of F initiates a HIGH-to-LOW transition of EF. When the FIFO is empty, the outputs are in a high-impedance state. Reads to an empty FIFO are ignored and do not increment the read pointer. From the empty condition, the FIFO can be read twer after a valid write. Retransmit The retransmit feature is beneficial when transferring packets of data. It enables the receipt of data to be acknowledged by the receiver and retransmitted if necessary. The retransmit (RT) input is active in the standalone and width expansion modes. The retransmit feature is intended for use when a 2-372Kiss number of writes equal-to-or-less-than the depth of the FIFO have occurred since the last MR cycie. A LOW pulse on RT resets the intemal read pointer to the first physical location of the FiFO. FR and W must both be HIGH while and tare after retransmit is LOW. With every read cycle after retransmit, previously accessed data is read and the read pointer incre- mented until equal to the write pointer. Full, Half Full, and Empty flags are governed by the relative locations of the read and write pointers and are updated during a retransmit cycle. Data written to the FIFO after activation of AT are transmitted also. The full depth of the FIFO can be repeatedly retransmitted. Standalone/Width Expansion Modes Standalone and width expansion modes are set by grounding expansion in (XT) and tying first load (FL) to Vec prior toa MR cycle. FIFOs can be expanded in width to provide word widths greater than nine in increments of nine. During width expan- sion mode, all control line inputs are common to all devices, and flag outputs from any device can be monitored. PRELIMINARY CY7C460A/CY7C462A CY7C464A/CY7C466A Depth Expansion Mode (see Figure 1) Depth expansion mode is entered when, during a MR cycle, expansion out (XO) of one device is connected to expansion in (XI) of the next device, with XO of the last device connected to XI of the first device. In the depth expansion mode, the first load (FL) input, when grounded, indicates that this is the first part to be loaded. Ail other devices must have this pin HIGH. To enable the correct FIFO, XO is pulsed LOW when the last physical location of the previous FIFO is written to and is pulsed LOW again when the fast physical location is read. Only one FIFO is enabled for read and one is enabled for write at any given time. All other devices are in standby. FIFOs can also be expanded simultaneously in depth and width. Consequently, any depth or width FIFO can be created with word widths in increments of nine. When expanding in depth, a composite FF is created by ORing the FFs together. Likewise, a composite EF is created by ORing EFs together. AF and RT functions are not available in depth expansion mode. | xo Ww R FF EF Oca 9 9 CY7C460A Que CY7C4E24 CY7C4648 CY7C466A FL Veo x RO } FULL FF EF EMPTY 9 CY7C460A CY7C462A CY7CA64A CYTOABEA FC i RT XO > | i EF 9 CY7C460A CY7C462A CY7C484A CY7CAB6A AS FL + ] XT * FIRST DEVICE C460A~17 Figure 1. Depth Expansion 2-373 a)a; CY7C460A/CY7C462A PRELIMINARY CYPRESS CY7C464A/CY7C466A Ordering Information 8K x 9 Asynchronous FIFO Ordering Code Package Type 28-Lead (300-Mil) Molded DIP 16K x 9 Asynchronous FIFO ) Ordering Code Package Type 2-374a CY7C460A/CY7C462A PRELIMINARY CYPRESS CY7C464A/CY7C466A Ordering Information (continued) 32K x 9 Asynchronous FIFO ns) Ordering Code Package Type 64K x 9 Asynchronous FIFO ns) Ordering Code Package Type 2-375CY7C460A/CY7C462A Bose: PRELIMINARY CY7C464A/CY7C466A MILITARY SPECIFICATIONS Group A Subgroup Testing DC Characteristics Switching Characteristics Parameter Subgroups tac 9,10, 11 ta 9, 10,17 tar 9,10, 11 a tpR 9,10, 11 tA 9, 10, 11 pvr 8,10, 11 tHzR 9, 10, 17 : two 9, 10, 17 tepw 9,10, 11 tHwz 9,10, 14 iwr 9,10, 71 tsp 9, 10, 11 tup 9,10, 11 tMAsc 9, 10, 11 tema 9,10, 11 taur 9,10, 71 taPw 9, 10, 11 twew 9,10, 11 tatc 9,10, 11 teat 9, 10, 11 tate 9,10, 11 tere 9, 10, 11 tro 9, 70, 11 tREF 9,10, 14 tree 9, 10,17 twer 9, 10, 11 twer 9,10, 11 WHE 3, 10.14 taHE 9, 10, 11 trac 9,10, 44 tRPE , 9, 10, 11 | i twpr 9,10, 11 txOL 9, 10.11 KOH 9, 10.11 Document #: 38-00627 2-376