© Semiconductor Components Industries, LLC, 2016
June, 2019 − Rev. 7
1Publication Order Number:
FAN9673/D
FAN9673
Three-Channel Interleaved
CCM PFC Controller
Description
The FAN9673 is an interleaved three−channel Continuous
Conduction Mode (CCM) Power Factor Correction (PFC) controller
IC intended for PFC pre−regulators. Incorporating circuits for the
implementation of leading edge, average current, and “boost”−type
power factor correction, the FAN9673 enables the design of a power
supply that fully complies with the IEC1000−3−2 specification.
Interleaved operation provides substantial reduction in the input and
output ripple currents and the conducted EMI filtering becomes easier
and cost effective.
An innovative channel management function allows slave channels
to be loaded and unloaded smoothly in lower power−level conditions
according to setting voltage on the CM pin, improving the PFC
converter’s load transient response.
The FAN9673 also incorporates a variety of protection functions,
including: peak current limiting, input voltage brownout protection,
and TriFault Detect function.
Features
•Continuous Conduction Mode Control
•Three−Channel PFC Control (Maximum)
•Average Current−Mode Control
•PFC Slave Channel Management Function
•Programmable Operation Frequency Range: 18 kHz ∼ 40 kHz
or 55 kHz ∼ 75 kHz
•Programmable PFC Output Voltage
•Dual Current Limit Functions
•TriFault Detect Protects Against Feedback Loop Failure
•Sag Protection
•Programmable Soft−Start
•Under−Voltage Lockout (UVLO)
•Differential Current Sensing
•Available in 32−Pin LQFP Package
Typical Applications
•High Power AC−DC Power Supply
•DC Motor Power Supply
•White Goods; e.g. Air Conditioner Power Supply
•Server and Telecom Power Supply
•Industrial Welding and Power Supply
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MARKING DIAGRAM
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
ORDERING INFORMATION
Z = Assembly Plant Code
X = Year Code
Y = Work Code
TT = Die Run Code
T = Package Type (Q:LQFP)
M = Manufacture Flow Code
32 31 30 29 28 27 26 25
10 11 12 13 14 15 169
1 2 3 4 5 6 7 8
24 23 22 21 20 19 18 17
BIBO
PVO
ILIMIT
GC
RI
RLPK
ILIMIT2
LPK
GND
CS1+
CS1−
CS2+
CS2−
LS
RDY
IEA1
IEA2
IEA3
CM1
CM2
VIR
IAC
SS
VEA
FBPFC
VDD
OPFC1
OPFC2
ZXYTT
TM
ON
F A N 9 6 7 3
CM3
CS3+
CS3−
OPFC3
LQFP32
CASE 561AB
FAN9673
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ORDERING INFORMATION
Part Number
Operating
Temperature Range Package Packing Method
FAN9673Q −40°C to 105°C32LD, LQFP, JEDEC MS−026, Variation BBA, 7 mm
Square
Tray
FAN9673QX Tape & Reel
TYPICAL APPLICATION
Figure 1. Typical Application Diagram for Three−Channel PFC Converter
LPFC1 DPFC1
CB+
RB1
RA1
RA2
LPFC2 DPFC2
LPFC3 DPFC3
VPFC
IEA1
SS
BIBO
CS1+
IAC
ILIMIT2
OPFC1
VDD
VIR
FBPFC
VEA CVC1
RVC1
CVC2
CSS
CM1 CM2 CM3
CS1−CS2+ CS2−CS3+ CS3−
IEA2
IEA3
OPFC2 OPFC3
CVDD
FAN9673
RILIMIT2
CILIMIT2
COUT
RFB1
RFB2
RFB3
CFB3
CVIR RVIR
CIC11
RIC1
CIC12
CIC21
RIC2
CVI22
CIC31
RIC3
CIC32
SPFC1
RSEN1
Driver Circuit
SPFC2
RSEN2
Driver Circuit
SPFC3
RSEN3
Driver Circuit
RF
CF1
CF2
RI
PVO
LPK
RDY
ILIMIT
RRI
MCU signal(DC)
MCU
CILIMIT
RILIMIT
RLPKGND
CRLPK
RRLPK
MCU
CLPK
RLPK
CB2
RB1
RB2
RB4
CB1
RB3
Channel Enable
GC
LS
RGC
CGC
RLS
VIN
Standby Power
AC Line
In
EMI
Filter
*D
BP
* About DBP please reference System Design Precautions
FAN9673
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BLOCK DIAGRAM
Figure 2. Functional Block Diagram
HV: High Voltage Range AC Input, AC180 ~ 264 V
* FR: Full Range AC Input, AC85 V~264 V
10uA
CS1+
27 OPFC1
23
LPT1
CS1−22
CS2+
26 OPFC2
21
LPT2
CS2−20
CS3+
25 OPFC3
19
LPT3
CS3−18
IEA1
IEA2
IEA3 12
11
10
RI
VDD VIR
28
Oscillator
IEA_SAW3
Dead3
IEA_SAW2
Dead2
IEA_SAW1
Dead1
CM1
CM2
CM3
LS 17
PFC OVP
VDD OVP
PFC UVP
AC UVP
Brown In /Out
FR: 1.05V/1.9V
HV: 1.05V/1.75V
VEA LPD
ILIMIT
5
16
20uA
VVEA > VSS
VEA
31
SS
ILIMIT2
CS1
3
GMI3
UVLO
VDD
24
GND
32
RLPK
FR: 2.4V/1.25V
HV: 2.4/1.55V
RDY
5V
9
60uA
SS
Brown Out,
Protection
55uA 55uA 55uA
VEA 30
PVO 2
IAC
6
LPK 8
A
C
B
FBPFC
29
GMI2
GMI1
1.2V / RRI
CM3
15
CM2
14
CM1
13 1
BIBO
ILIMIT2
CS2
ILIMIT2
CS3
VGMV−
ILIMIT2
7
1/4X
GC 4
VBIBO−UVP −VBIBO−UVP
0.3V
2.75V/2.5V
0.5V
VDD
24V/23V
VFBPFC
VVEA
VBIBO
VVIR
< 1.5V, FR
VVIR
> 3.5V, HV
Q
Q
SET
CLR
S
R
Q
Q
SET
CLR
S
R
Q
Q
SET
CLR
S
R
Q
Q
SET
CLR
S
R
Q
Q
SET
CLR
S
R
Q
Q
SET
CLR
S
R
2.5V
GMV
Peak Detector
Ratio Imo
RM
Brown out
PIN CONFIGURATION
Figure 3. Pin Layout (Top View)
32 31 30 29 28 27 26 25
10 11 12 13 14 15 169
1 2 3 4 5 6 7 8
24 23 22 21 20 19 18 17
BIBO
PVO
ILIMIT
GC
RI
RLPK
ILIMIT2
LPK
GND
CS1+
CS1−
CS2+
CS2−
LS
RDY
IEA1
IEA2
IEA3
CM1
CM2
VIR
IAC
SS
VEA
FBPFC
VDD
OPFC1
OPFC2
ZXYTT
TM
ON
F A N 9 6 7 3
CM3
CS3+
CS3−
OPFC3
FAN9673
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Table 1. PIN DEFINITIONS
Pin # Name Description
1 BIBO Brown In/Out Level Setting: This pin is used for brown in/out setting.
2 PVO Programmable Output Voltage: DC voltage from a microcontroller (MCU) can be applied to this pin to
program the output voltage level. The operation range is 3.5 V ∼ 0.5 V. If VPO < 0.5 V, the PVO function
is disabled.
3 ILIMIT Current Command Clamp Setting: Average current mode is to control average value of inductor current
by a current command. Connecting a resistor and a capacitor to this pin can determine a limit value of
the current command.
4 GC Input Voltage Gain Control: Connecting a resistor on this pin to set a gain on the input−voltage signal to
match FBPFC. The signal here is used for the LPT function. A small capacitor connecting from GC to
GND is recommended for noise filtering.
5 RI Oscillator Setting: There are two oscillator frequency ranges: 18 ∼ 40 kHz and 50 ∼ 75 kHz. A resistor
connected from RI to ground determines the switching frequency. A resistor value between
10.6 k ∼44.4 k is recommended.
6 RLPK Ratio of VLPK and VIN: Connect a resistor and a capacitor to this pin to adjust the ratio of VIN peak to
VLPK. Typical value is 12.4 k (1:100 of VLPK and VIN peak). The accuracy of VLPK is primarily deter-
mined by the tolerance of RRLPK at this pin.
7 ILIMIT2 Peak Current Limit Setting: Connect a resistor and a capacitor to this pin to set the over−current limit
threshold and to protect power devices from damage due to inductor saturation. This pin sets the over−
current threshold for cycle−by−cycle current limit.
8 LPK Peak of Line Voltage: This pin can be used to provide information about the peak amplitude od the line
voltage to an MCU.
9 RDY Output Ready Signal: When the feedback voltage on FBPFC exceeds 2.4 V, the RDY pin outputs a
high−state VRDY signal to inform the MCU the downstream power stage can start normal operation.
If AC brownout is detected, the VRDY signal is LOW to signal the MCU the PFC is not ready.
10 IEA1 Output 1 of PFC Current Amplifier: The signal from this pin is compared with an internal sawtooth sig-
nal to determine the pulse width for PFC gate drive 1.
11 IEA2 Output 2 of PFC Current Amplifier: The signal from this pin is compared with an internal sawtooth sig-
nal to determine the pulse width for PFC gate drive 2.
12 IEA3 Output 3 of PFC Current Amplifier: The signal from this pin is compared with an internal sawtooth sig-
nal to determine the pulse width for PFC gate drive 3.
13 CM1 Channel 1 Management Setting: This pin is used to configure the characteristics of PFC enable/
disable. Pull voltage on this pin LOW (= 0 V) to enable and HIGH (> 4 V) to disable the whole PFC
system.
14 CM2 Channel 2 Management Setting: There are two control methods for channel 2. The first uses an exter-
nal signal to enable/disable channel 2 (VCM2 = 0 V/VCM2 > 4 V). The second is linear increase/de-
crease loading of channel 2 when VVEA, proportional to power level, meets the setting level on VCM2.
15 CM3 Channel 3 Management Setting: Same as the CM2 pin, but for Channel 3.
16 VIR Input Voltage Range Setting: A capacitor and a resistor are connected in parallel from this pin to GND.
When VVIR > 3.5 V, the PFC controller only works for the high−voltage input range (180 VAC ∼264 VAC)
and RIAC must be 12 M. When VVIR < 1.5 V, the PFC controller works for the Universal Input voltage
range (90 VAC ∼264 VAC) and RIAC must be 6 M. Voltage between 1.5 V and 3.5 V is not allowed.
17 LS Setting for Current Predict Function: A resistor, connected from this pin to ground, is used to adjust the
compensation of linear predict function (LPT). A small capacitor connected from this pin to GND is
recommended for noise filtering.
18 CS3−Channel 3 Negative PFC Current Sense Input
19 CS3+ Channel 3 Positive PFC Current Sense Input
20 CS2−Channel 2 Negative PFC Current Sense Input
21 CS2+ Channel 2 Positive PFC Current Sense Input
22 CS1−Channel 1 Negative PFC Current Sense Input
23 CS1+ Channel 1 Positive PFC Current Sense Input
24 GND Ground Reference and Return
25 OPFC3 Channel 3 PFC Gate Drive: The totem−pole output drive for the MOSFET or IGBT. This pin has an
internal 15 V clamp to protect the external power switch.
FAN9673
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Table 1. PIN DEFINITIONS (continued)
Pin # DescriptionName
26 OPFC2 Channel 2 PFC Gate Drive: The totem−pole output drive for the MOSFET or IGBT. This pin has an
internal 15 V clamp to protect the external power switch.
27 OPFC1 Channel 1 PFC Gate Drive: The totem−pole output drive for the MOSFET or IGBT. This pin has an
internal 15 V clamp to protect the external power switch.
28 VDD External Bias Supply for the IC: The typical turn−on and turn−off threshold voltages are 12.8 V and
10.8 V respectively.
29 FBPFC Voltage Feedback Input for PFC: Inverting input of the PFC error amplifier. This pin is connected to the
PFC output through a resistor−divider network.
30 VEA Output of PFC Voltage−Loop Amplifier: An error−amplifier output for the PFC voltage feedback loop.
A compensation network is connected between this pin and ground.
31 SS Soft−Start: Connect a capacitor to this pin to set the soft−start time. Pulling this pin to ground can dis-
able the gate drive outputs OPFC1, OPFC2 and OPFC3.
32 IAC Input AC Current: During normal operation, this input provides a current reference for an internal gain
modulator. The recommended maximum current on IAC is 65 A.
ABSOLUTE MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Symbol Parameter Min Max Unit
VDD DC Supply Voltage 30 V
VOPFC Voltage on OPFC1, OPFC2, OPFC3 Pins −0.3 VDD + 0.3 V V
VLVoltage on IAC, BIBO, LPK RLPK, FBPFC, VEA, CS1+, CS2+, CS3+,
CS1−, CS2−, CS3−, CM1, CM2, CM3, ILIMIT, ILIMIT2, RI, PVO, GC, LS,
VIR Pins
−0.3 7.0 V
VIEA Voltage on IEA1, IEA2, IEA3, SS Pins 0 8 V
IIAC Input AC Current 1 mA
IPFC−OPFC Peak PFC OPFC Current, Source or Sink 0.5 A
PDPower Dissipation, TA < 50 °C 1640 mW
RJ−AThermal Resistance (Junction−to−Air) 77 °C/W
TJOperating Junction Temperature −40 150 °C
TSTG Storage Temperature Range −55 150 °C
TLLead temperature (Soldering) 260 °C
ESD Electrostatic Discharge Capability Human Body Model,
ANSI/ESDA/JEDEC JS−001−2012
4kV
Charged Device Model,
JESD22−C101
2
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
RECOMMENDED OPERATING CONDITIONS
Symbol Parameter Min Typ Max Unit
VDD−OP Operating Voltage 15 V
LMISMATCH Boost Inductor Mismatch −5 +5 %
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
1. All voltage values, except differential voltage, are given with respect to GND pin.
2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
FAN9673
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ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 15 V and TJ = −40~105°C)
Symbol Parameter Condition Min Typ Max Unit
VDD SECTION
IDD ST Startup Current VDD = VTH−ON - 0.1 V 30 80 A
IDD−OP Operating Current VDD = 14 V, Output Not Switching, RRI =
25 k
4 6 7 mA
VTH−ON Turn−On Threshold Voltage VDD Rising 11.7 12.8 13.9 V
ΔVTH UVLO Hysteresis 2 3 V
VDD−OVP VDD OVP Threshold OPFC1~3 Disabled, IEA1~3 and SS Pull Low 23 24 25 V
ΔVDD−OVP VDD OVP Hysteresis 1 V
tD−OVP VDD OVP Debounce Time 80 μs
OSCILLATOR (Note 3)
VRI Sourcing Voltage on RI RRI = 25 k1.15 1.201.25 V
fOSC1 PFC Frequency Test Case 1 RRI = 25 k30 32 34 kHz
fOSC2 PFC Frequency Test Case 2 RRI = 12.5 k58 62 66 kHz
fDV Voltage Stability 13 V ≤ VDD ≤ 22 V 2 %
fDT Temperature Stability 2 %
ΔVIEA−SAW32 VIEA−SAW of PFC Frequency 32 kHz RRI = 25 k5 V
ΔVIEA−SAW64 VIEA−SAW of PFC Frequency 64 kHz RRI = 12.5 k5.15 V
DPFC−MAX Maximum Duty Cycle VIEA > 7 V 94 97 %
DPFC−MIN Minimum Duty Cycle VIEA < 1 V 0 %
fRANGE1 Frequency Range 1 (Notes 3, 4) 18 40 kHz
fRANGE2 Frequency Range 2 (Notes 3, 4) 55 75 kHz
tDEAD−MIN Minimum Dead Time RRI = 10.7 k600 ns
INPUT−RANGE SETTING (VIR)
VVIR−HHIGH Setting Level for High Voltage In-
put Range
RVIR = 500 k (VVIR = 5 V) 3.5 V
VVIR−LLOW Setting Level for Low Voltage In-
put Range or Full Voltage Input Range
VVIR = 0 V 1.5 V
IVIR Sourcing Current of VIR Pin 7 10 13 A
PFC SOFT−START
ISS Constant Current Output for Soft−Start System Brown−in 22 A
VSS Maximum Voltage on SS 6.8 V
ISS−Discharge Discharge Current of SS Pin Brownout, SAG, VCM1 > 4 V, RRI Open /
Short, OTP
60 A
VOLTAGE ERROR AMPLIFIER
VREF Reference Voltage PVO = GND, TJ = 25°C 2.45 2.50 2.55 V
AVOpen-Loop Gain (Note 3) 42 65 dB
Gmv Transconductance VNONINV − VINV = 0.5 V, TJ = 25°C 100 S
IFBPFC−LMaximum Source Current VFBPFC = 2 V, VVEA = 3 V 40 50 A
IFBPFC−HMaximum Sink Current VFBPFC = 3 V, VVEA = 3 V −50 −40 A
IBS Input Bias Current Range −1 1 A
IFBPFC−FL Pull High Current for FBPFC FBPFC Floating 500 nA
VVEA-HOutput High Voltage on VVEA VFBPFC = 2 V 5.7 6.0 V
VVEA-LOutput Low Voltage on VVEA VFBPFC = 3 V 0 0.15 V
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ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 15 V and TJ = −40~105°C)
Symbol UnitMaxTypMinConditionParameter
VOLTAGE ERROR AMPLIFIER
IVEA−DIS Discharge Current Brownout, RRI Open /Short, OTP, SAG 10 A
VVEA-OFF Threshold Voltage for Low−Power De-
tection
When VVEA < VVEA−OFF
, VOPFC1~3 are Off &
VIEA1~3 are Pulled Low
0.3 V
CURRENT ERROR AMPLIFIERS
Gmi Transconductance VNONINV = VINV, VIEA = 4 V,
VILIMIT > 0.6 V, TJ = 25°C
88 S
VOFFSET Input Offset Voltage VVEA = 0.45 V, RIAC = 12 M,
VIAC = 311 V, VFBPFC = 2 V,
VVIR > 5 V, TJ = 25°C
0 mV
VIEA−HOutput High Voltage 6.8 7.0 V
VIEA−LOutput Low Voltage 0 0.4 V
ILSourcing Current VNONINV − VINV, = +0.6 V,
VIEA = 1 V, VILIMIT >0.6 V
35 50 A
IHSinking Current VNONINV − VINV, = −0.6 V,
VIEA = 6.5 V, VILIMIT >0.6 V
−50 −35 A
AIOpen−Loop Gain (Note 3) 40 50 dB
IIEA−LOW IEA Pin Pull−Low Capability VIEA ≥ 5 V 500 μA
GAIN MODULATOR (Current Command Generator)
IAC Input for AC Current (Notes 3, 5) Multiplier Linear Range 0 65 A
BW Bandwidth (Notes 3, 5) IAC = 40 A2 kHz
VRM Gain Modulator Output (IMO* RM) Test
Cases
VIAC = 106.07 V, RIAC = 6 M, VFBPFC =
2.25 V, VBIBO = 2 V, VCM2, VCM3 > 4.5 V,
TJ = 25°C
0.490 V
VIAC = 120.21 V, RIAC = 6 M, VFBPFC =
2.25 V, VBIBO = 2 V, VCM2, VCM3 > 4.5 V,
TJ = 25°C
0.430
VIAC = 155.56 V, RIAC = 6 M, VFBPFC =
2.25 V, VBIBO = 2 V, VCM2, VCM3 > 4.5 V,
TJ = 25°C
0.327
VIAC = 311.13 V, RIAC = 12 M, VFBPFC =
2.25 V, VBIBO = 2 V, VCM2, VCM3 > 4.5 V,
VVIR > 3.5 V, TJ = 25°C
0.320
VIAC = 373.35 V, RIAC = 12 M, VFBPFC =
2.25 V, VBIBO = 2 V, VCM2, VCM3 > 4.5 V,
VVIR > 3.5 V, TJ = 25°C
0.260
RMResistor of Gain Modulator Output RM = VRM /IMO 7.5 k
ILIMIT (Current Command Limit)
VRM−RRange of Peak Value in Current Com-
mand (VILIMIT/4)
0.2 0.8 V
VRM−ILIMIT Current Command Limit Test Case RILIMIT = 42 k, RRI = 25 k,
VRM−LIMIT = RILIMIT * IILIMIT/4
0.504 V
IILIMIT Sourcing Current of ILIMIT Pin RRI = 25 k49 A
ILIMIT2 (CS1 /CS2 /CS3, Pulse−by−Pulse Current Limit)
VILIMIT2−CS1 Peak Current Limit Voltage Test Case RILIMIT2 = 30 k, RRI = 25 k,
CS1~3 > VILIMIT2
OPFC1 Disables, VIEA1~3 Pull Low
1.48 V
VILIMIT2−CS2 1.48 V
VILIMIT2−CS3 1.48 V
IILIMIT2 Sourcing Current for ILIMIT2 Pin RRI = 25 k, TJ = 25°C49.5 A
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ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 15 V and TJ = −40~105°C)
Symbol UnitMaxTypMinConditionParameter
ILIMIT2 (CS1 /CS2 /CS3, Pulse−by−Pulse Current Limit)
tPFC−BNK1 Leading−Edge Blanking Time of ILIMIT
of Each Channel
VDD = 15 V, OPFC Drops to 9 V 250 ns
tPFC−BNK2 250 ns
tPFC−BNK3 250 ns
tPD1 Propagation Delay to Output of Each
Channel
200 400 ns
tPD2 200 400 ns
tPD3 200 400 ns
VILIMIT2−OPEN Threshold of ILIMIT2 Open−Circuit Pro-
tection
OPFC1~3 Disabled and VIEA1~3 Pull Low 3.8 4.0 4.2 V
TriFault Detect™
VPFC−UVP FBPFC Under−Voltage Protection 0.4 0.5 0.6 V
VPFC−OVP FBPFC Over−Voltage Protection (OVP) 2.70 2.75 2.80 V
ΔVPFC−OVP FBPFC OVP 200 250 300 mV
tFBPFC-OPEN FBPFC Open Delay (Note 3) VFBPFC = VPFC−UVP to FBPFC Open, 470 pF
from FBPFC to GND
2 ms
tFBPFC−UVP Under−Voltage Protection Debounce
Time
50 s
PVO
VPVO Programmable Output Setting Range on
PVO Pin
0.3 3.5 V
VPVO_DIS PVO Disable Voltage PVO< VPVO_DIS 0.2 V
VPVO−CLAMPH Low−clamp of FBPFC based on PVO FBPFC Connected to VEA, VPVO = 4 V 1.6 V
VFBPFC1 FBPFC Voltage Test Cases FBPFC Connected to VEA, VPVO = 0.3 V 2.425 V
VFBPFC2 FBPFC Connected to VEA, VPVO = 3.5 V 1.625 V
IPVO−Discharge PVO Discharge Current PVO Open 1A
GAIN COMPENSATION (GC) SECTION (Note 6)
IGC−L1 Test Cases of Mirror Current of IAC on
GC Pin
VVIR = 0 V, VIAC = 127.28 V, RIAC = 6 M,20.71 A
IGC−L2 VVIR = 0 V, VIAC = 311.13 V, RIAC = 6 M,51.86 A
IGC−HV VVIR = 5 V, VIAC = 311.13 V, RIAC = 12 M.51.86 A
IGC−OPEN Pull High Current for GC−Pin Open 100 nA
VGC−OPEN GC−Pin Open Voltage VGC > VGC−OPEN VIEA, OPFC1, 2, 3 Blanking 2.85 3.00 3.15 V
INDUCTANCE SETTING (LS) SECTION (Note 6)
RLS Acceptable Range of Inductance Setting 12 87 k
VLS−MIN Voltage Difference between VFBPFC and
VGC on LS Pin
VFBPFC – VGC ≥ 0 V50 mV
BROWN IN /OUT
VBIBO−FL Threshold of Brown−out at VIR=LOW
Setting (Full AC−Input Range)
VVIR < 1.5 V, RIAC = 6 M1.00 1.05 1.10 V
ΔVBIBO−FHysteresis VBIBO > VBIBO−FL+△VBIBO−F
,
Brown−in, Start SS
850 mV
VBIBO−HL Threshold of BO at VIR=HIGH Setting
(High AC−Input Range)
VVIR > 3.5 V, RIAC = 12 M1.00 1.05 1.10 V
ΔVBIBO−HHysteresis VBIBO > VBIBO−HL +△VBIBO−H,
Brown−in, Start SS
700 mV
tUVP Under−Voltage Protection Delay Time 450 ms
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ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 15 V and TJ = −40~105°C)
Symbol UnitMaxTypMinConditionParameter
SAG PROTECTION SECTION
VSAG SAG Voltage of BIBO 1. VBIBO < VSAG & VRDY High for 33 ms, or
2. VBIBO < VSAG & VRDY Low, Brownout,
0.85 V
tSAG−DT SAG Debounce Time VBIBO < VSAG & VRDY High 33 ms
RLPK, VOLTAGE−SETTING RESISTANCE FOR PEAK DETECTOR
IRLPK−OPEN Pull High Current for RLPK Open 100 nA
VRLPK−OPEN Threshold of RLPK−pin Open−Circuit
Protection
RLPK Open 2.28 2.40 2.52 V
LPK, PEAK−DETECTOR OUTPUT (Note 7)
VLPK−H1 VLPK Output Test Cases VIAC = 311 V, RIAC = 1 2M,
VVIR > 3.5 V, RLPK = 12.4 k,
TJ = 25°C
3.168 V
VLPK−H2 VIAC = 373 V, RIAC = 12 M,
VVIR > 3.5 V, RLPK = 12.4 k,
TJ = 25°C
3.80 V
VLPK−L1 VIAC = 127 V, RIAC = 6 M,
VVIR < 1.5 V, RLPK = 12.4 k,
TJ = 25°C
1.29 V
VLPK−L2 VIAC = 373 V, RIAC = 6 M,
VVIR < 1.5 V, RLPK = 12.4 k,
TJ = 25°C
3.80 V
VAC−OFF AC OFF Threshold Voltage Test Case VIAC = 373 V, RIAC = 12 M, VVIR > 3.5V
After tAC−OFF VIEA Pull Low
32 V
VAC−ON AC ON Threshold Voltage Test Case VIAC = 373 V, RIAC = 12 M, VVIR > 3.5 V VAC−OF
F +26
V
CM1 SECTION
ICM1 CM1 Sourcing Current 55 A
VCM1−disable PFC Disable Voltage ICM1 * RCM1 > 4 V
OPFC1~3 Disabled and IEA1~3 Pull Low
and SS Pull Low
4 V
1Phase of OPFC1 When ICM1 * RCM1 < 4 V or Short 0°
2Phase of OPFC2 (Note 8) 110 120 130 °
3Phase of OPFC3 (Note 8) 230 240 250 °
CM2 SECTION
ICM2 CM2 Sourcing Current 55 A
VCM2−disable Channel−2 Disable Voltage ICM2 * RCM2 > 4 V or CM2 Floating
OPFC2 Disables and IEA2 PulIs Low
4 V
VCM2−range Set VEA Unload Voltage 0 3.8 V
1Phase of OPFC1 (Note 8) ICM2 * RCM2 > 4 V or CM2 Floating 0°
3Phase of OPFC3 (Note 8) 170 180 190 °
CM3 SECTION
ICM3 CM3 Output Current 55 A
VCM3−disable Channel−3 Disable Voltage ICM3 * RCM3 > 4 V or CM3 Floating
OPFC3 Disables and IEA3 PulIs Low
4 V
VCM3−range Set VEA Unload Voltage 0 3.8 V
1Phase of OPFC1 (Note 8) When ICM3 * RCM3 > 4 V or CM3 Floating 0°
2Phase of OPFC2 (Note 8) 170 180 190 °
FAN9673
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ELECTRICAL CHARACTERISTICS (Unless otherwise noted, VDD = 15 V and TJ = −40~105°C)
Symbol UnitMaxTypMinConditionParameter
RDY SECTION
VFB−RD Level of VFBPFC to Pull RDY High VPVO = 0 V, Brown−in, VFBPFC > VFB−RD 2.3 2.4 2.5 V
ΔVFB−RD−LHysteresis VPVO = 0 V, VIR < 1.5 V 1.15 V
ΔVFB−RD−HHysteresis VPVO = 0 V, VIR > 3.5 V 0.85 V
ZRDY Pull High Input Impedance TJ = 25°C 100 k
VRDY−High HIGH Voltage of RDY 4.8 5.0 V
VRDY−Low LOW Voltage of RDY Pull High Current = 1 mA 0.5 V
PFC OUTPUT DRIVER 1~3
VGATE−CLAMP Gate Output Clamping Voltage VDD = 22 V 13 15 17 V
VGATE−LGate Low Voltage VDD = 15 V, IO = 100 mA 1.5 V
VGATE−HGate High Voltage VDD = 13 V, IO = 100 mA 8 V
trGate Rising Time VDD = 15 V, CL = 4.7 nF,
VOPFC from 2 V to 9 V
70 ns
tfGate Falling Time VDD = 15 V, CL = 4.7 nF,
VOPFC from 9 V to 2 V
60 ns
OTP
TOTP−ON Over−Temperature Protection (Note 3) 140 °C
ΔTOTP Hysteresis (Note 3) 30 °C
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
3. This parameter, although guaranteed by design, is not 100% production tested.
4. The setting range of resistance at the RI pin is between 53.3 k and 10.7 k.
5. Frequency of AC input should be <75 Hz.
6. The RLS and RGC setting suggestion follows the calculation result from application notes AN−4164 and AN−4165.
7. LPK specification is guaranteed at state of PFC working.
8. Pull the CM pin low to ground, ensuring VCM < 0.2 V, to enable an individual channel.
THEORY OF OPERATION
Continuous Conduction Mode (CCM)
The boost converter, shown in Figure 4, is the most
popular topology for power factor correction in AC−DC
power supplies. This popularity can be attributed to the
continuous input current waveform provided by the boost
inductor and the boost converter’s input voltage range low
down to 0 V. These fundamental properties make
close−to−unity power factor easier to achieve.
Figure 4. Basic PFC Boost Converter
L
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The boost converter can operate in Continuous
Conduction Mode (CCM) or in Boundary Conduction Mode
(BCM). These two descriptive names refer to the current
flowing in the energy storage inductor of the boost power
stage.
Figure 5. Basic PFC Boost Converter
Typical Inductor Current Waveform In Continuous Conduction Mode
Typical Inductor Current Waveform In Boundary Conduction Mode
t
t
I
I
0A
As the names indicate, the inductor current in CCM is
continuous and always above zero. In BCM, the new
switching period is initiated when the inductor current
returns to zero. There are many fundamental differences in
CCM and BCM operations and the respective designs of the
boost converter. The FAN9673 is design for CCM control,
as Figure 5 shows. This method reduces inductor current
ripple because the start current of each cycle is not 0 A
typically. The ripple is controlled by the operation frequency
and inductance design. This characteristic makes the peak
current in the power semiconductor devices lower.
Gain Modulator (IA, LPK, VEA)
The FAN9673 employs two control loops for power factor
correction: a current control loop and a voltage control loop.
The current control loop shapes inductor current, as shown
in Figure 6, through a current command, IMO, from the gain
modulator.
Figure 6. CCM PFC Operation Waveforms
IL
VGS
IL
Average of IL+IMO RM
RCS
The gain modulator is the block that provides the
reference to control PFC input current. The output signal of
the gain modulator, IMO, is a function of VVEA, IIAC, and
VLPK; as shown in the Figure 7.
These are the three inputs to the gain modulator:
•IIAC: A current representing the instantaneous input
voltage (amplitude and wave shape) to the PFC. The
rectified AC input sine wave is converted to a
proportional current via a resistor and fed into the gain
modulator. A sampling mechanism on IIAC minimizes
ground noise, important in high−power, switching−power
conversion environment. The gain modulator responds
linearly to IAC.
•VLPK: Voltage proportional to the peak-voltage output of
the bridge rectifier when the PFC is working. The signal
is the output of peak−detect circuit detecting from the IAC.
This factor of the gain modulator is input−voltage
feed−forward control. This voltage information is not
valid when the PFC is not working.
•VVEA: The output of the voltage error amplifier. The gain
modulator responds linearly to variations of this voltage.
The output of the gain modulator is a current signal, IMO,
as eq. 1:
IMO +K IAC VVEA
VLPK
2(eq. 1)
where the K term is about 0.8 for VIR < 1.5 V and 3.2 for
VIR > 3.5V respectively.
The current signal, IMO, is in the form of a full−wave
rectified sinusoid at twice of the line frequency. The gain
modulator forms the reference for the current−loop and
ultimately controls the instantaneous current drawn from the
power line.
Figure 7. Input of Gain Modulation
IAC
VLPK
Gain Modulator
RIAC
I
IAC
VIN
IL
Peak
Detector
RCS
VEA
2.5V
VFBPFC
A (IAC)
B (VEA)
C (VLPK)
A
C
B
VPFC
CO
RFB1
RFB2
VFBPFC
VO
IL
C. Comd.
PO
V
VEA
Current Command
(C. Comd.)
Current Command
(C. Comd.)
A x B
C2
=
IMO
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Current Balance
Current matching of different channel is an important
topic of multi−channel control. In FAN9673, control of
current in each channel is based on sensed signal VCS to
track the current command from the gain modulator, as
shown in Figure 8.
Figure 8. Average Current Mode Control
AVG
IL, Low Inductance Frequency
IL, High Inductance Frequency
The main factors to balance current in each channel are
layout and device tolerance. The tolerance of the shunt
resistor for the current sense is especially important. If the
feedback signal, VCS, has large deviation due to the
tolerance of the sense resistor, the current of the channels
tends to be unbalanced. High precision resistors are
recommended.
High−power applications implies current values are high,
so the distance of layout trace between the current sense
resistors and the controller or power ground (negative of
output capacitor) to IC ground is important, as shown in
Figure 9. The longer trace and large current make the offset
voltage and ground bounce differ significantly for different
channels. Decreasing the deviation help balancing different
channels. Please check the layout guidance in application
notes AN−4164 or AN−4165.
Figure 9. Current Balance Factors
VIN
RCS2
VO
Gate2
Gate1
GND
Differential
Sense Filter
RCS1
Differential
Sense Filter
CS2+CS2−
CS1+
CS1−
Close
Filter Ground
IC GND to Power ground
VCS1 V
FAN9673
Interleaving
The FAN9673 controller is used to control three−channel
boost converters connected in parallel. The controller
operates in average−current mode and supports Continuous
Conduction Mode (CCM). Each channel affords one−third
the power when the system operates close to full load or
when channel management is disabled.
Parallel power processing increases the number of power
components, but the current rating of independent channels
is reduced, allowing power semiconductors with lower
current ratings to be applied.
The switches of the three boost converters can operate at
three−channel with 120° out−of−phase or two−channel with
180° out−of−phase (one channel disable at light load). The
interleaving controller can reduce the total ripple current of
input. Simultaneously, the output current ripple of each
channel is evenly distributed and sequentially rippled on the
output capacitor, which can extend the life of the capacitor.
Channel Management 2/3: CM Control
The CM pin is used for controlling channel management.
The channel management is realized by changing a gain,
acting as changing relative weighting, for the current
command. The relationship of CM and the gain of the slave
channel is shown in Figure 10. The level of CM set the
threshold of power level, representing by VVEA, for
reducing the current command for the slave PFC. The
FAN9673 starts to reduce the current command (IMO ×RM)
for channel 2/3 by Gain2/3 from one to zero when the VVEA
level is lower than its CM level, as Figure 11 and Figure 12
show. The output power of the slave channel is reduced in
response to reduction in current command. For example,
when CM2 is set at 3 V and VVEA is less than the CM2
voltage, the channel management block reduces the
command for channel 2 as:
Vgmi2)+IMO RM Gain2 (eq. 2)
Figure 10. Current Balance Factors
Command
Generator
VIN
VO
Current
Command Current
Loop 1
ISENSE1
Current
Loop 2
CM
Block
ISENSE2
Voltage
Loop
VO
VVEA
Gain1
100%
Gain2
0~100%
Gate2 Gate1
Gate2
Gate1
V
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Figure 11. VVEA and CM Relationship
VEA
0VCM
Channel
Management
IL1
VAC
IL2
VAC
Vgmi+
0< Gain2 <1 Gain2 = 1Gain2 = 0
Without Channel
Management
time
Figure 12. VVEA and VCM Relationship in
Channel Management Operation
IL1
Gain to I L2
Channel Management
Area, Gain2 < 1
VAC
VCM
IL2
VVEA
Gain2=1
PO
Table 2 explains the phase and gain change of each
channel when the PFC operates at various loads. The loading
decreases the gain to the slave until it is disabled. The phase
of Channel Management (CM) mode doesn’t change when
channel 3 is disabled. The behavior shown in Figure 13.
Figure 13. Phase and Gain Change of CM Control
IL1
IL2
IL3
Mid. load ~ light load, linear decrease gain of
channel 2 & 3, final only left Channel 1 at light load
Po
IL1
IL2
IL3
Full load, all channel operation
0°120°240°
Table 2. PHASE AND GAIN CHANGE OF CM CONTROL
CM (Channel Management) Phase and Gain
Channel 1 Channel 2 Channel 3
Heavy Load (All Channel 100% Works) 0° (Gain1 = 1) 120° (Gain2 = 1) 240° (0 < Gain3 < 1)
Mid. Load (Channel 3 is Disabled) 0° (Gain1 = 1) 120° (0 < Gain2 < 1) Disable (Gain3 = 0)
Light Load (Only Channel1 Left) 0° (Gain1 = 1) Disable (Gain2 = 0) Disable (Gain3 = 0)
Channel Management 2: External Control
Channel Management (CM) function can also be accessed
by an MCU through the connection shown in Figure 14. CM
pins have internal pull−up current source. If VCM > 4 V, the
channel is disabled. To enable the channel, make VCM = 0 V,
as shown in Figure 15.
The CM pin of the slave should be connected with a switch
S2 to ground. One pin of MCU must read the VVEA signal to
determine when to turn on/off the slave channel. For
example, as shown in Figure 16, two thresholds, VP2−OFF−L
and VP2−OFF−H, are set in MCU program. When
VVEA <V
P2−OFF−L, the slave PFC turns off. If
VVEA >V
P2−OFF−H, the slave PFC turns on.
FAN9673
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14
Figure 14. Channel Management by MCU
Gain
Modulator
CS+
OSC
CS−
Sample
& Hold
CM
CM
gmi
55uA
Channel
enable
signal
from MCU
S
Figure 15. Channel Management by MCU
time
0
VCM
(V)
6
IL
VAC
VCM−LIMIT (4V)
VVEA
time
Figure 16. Channel Management by
External Signal from MCU
IL1
à
MCU S2
MCU Turn−Off Slaver
VAC
VP2−OFF−H
IL2
VVEA
VP2−OFF−L
PO
When CM is accessed this way, relative phase of OPFC of
each channel changes when the loading changes, as
illustrated in Table 3 and Figure 17. When the MCU disables
channel 3 at mid−load, the relative phase angle of channel 2
to channel 1 shifts from 120°C to 180°C. Gain2/3 of each
channel under this control method switches between 100%
and 0%.
Figure 17. Phase Change under
External Signal Control
à 180˚
IL1
IL2
IL3
IL1
IL2
IL3
Full load, all channel operation
Mid. load, disable channel 3 by external signal
120˚
0°180°
Table 3. PHASE CHANGE OF EXTERNAL SIGNAL CONTROL
External Signal Control
Phase
(Disable Channel: VCM > 4 V, Enable Channel: VCM = 0 V)
Channel 1 Channel 2 Channel 3
Heavy Load (All Channels Enabled) 0°120°240°
Mid. Load (Channel3 Disabled) 0°180°Disable (VCM3 > 4 V)
Light Load (Channel 2/3 Disabled) 0°Disable (VCM2 > 4 V) Disable (VCM3 > 4 V)
Disable All System VCM1 > 4 V, All Channels Disabled
FAN9673
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FUNCTIONAL DESCRIPTION
Internal Oscillator (RI)
Frequency of an internal oscillator is determined by an
external resistor, RRI, on the RI pin. The frequency of the
oscillator is given by eq. 3. The frequency can be freely set
in two ranges, 18 kHz ~ 40 kHz and 55 kHz~75 kHz. Setting
frequency between 40 kHz and 55 kHz is not allowed in
FAN9673.
fosc +8 108
RRI
(eq. 3)
Current−Control Loop of Boost Stage
As shown in Figure 18, the two control loops for power
factor correction are a current−control loop and a
voltage−control loop. Based on the reference signal
obtained at the IAC pin, the error amplifier in
current−control loop regulates current signal as:
IL RCS +IMO RM Gain2ń3+K IAC VEA
VLPK
2 RM Gain2ń3
(eq. 4)
Average value of sensed current, IL×RCS, is regulated to
the current command, IMO ×RM. Gain2/3 is a gain between
0 ~ 1 when the channel management block is engaged for
the slave channels. Gain2/3 term is equal to one for channel 1.
Voltage−Control Loop of Boost Stage
The voltage−control loop regulates PFC output voltage by
using the internal error amplifier, Gmv, making voltage on
FBPFC same as the internal reference voltage, 2.5 V. It
stabilizes PFC output voltage and decreases 120−Hz ripple
on PFC output voltage.
Figure 18. Gain Modulation Block
IEA
VIN
IMO
OPFC
FBPFC RFB3
VPFC
RI
IL
RCS
Drive
Logic
OSC
CS+
IAC
VEA
RIAC
CV2 CV1
RV1
PVO
CM
CM RM
gmi
gmv
RFB1+FB2
LS
CI2
CI1
RI1
LPK Peak
Detecter
2.5V
CS−
GC
LPT
TriFault Detect Technology
To improve power supply reliability, reduce system
component count, and simplify compliance to UL 1950
safety standards, the FAN9673 brings TriFault Detect
technology. This feature monitors FBPFC for certain PFC
fault conditions.
In the case of a feedback path failure, the output of the PFC
can exceed operating limits. Should FBPFC go too low, too
high, or open, the TriFault Detect senses the fault and
terminates the PFC output drive.
TriFault Detect is an entirely internal circuit. It requires no
external components to perform its function.
PFC Over−Voltage Protection (OVP)
FAN9673 has an auto−restart OVP function. When the
feedback level, VFBPFC, reaches 2.75 V (reference level is
2.5 V), the PFC gate signal stops. The PFC gate signal
resumes when VFBPFC returns to 2.5 V.
PFC Brown In/Out (BIBO)
An internal AC Under−Voltage Protection (UVP)
comparator monitors the AC input information from VIN, as
shown in Figure 19. The OPFC is disabled when the VBIBO
is less than 1.05 V for 410 ms. If VBIBO is larger than 1.9 V
(VVIR < 1.5 V) or 1.75 V (VVIR > 3.5 V), the PFC stage is
enabled. The VIR pin is used to set the AC input range
according to Table 4.
Table 4. BIBO SETTING OF VARIOUS AC INPUT
Input
Range AC (V)
RVIR
Setting
(kW)
RIAC
Setting
(MW)BIBO Level (V)
Full−Range 85 ∼ 264 10 6 85/75
HV−Single 180 ∼ 264 470 12 170/160
Figure 19. VBIBO According to the PFC Operation
VIN
VBIBO
PFC runs
1.9V/1.7V (PFC brown−in threshold)
1.05V (brownout protection trip point)
PFC Gate Driver
For high−power applications, the switch device of the
system requires high driving current. The totem−pole circuit
shown in Figure 20 is recommended.
FAN9673
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16
Figure 20. Gate Drive Circuit
VDD
SPFC
RCS
Differential Current Sensing (CS+, CS−)
Switching noise problems in interleaved PFC control is
more critical than on a single channel, especially for current
sensing. The FAN9673 uses a differential amplifier to
eliminate switching noise from other channels. The
FAN9673 has three groups of differential current−sensing
pins. The CSn+ and CSn− are the inputs of the internal
differential amplifiers. This makes the PFC more stable in
higher−power applications and eliminates switching noise
from other channels. As Figure 21 shows, ground bounce
can be decreased by a differential sense function.
Figure 21. Gate Drive Circuit
PeriodPeriod
Differential
Current Sense
Linear Predict Function (GC & LS)
Current sense signal reflects inductor current only when
OPFC is on. The linear predict function is used to emulate
the behavior of inductor current when the OPFC is off.
Resistor on the LS pin is used to set equivalent inductance
value for the internal emulator. Resistor on the GC pin is
used to align sensed input voltage (IAC) and output voltage
(FBPFC) signals. Values of those resistors can be
determined by:
RLS +LPFC
1.5 10*9 RCS (RFB1)RFB2)RFB3)
RFB3
(eq. 5)
RGC +6 106
(RFB1)RFB2)RFB3
RFB3
)(eq. 6)
Care must be taken that RLS value need to be within
12~87 k.
Current−Limit Protection
The FAN9673 includes three factors that limits current to
manage OCP and inductor saturation: VVEA limit, VILIMIT,
and VILIMIT2. The current-limit thresholds, VILIMIT1 and
VILIMIT2, are configurable through ILIMIT and ILIMIT2
pins.
Power (Normal State)
In the normal case, average input power is controlled by
the command VVEA. When VVEA rises to 5.6 V, it is
internally clamped. Input power can’t increase further.
Current Limit 1 (Abnormal State)
The current command from the gain modulator is
K×IAC ×VVEA/VLPK2. In abnormal state, such as AC cycle
miss and recover in a short period, the VLPK has a delay
before returning to the original level. This delay makes the
current command increased. If the command is greater than
the limit clamp level, VILIMIT, current command will be
clamped, as shown in Figure 22 and Figure 23. The peak
current of this state can be used as the maximum current for
inductor design, assuring inductor is not saturated.
Figure 22. Current Command Limit by ILIMIT
RI
5
ILIMIT
3
1.2V
A
C
B
Gain Modulator
I
RILIMIT
VRM 4
I × RILIMIT
Current Limit 2 (Saturation State)
Use 80% ~ 90% of the maximum current of the switch
device to serve as the saturation protection. VLIMIT2 is a
cycle−by−cycle limit.
Figure 23. ILIMIT and ILIMIT2 Setting
VCS
PFC
Command
Gmi+
VCS.PK
VILIMIT/4
VILIMIT2 = Saturation Protection
Right design,
max power
limited by
VVEA
Right design at
abnormal test,
command from
Multiplier clamp
by V ILIMIT
Wrong design at
abnormal test, but
protect by V ILIMIT2
Non−Saturation V
Case1:
Max. Power (Normal),
VVEA−MAX “B” = 6 V
Case2:
> Max. Power (Abnormal),
VVEA−MAX “B” = 6 V
AC cycle drop
VVEA = 6V, but “C” abnormal
short time, clamp by VILIMIT
Case3:
> Max. Power (Abnormal),
AC cycle drop, as left case,
but user uses wrong choke
can not afford current at Max.
mommand.
Programmable PFC Output Voltage (PVO)
In some cases, decreasing the PFC output voltage can
improve efficiency of the PFC stage. The PVO pin is used
to program output voltage, as shown in Figure 24. An
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17
external voltage signal, from MCU or other source, is
provided to PVO pin.
This function is enabled when VPVO > 0.5 V. Upon
enabled, VFBPFC regulation target becomes:
VFBPFC +2.5 V *ƪVPVO
4ƫ(eq. 7)
For instance, if PVO input is 1 V, RFB1+RFB2 = 3.7 M,
and RFB3 = 23.7 k, VFBPFB will be regulated to 2.25 V,
making PFC VO = 354 V.
Figure 24. Programmable PFC Output Voltage
RFB2
RFB3
FBPFC
VPFC
VO
VFBPFC
2.25V
2.5V
354V
393V
PVO
IL
RCS
2.5V
gmv
External
Signal
(MCU)
Voltage Protection
1V
0V
VFBPFC
R
PVO
FB1
RDY Function and AC Line Off/AC “SAG”
The ready (RDY) function is used to signal the MCU that
the PFC stage is ready and the downstream power stage can
start to operate. When the feedback voltage on FBPFC rises
above 2.4 V, VRDY signal pulls HIGH as shown in Figure 25.
If the AC line is OFF (or AC signal drops for a long time),
the FAN9673 enters brown−out and VRDY pulls LOW to
indicate to the MCU that the power stage should stop, as
shown in Figure 26.
When the AC signal drops for only a short time (i.e. 1~1.5
AC cycles), brown−out is not triggered and VFBPFC may not
drop too much. In this case, RDY will not go LOW as shown
in Figure 27.
AC “sag” means the AC drops to a low level, such as
110 V / 220 V → 40 V. AC “missing” means the AC drops
to 0 V. If AC drops, the PFC attempts to transfer energy to
VO before VO drops to the 50% level. If AC is 0 V, the PFC
can’t transfer energy. If the level reaches 50%, the PFC
stops, and FAN9673 resets and waits for AC to return.
Figure 25. RDY Function to MCU
RDY
FBPFC
IL
RFB1 + FB2
RFB3
VPFC
VREF
MCU
FR: 2.4V/1.25V
HV: 2.4V/1.55V
Brown out
Figure 26. When AC Drops for a Long Time
IL
VFBPFC
VVEA
PFC Soft Start
VRDY à
MCU Second Power Stage working
AC OFF
(AC Long Time Drop)
Brownout &
RDY Pull−Low
PFC Soft
Start
V
AC
VSS
VIN−OK = 2.4V
VIN−OFF = 1.25V (FR) /
1.55V (HV)
Figure 27. AC Drops Briefly
PFC Soft Start
Second Power Stage working
AC Short Time Drop
à
IL
V
AC
VIN−OK = 2.4V
V = 1.25V (FR) /
1.55V (HV)
IN−OFF
VFBPFC
VVEA
VRDY MCU
VSS
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18
Soft−Start
Soft−start is combined with RDY pin operation, as
Figure 26 and Figure 27 show. During startup, the RDY pin
remains LOW until the PFC output voltage reaches 96% of
its nominal value. When the supply voltage of the
downstream converter is controlled by the RDY pin, the
PFC stage always starts with no load because the
downstream converter does not operate until the PFC output
voltage reaches the required level for the design.
Usually, the error amplifier output, VVEA, is saturated to
HIGH during startup because the actual output voltage is
less than the target value. VVEA remains saturated to HIGH
until the PFC output voltage reaches its target value. Once
the PFC output reaches its target value, the error amplifier
comes out of saturation. However, it takes several line cycles
for VVEA to drop to its proper value for output regulation,
which delivers more power to the load than required and
causes output voltage overshoot. To prevent output voltage
overshoot during startup caused by the saturation of error
amplifier, the FAN9673 clamps the error amplifier output
voltage (VEA) by the VSS value until PFC output reaches
96% of its nominal value.
Input Voltage Peak Detection
The input AC peak voltage is sensed at the IAC pin.
Ideally, RMS value of the input voltage should be used for
feed−forward control in the gain modulator circuit. Since the
RMS value of the AC input voltage is directly proportional
to its peak, it is sufficient to find the peak instead of the
more−complicated and slower method of integrating the
input voltage over a half line cycle. The internal circuit of the
IAC pin works with peak detection on the input AC
waveform and output to the LPK pin for MCU use, as shown
in Figure 28.
Figure 28. Waveform of LPK Function
VIN/100
VLPK
95%
tUPDATE = 3.5 ms
VAC−OFF =10%* VLPK
tBLANK =5ms
No update after AC−OFF
VAC−ON =20%*V
LPK
tBLANK =5ms
tAC−OFF =2.5ms
VIN /100 >VLPK +0.2V
Step−up tracking
IEA pull low
tAC−OFF =2.5ms
IEA pull low
One of the important benefits of this approach is that the
peak indicates the correct RMS value even at no load. At no
load, the HF filter capacitor at the input side of the boost
converter is not discharged around the zero−crossing of the
line waveform. Another notable benefit is that, during line
transients, when the peak exceeds the previously measured
value, the input−voltage feed−forward circuit can react
immediately without waiting for a valid integral value at the
end of the half−line period.
The relationship of VIN.PK to VLPK is shown in Figure 29.
The peak detection circuits recognizes the VIN information
from IAC. When recommended design values in Table 4 are
followed, RLPK pin sets the ratio of VIN to VLPK via a
resistor RRLPK as described in eq. 8. The target value of
VLPK is usually set as one percent (1%) of VIN_pk. The
maximum VLPK should not exceed 3.8 V when system
operation is at maximum AC input.
As in the below design example, assume the maximum
VIN.PK at 373 V (264 VAC), the relationship of
VIN.PK/V
LPK is 100, and VLPK = 3.73 V < 3.8 V.
VLPK +VIN.PK
100 RRLPK
12.4k (eq. 8)
Figure 29. Relationship of VIN.PK to VLPK
Peak
Detector
Ratio
IAC
RIAC
LPK
RLPK
VLPK
VIN
R
LPK
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Typical Performance Characteristics
Typical characteristics are provided at TA = 25°C and VDD = 15 V unless otherwise noted.
Figure 30. IDD−OP vs. Temperature Figure 31. VDD−OVP vs. Temperature
Figure 32. fosc vs. Temperature Figure 33. VRI vs. Temperature
Figure 34. VBIBO−FL vs. Temperature Figure 35. VBIBO−FH vs. Temperature
Figure 36. VBIBO−HL vs. Temperature Figure 37. VBIBO−HH vs. Temperature
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Typical Performance Characteristics (continued)
Typical characteristics are provided at VDD = 15 V unless otherwise noted.
Figure 38. VFBPFC−RD vs. Temperature Figure 39. GmV−MAX vs. Temperature
Figure 40. VOFFSET vs. Temperature Figure 41. GMI vs. Temperature
Figure 42. VPFC−OVP vs. Temperature Figure 43. VREF vs. Temperature
Figure 44. ILIMIT vs. Temperature Figure 45. VLIMIT vs. Temperature
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Typical Performance Characteristics (continued)
Typical characteristics are provided at VDD = 15 V unless otherwise noted.
Figure 46. ILIMIT2 vs. Temperature Figure 47. VILIMIT2−CS1 vs. Temperature
Figure 48. tPFC−BNK vs. Temperature Figure 49. VRLPK−OPEN vs. Temperature
Figure 50. VLPK−H1 vs. Temperature Figure 51. VLPK−H2 vs. Temperature
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Table 5. TYPICAL APPLICATION CIRCUIT
Application Output Power Input Voltage Output Voltage/Output Current
Single−Stage, Three−Channel PFC 5000 W 180 ∼ 264 VAC 393 V/12.72 A
Features
•180 VAC ~264 V, Three−Channel PFC Using FAN9673
•Switch−Charge Technique of Gain Modulator for Better
PF and Lower THD
•40 kHz Low Switching Frequency Operation with IGBT
•Protections: Over−Voltage Protection (OVP),
Under−Voltage Protection (UVP), and Over−Current
Protection (ILIMIT), Inductor Saturation Protection
(ILIMIT2)
Figure 52. Schematic of Design Example
SPFC1~3
CB
Rsen1
RB1
VPFC
IEA1
RI
SS
LPK
CS1−
IAC
ILIMIT2
GND
OPFC1
VIR
VDD
FBPFC
VEA CVC1
RVC1
CVC2
CSS
PVOCM1 CM2 CM3
CS1+ CS2− CS2+ CS3− CS3+
IEA2
IEA3
LS
GC
RDY ILIMIT
OPFC2 OPFC3
FAN9673
RILIMIT2
CILIMIT2
RRI
MCU signal
(DC)
COUT
RFB1
RFB3
CFB
CVDD
RVIR
CVIR
MCU/
Sec. Stage
(PFC Ready)
FGH40N60SMDF
CIC11
RIC11
CIC12
CIC21
RIC21
CIC122
CIC31
RIC31
CIC32
RF1~2
CF1
CB2
BIBO
RB1
RB2
RA1
RA2
RB4
RFB2
VDD
Rsen2
VDD
Rsen3
VDD
CF2
LPFC1 DPFC1
FFH30S60STU
LPFC2
LPFC3
DPFC2
FFH30S60STU
DPFC3
FFH30S60STU
RLPK
RLPK
CRLPK
CB1
RB3
RGC
CGC
RLS
CLS
MCU
CLPK
RLPK
RILIMIT
CILIMIT
DC Setting Level
Standby
Power
* DBP1, 2
1N5406
1 F
1 M
1 M
6 M
6 M
200 k
16.2 k
47 nF 0.47 F0.47 F
12.1 k
43 k
38.2 k
10 k
4.7 k
10 nF
470 pF
470 pF
10 nF
0.1 F
100 H
100 H
100 H
15 m15 m15 m
470
2.2 nF
2.2 nF
20 k30 k
10 nF
2.2 M
1.5 M
23.7 k
470 pF
2040 F
100 nF
100 pF
100 pF
100 pF
22 F
1 nF
1 nF
75 k
17.4 k
17.4 k
17.4 k
470 k
1 F
1 nF
1 nF
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Specification
•VDD Maximum Rating: 20 V
•VDD OVP: 24 V
•VCC UVLO: 10.3 V/12.8 V
•PVO: 0 V ∼ 1 V
•PFC Soft−Start: CSS = 0.47 F
•Brown−In/Out: 175 V/165 V
•Switching Frequency: 40 kHz
•VFBPFC for RDY: 2.4 V/1.55 V (96% / 62%)
•RIAC: 12 M
Inductor Schematic Diagram
•Core: QP2925H (3C94)
•Bobbin: 4 Pins
Figure 53. Inductor Schematic Diagram
Table 6. WINDING SPECIFICATION
No. Winding Pin (S " F) Wire Turns Winding Method
1 N1 1 → 4 0.1 ×40 *1 46 Solenoid Winding
2Insulation: Polyester Tape t = 0.025 mm, 2−Layer
3Copper−Foil 1.2T to PIN3
Table 7. MOSFET AND DIODE REFERENCE SPECIFICATION
IGBT’s
Voltage Rating
600 V (IGBT) FGH40N60SMDF
Boost Diodes
600 V FFH30S60STU
Typical Performance
Table 8. EFFICIENCY
25% Load 50% Load 75% Load 100% Load
180 V/50 Hz 96.5% 96.5% 96.5% 96.2%
220 V/50 Hz 97.0% 97.1% 97.2% 97.1%
264 V/50 Hz 97.6% 97.9% 97.7% 97.6%
Table 9. POWER FACTOR
25% Load 50% Load 75% Load 100% Load
180 V/50 Hz 0.9912 0.9947 0.9971 0.9974
220 V/50 Hz 0.9800 0.9868 0.9905 0.9924
264 V/50 Hz 0.9365 0.9369 0.9526 0.9600
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Table 10. TOTAL HARMONIC DISTORTION
25% Load 50% Load 75% Load 100% Load
180 V/50 Hz 10.55% 9.17% 6.62% 6.40%
220 V/50 Hz 14.32% 14.36% 12.55% 11.26%
264 V/50 Hz 25.85% 33.22% 29.59% 27.29%
System Design Precautions
•Pay attention to the inrush current when AC input is first
connected to the boost PFC convertor. It is recommended
to use NTC and a parallel connected relay circuit to reduce
inrush current.
•Add bypass diode to provide a path for inrush current
when PFC start up.
•The PFC stage is normally used to provide power to a
downstream DC−DC or inverter. It’s recommend that
downstream power stage is enabled to operate at full load
once the PFC output voltage has reaches a level close to
the specified steady−state value.
•The PVO function is used to change the output voltage of
PFC, VPFC. The VPFC should be kept at least 25 V higher
than VIN.
LQFP−32, 7x7
CASE 561AB−01
ISSUE O
DATE 19 JUN 2008
MECHANICAL CASE OUTLINE
PACKAGE DIMENSIONS
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