DF2B7AE,H3F - TOSHIBA - Datasheet.Live

DF2B7AE

ESD Protection Diodes Silicon Epitaxial Planar

DF2B7AE

Start of commercial production

2016-10

1. General

General

The DF2B7AE is a TVS diode (ESD protection diode) protects

semiconductor devices used in mobile device interfaces and other

applications to protect against static electricity and noise.

Utilizing snapback characteristics, the DF2B7AE provides low dynamic

resistance and superior protective performance. Furthermore, the

DF2B7AE is housed in an ultra-compact package (0.8 × 1.2 mm) to

meet applications that require a small footprint.

2. Applications

Applications

Mobile Equipment

 Smartphones

 Tablets

 Notebook PCs

Desktop PCs

Note: This product is designed for protection against electrostatic discharge (ESD) and is not intended for any other

purpose, including, but not limited to, voltage regulation.

3. Features

Features

(1) Suitable for use with a 5 V signal line. (VRWM ≤ 5.5 V)

(2) Protects devices with its high ESD performance.

(VESD = ±30 kV (Contact / Air) @IEC61000-4-2)

(3) Low dynamic resistance protects semiconductor devices from static electricity and noise.

(RDYN = 0.2 Ω (typ.))

(4) Snapback characteristics realizing low clamping voltage protects semiconductor devices.

(VC = 11 V@IPP = 4 A (typ.))

(5) Compact package is suitable for use in high density board layouts such as in mobile devices.

SOD-523: 0.8 × 1.2 mm size (Toshiba package name: ESC)

4. Example of Circuit Diagram

Example of Circuit Diagram

2016-11-01

Rev.1.0

DF2B7AE

5. Quick Reference Data

Quick Reference Data

Characteristics

Working peak reverse voltage

Total capacitance

Dynamic resistance

Electrostatic discharge voltage

(IEC61000-4-2) (Contact)

Symbol

VRWM

RDYN

VESD

Note

(Note 1)

(Note 2)

(Note 3)

Test Condition



VR = 0 V, f = 1 MHz



Min



Typ.



8.5

0.2



Max

5.5



Unit

Ω

Note 1: Recommended operating condition.

Note 2: TLP parameters: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of

dynamic resistance using least squares fit of TLP characteristics between IPP1 = 8 A and IPP2 = 16 A.

Note 3: Criterion: No damage to devices.

5.1.

5.1. ESD Clamp Waveform (Note)

ESD Clamp Waveform (Note)

Fig.

Fig. 5.1.1

5.1.1

5.1.1 +8 kV

+8 kV

+8 kV Fig.

Fig.

Fig. 5.1.2

5.1.2

5.1.2 -8 kV

-8 kV

Fig.

Fig. 5.1.3

5.1.3

5.1.3 IEC61000-4-2 (Contact)

IEC61000-4-2 (Contact)

Note: The above characteristics curves are presented for reference only and not guaranteed by production test,

unless otherwise noted.

2016-11-01

Rev.1.0

DF2B7AE

5.2.

5.2. TLP Characteristics (Note)

TLP Characteristics (Note)

Note: The above characteristics curves are presented for reference only and not guaranteed by production test,

unless otherwise noted.

5.3.

5.3. Clamp Voltage V

Clamp Voltage V

Clamp Voltage VC

C - Peak Pulse Current (I

- Peak Pulse Current (I

- Peak Pulse Current (IPP

PP) (Note)

) (Note)

Fig.

Fig. 5.3.1

5.3.1

5.3.1 V

C - I

- I

- IPP

PP Fig.

Fig.

Fig. 5.3.2

5.3.2

5.3.2 Based on IEC61000-4-5 8/20

Based on IEC61000-4-5 8/20

Based on IEC61000-4-5 8/20 µ

µs pulse.

s pulse.

Note: The above characteristics curves are presented for reference only and not guaranteed by production test,

unless otherwise noted.

2016-11-01

Rev.1.0

DF2B7AE

6. Absolute Maximum Ratings (Note) (Unless otherwise specified, T

Absolute Maximum Ratings (Note) (Unless otherwise specified, T

Absolute Maximum Ratings (Note) (Unless otherwise specified, Ta

a = 25

= 25

= 25 



)

)

Characteristics

Electrostatic discharge voltage (IEC61000-4-2) (Contact)

Electrostatic discharge voltage (IEC61000-4-2) (Air)

Peak pulse power (tp = 8/20 µs)

Peak pulse current (tp = 8/20 µs)

Junction temperature

Storage temperature

Symbol

VESD

PPK

IPP

Tstg

Note

(Note 1)

(Note 2)

Rating

±30

150

-55 to 150

Unit



Note: Using continuously under heavy loads (e.g. the application of high temperature/current/voltage and the

significant change in temperature, etc.) may cause this product to decrease in the reliability significantly even

if the operating conditions (i.e. operating temperature/current/voltage, etc.) are within the absolute maximum

ratings.

Please design the appropriate reliability upon reviewing the Toshiba Semiconductor Reliability Handbook

("Handling Precautions"/"Derating Concept and Methods") and individual reliability data (i.e. reliability test

report and estimated failure rate, etc).

Note 1: According to IEC61000-4-2.

Note 2: According to IEC61000-4-5.

7. Electrical Characteristics (Unless otherwise specified, T

Electrical Characteristics (Unless otherwise specified, T

Electrical Characteristics (Unless otherwise specified, Ta

a = 25

= 25

= 25 



)

)

VRWM: Working peak reverse voltage

VBR: Reverse breakdown voltage

IBR: Reverse breakdown current

IR: Reverse current

VC: Clamp voltage

IPP: Peak pulse current

RDYN: Dynamic resistance

Fig.

Fig. 7.1

7.1

7.1 Definitions of Electrical Characteristics

Definitions of Electrical Characteristics

Characteristics

Working peak reverse voltage

Total capacitance

Dynamic resistance

Reverse breakdown voltage

Reverse current

Clamp voltage

Symbol

VRWM

RDYN

VBR

Note

(Note 1)

(Note 2)

(Note 3)

(Note 2)

Test Condition



VR = 0 V, f = 1 MHz



IBR = 1 mA

VRWM = 5.5 V

IPP = 1 A

IPP = 4 A

ITLP = 16 A

ITLP = 30 A

Min



5.8



Typ.



8.5

0.2

6.8



Max

5.5



7.8

100



Unit

Ω

Note 1: Recommended operating condition.

Note 2: TLP parameters: Z0 = 50 Ω, tp = 100 ns, tr = 300 ps, averaging window: t1 = 30 ns to t2 = 60 ns, extraction of

dynamic resistance using least squares fit of TLP characteristics between IPP1 = 8 A and IPP2 = 16 A.

Note 3: Based on IEC61000-4-5 8/20 µs pulse.

2016-11-01

Rev.1.0

DF2B7AE

8. Characteristics Curves (Note)

Characteristics Curves (Note)

Fig.

Fig. 8.1

8.1

8.1 I - V

I - V

I - V Fig.

Fig.

Fig. 8.2

8.2

8.2 I

R - V

- V

- VR

Fig.

Fig. 8.3

8.3

8.3 C

t - V

- V

- VR

RFig.

Fig.

Fig. 8.4

8.4

8.4 C

t - f

- f

Fig.

Fig. 8.5

8.5

8.5 S21 - f

S21 - f

Note: The above characteristics curves are presented for reference only and not guaranteed by production test,

unless otherwise noted.

2016-11-01

Rev.1.0

DF2B7AE

9. Packaging and Internal Circuit (Note)

Packaging and Internal Circuit (Note)

ESC

1: Pin 1

2: Pin 2

Note: Connect Pin 2 to GND when using Pin 1 for I/O.

Connect Pin 1 to GND when using Pin 2 for I/O.

10.

10. Marking (Top view)

Marking (Top view)

11.

11. Land Pattern Dimensions (for reference only)

Land Pattern Dimensions (for reference only)

Unit: mm

2016-11-01

Rev.1.0

DF2B7AE

Package Dimensions

Unit: mm

Weight: 1.4 mg (typ.)

Package Name(s)

JEDEC: SOD-523

Nickname: ESC

2016-11-01

Rev.1.0

DF2B7AE

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application circuits, or any other referenced documents; and (c) validating all operating parameters for such designs and applications.

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2016-11-01

Rev.1.0