Datasheet PD48288209A PD48288218A PD48288236A R10DS0097EJ0100 Rev.1.00 February 28, 2012 288M-BIT Low Latency DRAM Common I/O Description The PD48288209A is a 33,554,432-word by 9 bit, the PD48288218A is a 16,777,216-word by 18 bit and the PD48288236A is a 8,388,608-word by 36 bit synchronous double data rate Low Latency RAM fabricated with advanced CMOS technology using one-transistor memory cell. The PD48288209A, PD48288218A and PD48288236A integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (CK and CK#) are latched on the positive edge of CK and CK#. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration. Specification Features * Density: 288M bit * SRAM-type interface * Organization * Double-data-rate architecture - Common I/O: 4M words x 9 bits x 8 banks 2M words x 18 bits x 8 banks * PLL circuitry * Cycle time: 1.875 ns @ tRC = 15 ns 1M words x 36 bits x 8 banks * Operating frequency: 533 / 400 / 300 MHz 2.5 ns @ tRC = 15 ns * Interface: HSTL I/O 2.5 ns @ tRC = 20 ns * Package: 144-pin TAPE FBGA 3.3 ns @ tRC = 20 ns - Package size: 18.5 x 11 - Leaded and Lead free * Power supply * Non-multiplexed addresses * Multiplexing option is available. - 2.5 V VEXT * Data mask for WRITE commands - 1.8 V VDD * Differential input clocks (CK and CK#) - 1.5 V or 1.8 V VDDQ * Refresh command - Auto Refresh - 8192 cycle / 32 ms for each bank - 64K cycle / 32 ms for total * Operating case temperature : Tc = 0 to 95C R10DS0097EJ0100 Rev.1.00 February 28, 2012 * Differential input data clocks (DK and DK#) * Data valid signal (QVLD) * Programmable burst length: 2 / 4 / 8 (x9 / x18 / x36) * User programmable impedance output (25 - 60 ) * JTAG boundary scan Page 1 of 48 PD48288209A, PD48288218A, PD48288236A Ordering Information Part number Cycle Clock Time Frequency Random Organization Core Supply Core Supply Output Supply Cycle ns MHz Ns PD48288209AFF-E18-DW1-A 1.875 533 15 PD48288209AFF-E24-DW1-A 2.5 400 15 PD48288209AFF-E25-DW1-A 2.5 400 20 PD48288209AFF-E33-DW1-A 3.3 300 20 PD48288218AFF-E18-DW1-A 1.875 533 15 PD48288218AFF-E24-DW1-A 2.5 400 15 PD48288218AFF-E25-DW1-A 2.5 400 20 PD48288218AFF-E33-DW1-A 3.3 300 20 PD48288236AFF-E18-DW1-A 1.875 533 15 PD48288236AFF-E24-DW1-A 2.5 400 15 PD48288236AFF-E25-DW1-A 2.5 400 20 PD48288236AFF-E33-DW1-A 3.3 300 20 PD48288209AFF-E18-DW1 1.875 533 15 PD48288209AFF-E24-DW1 2.5 400 15 PD48288209AFF-E25-DW1 2.5 400 20 PD48288209AFF-E33-DW1 3.3 300 20 PD48288218AFF-E18-DW1 1.875 533 15 PD48288218AFF-E24-DW1 2.5 400 15 PD48288218AFF-E25-DW1 2.5 400 20 PD48288218AFF-E33-DW1 3.3 300 20 PD48288236AFF-E18-DW1 1.875 533 15 PD48288236AFF-E24-DW1 2.5 400 15 PD48288236AFF-E25-DW1 2.5 400 20 PD48288236AFF-E33-DW1 3.3 300 20 R10DS0097EJ0100 Rev.1.00 February 28, 2012 (word x bit) 32 M x 9 Package Voltage Voltage Voltage (VEXT) (VDD) (VDDQ) V V V 2.5 + 0.13 1.8 0.1 1.5 0.1 144-pin or TAPE FBGA 1.8 0.1 (18.5 x 11) 2.5 - 0.12 16 M x 18 Lead-free 8 M x 36 32 M x 9 2.5 + 0.13 2.5 - 0.12 16 M x 18 1.8 0.1 1.5 0.1 144-pin or TAPE FBGA 1.8 0.1 (18.5 x 11) Lead 8 M x 36 Page 2 of 48 PD48288209A, PD48288218A, PD48288236A Pin Arrangement 144-pin TAPE FBGA (18.5 x 11) (Top View) [Common I/O x9] A B C D E 1 2 3 4 VREF VSS VEXT VSS VDD VTT Note 1 (A22) Note 1 (A21) Note 3 DNU Note 3 DNU Note 3 DNU Note 3 DNU Note 3 Note 3 DNU Note 3 DNU Note 3 DNU Note 3 DNU Note 3 5 6 7 VSSQ 8 9 10 11 12 VSS VEXT TMS TCK VSSQ DQ0 Note 3 VDD DNU Note 3 VDDQ VDDQ DQ1 DNU VTT VSSQ VSSQ QK0# QK0 VSS VDDQ VDDQ DQ2 Note 3 A20 DNU Note 3 F A5 DNU DNU VSSQ VSSQ DQ3 DNU QVLD G A8 A6 A7 VDD VDD A2 A1 A0 H BA2 A9 VSS VSS VSS VSS A4 A3 J Note 2 Note 2 NF NF VDD VDD VDD VDD BA0 CK K DK DK# VDD VDD VDD VDD BA1 CK# L REF# CS# VSS VSS VSS VSS A14 A13 M WE# A16 A17 VDD VDD A12 A11 A10 N P R T A18 A15 VSS VTT Note 3 DNU Note 3 DNU Note 3 DNU Note 3 DNU Note 3 Note 3 DNU Note 3 DNU Note 3 DNU Note 3 DNU Note 3 VSSQ VSSQ VDDQ VDDQ VSSQ VSSQ VDDQ VDDQ DQ4 DQ5 DQ6 DQ7 Note 3 DNU Note 3 DNU Note 3 DNU Note 3 DNU Note 3 A19 DM VSS VTT U VDD DNU DNU VSSQ VSSQ DQ8 DNU VDD V VREF ZQ VEXT VSS VSS VEXT TDO TDI Notes 1. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to VSS, or left open. 2. No function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may optionally be connected to VSS, or left open. 3. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to VSS, or left open. CK, CK# CS# WE# REF# A0-A20 A21-A22 BA0-BA2 DQ0-DQ8 DK, DK# DM QK0, QK0# QVLD ZQ : Input clock : Chip select : WRITE command : Refresh command : Address inputs : Reserved for the future : Bank address input : Data input/output : Input data clock : Input data Mask : Output data clock : Data Valid : Output impedance matching TMS TDI TCK TDO VREF VEXT VDD VDDQ VSS VSSQ VTT NF DNU : IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : DQ Power Supply : Ground : DQ Ground : Power Supply : No function : Do not use # indicates active LOW signal. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 3 of 48 PD48288209A, PD48288218A, PD48288236A Pin Arrangement 144-pin TAPE FBGA (18.5 x 11) (Top View) [Common I/O x18] A B 1 2 3 4 VREF VSS VEXT VSS VDD C VTT Note 1 D (A22) Note 1 Note 3 DNU Note 3 DNU Note 3 DNU Note 3 E (A21) DNU F A5 G H DQ4 5 6 7 8 VSSQ 9 10 11 12 VSS VEXT TMS TCK VSSQ DQ0 Note 3 VDD DNU Note 3 DQ5 VDDQ VDDQ DQ1 DNU VTT DQ6 VSSQ VSSQ QK0# QK0 VSS Note 3 Note 1 DQ7 VDDQ VDDQ DQ2 DNU DNU DQ8 VSSQ VSSQ DQ3 DNU QVLD A8 A6 A7 VDD VDD A2 A1 A0 BA2 A9 VSS VSS VSS VSS A4 A3 Note 3 Note 3 (A20) J Note 2 Note 2 NF NF VDD VDD VDD VDD BA0 CK K DK DK# VDD VDD VDD VDD BA1 CK# L REF# CS# VSS VSS VSS VSS A14 A13 M WE# A16 A17 VDD VDD A12 A11 A10 N P R T A18 A15 VSS VTT Note 3 DNU Note 3 DNU QK1 Note 3 DNU Note 3 DQ14 DQ15 QK1# DQ16 VSSQ VSSQ VDDQ VDDQ VSSQ VSSQ VDDQ VDDQ DQ9 DQ10 DQ11 DQ12 Note 3 DNU Note 3 DNU Note 3 DNU Note 3 DNU Note 3 A19 DM VSS VTT U VDD DNU DQ17 VSSQ VSSQ DQ13 DNU VDD V VREF ZQ VEXT VSS VSS VEXT TDO TDI Notes 1. Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to VSS, or left open. 2. No function. This signal is internally connected and has parasitic characteristics of a clock input signal. This may optionally be connected to VSS, or left open. 3. Do not use. This signal is internally connected and has parasitic characteristics of a I/O. This may optionally be connected to VSS, or left open. CK, CK# CS# WE# REF# A0-A19 A20-A22 BA0-BA2 DQ0-DQ17 DK, DK# DM QK0-QK1, QK0#-QK1# QVLD ZQ : Input clock : Chip select : WRITE command : Refresh command : Address inputs : Reserved for the future : Bank address input : Data input/output : Input data clock : Input data Mask : Output data clock : Data Valid : Output impedance matching TMS TDI TCK TDO VREF VEXT VDD VDDQ VSS VSSQ VTT NF DNU : IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : DQ Power Supply : Ground : DQ Ground : Power Supply : No function : Do not use # indicates active LOW signal. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 4 of 48 PD48288209A, PD48288218A, PD48288236A Pin Arrangement 144-pin TAPE FBGA (18.5 x 11) (Top View) [Common I/O x36] 1 2 3 4 A VREF VSS VEXT B VDD DQ8 C VTT D Note (A22) Note 5 6 7 8 9 10 11 12 VSS VSS VEXT TMS TCK DQ9 VSSQ VSSQ DQ1 DQ0 VDD DQ10 DQ11 VDDQ VDDQ DQ3 DQ2 VTT DQ12 DQ13 VSSQ VSSQ QK0# QK0 VSS Note E (A21) DQ14 DQ15 VDDQ VDDQ DQ5 DQ4 (A20) F A5 DQ16 DQ17 VSSQ VSSQ DQ7 DQ6 QVLD G A8 A6 A7 VDD VDD A2 A1 A0 H BA2 A9 VSS VSS VSS VSS A4 A3 J DK0 DK0# VDD VDD VDD VDD BA0 CK K DK1 DK1# VDD VDD VDD VDD BA1 CK# L REF# CS# VSS VSS VSS VSS A14 A13 M WE# A16 A17 VDD VDD A12 A11 A10 N A18 DQ24 DQ25 VSSQ VSSQ DQ35 DQ34 (A19) P A15 DQ22 DQ23 VDDQ VDDQ DQ33 DQ32 DM R VSS QK1 QK1# VSSQ VSSQ DQ31 DQ30 VSS T VTT DQ20 DQ21 VDDQ VDDQ DQ29 DQ28 VTT U VDD DQ18 DQ19 VSSQ VSSQ DQ27 DQ26 VDD V VREF ZQ VEXT VSS VSS VEXT TDO TDI Note Note Reserved for future use. This signal is internally connected and has parasitic characteristics of an address input signal. This may optionally be connected to VSS, or left open. CK, CK# CS# WE# REF# A0-A18 A19-A22 BA0-BA2 DQ0-DQ35 DK0-DK1, DK0#-DK1# DM QK0-QK1, QK0#-QK1# QVLD ZQ : Input clock : Chip select : WRITE command : Refresh command : Address inputs : Reserved for the future : Bank address input : Data input/output : Input data clock : Input data Mask : Output data clock : Data Valid : Output impedance matching TMS TDI TCK TDO VREF VEXT VDD VDDQ VSS VSSQ VTT : IEEE 1149.1 Test input : IEEE 1149.1 Test input : IEEE 1149.1 Clock input : IEEE 1149.1 Test output : HSTL input reference input : Power Supply : Power Supply : DQ Power Supply : Ground : DQ Ground : Power Supply # indicates active LOW signal. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 5 of 48 PD48288209A, PD48288218A, PD48288236A Pin Description (1/2) Symbol CK, CK# Type Input Description Clock inputs: CK and CK# are differential clock inputs. This input clock pair registers address and control inputs on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK. CS# Input Chip select CS# enables the commands when CS# is LOW and disables them when CS# is HIGH. When the command is disabled, new commands are ignored, but internal operations continue. WE#, REF# Input WRITE command pin, Refresh command pin: WE#, REF# are sampled at the positive edge of CK, WE#, and REF# define (together with CS#) the command to be executed. A0-A20 Input Address inputs: A0-A20 define the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. In the x36 configuration, A19-A20 are reserved for address expansion; in the x18 configuration, A20 is reserved for address expansion. These expansion addresses can be treated as address inputs, but they do not affect the operation of the device. A21-A22 Input Reserved for future use: These signals should be tied to VSS or leave open. BA0-BA2 Input Bank address inputs; Select to which internal bank a command is being applied. DQ0-DQxx Input Data input/output: /Output The DQ signals form the 9/18/36 bit data bus. During READ commands, the data is referenced to both edges of QKx. During WRITE commands, the data is sampled at both edges of DKx. x 9 device uses DQ0 to DQ8. x18 device uses DQ0 to DQ17. x36 device uses DQ0 to DQ35. QKx, QKx# Output Output data clocks: QKx and QKx# are opposite polarity, output data clocks. They are always free running and edgealigned with data output from the PD48288209/18/36A. QKx# is ideally 180 degrees out of phase with QKx. For the x36 device, QK0 and QK0# are aligned with DQ0-DQ17. QK1 and QK1# are aligned with DQ18-DQ35. For the x18 device, QK0 and QK0# are aligned with DQ0-DQ8. QK1 and QK1# are aligned with DQ9-DQ17. For the x9 device, QK0 and QK0# are aligned with DQ0-DQ8. DKx, DKx# Input Input data clock; DKx and DKx# are the differential input data clocks. All input data is referenced to both edges of DK. DK# is ideally 180 degrees out of phase with DK. For the x36 device, DQ0-DQ17 are referenced to DK0 and DK0#, and DQ18-DQ35 are referenced to DK1 and DK1#. For the x9 and x18 devices, all DQs are referenced to DK and DK#. DM Input Input data mask; The DM signal is the input mask signal for WRITE data. Input data is masked when DM is sampled HIGH along with the WRITE input data. DM is sampled on both edges of DK (DK1 for the x36 configuration). The signal should be VSS if not used. QVLD Output Data valid; The QVLD indicates valid output data. QVLD is edge-aligned with QKx and QKx#. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 6 of 48 PD48288209A, PD48288218A, PD48288236A (2/2) Symbol ZQ Type Description Input External impedance [25 - 60 ]; /Output This signal is used to tune the device outputs to the system data bus impedance. DQ output impedance is set to 0.2 x RQ, where RQ is a resistor from this signal to VSS. Connecting ZQ to VSS invokes the minimum impedance mode. Connecting ZQ to VDDQ invokes the maximum impedance mode. Refer to Figure 2-5. Mode Register Bit Map to activate this function. TMS , TDI Input JTAG function pins: IEEE 1149.1 test inputs: These balls may be left as no connects if the JTAG function is not used in the circuit TCK Input JTAG function pin; IEEE 1149.1 clock input: This ball must be tied to VSS if the JTAG function is not used in the circuit. TDO Output JTAG function pin; IEEE 1149.1 test output: JTAG output. This ball may be left as no connect if JTAG function is not used. VREF Input Input reference voltage; Nominally VDDQ/2. Provides a reference voltage for the input buffers. VEXT Supply Power supply; 2.5 V nominal. See Recommended DC Operating Conditions for range. VDD Supply Power supply; 1.8 V nominal. See Recommended DC Operating Conditions for range. VDDQ Supply DQ power supply; Nominally, 1.5 V or 1.8 V. Isolated on the device for improved noise immunity. See Recommended DC Operating Conditions for range. VSS Supply Ground VSSQ Supply DQ ground; Isolated on the device for improved noise immunity. VTT Supply Power supply; Isolated termination supply. Nominally, VDDQ/2. See Recommended DC Operating Conditions for range. NF No function; These balls may be connected to VSS. DNU Do not use; These balls may be connected to VSS. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 7 of 48 PD48288209A, PD48288218A, PD48288236A Block Diagram A0-Axx , B0, B1, B2 R10DS0097EJ0100 Rev.1.00 February 28, 2012 Column Decoder Sense Amp and Data Bus Bank 3 Column Decoder Sense Amp and Data Bus Control Logic and Timing Generator DM DQxx Bank 7 VREF Output Buffers Memory Array CS# QKx, QKx# Bank 6 WE# QVLD Input Buffers Memory Array DK0-DK1 Output Data Clock Memory Array Row Decoder DK0#-DK1# Output Data Valid Bank 5 Bank 2 CK Bank 4 Memory Array Column Decoder Column Decoder Memory Array Memory Array Row Decoder Sense Amp and Data Bus Row Decoder Sense Amp and Data Bus Sense Amp and Data Bus Column Decoder Row Decoder Bank 1 Row Decoder CK# Bank 0 Memory Array Column Decoder Column Decoder Memory Array Refresh Counter Row Decoder Sense Amp and Data Bus Row Decoder Sense Amp and Data Bus Sense Amp and Data Bus Column Decoder Row Decoder Row Address Buffer REF# Column Address Buffer Page 8 of 48 PD48288209A, PD48288218A, PD48288236A Contents 1. Electrical Characteristics............................................................................................................10 2. Operation......................................................................................................................................17 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 2.17 Command Operation ................................................................................................................ 17 Description of Commands ....................................................................................................... 17 Initialization ............................................................................................................................... 18 Power-On Sequence ................................................................................................................. 19 Programmable Impedance Output Buffer............................................................................... 19 PLL Reset .................................................................................................................................. 19 Clock Input ................................................................................................................................ 19 Mode Register Set Command (MRS)....................................................................................... 21 Read & Write configuration (Non Multiplexed Address Mode) ............................................. 22 Write Operation (WRITE) .......................................................................................................... 23 Read Operation (READ)............................................................................................................ 26 Refresh Operation: AUTO REFRESH Command (AREF)....................................................... 30 On-Die Termination................................................................................................................... 31 Operation with Multiplexed Address....................................................................................... 34 Address Mapping in Multiplexed Mode................................................................................... 36 Read & Write configuration in Multiplexed Address Mode ................................................... 37 Refresh Command in Multiplexed Address Mode.................................................................. 37 3. JTAG Specification......................................................................................................................39 4. Package Dimensions...................................................................................................................46 5. Recommended Soldering Condition .........................................................................................47 R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 9 of 48 PD48288209A, PD48288218A, PD48288236A 1. Electrical Characteristics Absolute Maximum Ratings Parameter Symbol Conditions Rating Unit Supply voltage VEXT -0.3 to +2.8 V Supply voltage VDD -0.3 to +2.1 V VDDQ -0.3 to +2.1 V Input / Output voltage VIH / VIL -0.3 to +2.1 V Junction temperature Tj MAX. 110 C Storage temperature Tstg -55 to +125 C Output supply voltage, Input voltage, Input / Output voltage Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended DC Operating Conditions 0C TC 95C; 1.7 V VDD 1.9 V, unless otherwise noted. Parameter Symbol Conditions MIN. TYP. MAX. Unit Note Supply voltage VEXT 2.38 2.5 2.63 V 1 Supply voltage VDD 1.7 1.8 1.9 V 1 Output supply voltage VDDQ 1.4 VDD V 1, 2, 3 Reference Voltage VREF 0.49 x VDDQ 0.5 x VDDQ 0.51 x VDDQ V 1, 4, 5 Termination voltage VTT 0.95 x VREF VREF 1.05 x VREF V 1, 6 Input HIGH voltage VIH (DC) VREF + 0.1 V 1 Input LOW voltage VIL (DC) V 1 VREF - 0.1 Notes 1. 2. 3. 4. All voltage referenced to VSS (GND). During normal operation, VDDQ must not exceed VDD. VDDQ can be set to a nominal 1.5 V 0.1 V or 1.8 V 0.1 V supply. Typically the value of VREF is expect to be 0.5 x VDDQ of the transmitting device. VREF is expected to track variations in VDDQ. 5. Peak-to-peak AC noise on VREF must not exceed 2% VREF(DC). 6. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 10 of 48 PD48288209A, PD48288218A, PD48288236A DC Characteristics 0C TC 95C; 1.7 V VDD 1.9 V, unless otherwise noted Parameter Symbol Test condition MIN. MAX. Unit Note Input leakage current ILI -5 +5 A 1,2 Output leakage current ILO -5 +5 A 1,2 Reference voltage current IREF -5 +5 A 1,2 Output high current IOH VOH = VDDQ/2 (VDDQ/2) / (1.15 x RQ/5) (VDDQ/2) / (0.85 x RQ/5) mA 3,4 Output low current IOL VOL = VDDQ/2 (VDDQ/2) / (1.15 x RQ/5) (VDDQ/2) / (0.85 x RQ/5) mA 3,4 Notes 1. Outputs are impedance-controlled. | IOH | = (VDDQ/2)/(RQ/5) for values of 125 RQ 300 . 2. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) for values of 125 RQ 300 . 3. IOH and IOL are defined as absolute values and are measured at VDDQ/2. IOH flows from the device, IOL flows into the device. 4. If MRS bit A8 is 0, use RQ = 250 in the equation in lieu of presence of an external impedance matched resistor. Capacitance (TA = 25 C, f = 1MHz) Parameter Symbol Test conditions MIN. MAX. Unit Address / Control Input capacitance CIN VIN = 0 V 1.5 2.5 pF I/O, Output, Other capacitance CI/O VI/O = 0 V 3.5 5.0 pF Clock Input capacitance Cclk Vclk = 0 V 2.0 3.0 pF JTAG pins CJ VJ = 0 V 2.0 5.0 pF (DQ, DM, QK, QVLD) Remark These parameters are periodically sampled and not 100% tested. Capacitance is not tested on ZQ pin. Recommended AC Operating Conditions 0C TC 95C; 1.7 V VDD 1.9 V, unless otherwise noted Parameter Symbol Input HIGH voltage VIH (AC) Input LOW voltage VIL (AC) Conditions MIN. MAX. VREF + 0.2 VREF - 0.2 Unit Note V 1 V 1 Note 1. Overshoot: VIH (AC) VDDQ + 0.7 V for t tCK/2 Undershoot: VIL (AC) - 0.5 V for t tCK/2 Control input signals may not have pulse widths less than tCKH (MIN.) or operate at cycle rates less than tCK (MIN.). R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 11 of 48 PD48288209A, PD48288218A, PD48288236A DC Characteristics IDD / ISB Operating Conditions Parameter Symbol Test condition MAX. Unit -E18 -E24 -E25 -E33 Standby current ISB1 tCK = Idle VDD All banks idle, no inputs toggling x9/x18 55 55 55 55 x36 55 55 55 55 5 5 5 5 x9/x18 250 215 215 190 x36 250 215 215 190 5 5 5 5 x9/x18 333 302 266 239 x36 375 344 302 283 10 10 10 10 x9/x18 360 345 288 262 x36 433 418 348 339 10 10 10 10 377 357 299 276 15 15 15 15 x9/x18 604 464 464 362 x36 563 432 432 338 45 30 30 25 x9/x18 260 219 205 173 x36 258 216 203 171 10 10 10 10 VEXT Active standby ISB2 current CS# = HIGH, No commands, half bank / address / VDD data change once every four clock cycles VEXT Operating current IDD1 BL=2, sequential bank access, bank transitions VDD once every tRC, half address transitions once every tRC, read followed by write sequence, VEXT mA mA mA continuous data during WRITE commands. Operating current IDD2 BL=4, sequential bank access, bank transitions VDD once every tRC, half address transitions once every tRC, read followed by write sequence, VEXT mA continuous data during WRITE commands. Operating current IDD3 BL=8, sequential bank access, bank transitions VDD x9/x18 mA once every tRC, half address transitions once every tRC, read followed by write sequence, VEXT continuous data during WRITE commands. Burst refresh IREF1 current Disturbed IREF2 IDD2W IDD4W IDD8W IDD2R read current VEXT BL=2, cyclic bank access, half of address bits VDD measurement is taken during continuous WRITE VEXT BL=4, cyclic bank access, half of address bits VDD measurement is taken during continuous WRITE VEXT BL=8, cyclic bank access, half of address bits VDD measurement is taken during continuous WRITE VEXT BL=2, cyclic bank access, half of address bits VDD change every clock cycle, measurement is taken IDD4R read current Operating burst continuous data x9/x18 890 691 691 542 x36 998 792 792 641 40 35 35 30 x9/x18 609 478 478 380 x36 753 608 608 498 25 20 20 20 478 378 378 303 25 20 20 20 x9/x18 927 712 712 551 x36 925 710 710 549 40 35 35 30 x9/x18 619 477 477 377 x36 643 494 494 390 25 20 20 20 475 368 368 292 25 20 20 20 x9/x18 mA mA mA mA mA change every four clocks, continuous data, read current Operating burst VDD change every two clocks, continuous data, write current Operating burst VEXT change every clock cycle, continuous data, write current Operating burst for all banks Single bank refresh, sequential bank access, half address transitions once every tRC, write current Operating burst VDD address/data, command bus remains in refresh refresh current Operating burst Eight bank cyclic refresh, continuous during continuous READ VEXT BL=4, cyclic bank access, half of address bits VDD change every two clocks, measurement is taken IDD8R during continuous READ VEXT BL=8, cyclic bank access, half of address bits VDD x9/x18 mA mA mA change every four clocks, measurement is taken during continuous READ R10DS0097EJ0100 Rev.1.00 February 28, 2012 VEXT Page 12 of 48 PD48288209A, PD48288218A, PD48288236A Remarks 1. IDD specifications are tested after the device is properly initialized. 0C TC 95C; 1.7 V VDD 1.9 V, 2.38 V VEXT 2.63 V, 1.4 V VDDQ VDD, VREF = VDDQ/2 2. tCK = tDK = MIN., tRC = MIN. 3. Input slew rate is specified in Recommended DC Operating Conditions and Recommended AC Operating Conditions. 4. IDD parameters are specified with ODT disabled. 5. Continuous data is defined as half the DQ signals changing between HIGH and LOW every half clock cycles (twice per clock). 6. Continuous address is defined as half the address signals between HIGH and LOW every clock cycles (once per clock). 7. Sequential bank access is defined as the bank address incrementing by one ever tRC. 8. Cyclic bank access is defined as the bank address incrementing by one for each command access. For BL=4 this is every other clock. 9. CS# is HIGH unless a READ, WRITE, AREF, or MRS command is registered. CS# never transitions more than per clock cycle. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 13 of 48 PD48288209A, PD48288218A, PD48288236A AC Characteristics AC Test Conditions Input waveform VDDQ VIH(AC) MIN. VIL(AC) MAX. VSS Rise Time: 2 V/ns Fall Time: 2 V/ns Output waveform Test Points VDDQ / 2 VDDQ / 2 Output load condition VTT 50 DQ Test point 10pF R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 14 of 48 PD48288209A, PD48288218A, PD48288236A AC Characteristics <Read and Write Cycle> Parameter Symbol -E18 -E24 -E25 -E33 Unit (533 MHz) (400 MHz) (400 MHz) (300 MHz) MIN. MAX. MIN. MAX. MIN. MAX. MIN. MAX. Note Clock Clock cycle time (CK,CK#,DK,DK#) tCK, tDK 1.875 5.7 2.5 5.7 2.5 5.7 3.3 5.7 ns Clock frequency (CK,CK#,DK,DK#) tCK, tDK 175 533 175 400 175 400 175 300 MHz Random Cycle time tRC 15 Clock Jitter: period tJIT PER -100 Clock Jitter: cycle-to-cycle tJIT CC 15 100 -150 200 20 150 -150 300 20 150 -200 300 ns 200 ps 400 ps Clock HIGH time (CK,CK#,DK,DK#) tCKH, tDKH 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 Cycle Clock LOW time (CK,CK#,DK,DK#) tCKL, tDKL 0.45 0.55 0.45 0.55 0.45 0.55 0.45 0.55 Cycle Clock to input data clock tCKDK -0.3 0.3 -0.45 0.5 -0.45 0.5 -0.45 1.0 ns Mode register set cycle time tMRSC 6 6 6 6 Cycle 1, 2 to any command PLL Lock time tCK Lock 15 15 15 15 s Clock static to PLL reset tCK Reset 30 30 30 30 ns Output data clock HIGH time tQKH 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCKH Output data clock LOW time tQKL 0.9 1.1 0.9 1.1 0.9 1.1 0.9 1.1 tCKL QK edge to clock edge skew tCKQK -0.2 0.2 -0.25 0.25 -0.25 0.25 -0.3 0.3 ns QK edge to output data edge tQKQ0, tQKQ1 -0.12 0.12 -0.2 0.2 -0.2 0.2 -0.25 0.25 ns 3, 5 tQKQ -0.22 0.22 -0.3 0.3 -0.3 0.3 -0.35 0.35 ns 4, 5 tQKVLD -0.22 0.22 -0.3 0.3 -0.3 0.3 -0.35 0.35 ns Address/command and input tAS/tCS 0.3 0.4 0.4 0.5 ns Data-in and data mask to DK tDS 0.17 0.25 0.25 0.3 ns Address/command and input tAH/tCH 0.3 0.4 0.4 0.5 ns Data-in and data mask to DK tDH 0.17 0.25 0.25 0.3 ns Output Times QK edge to any output data QK edge to QVLD Setup Times Hold Times Notes 1. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. 2. Frequency drift is not allowed. 3. tQKQ0 is referenced to DQ0-DQ17 in x36 and DQ0-DQ8 in x18. tQKQ1 is referenced to DQ18-DQ35 in x36 and DQ9-DQ17 in x18. 4. tQKQ takes into account the skew between any QKx and any DQ. 5. tQKQ, tQKQX are guaranteed by design. Remark All timing parameters are measured relative to the crossing point of CK/CK#, DK/DK# and to the crossing point with VREF of the command, address, and data signals. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 15 of 48 PD48288209A, PD48288218A, PD48288236A Figure 1-1. Clock / Input Data Clock Command / Address Timings tCK tCKH tCKL CK# CK COMMAND, ADDRESS VALID tCKDK VALID VALID tCKDK tAS tAH DKx# DKx tDK tDKH tDKL Don't care Temperature and Thermal Impedance Temperature Limits Parameter Symbol MIN. MAX. Unit Note Reliability junction temperature TJ 0 +110 C 1 Operating junction temperature TJ 0 +100 C 2 Operating case temperature TC 0 +95 C 3 Notes 1. Temperatures greater than 110C may cause permanent damage to the device. This is a stress rating only and functional operation of the device at or above this is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability of the part. 2. Junction temperature depends upon cycle time, loading, ambient temperature, and airflow. 3. MAX operating case temperature; TC is measured in the center of the package. Device functionality is not guaranteed if the device exceeds maximum TC during operation. Thermal Impedance Substrate ja (C/W) jb jc Air Flow = 0 m/s Air Flow = 1 m/s Air Flow = 2 m/s (C/W) (C/W) Ball 4 - Layer Lead 24.8 20.7 19.6 14.8 1.8 4 - Layer Lead free 24.6 20.5 19.4 14.6 1.8 R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 16 of 48 PD48288209A, PD48288218A, PD48288236A 2. Operation 2.1 Command Operation According to the functional signal description, the following command sequences are possible. All input states or sequences not shown are illegal or reserved. All command and address inputs must meet setup and hold times around the rising edge of CK. Table 2-1. Address Widths at Different Burst Lengths Burst Length Configuration x9 x18 x36 BL=2 A0-A20 A0-A19 A0-A18 BL=4 A0-A19 A0-A18 A0-A17 BL=8 A0-A18 A0-A17 N/A Table 2-2. Command Table Operation A0-An Note1 BA0-BA2 Note CS# WE# REF# Device DESELECT / No Operation DESEL / NOP H X X X X MRS: Mode Register Set MRS L L L OPCODE X 2 READ READ L H H A BA 3 WRITE WRITE L L H A BA 3 AUTO REFRESH AREF L H L X BA Notes Code 1. n = 20. 2. Only A0-A17 are used for the MRS command. 3. See Table 2-1. Remark X = "Don't Care", H = logic HIGH, L = logic LOW, A = valid address, BA = valid bank address 2.2 Description of Commands DESEL / NOP Note1 The NOP command is used to perform a no operation to the PD48288209/18/36A, which essentially deselects the chip. Use the NOP command to prevent unwanted commands from being registered during idle or wait states. Operations already in progress are not affected. Output values depend on command history. MRS The mode register is set via the address inputs A0-A17. See Figure 2-5. Mode Register Bit Map for further information. The MRS command can only be issued when all banks are idle and no bursts are in progress. READ The READ command is used to initiate a burst read access to a bank. The value on the BA0-BA2 inputs selects the bank, and the address provided on inputs A0-A20 selects the data location within the bank. WRITE The WRITE command is used to initiate a burst write access to a bank. The value on the BA0-BA2 inputs selects the bank, and the address provided on inputs A0-A20 selects the data location within the bank. Input data appearing on the DQ is written to the memory array subject to the DM input logic level appearing coincident with the data. If the DM signal is registered LOW, the corresponding data will be written to memory. If the DM signal is registered HIGH, the corresponding data inputs will be ignored (i.e., this part of the data word will not be written). R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 17 of 48 PD48288209A, PD48288218A, PD48288236A AREF The AREF is used during normal operation of the PD48288209/18/36A to refresh the memory content of a bank. The command is non-persistent, so it must be issued each time a refresh is required. The value on the BA0-BA2 inputs selects the bank. The refresh address is generated by an internal refresh controller, effectively making each address bit a "Don't Care" during the AREF command. The PD48288209/18/36A requires 64K cycles at an average periodic interval of 0.49s Note2 (MAX.). To improve efficiency, eight AREF commands (one for each bank) can be posted to PD48288209/18/36A at periodic intervals of 3.9 s Note3. Within a period of 32 ms, the entire memory must be refreshed. The delay between the AREF command and a subsequent command to same bank must be at least tRC as continuous refresh. Other refresh strategies, such as burst refresh, are also possible. Notes 1. When the chip is deselected, internal NOP commands are generated and no commands are accepted. 2. Actual refresh is 32 ms / 8k / 8 = 0.488 s. 3. Actual refresh is 32 ms / 8k = 3.90 s. 2.3 Initialization The PD48288209/18/36A must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operations or permanent damage to the device. The following sequence is used for Power-Up: 1. Apply power (VEXT, VDD, VDDQ, VREF, VTT) and start clock as soon as the supply voltages are stable. Apply VDD and VEXT before or at the same time as VDDQ. Apply VDDQ before or at the same time as VREF and VTT. Although there is no timing relation between VEXT and VDD, the chip starts the power-up sequence only after both voltages are at their nominal levels. VDDQ supply must not be applied before VDD supply. CK/CK# must meet VID(DC) prior to being applied. Maintain all remaining balls in NOP conditions. Note No rule of apply power sequence is the design target. 2. Maintain stable conditions for 200 s (MIN.). 3. Issue at least three or more consecutive MRS commands: two dummies or more plus one valid MRS. It is recommended that all address pins are held LOW during the dummy MRS commands. 4. tMRSC after valid MRS, an AUTO REFRESH command to all 8 banks must be issued. 5. After AUTO REFRESH command to all 8 banks, wait for 1,024 cycles including NOP or REF command in order to ready for normal WRITE operation and wait for 15 s in order to be ready for normal READ operation with CK/CK# toggling. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 18 of 48 PD48288209A, PD48288218A, PD48288236A 2.4 Power-On Sequence Figure 2-1. Power-Up Sequence VEXT VDD VDDQ VREF VTT CK# CK NOP COMMAND NOP ADDRESS MRS MRS Note 1, 2 Note 1, 2 A A MRS NOP RF0 RF1 RF7 WR RD Note 2 A tMRSC 200s MIN. Refresh all banks 1,024 cycles 15s Don't care Notes 1. Recommended all address pins held LOW during dummy MRS commands. 2. A6 and A10-A17 must be LOW. Remark WR : WRITE command RD : READ command MRS : MRS command RFp : REFRESH bank p 2.5 Programmable Impedance Output Buffer The PD48288209/18/36A is equipped with programmable impedance output buffers. This allows a user to match the driver impedance to the system. To adjust the impedance, an external precision resistor (RQ) is connected between the ZQ ball and VSS. The value of the resistor must be five times the desired impedance. For example, a 300 resistor is required for an output impedance of 60 . To ensure that output impedance is one fifth the value of RQ (within 15 percent), the range of RQ is 125 to 300 . Output impedance updates may be required because, over time, variations may occur in supply voltage and temperature. The device samples the value of RQ. An impedance update is transparent to the system and does not affect device operation. All data sheet timing and current specifications are met during an update. 2.6 PLL Reset The PD48288209/18/36A utilizes internal Phase-locked loops for maximum output, data valid windows. It can be placed into a stopped-clock state to minimize power with a modest restart time of 15 s. The clock (CK/CK#) must be toggled for 15 s in order to stabilize PLL circuits for next READ operation. 2.7 Clock Input Table 2-3. Clock Input Operation Conditions Parameter Symbol Conditions MIN. MAX. Unit Note Clock Input Voltage Level VIN (DC) CK and CK# -0.3 VDDQ + 0.3 V Clock Input Differential Voltage Level VID (DC) CK and CK# 0.2 VDDQ + 0.6 V 8 Clock Input Differential Voltage Level VID (AC) CK and CK# 0.4 VDDQ + 0.6 V 8 Clock Input Crossing Point Voltage Level VIX (AC) CK and CK# VDDQ/2 - 0.15 VDDQ/2 + 0.15 V 9 R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 19 of 48 PD48288209A, PD48288218A, PD48288236A Figure 2-2. Clock Input VIN(DC) MAX. Maximum Clock Level CK# VDDQ/2 + 0.15 VIX(AC) MAX. Note11 VDDQ/2 Note 10 VID(DC) Note12 VID(AC) VDDQ/2 - 0.15 VIX(AC) MIN. CK VIN(DC) MIN. Minimum Clock Level Notes 1. DKx and DKx# have the same requirements as CK and CK#. 2. All voltages referenced to VSS. 3. Tests for AC timing, IDD and electrical AC and DC characteristics may be conducted at normal reference/supply voltage levels; but the related specifications and device operations are tested for the full voltage range specified. 4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or the crossing point for CK/CK#), and parameters specifications are tested for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 2V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the HSTL Standard (i.e. the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above[below] the DC input LOW[HIGH] level). 6. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross. The input reference level for signal other than CK/CK# is VREF. 7. CK and CK# input slew rate must be >= 2V/ns (>=4V/ns if measured differentially). 8. VID is the magnitude of the difference between the input level on CK and input level on CK#. 9. The value of VIX is expected to equal VDDQ/2 of the transmitting device and must track variations in the DC level of the same. 10. CK and CK# must cross within the region. 11. CK and CK# must meet at least VID(DC) (MIN.) when static and centered around VDDQ/2. 12. Minimum peak-to-peak swing. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 20 of 48 PD48288209A, PD48288218A, PD48288236A 2.8 Mode Register Set Command (MRS) The mode register stores the data for controlling the operating modes of the memory. It programs the PD48288209/18/36A configuration, burst length, and I/O options. During a MRS command, the address inputs A0- A17 are sampled and stored in the mode register. tMRSC must be met before any command can be issued to the PD48288209/18/36A. The mode register may be set at any time during device operation. However, any pending operations are not guaranteed to successfully complete, and all memory cell data are not guaranteed. Since MRS is used for internal test mode entry, bits A6 and A10-A17 must be set to all "0" at the MRS setting. Figure 2-3. Mode Register Set Timing tMRSC CK# CK COMMAND MRS NOP NOP AC QVLD QKx QKx# Don't care Remark MRS: MRS command AC : any command Figure 2-4. Mode Register Set CK# CK CS# WE# REF# ADDRESS COD BANK ADDRESS Don't care Remark COD: code to be loaded into the register. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 21 of 48 PD48288209A, PD48288218A, PD48288236A Figure 2-5. Mode Register Bit Map A17-A10 A9 Note 1 Reserved A8 Impedance On-Die Termination Matching On-Die Termination A9 A7 A6 A5 PLL Reset Unused Address Mux PLL Reset Termination A4 A3 A2 A1 Configuration Burst Length Configuration Burst Length A7 PLL Reset A4 A3 A0 BL A2 A1 A0 Configuration 0 Disabled (default) 0 PLL reset (default) 0 0 2 (default) 0 0 0 1 Note 2 (default) 1 Enabled 1 PLL enabled 0 1 4 0 0 1 1 Note 2 1 0 8 Note 2 0 1 0 2 1 1 Not valid 0 1 1 3 1 0 0 4 Address Mux 1 0 1 5 Nonmultiplexed (default) 1 1 0 Reserved 0 1 1 1 Reserved 1 Address multiplexed Impedance Matching A8 0 1 Address Mux Resistor A5 Internal 50 W Note 3 (default) External Note 2 Note 4 Notes 1. Bits A6 and A10-A17 must be set to all `0'. A18-An are "Don't Care". 2. BL=8 is not available for configuration 1 and 4. 3. 30% temperature variation. 4. Within 15%. 2.9 Read & Write configuration (Non Multiplexed Address Mode) Table 2-4 shows, for different operating frequencies, the different PD48288209/18/36A configurations that can be programmed into the mode register. The READ and WRITE latency (tRL and tWL) values along with the row cycle times (tRC) are shown in clock cycles as well as in nanoseconds. Table 2-4. Configuration Table Parameter Configuration Note2 1 2 3 Unit Note2, 3 4 5 tRC 4 6 8 3 5 tCK tRL 4 6 8 3 5 tCK tWL 5 7 9 4 6 tCK Valid frequency range 266-175 400-175 533-175 200-175 333-175 MHz Notes 1. Apply to the entire table. tRC < 20 ns in any configuration only available with -E24 and -E18 speed grades. 2. BL= 8 is not available. 3. The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ to the same bank. In this instance the minimum tRC is 4 cycles. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 22 of 48 PD48288209A, PD48288218A, PD48288236A 2.10 Write Operation (WRITE) Write accesses are initiated with a WRITE command, as shown in Figure 2-6. Row and bank addresses are provided together with the WRITE command. During WRITE commands, data will be registered at both edges of DK according to the programmed burst length (BL). A WRITE latency (WL) one cycle longer than the programmed READ latency (RL + 1) is present, with the first valid data registered at the first rising DK edge WL cycles after the WRITE command. Any WRITE burst may be followed by a subsequent READ command. Figure 2-10. WRITE Followed By READ: BL=2, RL=4, WL=5, Configuration 1 and Figure 2-11. WRITE Followed By READ: BL=4, RL=4, WL=5, Configuration 1 illustrate the timing requirements for a WRITE followed by a READ for bursts of two and four, respectively. Setup and hold times for incoming input data relative to the DK edges are specified as tDS and tDH. The input data is masked if the corresponding DM signal is HIGH. The setup and hold times for data mask are also tDS and tDH. Figure 2-6. WRITE Command CK# CK CS# WE# REF# ADDRESS A BANK ADDRESS BA Don't care Remark A : Address BA : Bank address Figure 2-7. Basic WRITE Burst / DM Timing CK# CK tCKDK DKx# DKx Write Latency DQ tDS tDH tDS D0 D1 D2 tDH D3 DM Data masked tDS tDH Data masked Don't care R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 23 of 48 PD48288209A, PD48288218A, PD48288236A Figure 2-8. WRITE Burst Basic Sequence: BL=2, RL=4, WL=5, Configuration 1 0 1 2 3 4 5 6 7 8 COMMAND WR WR WR WR WR WR WR WR WR ADDRESS A BA0 A BA1 A BA2 A BA3 A BA0 A BA4 A BA5 A BA6 A BA7 D0a D0b D1a D1b D2a D2b D3a CK# CK WL = 5 DK# DK DQ D3 Don't care Figure 2-9. WRITE Burst Basic Sequence: BL=4, RL=4, WL=5, Configuration 1 0 1 2 3 4 5 6 7 8 COMMAND WR NOP WR NOP WR NOP WR NOP WR ADDRESS A BA0 CK# CK A BA1 A BA0 A BA3 A BA0 WL = 5 DK# DK D0a D0b DQ D0c D0d D1a D1b D1c D1 Don't care Remarks 1. 2. WR A/Bap WL Dpq : WRITE command : Address A of bank p : WRITE latency : Data q to bank p Any free bank may be used in any given command. The sequence shown is only one example of a bank sequence. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 24 of 48 PD48288209A, PD48288218A, PD48288236A Figure 2-10. WRITE Followed By READ: BL=2, RL=4, WL=5, Configuration 1 0 1 2 3 4 5 6 7 8 9 COMMAND WR NOP RD RD NOP NOP NOP NOP NOP NOP ADDRESS A BA0 A BA1 A BA2 CK# CK RL = 4 WL = 5 DKx# DKx DQ D0a D0b Q1a Q1b Q2a Q2b QVLD QKx QKx# Don't care Undefined Figure 2-11. WRITE Followed By READ: BL=4, RL=4, WL=5, Configuration 1 0 1 2 3 4 5 6 7 8 9 COMMAND WR NOP NOP RD NOP RD NOP NOP NOP NOP ADDRESS A BA0 CK# CK A BA1 A BA2 RL = 4 WL = 5 DKx# DKx D0a D0b DQ D0c D0d Q1a Q1b Q1c Q1d Q2a QVLD QKx QKx# Don't care Remark Undefined WR : WRITE command RD : READ command A/BAp : Address A of bank p WL : WRITE latency RL : READ latency Dpq : Data q to bank p Qpq : Data q from bank p R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 25 of 48 PD48288209A, PD48288218A, PD48288236A 2.11 Read Operation (READ) Read accesses are initiated with a READ command, as shown in Figure 2-12. Row and bank addresses are provided with the READ command. During READ bursts, the memory device drives the read data edge-aligned with the QK signal. After a programmable READ latency, data is available at the outputs. The data valid signal indicates that valid data will be present in the next half clock cycle. The skew between QK and the crossing point of CK is specified as tCKQK. tQKQ0 is the skew between QK0 and the last valid data edge considered the data generated at the DQ0-DQ17 in x36 and DQ0-DQ8 in x18 data signals. tQKQ1 is the skew between QK1 and the last valid data edge considered the data generated at the DQ18-DQ35 in x36 and DQ9- DQ17 in x18 data signals. tQKQx is derived at each QKx clock edge and is not cumulative over time. After completion of a burst, assuming no other commands have been initiated, DQ will go High-Z. Back-to-back READ commands are possible, producing a continuous flow of output data. Minimum READ data valid window can be expressed as MIN.(tQKH, tQKL) - 2 x MAX.(tQKQx) Any READ burst may be followed by a subsequent WRITE command. Figure 2-16. READ followed by WRITE, BL=2, RL=4, WL=5, Configuration 1 and Figure 2-17. READ followed by WRITE, BL=4, RL=4, WL=5, Configuration 1 illustrate the timing requirements for a READ followed by a WRITE. Figure 2-12. READ Command CK# CK CS# WE# REF# ADDRESS A BANK ADDRESS BA Don't care Remark A : Address BA : Bank address R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 26 of 48 PD48288209A, PD48288218A, PD48288236A Figure 2-13. Basic READ Burst Timing tCKH tCKL tCK CK# CK tQKL tCKQK tQKH QKx QKx# tQKVLD tQKVLD QVLD DQ Q0 Q1 Q2 Q3 tQKQ tQKQ tQKQ Note 1 Undefined Note 1. Minimum READ data valid window can be expressed as MIN.(tQKH, tQKL) - 2 x MAX.(tQKQx) tCKH and tCKL are recommended to have 50% / 50% duty. Remarks 1. 2. 3. R10DS0097EJ0100 Rev.1.00 February 28, 2012 tQKQ0 is referenced to DQ0-DQ17 in x36 and DQ0-DQ8 in x18. tQKQ1 is referenced to DQ18-DQ35 in x36 and DQ9-DQ17 in x18. tQKQ takes into account the skew between any QKx and any DQ. tCKQK is specified as CK rising edge to QK rising edge. Page 27 of 48 PD48288209A, PD48288218A, PD48288236A Figure 2-14. READ Burst Basic Sequence: BL=2, RL=4, Configuration 1 0 1 2 3 4 5 6 7 8 COMMAND RD RD RD RD RD RD RD RD RD ADDRESS A BA0 A BA1 A BA2 A BA3 A BA0 A BA7 A BA6 A BA5 A BA4 CK# CK RL = 4 QKx QKx# QVLD Q0a Q0b Q1a Q1b Q2a Q2b Q3a Q3b Q0a DQ Undefined Don't care Figure 2-15. READ Burst Basic Sequence: BL=4, RL=4, Configuration 1 0 1 2 3 4 5 6 7 8 COMMAND RD NOP RD NOP RD NOP RD NOP RD ADDRESS A BA0 CK# CK A BA1 A BA0 A BA1 A BA3 RL = 4 QKx QKx# QVLD Q0a Q0b DQ Q0c Q0d Q1a Q1b Q1c Q1d Q0a Don't care Remark RD A/BAp RL Qpq Undefined : READ command : Address A of bank p : READ latency : Data q from bank p R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 28 of 48 PD48288209A, PD48288218A, PD48288236A Figure 2-16. READ followed by WRITE, BL=2, RL=4, WL=5, Configuration 1 9 0 1 2 3 4 5 6 7 8 COMMAND RD WR WR NOP NOP NOP NOP NOP NOP ADDRESS A BA0 A BA1 A BA2 D1a D1b D2a D2b CK# CK RL = 4 WL = 5 DKx# DKx DQ Q0a Q0b QVLD QKx QKx# Undefined Don't care Figure 2-17. READ followed by WRITE, BL=4, RL=4, WL=5, Configuration 1 0 1 2 3 4 5 6 7 COMMAND RD NOP WR NOP NOP NOP NOP NOP ADDRESS A BA0 CK# CK A BA1 WL = 5 RL = 4 DKx# DKx Q0a Q0b Q0c DQ Q0d D1a D1b QVLD QKx QKx# Don't care Remark WR RD A/BAp WL RL Dpq Qpq Undefined : WRITE command : READ command : Address A of bank p : WRITE latency : READ latency : Data q to bank p : Data q from bank p R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 29 of 48 PD48288209A, PD48288218A, PD48288236A 2.12 Refresh Operation: AUTO REFRESH Command (AREF) AREF is used to perform a REFRESH cycle on one row in a specific bank. The row addresses are generated by an internal refresh counter; external address balls are "Don't Care." The delay between the AREF command and a subsequent command to the same bank must be at least tRC. Within a period of 32 ms (tREF), the entire memory must be refreshed. Figure 2-19 illustrates an example of a continuous refresh sequence. Other refresh strategies, such as burst refresh, are also possible. Figure 2-18. AUTO REFRESH Command CK# CK CS# WE# REF# ADDRESS BANK ADDRESS BA Don't care Remark BA: Bank address Figure 2-19. AUTO REFRESH Cycle CK# CK COMMAND ARFx ACy ACx tRC Remarks 1. ACx ACy Don't care : Any command on bank x ARFx : Auto refresh bank x ACy 2. : Any command on different bank. tRC is configuration-dependent. Refer to Table 2-4. Configuration Table. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 30 of 48 PD48288209A, PD48288218A, PD48288236A 2.13 On-Die Termination On-die termination (ODT) is enabled by setting A9 to "1" during an MRS command. With ODT on, all the DQs and DM are terminated to VTT with a resistance RTT. The command, address, and clock signals are not terminated. Figure 220 below shows the equivalent circuit of a DQ receiver with ODT. ODTs are dynamically switched off during READ commands and are designed to be off prior to the PD48288209/18/36A driving the bus. Similarly, ODTs are designed to switch on after the PD48288209/18/36A has issued the last piece of data. Table 2-5. On-Die Termination DC Parameters Description Symbol MIN. MAX. Units Note Termination voltage VTT 0.95 x VREF 1.05 x VREF V 1, 2 On-Die termination RTT 125 185 3 Notes 1. All voltages referenced to VSS (GND). 2. VTT is expected to be set equal to VREF and must track variations in the DC level of VREF. 3. The RTT value is measured at 95C TC. Figure 2-20. On- Die Termination-Equivalent Circuit VTT sw RTT DQ Receiver Figure 2-21. READ Burst with ODT: BL=2, Configuration 1 0 1 2 3 4 5 6 7 8 COMMAND RD RD RD NOP NOP NOP NOP NOP NOP ADDRESS A BA0 A BA1 A BA2 CK# CK RL = 4 QKx QKx# QVLD Q0a Q0b Q1a Q1b Q2a Q2b DQ ODT ODT ON ODT OFF Don't care Remark RD A/Bap RL Qpq R10DS0097EJ0100 Rev.1.00 February 28, 2012 ODT ON Undefined : READ command : Address A of bank p : READ latency : Data q from bank p Page 31 of 48 PD48288209A, PD48288218A, PD48288236A Figure 2-22. READ NOP READ with ODT: BL=2, Configuration 1 0 1 2 3 4 5 6 7 8 COMMAND RD NOP RD NOP NOP NOP NOP NOP NOP ADDRESS A BA0 CK# CK A BA2 RL = 4 QKx QKx# QVLD Q0a Q0b DQ ODT ODT ON ODT OFF Q2a Q2b ODT ON ODT ON ODT OFF Undefined Don't care Figure 2-23. READ NOP NOP READ with ODT: BL=2, Configuration 1 0 1 2 3 4 5 6 7 8 COMMAND RD NOP NOP RD NOP NOP NOP NOP NOP ADDRESS A BA0 9 CK# CK A BA2 RL = 4 QKx QKx# QVLD DQ Q0a Q0b ODT ODT ON ODT OFF Q2a Q2b ODT ON ODT OFF Don't care Remark RD A/BAp RL Qpq R10DS0097EJ0100 Rev.1.00 February 28, 2012 ODT ON Undefined : READ command : Address A of bank p : READ latency : Data q from bank p Page 32 of 48 PD48288209A, PD48288218A, PD48288236A Figure 2-24. READ followed by WRITE with ODT: BL=2, Configuration 1 0 1 2 3 4 5 6 7 8 COMMAND RD WR WR NOP NOP NOP NOP NOP NOP ADDRESS A BA0 A BA1 A BA2 D1a D1b D2a D2b 9 CK# CK RL = 4 WL = 5 DKx# DKx Q0a Q0b DQ QKx QKx# ODT ODT ON ODT ON ODT OFF Undefined Don't care Figure 2-25. WRITE followed by READ with ODT: BL=2, Configuration 1 0 1 2 3 4 5 6 7 8 9 COMMAND WR NOP RD RD NOP NOP NOP NOP NOP NOP ADDRESS A BA0 A BA1 A BA2 CK# CK RL= 4 WL = 5 DKx# DKx DQ D0a D0b Q1a Q1b Q2a Q2b QKx QKx# ODT ODT ON ODT OFF Don't care Remark RD WR A/BAp RL WL Qpq Dpq R10DS0097EJ0100 Rev.1.00 February 28, 2012 ODT ON Undefined : READ command : WRITE command : Address A of bank p : READ latency : WRITE latency : Data q from bank p : Data q to bank p Page 33 of 48 PD48288209A, PD48288218A, PD48288236A 2.14 Operation with Multiplexed Address In multiplexed address mode, the address can be provided to the PD48288209/18/36A in two parts that are latched into the memory with two consecutive rising clock edges. This provides the advantage that a maximum of 11 address balls are required to control the PD48288209/18/36A, reducing the number of balls on the controller side. The data bus efficiency in continuous burst mode is not affected for BL=4 and BL=8 since at least two clocks are required to read the data out of the memory. The bank addresses are delivered to the PD48288209/18/36A at the same time as the WRITE command and the first address part, Ax. This option is available by setting bit A5 to "1" in the mode register. Once this bit is set, the READ, WRITE, and MRS commands follow the format described in Figure 2-26. See Figure 2-28. Power-Up Sequence in Multiplexed Address Mode for the power-up sequence. Figure 2-26. Command Description in Multiplexed READ WRITE MRS CK# CK CS# WE# REF# ADDRESS Ax BANK ADDRESS BA Ay Ax Ay Ax Ay BA Don't care Remarks 1. 2. Ax, Ay : Address BA : Bank Address The minimum setup and hold times of the two address parts are defined tAS and tAH. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 34 of 48 PD48288209A, PD48288218A, PD48288236A Figure 2-27. Mode Register Set Command in Multiplexed Address Mode Ax A17 ***** A10 Ay A17 ***** A10 Note 1 Reserved A8 A9 A5 Impedance On-Die Termination Matching On-Die Termination A9x Termination A9 A8 PLL Reset Unused A4 A4 PLL Reset Address Mux PLL Reset Configuration Configuration A4x A3x BL A4y A3y A0x Configuration 0 Disabled (default) 0 PLL reset (default) 0 0 2 (default) 0 0 0 1 Note 2 (default) 1 Enabled 1 PLL enabled 0 1 4 0 0 1 1 Note 2 1 0 8 Note 2 0 1 0 2 1 1 Not valid 0 1 1 3 1 0 0 4 Note 2 1 0 1 5 1 1 0 Reserved 1 1 1 Reserved A8x Resistor 0 (default) External 1 Address Mux A5x Note 3 Remark A3 Burst Length Burst Length A9y Impedance Matching Notes 1. 2. 3. 4. A0 A3 0 Nonmultiplexed (default) 1 Address multiplexed Note 4 Bits A10-A17 must be set to all `0'. BL=8 is not available for configuration 1 and 4. 30% temperature variation. Within 15%. The address A0, A3, A4, A5, A8, and A9 must be set as follows in order to activate the mode register in the multiplexed address mode. Figure 2-28. Power-Up Sequence in Multiplexed Address Mode VEXT VDD VDDQ VREF VTT CK# CK COMMAND NOP NOP ADDRESS 200s MIN. MRS MRS MRS Note 1, 2 Note 1, 2 Note 2, 3 A A A 1 cycle MIN. 1 cycle MIN. NOP MRS NOP RF0 RF1 RF7 WR RD Note 4 Ax tMRSC Ay tMRSC Refresh all banks 1,024 cycles 15s Don't care Notes 1. Recommended all address pins held LOW during dummy MRS command. 2. A10-A17 must be LOW. 3. Address A5 must be set HIGH (muxed address mode setting when PD48288209/18/36A is in normal mode of operation). 4. Address A5 must be set HIGH (muxed address mode setting when PD48288209/18/36A is already in muxed address mode). Remark MRS : MRS command RFp : REFRESH Bank p WR : WRITE command RD : READ command R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 35 of 48 PD48288209A, PD48288218A, PD48288236A 2.15 Address Mapping in Multiplexed Mode The address mapping is described in Table 2-6 as a function of data width and burst length. Table 2-6. Address Mapping in Multiplexed Address Mode Data Burst Width Length x36 BL=2 BL=4 x18 BL=2 BL=4 BL=8 x9 BL=2 BL=4 BL=8 Ball Address A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay X A1 A2 X A6 A7 X A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 X Ay X A1 A2 X A6 A7 X A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay X A1 A2 X A6 A7 A19 A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay X A1 A2 X A6 A7 X A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 X Ay X A1 A2 X A6 A7 X A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay A20 A1 A2 X A6 A7 A19 A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay X A1 A2 X A6 A7 A19 A11 A12 A16 A15 Ax A0 A3 A4 A5 A8 A9 A10 A13 A14 A17 A18 Ay X A1 A2 X A6 A7 X A11 A12 A16 A15 Remark X means "Don't care". R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 36 of 48 PD48288209A, PD48288218A, PD48288236A 2.16 Read & Write configuration in Multiplexed Address Mode In multiplexed address mode, the READ and WRITE latencies are increased by one clock cycle. The PD48288209/18/36A cycle time remains the same, as described in Table 2-7. Table 2-7. Configuration in Multiplexed Address Mode Parameter Configuration Note2 1 2 3 Unit Note2, 3 5 4 tRC 4 6 8 3 5 tCK tRL 5 7 9 4 6 tCK tWL 6 8 10 5 7 tCK Valid frequency range 266-175 400-175 533-175 200-175 333-175 MHz Notes 1. Apply to the entire table. tRC < 20 ns in any configuration is only available with -E24 and -E18 speed grades. 2. BL = 8 is not available. 3. The minimum tRC is typically 3 cycles, except in the case of a WRITE followed by a READ to the same bank. In this instance the minimum tRC is 4 cycles. 2.17 Refresh Command in Multiplexed Address Mode Similar to other commands, the refresh command is executed on the next rising clock edge when in the multiplexed address mode. However, since only bank address is required for AREF, the next command can be applied on the following clock. The operation of the AREF command and any other command is represented in Figure 2-29. Figure 2-29. Burst REFRESH Operation 0 1 2 3 4 5 6 7 8 9 10 11 0 1 2 3 4 5 6 7 8 9 10 11 CK COMMAND AC NOP AREF AREF AREF AREF AREF AREF AREF AREF AC COMMAND AC NOP AREF AREF AREF AREF AREF AREF AREF AREF AC ADDRESS Ax Ay Ax Ay ADDRESS Ax Ay Ax Ay BANK ADDRESS BANK ADDRESS BAp BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BAp BAp BA0 BA1 BA2 BA3 BA4 BA5 BA6 BA7 BAp CK# CK# CK Don't care Don't care Remark AREF AC Ax Ay BAp : AUTO REFRESH : Any command : First part Ax of address : Second part Ay of address : Bank p is chosen so that tRC is met. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 37 of 48 PD48288209A, PD48288218A, PD48288236A Figure 2-30. WRITE Burst Basic Sequence: BL=4, with Multiplexed Addresses, Configuration 1 0 1 COMMAND WR NOP ADDRESS Ax BA0 Ay 2 3 4 5 6 7 8 WR NOP WR NOP WR NOP WR Ax BA1 Ay Ax BA2 Ay Ax BA3 Ay Ax BA0 CK# CK WL = 6 DKx# DKx D0a DQ D0b D0c D0d D1a D1 Don't care Figure 2-31. READ Burst Basic Sequence: BL=4, with Multiplexed Addresses, Configuration 1, RL=5 0 1 2 3 4 5 6 7 8 COMMAND RD NOP RD NOP RD NOP RD NOP RD ADDRESS Ax BA0 Ay Ax BA1 Ay Ax BA2 Ay Ax BA0 Ay Ax BA1 CK# CK RL = 5 QKx QKx# QVLD Q0a Q0b DQ Q0c Q0d Q1a Q1b Q1c Don't care Remark WR RD Ax/BAp Ay Dpq Qpq WL RL Undefined : WRITE command : READ command : Address Ax of bank p : Address Ay of bank p : Data q to bank p : Data q from bank p : WRITE latency : READ latency R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 38 of 48 PD48288209A, PD48288218A, PD48288236A 3. JTAG Specification These products support a limited set of JTAG functions as in IEEE standard 1149.1. Table 3-1. Test Access Port (TAP) Pins Pin name Pin assignments Description 12A Test Clock Input. All input are captured on the rising edge of TCK and all outputs propagate from the falling edge of TCK. TMS 11A Test Mode Select. This is the command input for the TAP controller state TDI 12V Test Data Input. This is the input side of the serial registers placed between TDI and TDO. The register placed between TDI and TDO is determined by the state of the TAP controller state machine and the instruction that is currently TDO 11V Test Data Output. This is the output side of the serial registers placed between TDI and TDO. Output changes in response to the falling edge of TCK. TCK Remark The device does not have TRST (TAP reset). The Test-Logic Reset state is entered while TMS is held HIGH for five rising edges of TCK. The TAP controller state is also reset on the POWER-UP. Table 3-2. JTAG DC Characteristics (0C TC 95C, 1.7 V VDD 1.9 V, unless otherwise noted) Parameter Symbol JTAG Input leakage current ILI JTAG I/O leakage current ILO Conditions MIN. MAX. Unit Notes 0 V VIN VDD -5.0 +5.0 A 0 V VIN VDD Q , -5.0 +5.0 A Outputs disabled JTAG input HIGH voltage VIH VREF + 0.15 VDD + 0.3 V 1, 2 JTAG input LOW voltage VIL VSSQ - 0.3 VREF - 0.15 V 1, 2 JTAG output HIGH voltage JTAG output LOW voltage Note VOH1 | IOHC | = 100 A VDDQ - 0.2 V VOH2 | IOHT | = 2 mA VDDQ - 0.4 V VOL1 IOLC = 100 A 0.2 V 1 VOL2 IOLT = 2 mA 0.4 V 1 1. All voltages referenced to VSS (GND). 2. Overshoot: VIH (AC) VDD + 0.7 V for t tCK/2. Undershoot: VIL (AC) -0.5 V for t tCK/2. During normal operation, VDDQ must not exceed VDD. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 39 of 48 PD48288209A, PD48288218A, PD48288236A JTAG AC Test Conditions Input waveform VDDQ VIH(AC) MIN. VIL(AC) MAX. VSS Rise Time: 2 V/ns Fall Time: 2 V/ns Output waveform Test Points VDDQ / 2 VDDQ / 2 Output load condition VTT 50 TDO Test point 10pF R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 40 of 48 PD48288209A, PD48288218A, PD48288236A Table 3-3. JTAG AC Characteristics (0C TC 95C) Parameter Symbol Conditions MIN. MAX. Unit Note Clock Clock cycle time tTHTH 20 ns Clock frequency fTF Clock HIGH time tTHTL 10 50 MHz ns Clock LOW time tTLTH 10 ns TCK LOW to TDO unknown tTLOX 0 ns TCK LOW to TDO valid tTLOV Output time 10 ns Setup time TMS setup time tMVTH 5 ns TDI valid to TCK HIGH tDVTH 5 ns Capture setup time tCSJ 5 ns TMS hold time tTHMX 5 ns TCK HIGH to TDI invalid tTHDX 5 ns Capture hold time tCHJ 5 ns 1 Hold time 1 Note 1. tCSJ and tCHJ refer to the setup and hold time requirements of latching data from the boundary scan register. JTAG Timing Diagram tTHTH TCK tMVTH tTHTL tTLTH TMS tTHMX tDVTH TDI tTHDX tTLOX tTLOV TDO R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 41 of 48 PD48288209A, PD48288218A, PD48288236A Table 3-4. Scan Register Definition (1) Register name Description Instruction register The 8 bit instruction registers hold the instructions that are executed by the TAP controller. The register can be loaded when it is placed between the TDI and TDO pins. The instruction register is automatically preloaded with the IDCODE instruction at powerup whenever the controller is placed in test-logic-reset state. Bypass register The bypass register is a single bit register that can be placed between TDI and TDO. It allows serial test data to be passed through the RAMs TAP to another device in the scan chain with as little delay as possible. The bypass register is set LOW (VSS) when the bypass instruction is executed. ID register The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit code when the controller is put in capture-DR state with the IDCODE command loaded in the instruction register. The register is then placed between the TDI and TDO pins when the controller is moved into shift-DR state. Boundary register The boundary register, under the control of the TAP controller, is loaded with the contents of the RAMs I/O ring when the controller is in capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to shift-DR state. Several TAP instructions can be used to activate the boundary register. The Scan Exit Order tables describe which device bump connects to each boundary register location. The first column defines the bit's position in the boundary register. The second column is the name of the input or I/O at the bump and the third column is the bump number. Table 3-5. Scan Register Definition (2) Register name Bit size Unit Instruction register 8 bit Bypass register 1 bit ID register 32 bit Boundary register 113 bit Table 3-6. ID Register Definition Part number Organization ID [31:28] vendor revision no. ID [27:12] part no. ID [11:1] vendor ID no. ID [0] fix bit PD48288209A 32M x 9 0100 0001 0000 1010 0111 00000010000 1 PD48288218A 16M x 18 0101 0001 0000 1010 0111 00000010000 1 PD48288236A 8M x 36 0110 0001 0000 1010 0111 00000010000 1 R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 42 of 48 PD48288209A, PD48288218A, PD48288236A Table 3-7. SCAN Exit Order Bit Signal name Bump Bit Signal name Bump Bit Signal name Bump no. x9 x18 x36 ID no. x9 x18 x36 ID no. x9 x18 x36 ID 1 DK DK DK1 K1 39 DNU DNU DQ30 R11 77 DNU DNU DQ2 C11 2 DK# DK# DK1# K2 40 DNU DNU DQ30 R11 78 DNU DNU DQ2 C11 3 CS# CS# CS# L2 41 DNU DNU DQ32 P11 79 DQ1 DQ1 DQ3 C10 4 REF# REF# REF# L1 42 DNU DNU DQ32 P11 80 DQ1 DQ1 DQ3 C10 5 WE# WE# WE# M1 43 DQ5 DQ10 DQ33 P10 81 DNU DNU DQ0 B11 6 A17 A17 A17 M3 44 DQ5 DQ10 DQ33 P10 82 DNU DNU DQ0 B11 7 A16 A16 A16 M2 45 DNU DNU DQ34 N11 83 DQ0 DQ0 DQ1 B10 8 A18 A18 A18 N1 46 DNU DNU DQ34 N11 84 DQ0 DQ0 DQ1 B10 9 A15 A15 A15 P1 47 DQ4 DQ9 DQ35 N10 85 DNU DQ4 DQ9 B3 10 DNU DQ14 DQ25 N3 48 DQ4 DQ9 DQ35 N10 86 DNU DQ4 DQ9 B3 11 DNU DQ14 DQ25 N3 49 DM DM DM P12 87 DNU DNU DQ8 B2 12 DNU DNU DQ24 N2 50 A19 A19 (A19) N12 88 DNU DNU DQ8 B2 13 DNU DNU DQ24 N2 51 A11 A11 A11 M11 89 DNU DQ5 DQ11 C3 14 DNU DQ15 DQ23 P3 52 A12 A12 A12 M10 90 DNU DQ5 DQ11 C3 15 DNU DQ15 DQ23 P3 53 A10 A10 A10 M12 91 DNU DNU DQ10 C2 16 DNU DNU DQ22 P2 54 A13 A13 A13 L12 92 DNU DNU DQ10 C2 17 DNU DNU DQ22 P2 55 A14 A14 A14 L11 93 DNU DQ6 DQ13 D3 18 DNU QK1 QK1 R2 56 BA1 BA1 BA1 K11 94 DNU DQ6 DQ13 D3 19 DNU QK1# QK1# R3 57 CK# CK# CK# K12 95 DNU DNU DQ12 D2 20 DNU DNU DQ20 T2 58 CK CK CK J12 96 DNU DNU DQ12 D2 21 DNU DNU DQ20 T2 59 BA0 BA0 BA0 J11 97 DNU DNU DQ14 E2 22 DNU DQ16 DQ21 T3 60 A4 A4 A4 H11 98 DNU DNU DQ14 E2 23 DNU DQ16 DQ21 T3 61 A3 A3 A3 H12 99 DNU DQ7 DQ15 E3 24 DNU DNU DQ18 U2 62 A0 A0 A0 G12 100 DNU DQ7 DQ15 E3 25 DNU DNU DQ18 U2 63 A2 A2 A2 G10 101 DNU DNU DQ16 F2 26 DNU DQ17 DQ19 U3 64 A1 A1 A1 G11 102 DNU DNU DQ16 F2 27 DNU DQ17 DQ19 U3 65 A20 (A20) (A20) E12 103 DNU DQ8 DQ17 F3 28 ZQ ZQ ZQ V2 66 QVLD QVLD QVLD F12 104 DNU DQ8 DQ17 F3 29 DQ8 DQ13 DQ27 U10 67 DQ3 DQ3 DQ7 F10 105 (A21) (A21) (A21) E1 30 DQ8 DQ13 DQ27 U10 68 DQ3 DQ3 DQ7 F10 106 A5 A5 A5 F1 31 DNU DNU DQ26 U11 69 DNU DNU DQ6 F11 107 A6 A6 A6 G2 32 DNU DNU DQ26 U11 70 DNU DNU DQ6 F11 108 A7 A7 A7 G3 33 DQ7 DQ12 DQ29 T10 71 DQ2 DQ2 DQ5 E10 109 A8 A8 A8 G1 34 DQ7 DQ12 DQ29 T10 72 DQ2 DQ2 DQ5 E10 110 BA2 BA2 BA2 H1 35 DNU DNU DQ28 T11 73 DNU DNU DQ4 E11 111 A9 A9 A9 H2 36 DNU DNU DQ28 T11 74 DNU DNU DQ4 E11 112 NF NF DK0# J2 37 DQ6 DQ11 DQ31 R10 75 QK0 QK0 QK0 D11 113 NF NF DK0 J1 38 DQ6 DQ11 DQ31 R10 76 QK0# QK0# QK0# D10 Note Any unused balls that are in the order will read as a logic "0". R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 43 of 48 PD48288209A, PD48288218A, PD48288236A JTAG Instructions Many different instructions (28) are possible with the 8-bit instruction register. All used combinations are listed in Table 3-8, Instruction Codes. These six instructions are described in detail below. The remaining instructions are reserved and should not be used. The TAP controller used in this RAM is fully compliant to the 1149.1 convention. Instructions are loaded into the TAP controller during the Shift-IR state when the instruction register is placed between TDI and TDO. During this state, instructions are shifted through the instruction register through the TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. Table 3-8 Instructions EXTEST Instruction Code [7:0] Description 0000 0000 The EXTEST instruction allows circuitry external to the component package to be tested. Boundary-scan register cells at output pins are used to apply test vectors, while those at input pins capture test results. Typically, the first test vector to be applied using the EXTEST instruction will be shifted into the boundary scan register using the PRELOAD instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on and the PRELOAD data is driven onto the output pins. IDCODE 0010 0001 The IDCODE instruction causes the ID ROM to be loaded into the ID register when the controller is in capture-DR mode and places the ID register between the TDI and TDO pins in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. SAMPLE / PRELOAD 0000 0101 SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction. When the SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP controller into the capture-DR state loads the data in the RAMs input and DQ pins into the boundary scan register. Because the RAM clock(s) are independent from the TAP clock (TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample metastable input will not harm the device, repeatable results cannot be expected. RAM input signals must be stabilized for long enough to meet the TAPs input data capture setup plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other TAP operation except capturing the I/O ring contents into the boundary scan register. Moving the controller to shift-DR state then places the boundary scan register between the TDI and TDO pins. CLAMP 0000 0111 When the CLAMP instruction is loaded into the instruction register, the data driven by the output balls are determined from the values held in the boundary scan register. Selects the bypass register to be connected between TDI and TDO. Data driven by output balls are determined from values held in the boundary scan register. High-Z 0000 0011 The High-z instruction causes the boundary scan register to be connected between the TDI and TDO. This places all RAMs outputs into a High-Z state. Selects the bypass register to be connected between TDI and TDO. All outputs are forced into high impedance state. BYPASS 1111 1111 When the BYPASS instruction is loaded in the instruction register, the bypass register is placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-DR state. This allows the board level scan path to be shortened to facilitate testing of other devices in the scan path. Reserved for Future Use - The remaining instructions are not implemented but are reserved for future use. Do not use these instructions. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 44 of 48 PD48288209A, PD48288218A, PD48288236A TAP Controller State Diagram 1 Test-Logic-Reset 0 1 0 1 Run-Test / Idle 1 Select-DR-Scan Select-IR-Scan 0 0 1 1 Capture-DR Capture-IR 0 0 0 Shift-DR 0 Shift-IR 1 1 1 1 Exit1-DR Exit1-IR 0 0 0 Pause-DR 1 1 0 0 Exit2-DR Exit2-IR 1 1 Update-DR 1 R10DS0097EJ0100 Rev.1.00 February 28, 2012 0 Pause-IR Update-IR 0 1 0 Page 45 of 48 PD48288209A, PD48288218A, PD48288236A 4. Package Dimensions 144-PIN TAPE FBGA ( BGA) (18.5x11) D w S A D1 D A ZE ZD B SD eD 12 11 10 9 8 7 6 5 4 3 2 1 A E1 E SE eE 4xC0.2 INDEX MARK E2 V U T R P N M L K J H G F E D C B A w S B INDEX MARK D2 10 A y1 S A2 S y S A1 b (UNIT:mm) Detail of A pa rt x M S AB A3 ITEM DIMENSIONS D 18.50 0.10 D1 17.90 D2 14.52 E 11.000.10 E1 10.70 E2 2.184 w 0.20 A 1.070.10 A1 0.390.05 A2 0.68 A3 0.08 MAX. eD 1.00 eE 0.80 SD 0.50 SE 2.00 b 0.510.05 x 0.15 y 0.10 y1 0.20 ZD 0.75 ZE 1.10 P144FF-80-DW1 R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 46 of 48 PD48288209A, PD48288218A, PD48288236A 5. Recommended Soldering Condition Please consult with our sales offices for soldering conditions of these products. Types of Surface Mount Devices PD48288209AFF-DW1 : 144-pin TAPE FBGA (18.5 x 11) PD48288218AFF-DW1 : 144-pin TAPE FBGA (18.5 x 11) PD48288236AFF-DW1 : 144-pin TAPE FBGA (18.5 x 11) Quality Grade * A quality grade of the products is "Standard". * Anti-radioactive design is not implemented in the products. * Semiconductor devices have the possibility of unexpected defects by affection of cosmic ray that reach to the ground and so forth. R10DS0097EJ0100 Rev.1.00 February 28, 2012 Page 47 of 48 PD48288209A, PD48288218A, PD48288236A Revision History Rev. Date Rev.0.01 Rev.1.00 '11.08.01 '12.02.28 Description Page - Summary New Preliminary Data Sheet New Data Sheet All trademarks and registered trademarks are the property of their respective owners. C - 48 Notice 1. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. 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You may not use any Renesas Electronics product for any application categorized as "Specific" without the prior written consent of Renesas Electronics. Further, you may not use any Renesas Electronics product for any application for which it is not intended without the prior written consent of Renesas Electronics. Renesas Electronics shall not be in any way liable for any damages or losses incurred by you or third parties arising from the use of any Renesas Electronics product for an application categorized as "Specific" or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics. The quality grade of each Renesas Electronics product is "Standard" unless otherwise expressly specified in a Renesas Electronics data sheets or data books, etc. "Standard": Computers; office equipment; communications equipment; test and measurement equipment; audio and visual equipment; home electronic appliances; machine tools; personal electronic equipment; and industrial robots. "High Quality": Transportation equipment (automobiles, trains, ships, etc.); traffic control systems; anti-disaster systems; anti-crime systems; safety equipment; and medical equipment not specifically designed for life support. "Specific": Aircraft; aerospace equipment; submersible repeaters; nuclear reactor control systems; medical equipment or systems for life support (e.g. artificial life support devices or systems), surgical implantations, or healthcare intervention (e.g. excision, etc.), and any other applications or purposes that pose a direct threat to human life. 8. You should use the Renesas Electronics products described in this document within the range specified by Renesas Electronics, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas Electronics shall have no liability for malfunctions or damages arising out of the use of Renesas Electronics products beyond such specified ranges. 9. Although Renesas Electronics endeavors to improve the quality and reliability of its products, semiconductor products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Further, Renesas Electronics products are not subject to radiation resistance design. Please be sure to implement safety measures to guard them against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas Electronics product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other appropriate measures. Because the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 10. Please contact a Renesas Electronics sales office for details as to environmental matters such as the environmental compatibility of each Renesas Electronics product. Please use Renesas Electronics products in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. 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