CY8C24X93 PSoC(R) Programmable System-on-Chip PSoC(R) Programmable System-on-Chip Features Powerful Harvard-architecture processor M8C CPU with a max speed of 24 MHz Operating Range: 1.71 V to 5.5 V Standby Mode 1.1 A (Typ) Deep Sleep 0.1 A (Typ) Operating Temperature range: -40 C to +85 C Flexible on-chip memory 8 KB flash, 1 KB SRAM 16 KB flash, 2 KB SRAM 32 KB flash, 2 KB SRAM Read while Write with EEPROM emulation 50,000 flash erase/write cycles In-system programming simplifies manufacturing process Four Clock Sources Internal main oscillator (IMO): 6/12/24 MHz Internal low-speed oscillator (ILO) at 32 kHz for watchdog and sleep timers External 32 KHz Crystal Oscillator External Clock Input Programmable pin configurations Up to 36 general purpose dual mode GPIO (Analog inputs and Digital I/O supported) High sink current of 25 mA per GPIO * Max sink current 120 mA for all GPIOs Source Current * 5 mA on ports 0 and 1 * 1 mA on ports 2,3 and 4 Configurable internal pull-up, high-Z and open drain modes Selectable, regulated digital I/O on port 1 Configurable input threshold on port 1 Cypress Semiconductor Corporation Document Number: 001-86894 Rev. *B * Versatile Analog functions Internal Low-Dropout voltage regulator for high power supply rejection ratio (PSRR) Full-Speed USB 12 Mbps USB 2.0 compliant Eight unidirectional endpoints One bidirectional endpoint Dedicated 512 byte SRAM No external crystal required Additional system resources I2C Slave: * Selectable to 50 kHz, 100 kHz, or 400 kHz Configurable up to 12 MHz SPI master and slave Three 16-bit timers Watchdog and sleep timers Integrated supervisory circuit 10-bit incremental analog-to-digital converter (ADC) with internal voltage reference Two general-purpose Comparators * 3 Voltage References (0.8 V, 1 V, 1.2 V) * Any pin to either comparator inputs * Low-power operation at 10 A One 8-bit IDAC with full scale range of 512 A One 8-bit Software PWM Development Platform PSoC DesignerTM IDE GPIOs and Package options 13 GPIOs - QFN 16 28 GPIOs - QFN 32 34 GPIOs - QFN 48 36 GPIOs - QFN 48 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised May 24, 2013 CY8C24X93 Logic Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 1.8/2.5/3V LDO [1] PWRSYS (Regulator) PSoC CORE SYSTEM BUS Global Analog Interconnect 1K/2K SRAM Supervisory ROM (SROM) Interrupt Controller 8K/16K/32K Flash Nonvolatile Memory Sleep and Watchdog CPU Core (M8C) 6/12/24 MHz Internal Main Oscillator (IMO) Internal Low Speed Oscillator (ILO) Multiple Clock Sources ANALOG SYSTEM Analog Reference ADC Two Comparators Analog Mux IDAC SYSTEM BUS USB I2C Slave Internal Voltage References System Resets POR and LVD SPI Master/ Slave Three 16-Bit Programmable Timers Digital Clocks SYSTEM RESOURCES Note 1. Internal voltage regulator for internal circuitry. Document Number: 001-86894 Rev. *B Page 2 of 65 CY8C24X93 Contents PSoC(R) Functional Overview ............................................ 5 PSoC Core .................................................................. 5 Analog system ............................................................. 5 Additional System Resources ..................................... 6 Getting Started .................................................................. 7 Silicon Errata ............................................................... 7 Development Kits ........................................................ 7 Training ....................................................................... 7 CYPros Consultants .................................................... 7 Solutions Library .......................................................... 7 Technical Support ....................................................... 7 Development Tools .......................................................... 8 PSoC Designer Software Subsystems ........................ 8 Designing with PSoC Designer ....................................... 9 Select User Modules ................................................... 9 Configure User Modules .............................................. 9 Organize and Connect ................................................ 9 Generate, Verify, and Debug ....................................... 9 Pinouts ............................................................................ 10 16-pin QFN (13 GPIOs) [2] ........................................ 10 32-pin QFN (28 GPIOs) [6] ........................................ 11 32-pin QFN (28 GPIOs) [10] ...................................... 12 48-pin QFN (34 GPIOs) [14] ...................................... 13 48-pin QFN (36 GPIOs (With USB)) [19] ................... 14 48-pin QFN (OCD) (36 GPIOs) [23] .......................... 15 Electrical Specifications (CY8C24193/493) .................. 16 Absolute Maximum Ratings (CY8C24193/493) ............................................................. 16 Operating Temperature (CY8C24193/493) ............................................................. 16 DC Chip-Level Specifications (CY8C24193/493) ............................................................. 17 DC GPIO Specifications (CY8C24193/493) ............................................................. 18 DC Analog Mux Bus Specifications (CY8C24193/493) ............................................................. 21 DC Low Power Comparator Specifications (CY8C24193/493) ............................................................. 21 Comparator User Module Electrical Specifications (CY8C24193/493) ............................................................. 21 ADC Electrical Specifications (CY8C24193/493) ............................................................. 22 DC POR and LVD Specifications (CY8C24193/493) ............................................................. 23 DC Programming Specifications (CY8C24193/493) ............................................................. 23 DC I2C Specifications (CY8C24193/493) ............................................................. 24 Shield Driver DC Specifications (CY8C24193/493) ............................................................. 24 DC IDAC Specifications (CY8C24193/493) ............................................................. 24 AC Chip-Level Specifications (CY8C24193/493) ............................................................. 25 Document Number: 001-86894 Rev. *B AC General Purpose I/O Specifications (CY8C24193/493) ............................................................. 26 AC Comparator Specifications (CY8C24193/493) ............................................................. 26 AC External Clock Specifications (CY8C24193/493) ............................................................. 26 AC Programming Specifications (CY8C24193/493) ............................................................. 27 AC I2C Specifications (CY8C24193/493) .................. 28 Electrical Specifications (CY8C24093/293/393/693) ............................................... 31 Absolute Maximum Ratings (CY8C24093/293/393/693) ............................................... 31 Operating Temperature (CY8C24093/293/393/693) ............................................... 31 DC Chip-Level Specifications (CY8C24093/293/393/693) ............................................... 32 DC GPIO Specifications (CY8C24093/293/393/693) ............................................... 33 DC Analog Mux Bus Specifications (CY8C24093/293/393/693) ............................................... 35 DC Low Power Comparator Specifications (CY8C24093/293/393/693) ............................................... 35 Comparator User Module Electrical Specifications (CY8C24093/293/393/693) ............................................... 36 ADC Electrical Specifications (CY8C24093/293/393/693) ............................................... 36 DC POR and LVD Specifications (CY8C24093/293/393/693) ............................................... 37 DC Programming Specifications (CY8C24093/293/393/693) ............................................... 37 DC I2C Specifications (CY8C24093/293/393/693) ............................................... 38 DC Reference Buffer Specifications (CY8C24093/293/393/693) ............................................... 38 DC IDAC Specifications (CY8C24093/293/393/693) ............................................... 38 AC Chip-Level Specifications (CY8C24093/293/393/693) ............................................... 39 AC GPIO Specifications (CY8C24093/293/393/693) ............................................... 40 AC Comparator Specifications (CY8C24093/293/393/693) ............................................... 41 AC External Clock Specifications (CY8C24093/293/393/693) ............................................... 41 AC Programming Specifications (CY8C24093/293/393/693) ............................................... 42 AC I2C Specifications (CY8C24093/293/393/693) ............................................... 43 Packaging Information ................................................... 46 Thermal Impedances ................................................. 49 Capacitance on Crystal Pins ..................................... 49 Solder Reflow Specifications ..................................... 49 Development Tool Selection ......................................... 50 Software .................................................................... 50 Page 3 of 65 CY8C24X93 Development Kits ...................................................... 50 Evaluation Tools ........................................................ 50 Device Programmers ................................................. 50 Ordering Information ...................................................... 51 Ordering Code Definitions ......................................... 51 Acronyms ........................................................................ 52 Document Conventions ................................................. 53 Units of Measure ....................................................... 53 Reference Documents .................................................... 53 Numeric Naming ............................................................. 53 Glossary .......................................................................... 54 Appendix A: Silicon Errata for the CY8C24093/293/393/693 Family ..................................... 55 CY8C24093/293/393/693 Qualification Status .......... 55 CY8C24093/293/393/693 Errata Summary ............... 55 Document Number: 001-86894 Rev. *B Appendix B: Silicon Errata for the PSoC(R) CY8C24193/493 Families .................................. 60 CY8C24193/493 Qualification Status ........................ 60 CY8C24193/493 Errata Summary ............................. 60 Document History Page ................................................. 64 Sales, Solutions, and Legal Information ...................... 65 Worldwide Sales and Design Support ....................... 65 Products .................................................................... 65 PSoC Solutions ......................................................... 65 Page 4 of 65 CY8C24X93 PSoC(R) Functional Overview The PSoC family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (MCU)-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The architecture for this device family, as shown in the Logic Block Diagram on page 2, consists of three main areas: The Core Analog System System Resources (including a full-speed USB port). reference. All the pins can be configured to connect to the analog system. ADC The ADC in the CY8C24x93 device is an incremental analog-to-digital converter with a range of 8 to 10 bits supporting signed and unsigned data formats. The input to the ADC can be from any pin. IDAC The IDAC can provide current source up to 512 A to any GPIO pin. In the CY8C24x93 family of devices 4 ranges of current source can be implemented that can vary in 255 steps, and are connected to analog mux bus. Table 1. IDAC Ranges A common, versatile bus allows connection between I/O and the analog system. Depending on the PSoC package, up to 36 GPIO are included in the CY8C24x93 PSoC device. The GPIO provides access to the MCU and analog mux. PSoC Core The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO and ILO. The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit Harvard-architecture microprocessor. Analog system The analog system is composed of an ADC, two comparators and an IDAC. It has an internal 0.8 V, 1 V or 1.2 V analog Document Number: 001-86894 Rev. *B Range Full Scale Range in A 1x 64 2x 128 4x 256 8x 512 Comparator The CY8C24x93 family has two high-speed, low-power comparators. The comparators have three voltage references, 0.8 V, 1.0 V and 1.2 V. Comparator inputs can be connected from any pin through the analog mux bus. The comparator output can be read in firmware for processing or routed out via specific pins (P1_0 or P1_4). The output of the two comparators can be combined with 2-input logic functions. The combinatorial output can be optionally combined with a latched value and routed to a pin output or to the interrupt controller. The input multiplexers and the comparator are controller through the CMP User Module. Page 5 of 65 CY8C24X93 Analog Multiplexer System The Analog Mux Bus can connect to every GPIO pin and can be internally connected to the ADC, Comprators or the IDAC. Other multiplexer applications include: Chip-wide mux that allows analog input from any I/O pin. Crosspoint connection between any I/O pin combinations. Additional System Resources System resources provide additional capability, such as configurable USB and I2C slave, SPI master/slave communication interface, three 16-bit programmable timers, software 8-bit PWM, low voltage detect, power on reset, and various system resets supported by the M8C. The merits of each system resource are listed here: Document Number: 001-86894 Rev. *B The I2C slave/SPI master-slave module provides 50/100/400 kHz communication over two wires. SPI communication over three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). Low-voltage detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced power-on-reset (POR) circuit eliminates the need for a system supervisor. A register-controlled bypass mode allows the user to disable the LDO regulator. An 8-bit Software PWM is provided for applications like buzzer control or lighting control. A 16-bit Timer acts as the input clock to the PWM. The ISR increments a software counter (8-bit), checks for PWM compare condition and toggles a GPIO accordingly. PWM Output is available on all GPIOs. Page 6 of 65 CY8C24X93 Getting Started The quickest way to understand PSoC silicon is to read this datasheet and then use the PSoC Designer Integrated Development Environment (IDE). This datasheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants For in depth information, along with detailed programming details, see the Technical Reference Manual for the PSoC devices. Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web at www.cypress.com/psoc. Solutions Library Silicon Errata Errata documents known issues with silicon including errata trigger conditions, scope of impact, available workarounds and silicon revision applicability. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Document Number: 001-86894 Rev. *B Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support Technical support - including a searchable Knowledge Base articles and technical forums - is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Page 7 of 65 CY8C24X93 Development Tools PSoC DesignerTM is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration Extensive user module catalog C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Integrated source-code editor (C and assembly) Debugger Free C compiler with no size restrictions or time limits Built-in debugger In-circuit emulation PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also lets you to create a trace buffer of registers and memory locations of interest. Built-in support for communication interfaces: 2 Hardware and software I C slaves and masters Full-speed USB 2.0 Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer Software Subsystems Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this lets you to use more than 100 percent of PSoC's resources for an application. Document Number: 001-86894 Rev. *B In-Circuit Emulator A low-cost, high-functionality in-circuit emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24 MHz) operation. Page 8 of 65 CY8C24X93 Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is: 1. Select user modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called "user modules". User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each eight bits of resolution. Using these parameters, you can establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All of the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the Document Number: 001-86894 Rev. *B internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. Organize and Connect Build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. Perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the "Generate Configuration Files" step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides APIs with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. A complete code development environment lets you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger (accessed by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full-speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. It lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Page 9 of 65 CY8C24X93 Pinouts 16-pin QFN (13 GPIOs) [2] Table 2. Pin Definitions - CY8C24093 [3] I/O I P2[5] Crystal output (XOut) 2 I/O I P2[3] Crystal input (XIn) 3 IOHR I P1[7] I2C SCL, SPI SS 2 4 IOHR I P1[5] I C SDA, SPI MISO 5 IOHR I P1[3] SPI CLK 6 IOHR I P1[1] ISSP CLK[4], I2C SCL, SPI MOSI 7 Power VSS IOHR I P1[0] ISSP DATA[4], I2C SDA, SPI CLK[5] 9 IOHR I P1[2] 10 IOHR I P1[4] Optional external clock (EXTCLK) 12 13 Input IOH P0[1], AI P0[3], AI P0[7], AI VDD AI , XOut, P2[5] AI , XIn, P2[3] AI , I2 C SCL, SPI SS, P1[7] AI , I2 C SDA, SPI MISO, P1[5] Ground connection 8 11 Figure 1. CY8C24093 Device Description XRES Active high external reset with internal pull-down I P0[4] Power VDD 14 IOH I P0[7] 15 IOH I P0[3] 16 IOH I P0[1] 1 2 14 13 1 Name 16 15 Analog 12 11 (Top View) 10 3 9 4 QFN 5 6 7 8 Digital P0[4] , AI XRES P1[4] , EXTCLK, AI P1[2] , AI AI, SPI CLK , P1[3] AI, ISSP CLK, SPI MOSI, P1[1] VSS AI, ISSP DATA , I2C SDA, SPI CLK , P1[0] Type Pin No. Supply voltage LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 2. No center pad. 3. 13 GPIOs. 4. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 5. Alternate SPI clock. Document Number: 001-86894 Rev. *B Page 10 of 65 CY8C24X93 32-pin QFN (28 GPIOs) [6] Table 3. Pin Definitions - CY8C24193 [7] I P0[1] I/O I P2[7] 3 I/O I P2[5] Crystal output (XOut) 4 I/O I P2[3] Crystal input (XIn) 5 I/O I P2[1] 6 I/O I P3[3] 7 I/O I P3[1] 8 IOHR I P1[7] I2C SCL, SPI SS 9 IOHR I P1[5] I2C SDA, SPI MISO 10 IOHR I P1[3] SPI CLK. 11 IOHR I P1[1] ISSP CLK[8], I2C SCL, SPI MOSI. P1[0] 14 IOHR I P1[2] 15 IOHR I P1[4] 16 IOHR 17 I Input ISSP DATA[8], I2C SDA, SPI CLK[9] Optional external clock input (EXTCLK) P1[6] XRES I/O I P3[0] 19 I/O I P3[2] 20 I/O I P2[0] 21 I/O I P2[2] 22 I/O I P2[4] 23 I/O I P2[6] 24 IOH I P0[0] 25 IOH I P0[2] 26 IOH I P0[4] 27 IOH I P0[6] 9 30 29 10 11 12 P0[0] , AI P2[6] , AI P2[4] , AI P2[2] , AI P2[0] , AI P3[2] , AI P3[0] , AI XRES [8] 18 Active high external reset with internal pull-down 32 31 Vss P0 [3], AI P0 [5], AI Ground connection. 15 16 I AI, E XTCLK, P 1[4] AI, P 1[6] VSS IOHR QFN (Top View) 24 23 22 21 20 19 18 17 13 14 Power 13 1 2 3 4 5 6 7 8 A I,ISSP CLK , I2C SCL, SPI MOSI, P1[1] Vss [8] AI , ISSP DATA , I2C SDA, SPI CLK, P1[0] AI, P 1[2] 12 AI , P0[1] AI , P2[7] AI, XOut, P2[5] AI , XIn, P2[3] AI , P2[1] AI , P3[3] AI , P3[1] AI , I2 C SCL, SPI SS, P1[7] P0 [4], AI P0 [2], AI IOH 2 Figure 2. CY8C24193 Description 26 25 1 Name P0 [7], AI Vd d P0 [6], AI Analog 28 27 Digital AI, I2C SDA, SPI MISO, P 1[5] AI, SPI CLK, P 1[3] Type Pin No. 28 Power VDD 29 IOH I P0[7] 30 IOH I P0[5] 31 IOH I P0[3] Supply voltage 32 Power VSS Ground connection CP Power VSS Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 6. 28 GPIOs. 7. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 8. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 9. Alternate SPI clock. Document Number: 001-86894 Rev. *B Page 11 of 65 CY8C24X93 32-pin QFN (28 GPIOs) [10] Table 4. Pin Definitions - CY8C24293 [11] P2[5] Crystal output (XOut) 3 I/O I P2[3] Crystal input (XIn) 4 I/O I P2[1] 5 I/O I P4[3] 6 I/O I P3[3] 7 I/O I P3[1] 8 IOHR I P1[7] I2C SCL, SPI SS 9 IOHR I P1[5] I2C SDA, SPI MISO 10 IOHR I P1[3] SPI CLK. 11 IOHR I P1[1] ISSP CLK [12], I2C SCL, SPI MOSI. 12 Power VSS Ground connection 13 IOHR I P1[0] ISSP DATA[12], I2C SDA, SPI CLK[13] 14 IOHR I P1[2] 15 IOHR I P1[4] 16 IOHR I P1[6] 17 Input 18 I/O I P3[0] 19 I/O I P3[2] 20 I/O I P4[0] 21 I/O I P4[2] 22 I/O I P2[0] 23 I/O I P2[2] 24 I/O I P2[4] 25 IOH I P0[0] 26 IOH I P0[2] 27 IOH I P0[4] 28 IOH I P0[6] 29 Power 30 IOH I P0[7] 31 IOH I P0[3] 32 Power VSS Ground connection CP Power VSS Center pad must be connected to ground AI , XOut ,P0[1] AI , XIn ,P2[5] AI ,P2[3] AI ,P2[ 1] AI ,P4[3] AI ,P3[3] AI ,P3[1] AI ,I2 C SCL, SPI SS,P1[7] Optional external clock input (EXTCLK) Active high external reset with internal pull-down P0 [4 ], AI P0 [2 ], AI P0 [0 ], AI P0[1] I 1 2 3 4 5 6 7 8 QFN (Top View) 24 23 22 21 20 19 18 17 P2[4] ,AI P2[2] ,AI P2[0] ,AI P4[2] ,AI P4[0] ,AI P3[2] ,AI P3[0] ,AI XRES AI, EXTCLK, P 1[ 4] AI, P 1[ 6] I I/O Vss P0 [3 ], AI P0 [7 ], AI VDD P0[6], AI IOH 2 32 31 30 29 28 27 26 25 1 XRES Figure 3. CY8C24293 Device Description 9 Name 10 11 12 13 14 15 16 Analog AI, I2C SDA , SPI MI SO, P 1[ 5] A I, SP I CLK, P 1[ 3] AI ,ISSP CLK , I2C SCL, SPI MOSI, P1[1] Vss [12] AI ,ISSP DATA , I2C SDA, SPI CLK, P1[0] AI, P 1[ 2] Digital [12] Pin No. VDD LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 10. 28 GPIOs. 11. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 12. On power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 13. Alternate SPI clock. Document Number: 001-86894 Rev. *B Page 12 of 65 CY8C24X93 48-pin QFN (34 GPIOs) [14] Table 5. Pin Definitions - CY8C24393, CY8C24693 [15, 16] Power 22 IOHR I P1[0] 23 24 IOHR IOHR I I P1[2] P1[4] 25 26 IOHR Input I P1[6] XRES 27 28 29 30 31 32 33 34 35 I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I AI , XIn ,P2[3] AI ,P2[1] AI ,P4[3] AI ,P4[1] AI ,P3[7] AI ,P3[5] AI ,P3[3] AI P3[1] AI ,I2 C SCL, SPI SS,P1[7] I2C SCL, SPI SS I2C SDA, SPI MISO No connection No connection SPI CLK ISSP CLK[17], I2C SCL, SPI MOSI Ground connection No connection No connection Supply voltage ISSP DATA[17], I2C SDA, SPI CLK[18] Optional external clock input (EXTCLK) Active high external reset with internal pull-down P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] 1 2 Pin No. 36 Digital Analog 5 6 Name IOH IOH I I P0[0] P0[2] 39 40 IOH IOH I I P0[4] P0[6] 41 42 43 44 45 46 47 48 CP Power IOH Power IOH Power I I P0[2], AI P0[0], AI Vd d P0[6], AI P0[4], AI (Top View) 37 38 I NC , P0[7], AI NC NC QFN 7 8 9 10 11 12 36 35 34 33 32 31 3 4 NC IOH 38 37 NC AI ,P2[7] AI , XOut,P2[5] 42 41 40 39 Crystal output (XOut) Crystal input (XIn) 46 45 44 43 I I No connection 15 16 17 18 19 20 21 22 23 24 IOHR IOHR Power NC P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] NC NC P1[3] P1[1] VSS NC NC VDD P0[1], AI Vss P0[3], AI I I I I I I I I I I I I Figure 4. CY8C24393, CY8C24693 Device Description 48 47 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOHR IOHR Name 13 14 Analog 30 29 28 27 26 25 NC P2[ 4], AI P2[ 2], AI P2[ 0], AI P4[ 2], AI P4[ 0], AI P3[ 6], AI P3[ 4], AI P3[ 2], AI P3[0], AI XRES P1[ 6], AI NC NC SPI C LK, A I, P1[3] AI, ISSP C LK, I2C SCL, SPI MOSI, P1[1] Vss NC NC Vdd 1 AI, ISSP DATA , I2C SDA, SPI CLK, P1[0] AI, P1 [2 ] AI, EXTCL K, P1[4] Digital I2 C SD A, SPI MIS O, A I, P1[5] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 VDD NC NC P0[7] NC P0[3] VSS P0[1] VSS Description No connection Supply voltage No connection No connection No connection Ground connection Center pad must be connected to ground LEGENDA = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output. Notes 14. 38 GPIOs. 15. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes. 16. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 17. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance (5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 18. Alternate SPI clock. Document Number: 001-86894 Rev. *B Page 13 of 65 CY8C24X93 48-pin QFN (36 GPIOs (With USB)) [19] Table 6. Pin Definitions - CY8C24493 [20, 21] IOHR I IOHR I Power I/O I/O Power IOHR I NC P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] NC NC P1[3] P1[1] VSS D+ DVDD P1[0] 23 24 IOHR IOHR P1[2] P1[4] 25 26 IOHR I Input I I P1[6] XRES 27 28 29 I/O I/O I/O I I I P3[0] P3[2] P3[4] 30 31 32 33 34 35 36 37 38 39 I/O I/O I/O I/O I/O I/O I/O IOH IOH IOH I I I I I I I I I I P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] No connection Crystal output (XOut) Crystal input (XIn) NC AI , P2[7] AI , XOut, P2[5] AI , XIn , P2[3] AI , P2[1] AI , P4[3] AI , P4[1] AI , P3[7] AI , P3[5] AI , P3[3] AI , P3[1] AI , I2 C SCL, SPI SS, P1[7] I2C SCL, SPI SS I2C SDA, SPI MISO No connection No connection SPI CLK ISSP CLK[20], I2C SCL, SPI MOSI Ground connection USB D+ USB DSupply voltage ISSP DATA[20], I2C SDA, SPI CLK[22] Vss P0[3], AI P0[5 ], AI P0[7], AI NC NC Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI I I I I I I I I I I I I Figure 5. CY8C24493 Description P0[1], AI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOHR IOHR Name 48 47 46 45 44 43 42 41 40 39 38 37 Analog 1 2 3 4 5 6 7 8 9 10 11 12 QFN (Top View) 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Digital 36 35 34 33 32 31 30 29 28 27 26 25 P2[6] , AI P2[4] ,AI P2[2] ,AI P2[0] ,AI P4[2] ,AI P4[0] ,AI P3[6] ,AI P3[4] , AI P3[2] ,AI P3[0] , AI XRES P1[6] , AI I2C SDA, SPI MISO, A I, P1[5] NC NC SPI CLK, A I, P1[3] [20] AI,ISSP CLK , I2C SCL, SPI MOSI, P1[1] Vss D+ DVdd [20, 22] AI,ISSP DATA, I2C SDA, SPI CLK, P1[0] AI, P1[2] AI, EXTCLK, P1[4] Pin No. Optional external clock input (EXTCLK) Active high external reset with internal pull-down Pin No. 40 41 42 43 44 45 46 47 48 CP Digital IOH IOH IOH IOH Analog I Power I I I Power IOH I Power Name P0[6] VDD NC NC P0[7] P0[5] P0[3] VSS P0[1] VSS Description Supply voltage No connection No connection Ground connection Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output. Notes 19. 36 GPIOs. 20. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance (5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 21. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 22. Alternate SPI clock. Document Number: 001-86894 Rev. *B Page 14 of 65 CY8C24X93 48-pin QFN (OCD) (36 GPIOs) [23] The 48-pin QFN part is for the CY8C240093 On-Chip Debug (OCD). Note that this part is only used for in-circuit debugging. Table 7. Pin Definitions - CY8C240093 [24, 25] I I 18 19 20 21 22 Power IOHR I VSS D+ DVDD P1[0] 23 IOHR I P1[2] 24 IOHR I P1[4] 25 26 IOHR I Input 27 28 29 30 31 32 33 34 35 36 Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I P1[6] XRES OCD mode direction pin Crystal output (XOut) Crystal input (XIn) OCDO A E , P2[7] I AI , XOut, P2[5] AI , XIn , P2[3] AI , P2[1] AI , P4[3] AI , P4[1] AI , P3[7] AI , P3[5] AI , P3[3] AI , P3[1] AI , I2 C SCL, SPI SS, P1[7] I2C SCL, SPI SS I2C SDA, SPI MISO OCD CPU clock output OCD high speed clock output SPI CLK. ISSP CLK[27], I2C SCL, SPI MOSI Ground connection USB D+ USB DSupply voltage ISSP DATA[27], I2C SDA, SPI CLK[28] Optional external clock input (EXTCLK) Active high external reset with internal pull-down P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] P2[6] OCDO Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI IOHR IOHR OCDOE P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] CCLK HCLK P1[3] P1[1] Vss P0[3], AI P0[5 ], AI P0[7], AI OCDE I I I I I I I I I I I I Figure 6. CY8C240093 Description P0[1], AI I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOHR IOHR Name 48 47 46 45 44 43 42 41 40 39 38 37 Analog 1 2 3 4 5 6 7 8 9 10 11 12 QFN (Top View) 13 14 15 16 17 18 19 20 21 22 23 24 1[26] 2 3 4 5 6 7 8 9 10 11 12 13 14[26] 15[26] 16 17 Digital 36 35 34 33 32 31 30 29 28 27 26 25 P2[6] , AI P2[4] , AI P2[2] , AI P2[0] , AI P4[2] , AI P4[0] , AI P3[6] , AI P3[4] , AI P3[2] , AI P3[0] , AI XRES P1[6] , AI I2C SDA, SPI MISO, AI, P1[5] CCLK HCLK SPI CLK, A I, P1[3] [27] AI,ISSP CLK6, I2C SCL, SPI MOSI, P1[1] Vss D+ DVdd [27, 28] AI,ISSP DATA1 , I2C SDA, SPI CLK, P1[0] AI, P1[2] AI, EXTCLK, P1[4] Pin No. Pin No. 37 Digital Analog IOH I P0[0] 38 39 IOH IOH I I P0[2] P0[4] 40 41 42[26] 43[26] 44 45 46 47 48 CP IOH I P0[6] VDD OCDO OCDE P0[7] P0[5] P0[3] VSS P0[1] VSS Power IOH IOH IOH I I I Power IOH I Power Name Description Supply voltage OCD even data I/O OCD odd data output Ground connection Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output. Notes 23. 36 GPIOs. 24. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes. 25. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 26. This pin (associated with OCD part only) is required for connecting the device to ICE-Cube In-Circuit Emulator for firmware debugging purpose. To know more about the usage of ICE-Cube, refer to CY3215-DK PSoC(R) IN-CIRCUIT EMULATOR KIT GUIDE. 27. On Power-up, the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1]) line drives resistive low for 512 sleep clock cycles and both the pins transition to High impedance state. On reset, after XRES de- asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance (5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 28. Alternate SPI clock. Document Number: 001-86894 Rev. *B Page 15 of 65 CY8C24X93 Electrical Specifications (CY8C24193/493) This section presents the DC and AC electrical specifications of the CY8C24193/493 PSoC devices. For the latest electrical specifications, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc. Figure 7. Voltage versus CPU Frequency 5.5 V VDD Voltage li d ng Va rati n e io Op Reg 1.71 V 750 kHz 3 MHz CPU 24 MHz Frequency Absolute Maximum Ratings (CY8C24193/493) Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 8. Absolute Maximum Ratings Symbol Description Conditions Min Typ Max Units TSTG Storage temperature Higher storage temperatures reduce data retention time. Recommended Storage Temperature is +25 C 25 C. Extended duration storage temperatures above 85 C degrades reliability. -55 +25 +125 C VDD Supply voltage relative to VSS - -0.5 - +6.0 V VIO DC input voltage - VSS - 0.5 - VDD + 0.5 V VIOZ DC voltage applied to tristate - VSS - 0.5 - VDD + 0.5 V IMIO Maximum current into any port pin - -25 - +50 mA ESD Electro static discharge voltage Human body model ESD 2000 - - V LU Latch up current In accordance with JESD78 standard - - 200 mA Min Typ Max Units - +85 C 70 C +100 C Operating Temperature (CY8C24193/493) Table 9. Operating Temperature Symbol Description Conditions TA Ambient temperature - -40 TC Commercial temperature range - 0 TJ Operational die temperature The temperature rise from ambient to junction is package specific. See the Thermal Impedances on page 49. The user must limit the power consumption to comply with this requirement. Document Number: 001-86894 Rev. *B -40 - Page 16 of 65 CY8C24X93 DC Chip-Level Specifications (CY8C24193/493) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 10. DC Chip-Level Specifications Symbol VDD [29, 43] Description Supply voltage Conditions See table DC POR and LVD Specifications (CY8C24093/293/393/693) on page 37 Min Typ Max Units 1.71 - 5.50 V IDD24 Supply current, IMO = 24 MHz Conditions are VDD 3.0 V, TA = 25 C, CPU = 24 MHz. - 2.88 4.00 mA IDD12 Supply current, IMO = 12 MHz Conditions are VDD 3.0 V, TA = 25 C, CPU = 12 MHz. - 1.71 2.60 mA IDD6 Supply current, IMO = 6 MHz Conditions are VDD 3.0 V, TA = 25 C, CPU = 6 MHz. - 1.16 1.80 mA ISB0 Deep sleep current VDD 3.0 V, TA = 25 C, I/O regulator turned off - 0.10 1.1 A ISB1 Standby current with POR, LVD VDD 3.0 V, TA = 25 C, I/O regulator turned off and sleep timer - 1.07 1.50 A ISBI2C Standby current with I2C enabled - 1.64 - A Conditions are VDD = 3.3 V, TA = 25 C and CPU = 24 MHz Notes 29. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 s, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be slower than 1 V/500 s to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter. 30. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken: a. Bring the device out of sleep before powering down. b. Assure that VDD falls below 100 mV before powering back up. c. Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep. d. Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register. For the referenced registers, refer to the Technical Reference Manual. In deep sleep/standby sleep mode, additional low power voltage monitoring circuitry allows VDD brown out conditions to be detected and resets the device when VDD goes lower than 1.1 V at edge rates slower than 1 V/ms. Document Number: 001-86894 Rev. *B Page 17 of 65 CY8C24X93 DC GPIO Specifications (CY8C24193/493) The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and -40 C TA 85 C, 2.4 V to 3.0 V and -40 C TA 85 C, or 1.71 V to 2.4 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 11. 3.0 V to 5.5 V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units RPU Pull-up resistor - 4 5.60 8 k VOH1 High output voltage Port 2 or 3 pins IOH < 10 A, maximum of 10 mA source current in all I/Os VDD - 0.20 - - V VOH2 High output voltage Port 2 or 3 Pins IOH = 1 mA, maximum of 20 mA source current in all I/Os VDD - 0.90 - - V VOH3 High output voltage IOH < 10 A, maximum of 10 mA source Port 0 or 1 pins with LDO regulator Disabled current in all I/Os for port 1 VDD - 0.20 - - V VOH4 High output voltage IOH = 5 mA, maximum of 20 mA source Port 0 or 1 pins with LDO regulator Disabled current in all I/Os for port 1 VDD - 0.90 - - V VOH5 IOH < 10 A, VDD > 3.1 V, maximum of High output voltage Port 1 Pins with LDO Regulator Enabled for 4 I/Os all sourcing 5 mA 3 V out 2.85 VOH6 High output voltage IOH = 5 mA, VDD > 3.1 V, maximum of 20 mA Port 1 pins with LDO regulator enabled for source current in all I/Os 3 V out 2.20 VOH7 High output voltage IOH < 10 A, VDD > 2.7 V, maximum of 20 mA Port 1 pins with LDO enabled for 2.5 V out source current in all I/Os 2.35 VOH8 High output voltage IOH = 2 mA, VDD > 2.7 V, maximum of 20 mA Port 1 pins with LDO enabled for 2.5 V out source current in all I/Os 1.90 VOH9 High output voltage IOH < 10 A, VDD > 2.7 V, maximum of 20 mA Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os 1.60 VOH10 High output voltage IOH = 1 mA, VDD > 2.7 V, maximum of 20 mA Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os 1.20 - - V VOL Low output voltage IOL = 25 mA, VDD > 3.3 V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]) - - 0.75 V VIL Input low voltage - - - 0.80 V 3.00 3.30 - - 2.50 2.75 - - 1.80 2.10 V V V V V VIH Input high voltage - 2.00 - - V VH Input hysteresis voltage - - 80 - mV IIL Input leakage (Absolute Value) - - 0.00 1 1 A CPIN Pin capacitance Package and pin dependent Temp = 25 C 0.50 1.70 7 pF VILLVT3.3 Input Low Voltage with low threshold enable Bit3 of IO_CFG1 set to enable low threshold set, Enable for Port1 voltage of Port1 input 0.8 V - - VIHLVT3.3 Input High Voltage with low threshold enable Bit3 of IO_CFG1 set to enable low threshold set, Enable for Port1 voltage of Port1 input 1.4 - - V VILLVT5.5 Input Low Voltage with low threshold enable Bit3 of IO_CFG1 set to enable low threshold set, Enable for Port1 voltage of Port1 input 0.8 V - - VIHLVT5.5 Input High Voltage with low threshold enable Bit3 of IO_CFG1 set to enable low threshold set, Enable for Port1 voltage of Port1 input 1.7 - - V Document Number: 001-86894 Rev. *B Page 18 of 65 CY8C24X93 Table 12. 2.4 V to 3.0 V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units 4 5.60 8 k IOH < 10 A, maximum of 10 mA source VDD - 0.20 current in all I/Os - - V High output voltage Port 2 or 3 Pins IOH = 0.2 mA, maximum of 10 mA source current in all I/Os VDD - 0.40 - - V VOH3 High output voltage Port 0 or 1 pins with LDO regulator Disabled for port 1 IOH < 10 A, maximum of 10 mA source VDD - 0.20 current in all I/Os - - V VOH4 High output voltage Port 0 or 1 pins with LDO regulator Disabled for Port 1 IOH = 2 mA, maximum of 10 mA source VDD - 0.50 current in all I/Os - - V VOH5A IOH < 10 A, VDD > 2.4 V, maximum of High output voltage Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out 1.50 1.80 2.10 V VOH6A High output voltage IOH = 1 mA, VDD > 2.4 V, maximum of Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out 1.20 - - V VOL Low output voltage IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) - - 0.75 V VIL Input low voltage - - - 0.72 V VIH Input high voltage - 1.40 - VH Input hysteresis voltage - - 80 - mV IIL Input leakage (absolute value) - - 1 1000 nA CPIN Capacitive load on pins Package and pin dependent Temp = 25 C 0.50 1.70 7 pF VILLVT2.5 Input Low Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 0.7 V - VIHLVT2.5 Input High Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 1.2 RPU Pull-up resistor - VOH1 High output voltage Port 2 or 3 pins VOH2 Document Number: 001-86894 Rev. *B V - V Page 19 of 65 CY8C24X93 Table 13. 1.71 V to 2.4 V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units 4 5.60 8 k IOH = 10 A, maximum of 10 mA VDD - 0.20 source current in all I/Os - - V High output voltage Port 2 or 3 pins IOH = 0.5 mA, maximum of 10 mA VDD - 0.50 source current in all I/Os - - V VOH3 High output voltage Port 0 or 1 pins with LDO regulator Disabled for Port 1 IOH = 100 A, maximum of 10 mA VDD - 0.20 source current in all I/Os - - V VOH4 High output voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 IOH = 2 mA, maximum of 10 mA source VDD - 0.50 current in all I/Os - - V VOL Low output voltage IOL = 5 mA, maximum of 20 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) - - 0.40 V VIL Input low voltage - - - 0.30 x VDD V VIH Input high voltage - 0.65 x VDD - - V VH Input hysteresis voltage - - 80 - mV IIL Input leakage (absolute value) - - 1 1000 nA CPIN Capacitive load on pins Package and pin dependent temp = 25 C 0.50 1.70 7 pF RPU Pull-up resistor - VOH1 High output voltage Port 2 or 3 pins VOH2 Table 14. GPIO Current Sink and Source Specifications Supply Voltage Mode Port 1 per I/O (max) Port 2/3/4 per I/O (max) Total Current Even Pins (max) Total Current Odd Pins (max) Units 1.71 - 2.4 Sink 5 5 20 30 mA 2.4 - 3.0 3.0 - 5.0 Source 2 0.5 Sink 10 10 Source 2 0.2 Sink 25 25 Source 5 1 10[31] 30 mA 30 mA 60 mA 10[31] 60 20[31] mA mA Note 31. Total current (odd + even ports) Document Number: 001-86894 Rev. *B Page 20 of 65 CY8C24X93 DC Analog Mux Bus Specifications (CY8C24193/493) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 15. DC Analog Mux Bus Specifications Symbol Description Conditions Min Typ Max Units RSW Switch resistance to common analog bus - - - 800 RGND Resistance of initialization switch to VSS - - - 800 The maximum pin voltage for measuring RSW and RGND is 1.8 V DC Low Power Comparator Specifications (CY8C24193/493) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 16. DC Comparator Specifications Symbol Description Conditions Min Typ Max Units 0.2 - 1.8 V VLPC Low power comparator (LPC) common Maximum voltage limited to VDD mode ILPC LPC supply current - - 10 80 A VOSLPC LPC voltage offset - - 2.5 30 mV Comparator User Module Electrical Specifications (CY8C24193/493) The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: -40 C TA 85 C, 1.71 V VDD 5.5 V. Table 17. Comparator User Module Electrical Specifications Symbol Min Typ Max Units 50 mV overdrive - 70 100 ns Offset Valid from 0.2 V to 1.5 V - 2.5 30 mV Current Average DC current, 50 mV overdrive - 20 80 A Supply voltage > 2 V Power supply rejection ratio - 80 - dB Supply voltage < 2 V Power supply rejection ratio - 40 - dB 1.5 V TCOMP PSRR Description Comparator response time Input range Document Number: 001-86894 Rev. *B Conditions - 0.2 Page 21 of 65 CY8C24X93 ADC Electrical Specifications (CY8C24193/493) Table 18. ADC User Module Electrical Specifications Symbol Description Conditions Min Typ Max Units 0 - VREFADC V Input VIN Input voltage range CIIN Input capacitance - RIN Input resistance Equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution ADC reference voltage FCLK - - - 5 pF 1/(500fF x data clock) 1/(400fF x data clock) 1/(300fF x data clock) - 1.14 - 1.26 V Data clock Source is chip's internal main oscillator. See AC Chip-Level Specifications on page 25 for accuracy 2.25 - 6 MHz S8 8-bit sample rate Data clock set to 6 MHz. sample rate = 0.001/ (2^Resolution/Data Clock) - 23.43 - ksps S10 10-bit sample rate Data clock set to 6 MHz. sample rate = 0.001/ (2^resolution/data clock) - 5.85 - ksps Reference VREFADC Conversion Rate DC Accuracy RES Resolution Can be set to 8, 9, or 10 bit 8 - 10 bits DNL Differential nonlinearity - -1 - +2 LSB INL Integral nonlinearity - -2 - +2 LSB EOFFSET Offset error 8-bit resolution 0 3.20 19.20 LSB 10-bit resolution 0 12.80 76.80 LSB EGAIN Gain error For any resolution -5 - +5 %FSR IADC Operating current - - 2.10 2.60 mA PSRR Power supply rejection ratio Power Document Number: 001-86894 Rev. *B PSRR (VDD > 3.0 V) - 24 - dB PSRR (VDD < 3.0 V) - 30 - dB Page 22 of 65 CY8C24X93 DC POR and LVD Specifications (CY8C24193/493) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 19. DC POR and LVD Specifications Symbol VPOR0 Description Conditions Min Typ Max Units 1.61 - 1.66 1.71 V 2.36 2.41 - 2.60 2.66 - 2.82 2.95 VPOR2 1.66 V selected in PSoC Designer VDD must be greater than or equal to 1.71 V 2.36 V selected in PSoC Designer during startup, reset from the XRES pin, or reset from watchdog. 2.60 V selected in PSoC Designer VPOR3 2.82 V selected in PSoC Designer VLVD0 2.45 V selected in PSoC Designer - 2.40 2.45 2.51 VLVD1 2.71 V selected in PSoC Designer 2.64[46] 2.71 2.78 VLVD2 2.92 V selected in PSoC Designer 2.85[47] 2.92 2.99 VLVD3 3.02 V selected in PSoC Designer 2.95[48] 3.02 3.09 VLVD4 3.13 V selected in PSoC Designer 3.06 3.13 3.20 VLVD5 1.90 V selected in PSoC Designer 1.84 1.90 2.32 VLVD6 1.80 V selected in PSoC Designer 1.75[49] 1.80 1.84 VLVD7 4.73 V selected in PSoC Designer 4.62 4.73 4.83 VPOR1 V DC Programming Specifications (CY8C24193/493) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 20. DC Programming Specifications Symbol Description VDDIWRITE Supply voltage for flash write operations IDDP Supply current during programming or verify VILP Input low voltage during programming or verify VIHP Input high voltage during programming or verify IILP Input current when Applying VILP to P1[0] or P1[1] during programming or verify IIHP Input current when applying VIHP to P1[0] or P1[1] during programming or verify VOLP Output low voltage during programming or verify VOHP Output high voltage during programming or verify FlashENPB Flash write endurance FlashDR Flash data retention - Conditions Min 1.71 Typ - Max 5.25 Units V - - 5 25 mA See appropriate DC GPIO Specifications (CY8C24093/293/393/693) on page 33 See appropriate DC GPIO Specifications (CY8C24093/293/393/693) on page 33 Driving internal pull-down resistor - - VIL V VIH - - V - - 0.2 mA - - 1.5 mA - - VSS + 0.75 V VOH - VDD V 50,000 20 - - - - - Years Driving internal pull-down resistor See appropriate DC GPIO Specifications (CY8C24093/293/393/693) on page 33. For VDD > 3V use VOH4 in Table 36 on page 33. Erase/write cycles per block Following maximum Flash write cycles; ambient temperature of 55 C Notes 32. Always greater than 50 mV above VPPOR1 voltage for falling supply. 33. Always greater than 50 mV above VPPOR2 voltage for falling supply. 34. Always greater than 50 mV above VPPOR3 voltage for falling supply. 35. Always greater than 50 mV above VPPOR0 voltage for falling supply. Document Number: 001-86894 Rev. *B Page 23 of 65 CY8C24X93 DC I2C Specifications (CY8C24193/493) The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and -40 C TA 85 C, 2.4 V to 3.0 V and -40 C TA 85 C, or 1.71 V to 2.4 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 21. DC I2C Specifications[36] Symbol VILI2C VIHI2C Description Input low level Input high level Conditions 3.1 V VDD 5.5 V Min - Typ - Max Units 0.25 x VDD V 2.5 V VDD 3.0 V - - 0.3 x VDD V 1.71 V VDD 2.4 V - - 0.3 x VDD V 1.71 V VDD 5.5 V 0.65 x VDD - VDD + 0.7 V[37] V Shield Driver DC Specifications (CY8C24193/493) The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and -40 C TA 85 C, 2.4 V to 3.0 V and -40 C TA 85 C, or 1.71 V to 2.4 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 22. Shield Driver DC Specifications Symbol VRef Description Reference buffer output Conditions 1.7 V VDD 5.5 V Min 0.942 Typ - Max 1.106 Units V VRefHi Reference buffer output 1.7 V VDD 5.5 V 1.104 - 1.296 V DC IDAC Specifications (CY8C24193/493) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 23. DC IDAC Specifications (8-bit IDAC) Symbol Description Min Typ Max Units Notes IDAC_DNL Differential nonlinearity -1 - 1 LSB IDAC_DNL Integral nonlinearity -2 - 2 LSB IDAC_Current Range = 4x 138 - 169 A DAC setting = 127 dec Range = 8x 138 - 169 A DAC setting = 64 dec Table 24. DC IDAC Specifications (7-bit IDAC) Symbol Description Min Typ Max Units Notes IDAC_DNL Differential nonlinearity -1 - 1 LSB IDAC_DNL Integral nonlinearity -2 - 2 LSB IDAC_Current Range = 4x 137 - 168 A DAC setting = 127 dec Range = 8x 138 - 169 A DAC setting = 64 dec Notes 36. Pull-up resistors on I2C interface cannot be connected to a supply voltage that is more than 0.7 V higher than the CY8C24x93 power supply. See the CY8C24x93 Silicon Errata document for more details. 37. Please refer to Item # 6 of the CY8C24x93 Family. Document Number: 001-86894 Rev. *B Page 24 of 65 CY8C24X93 AC Chip-Level Specifications (CY8C24193/493) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 25. AC Chip-Level Specifications Min Typ Max Units FIMO24 Symbol IMO frequency at 24 MHz Setting Description - Conditions 22.8 24 25.2 MHz FIMO12 IMO frequency at 12 MHz setting - 11.4 12 12.6 MHz FIMO6 IMO frequency at 6 MHz setting - 5.7 6.0 6.3 MHz FCPU CPU frequency - 0.75 - 25.20 MHz F32K1 ILO frequency - 15 32 50 kHz F32K_U ILO untrimmed frequency - 13 32 82 kHz DCIMO Duty cycle of IMO - 40 50 60 % DCILO ILO duty cycle - 40 50 60 % VDD slew rate during power-up - - 250 V/ms After supply voltage is valid 1 - - ms Applies after part has booted 10 - - s SRPOWER_UP Power supply slew rate tXRST External reset pulse width at power-up tXRST2 tJIT_IMO External reset pulse width after [39] power-up[50] 6 MHz IMO cycle-to-cycle jitter (RMS) - - 0.7 6.7 ns 6 MHz IMO long term N cycle-to-cycle jitter (RMS); N = 32 - - 4.3 29.3 ns 6 MHz IMO period jitter (RMS) - - 0.7 3.3 ns 12 MHz IMO cycle-to-cycle jitter (RMS) - - 0.5 5.2 ns 12 MHz IMO long term N cycle-to-cycle jitter (RMS); N = 32 - - 2.3 5.6 ns 12 MHz IMO period jitter (RMS) - - 0.4 2.6 ns 24 MHz IMO cycle-to-cycle jitter (RMS) - - 1.0 8.7 ns 24 MHz IMO long term N cycle-to-cycle jitter (RMS); N = 32 - - 1.4 6.0 ns 24 MHz IMO period jitter (RMS) - - 0.6 4.0 ns Note 38. The minimum required XRES pulse length is longer when programming the device (see Table 55 on page 42). 39. See the Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products - AN5054 for more information. Document Number: 001-86894 Rev. *B Page 25 of 65 CY8C24X93 AC General Purpose I/O Specifications (CY8C24193/493) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 26. AC GPIO Specifications Symbol FGPIO Description GPIO operating frequency Conditions Normal strong mode Port 0, 1 Min 0 0 tRISE23 tRISE23L tRISE01 tRISE01L tFALL tFALLL Rise time, strong mode, Cload = 50 pF Ports 2 or 3 Rise time, strong mode low supply, Cload = 50 pF, Ports 2 or 3 Rise time, strong mode, Cload = 50 pF Ports 0 or 1 Rise time, strong mode low supply, Cload = 50 pF, Ports 0 or 1 Fall time, strong mode, Cload = 50 pF all ports Fall time, strong mode low supply, Cload = 50 pF, all ports Typ Max Units - 6 MHz for MHz 1.71 V <VDD < 2.40 V - 12 MHz for MHz 2.40 V < VDD< 5.50 V - 80 ns VDD = 3.0 to 3.6 V, 10% to 90% 15 VDD = 1.71 to 3.0 V, 10% to 90% 15 - 80 ns VDD = 3.0 to 3.6 V, 10% to 90% LDO enabled or disabled VDD = 1.71 to 3.0 V, 10% to 90% LDO enabled or disabled VDD = 3.0 to 3.6 V, 10% to 90% 10 - 50 ns 10 - 80 ns 10 - 50 ns VDD = 1.71 to 3.0 V, 10% to 90% 10 - 70 ns Figure 8. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRise23 TRise01 TRise23L TRise01L TFall TFallL AC Comparator Specifications (CY8C24193/493) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 27. AC Low Power Comparator Specifications Symbol tLPC Description Comparator response time, 50 mV overdrive Conditions 50 mV overdrive does not include offset voltage. Min Typ Max Units - - 100 ns AC External Clock Specifications (CY8C24193/493) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 28. AC External Clock Specifications Symbol FOSCEXT Description Frequency (external oscillator frequency) Conditions - Min Typ Max Units 0.75 - 25.20 MHz High period - 20.60 - 5300 ns Low period - 20.60 - - ns Power-up IMO to switch - 150 - - s Document Number: 001-86894 Rev. *B Page 26 of 65 CY8C24X93 AC Programming Specifications (CY8C24193/493) Figure 9. AC Waveform SCLK (P1[1]) T FSCLK T RSCLK SDATA (P1[0]) TSSCLK T HSCLK TDSCLK The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 29. AC Programming Specifications Symbol tRSCLK tFSCLK tSSCLK tHSCLK FSCLK tERASEB tWRITE tDSCLK tDSCLK3 tDSCLK2 tXRST3 Description Rise time of SCLK Fall time of SCLK Data setup time to falling edge of SCLK Data hold time from falling edge of SCLK Frequency of SCLK Flash erase time (block) Flash block write time Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK External reset pulse width after power-up tXRES tVDDWAIT tVDDXRES tPOLL tACQ XRES pulse length VDD stable to wait-and-poll hold off VDD stable to XRES assertion delay SDAT high pulse time "Key window" time after a VDD ramp acquire event, based on 256 ILO clocks. "Key window" time after an XRES event, based on 8 ILO clocks tXRESINI Document Number: 001-86894 Rev. *B Conditions - - - - - - - 3.6 VDD 3.0 VDD 3.6 1.71 VDD 3.0 Required to enter programming mode when coming out of sleep - - - - - - Min 1 1 40 40 0 - - - - - 300 Typ - - - - - - - - - - - Max 20 20 - - 8 18 25 60 85 130 - Units ns ns ns ns MHz ms ms ns ns ns s 300 0.1 14.27 0.01 3.20 - - - - - - 1 - 200 19.60 s ms ms ms ms 98 - 615 s Page 27 of 65 CY8C24X93 AC I2C Specifications (CY8C24193/493) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 30. AC Characteristics of the I2C SDA and SCL Pins Symbol Description fSCL tHD;STA SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated tLOW LOW period of the SCL clock HIGH Period of the SCL clock tHIGH Setup time for a repeated START condition tSU;STA tHD;DAT[40] Data hold time Data setup time tSU;DAT Setup time for STOP condition tSU;STO tBUF Bus free time between a STOP and START condition Pulse width of spikes are suppressed by the input filter tSP Standard Mode Min Max 0 100 4.0 - 4.7 4.0 4.7 20 250 4.0 4.7 - - - - 3.45 - - - - Fast Mode Min 0 0.6 Max 400 - 1.3 - 0.6 - 0.6 - 20 0.90 100[53] - 0.6 - 1.3 - 0 50 Units kHz s s s s s ns s s ns Figure 10. Definition for Timing for Fast/Standard Mode on the I2C Bus Notes 40. To wake up from sleep using I2C hardware address match event, I2C interface needs 20 ns hold time on SDA line with respect to falling edge of SCL. See the CY8C24x93 Silicon Errata document for more details. 41. A Fast-Mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-86894 Rev. *B Page 28 of 65 CY8C24X93 Table 31. SPI Master AC Specifications Min Typ Max Units FSCLK Symbol SCLK clock frequency Description VDD 2.4 V VDD < 2.4 V Conditions - - - - 6 3 MHz MHz DC SCLK duty cycle - - 50 - % tSETUP MISO to SCLK setup time VDD 2.4 V VDD < 2.4 V 60 100 - - - - ns ns tHOLD SCLK to MISO hold time - 40 - - ns tOUT_VAL SCLK to MOSI valid time - - - 40 ns tOUT_H MOSI high time - 40 - - ns Figure 11. SPI Master Mode 0 and 2 SPI Master, modes 0 and 2 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TSETUP MISO (input) THOLD LSB MSB TOUT_SU TOUT_H MOSI (output) Figure 12. SPI Master Mode 1 and 3 SPI Master, modes 1 and 3 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TSETUP MISO (input) THOLD TOUT_SU MOSI (output) Document Number: 001-86894 Rev. *B LSB MSB TOUT_H MSB LSB Page 29 of 65 CY8C24X93 Table 32. SPI Slave AC Specifications Symbol FSCLK tLOW tHIGH tSETUP tHOLD tSS_MISO tSCLK_MISO tSS_HIGH tSS_CLK tCLK_SS Description SCLK clock frequency SCLK low time SCLK high time MOSI to SCLK setup time SCLK to MOSI hold time SS high to MISO valid SCLK to MISO valid SS high time Time from SS low to first SCLK Time from last SCLK to SS high Conditions Min - 42 42 30 50 - - 50 2/SCLK 2/SCLK - - - - - - - - - - Typ - - - - - - - - - - Max 4 - - - - 153 125 - - - Units MHz ns ns ns ns ns ns ns ns ns Figure 13. SPI Slave Mode 0 and 2 SPI Slave, modes 0 and 2 TSS_HIGH TCLK_SS TSS_CLK /SS 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TOUT_H TSS_MISO MISO (output) TSETUP MOSI (input) THOLD LSB MSB Figure 14. SPI Slave Mode 1 and 3 SPI Slave, modes 1 and 3 TSS_CLK TCLK_SS /SS 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TOUT_H TSCLK_MISO TSS_MISO MISO (output) MSB TSETUP MOSI (input) Document Number: 001-86894 Rev. *B LSB THOLD MSB LSB Page 30 of 65 CY8C24X93 Electrical Specifications (CY8C24093/293/393/693) This section presents the DC and AC electrical specifications of the CY8C24093/293/393/693 PSoC devices. For the latest electrical specifications, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc. Figure 15. Voltage versus CPU Frequency 5.5V Vdd Voltage li d ng Va rati n e io Op Reg 1.71V 750 kHz 3 MHz CPU 24 MHz Frequency Absolute Maximum Ratings (CY8C24093/293/393/693) Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 33. Absolute Maximum Ratings Conditions Min Typ Max Units TSTG Symbol Storage temperature Description Higher storage temperatures reduce data retention time. Recommended Storage Temperature is +25 C 25 C. Extended duration storage temperatures above 85 C degrades reliability. -55 +25 +125 C VDD Supply voltage relative to VSS - -0.5 - +6.0 V VIO DC input voltage - VSS - 0.5 - VDD + 0.5 V VIOZ[42] DC voltage applied to tristate - VSS - 0.5 - VDD + 0.5 V IMIO Maximum current into any port pin - -25 - +50 mA ESD Electrostatic discharge voltage Human body model ESD 2000 - - V LU Latch-up current In accordance with JESD78 standard - - 200 mA Operating Temperature (CY8C24093/293/393/693) Table 34. Operating Temperature Min Typ Max Units TA Symbol Ambient temperature Description - Conditions -40 - +85 C TC Commercial temperature range - 0 70 C TJ Operational die temperature The temperature rise from ambient to junction is package specific. Refer the Thermal Impedances on page 49. The user must limit the power consumption to comply with this requirement. +100 C -40 - Note 42. Port1 pins are hot-swap capable with I/O configured in High-Z mode, and pin input voltage above VDD. Document Number: 001-86894 Rev. *B Page 31 of 65 CY8C24X93 DC Chip-Level Specifications (CY8C24093/293/393/693) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 35. DC Chip-Level Specifications Symbol VDD [43, 44, 45] VDDUSB[43, 44, 45] Description Conditions Min Typ Max Units Supply voltage No USB activity. Refer the table DC POR and LVD Specifications (CY8C24093/293/393/693) on page 37 1.71 - 5.50 V Operating voltage USB activity, USB regulator enabled 4.35 - 5.25 V USB activity, USB regulator bypassed 3.15 3.3 3.60 V IDD24 Supply current, IMO = 24 MHz Conditions are VDD 3.0 V, TA = 25 C, CPU = 24 MHz. No I/O sourcing current - - 4.00 mA IDD12 Supply current, IMO = 12 MHz Conditions are VDD 3.0 V, TA = 25 C, CPU = 12 MHz. No I/O sourcing current - - 2.60 mA IDD6 Supply current, IMO = 6 MHz Conditions are VDD 3.0 V, TA = 25 C, CPU = 6 MHz. No I/O sourcing current - - 1.80 mA ISB0 Deep sleep current VDD 3.0 V, TA = 25 C, I/O regulator turned off - 0.10 1.05 A ISB1 Standby current with POR, LVD VDD 3.0 V, TA = 25 C, I/O regulator and sleep timer turned off - 1.07 1.50 A ISBI2C Standby current with I2C enabled - 1.64 - A Conditions are VDD = 3.3 V, TA = 25 C and CPU = 24 MHz Notes 43. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 s, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be slower than 1 V/500 s to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter. 44. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken: a.Bring the device out of sleep before powering down. b.Assure that VDD falls below 100 mV before powering back up. c.Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep. d.Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register. For the referenced registers, refer to the CY8C24x93 Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows VDD brown out conditions to be detected for edge rates slower than 1V/ms. 45. For USB mode, the VDD supply for bus-powered application should be limited to 4.35 V-5.35 V. For self-powered application, VDD should be 3.15 V-3.45 V. Document Number: 001-86894 Rev. *B Page 32 of 65 CY8C24X93 DC GPIO Specifications (CY8C24093/293/393/693) The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and -40 C TA 85 C, 2.4 V to 3.0 V and -40 C TA 85 C, or 1.71 V to 2.4 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 36. 3.0 V to 5.5 V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units RPU Pull-up resistor - 4 5.60 8 k VOH1 High output voltage Port 2 or 3 or 4 pins IOH < 10 A, maximum of 10 mA source current in all I/Os VDD - 0.20 - - V VOH2 High output voltage Port 2 or 3 or 4 pins IOH = 1 mA, maximum of 20 mA source current in all I/Os VDD - 0.90 - - V VOH3 High output voltage Port 0 or 1 pins with LDO regulator Disabled for port 1 IOH < 10 A, maximum of 10 mA source current in all I/Os VDD - 0.20 - - V VOH4 High output voltage Port 0 or 1 pins with LDO regulator Disabled for port 1 IOH = 5 mA, maximum of 20 mA source current in all I/Os VDD - 0.90 - - V VOH5 High output voltage IOH < 10 A, VDD > 3.1 V, maximum of 4 I/Os Port 1 Pins with LDO Regulator Enabled all sourcing 5 mA for 3 V out 2.85 3.00 3.30 V VOH6 High output voltage IOH = 5 mA, VDD > 3.1 V, maximum of 20 mA Port 1 pins with LDO regulator enabled for source current in all I/Os 3 V out 2.20 - - V VOH7 High output voltage IOH < 10 A, VDD > 2.7 V, maximum of 20 mA Port 1 pins with LDO enabled for 2.5 V out source current in all I/Os 2.35 2.50 2.75 V VOH8 High output voltage IOH = 2 mA, VDD > 2.7 V, maximum of 20 mA Port 1 pins with LDO enabled for 2.5 V out source current in all I/Os 1.90 - - V VOH9 High output voltage IOH < 10 A, VDD > 2.7 V, maximum of 20 mA Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os 1.60 1.80 2.10 V VOH10 High output voltage IOH = 1 mA, VDD > 2.7 V, maximum of 20 mA Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os 1.20 - - V VOL Low output voltage IOL = 25 mA, VDD > 3.3 V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]) - - 0.75 V VIL Input low voltage - - - 0.80 V VIH Input high voltage - 2.00 - - V VH Input hysteresis voltage - - 80 - mV IIL Input leakage (Absolute Value) - - 0.001 1 A CPIN Pin capacitance Package and pin dependent Temp = 25 C 0.50 1.70 7 pF VILLVT3.3 Input Low Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 0.8 V - - VIHLVT3.3 Input High Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 1.4 - - V VILLVT5.5 Input Low Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 0.8 V - - VIHLVT5.5 Input High Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 1.7 - - V Document Number: 001-86894 Rev. *B Page 33 of 65 CY8C24X93 Table 37. 2.4 V to 3.0 V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units 4 5.60 8 k IOH < 10 A, maximum of 10 mA source current in all I/Os VDD - 0.20 - - V High output voltage Port 2 or 3 or 4 pins IOH = 0.2 mA, maximum of 10 mA source current in all I/Os VDD - 0.40 - - V VOH3 High output voltage Port 0 or 1 pins with LDO regulator Disabled for port 1 IOH < 10 A, maximum of 10 mA source current in all I/Os VDD - 0.20 - - V VOH4 High output voltage Port 0 or 1 pins with LDO regulator Disabled for Port 1 IOH = 2 mA, maximum of 10 mA source current in all I/Os VDD - 0.50 - - V VOH5A High output voltage IOH < 10 A, VDD > 2.4 V, maximum of Port 1 pins with LDO enabled for 1.8 V out 20 mA source current in all I/Os 1.50 1.80 2.10 V VOH6A High output voltage IOH = 1 mA, VDD > 2.4 V, maximum of 20 mA Port 1 pins with LDO enabled for 1.8 V out source current in all I/Os 1.20 - - V VOL Low output voltage - - 0.75 V VIL Input low voltage - - - 0.72 VIH Input high voltage - 1.40 - VH Input hysteresis voltage - - 80 - mV IIL Input leakage (absolute value) - - 1 1000 nA CPIN Capacitive load on pins Package and pin dependent Temp = 25 C 0.50 1.70 7 pF VILLVT2.5 Input Low Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 0.7 V - VIHLVT2.5 Input High Voltage with low threshold enable set, Enable for Port1 Bit3 of IO_CFG1 set to enable low threshold voltage of Port1 input 1.2 RPU Pull-up resistor - VOH1 High output voltage Port 2 or 3 or 4 pins VOH2 IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) V V - V Table 38. 1.71 V to 2.4 V DC GPIO Specifications Symbol Description Conditions Min Typ Max Units 4 RPU Pull-up resistor - 5.60 8 k VOH1 High output voltage Port 2 or 3 or 4 pins IOH = 10 A, maximum of 10 mA VDD - 0.20 source current in all I/Os - - V VOH2 High output voltage Port 2 or 3 or 4 pins IOH = 0.5 mA, maximum of 10 mA VDD - 0.50 source current in all I/Os - - V VOH3 High output voltage Port 0 or 1 pins with LDO regulator Disabled for Port 1 IOH = 100 A, maximum of 10 mA VDD - 0.20 source current in all I/Os - - V VOH4 High output voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 IOH = 2 mA, maximum of 10 mA source VDD - 0.50 current in all I/Os - - V VOL Low output voltage IOL = 5 mA, maximum of 20 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) - 0.40 V Document Number: 001-86894 Rev. *B - Page 34 of 65 CY8C24X93 Table 38. 1.71 V to 2.4 V DC GPIO Specifications (continued) Symbol Description Conditions Min Typ Max Units VIL Input low voltage - - - 0.30 x VDD V VIH Input high voltage - 0.65 x VDD - - V VH Input hysteresis voltage - - 80 - mV IIL Input leakage (absolute value) - - 1 1000 nA CPIN Capacitive load on pins Package and pin dependent temp = 25 C 0.50 1.70 7 pF Min Typ Max Units Table 39. DC Characteristics - USB Interface Symbol Description Conditions RUSBI USB D+ pull-up resistance With idle bus 900 - 1575 RUSBA USB D+ pull-up resistance While receiving traffic 1425 - 3090 VOHUSB Static output high - 2.8 - 3.6 V VOLUSB Static output low - - - 0.3 V VDI Differential input sensitivity - 0.2 - VCM Differential input common mode range - 0.8 - 2.5 V VSE Single ended receiver threshold - 0.8 - 2.0 V CIN Transceiver capacitance - - - 50 pF V IIO High Z state data line leakage On D+ or D- line -10 - +10 A RPS2 PS/2 pull-up resistance - 3000 5000 7000 REXT External USB series resistor In series with each USB pin 21.78 22.0 22.22 DC Analog Mux Bus Specifications (CY8C24093/293/393/693) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 40. DC Analog Mux Bus Specifications Symbol RSW Description Conditions Switch resistance to common analog bus - RGND Resistance of initialization switch to VSS The maximum pin voltage for measuring RSW and RGND is 1.8 V - Min Typ Max Units - - 800 - - 800 DC Low Power Comparator Specifications (CY8C24093/293/393/693) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 41. DC Comparator Specifications Conditions Min Typ Max Units VLPC Symbol Low power comparator (LPC) common mode Description Maximum voltage limited to VDD 0.0 - 1.8 V ILPC LPC supply current - - 10 40 A VOSLPC LPC voltage offset - - 3 30 mV Document Number: 001-86894 Rev. *B Page 35 of 65 CY8C24X93 Comparator User Module Electrical Specifications (CY8C24093/293/393/693) The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: -40 C TA 85 C, 1.71 V VDD 5.5 V. Table 42. Comparator User Module Electrical Specifications Symbol Min Typ Max Units 50 mV overdrive - 70 100 ns Offset Valid from 0.2 V to VDD - 0.2 V - 2.5 30 mV Current Average DC current, 50 mV overdrive - 20 80 A Supply voltage > 2 V Power supply rejection ratio - 80 - dB Supply voltage < 2 V Power supply rejection ratio - 40 - dB - 0 1.5 V tCOMP PSRR Description Comparator response time Input range Conditions ADC Electrical Specifications (CY8C24093/293/393/693) Table 43. ADC User Module Electrical Specifications Symbol Description Conditions Min Typ Max Units 0 - VREFADC V - - 5 pF Input VIN Input voltage range CIIN Input capacitance - RIN Input resistance Equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution ADC reference voltage - 1.14 - 1.26 V 2.25 - 6 MHz - 1/(500fF x 1/(400fF x 1/(300fF x data clock) data clock) data clock) Reference VREFADC Conversion Rate FCLK Data clock Source is chip's internal main oscillator. See AC Chip-Level Specifications for accuracy S8 8-bit sample rate Data clock set to 6 MHz. sample rate = 0.001/ (2^Resolution/Data Clock) - 23.43 - ksps S10 10-bit sample rate Data clock set to 6 MHz. sample rate = 0.001/ (2^resolution/data clock) - 5.85 - ksps RES Resolution Can be set to 8-, 9-, or 10-bit 8 - 10 bits DC Accuracy DNL Differential nonlinearity - -1 - +2 LSB INL Integral nonlinearity - -2 - +2 LSB EOFFSET Offset error 8-bit resolution 0 3.20 19.20 LSB 10-bit resolution 0 12.80 76.80 LSB Gain error For any resolution -5 - +5 %FSR IADC Operating current - - 2.10 2.60 mA PSRR Power supply rejection ratio PSRR (VDD > 3.0 V) - 24 - dB PSRR (VDD < 3.0 V) - 30 - dB EGAIN Power Document Number: 001-86894 Rev. *B Page 36 of 65 CY8C24X93 DC POR and LVD Specifications (CY8C24093/293/393/693) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 44. DC POR and LVD Specifications Symbol Description Conditions Min VPOR0 1.66 V selected in PSoC Designer 2.36 V selected in PSoC Designer - VPOR2 2.60 V selected in PSoC Designer VDD must be greater than or equal to 1.71 V during startup, reset from the XRES pin, or reset from watchdog. 1.61 VPOR1 - 2.60 2.66 VPOR3 2.82 V selected in PSoC Designer - 2.82 2.95 VLVD0 2.45 V selected in PSoC Designer 2.40 2.45 2.51 VLVD1 2.71 V selected in PSoC Designer 2.64[46] 2.71 2.78 VLVD2 2.92 V selected in PSoC Designer 2.85[47] 2.92 2.99 VLVD3 3.02 V selected in PSoC Designer 2.95[48] 3.02 3.09 VLVD4 3.13 V selected in PSoC Designer 3.06 3.13 3.20 VLVD5 1.90 V selected in PSoC Designer 1.84 1.90 2.32 VLVD6 1.80 V selected in PSoC Designer 1.75[49] 1.80 1.84 VLVD7 4.73 V selected in PSoC Designer 4.62 4.73 4.83 - Typ Max Units 1.66 1.71 V 2.36 2.41 V DC Programming Specifications (CY8C24093/293/393/693) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 45. DC Programming Specifications Symbol VDDIWRITE IDDP VILP VIHP IILP IIHP VOLP VOHP FlashENPB FlashDR Description Supply voltage for flash write operations Supply current during programming or verify Input low voltage during programming or verify - Conditions Min 1.71 Typ - Max 5.25 Units V - - 5 25 mA - - VIL V VIH - - V - - 0.2 mA - - 1.5 mA - - VSS + 0.75 V VOH - VDD V 50,000 20 - - - - - Years See the appropriate DC GPIO Specifications (CY8C24093/293/393/693) on page 33 Input high voltage during See the appropriate DC GPIO programming or verify Specifications (CY8C24093/293/393/693) on page 33 Input current when Applying VILP Driving internal pull-down resistor to P1[0] or P1[1] during programming or verify Input current when applying VIHP Driving internal pull-down resistor to P1[0] or P1[1] during programming or verify Output low voltage during programming or verify Output high voltage during See appropriate DC GPIO Specifications programming or verify (CY8C24093/293/393/693) on page 33. For VDD > 3 V use VOH4 in Table 34 on page 31. Flash write endurance Erase/write cycles per block Flash data retention Following maximum Flash write cycles; ambient temperature of 55 C Notes 46. Always greater than 50 mV above VPPOR1 voltage for falling supply. 47. Always greater than 50 mV above VPPOR2 voltage for falling supply. 48. Always greater than 50 mV above VPPOR3 voltage for falling supply. 49. Always greater than 50 mV above VPPOR0 voltage for falling supply. Document Number: 001-86894 Rev. *B Page 37 of 65 CY8C24X93 DC I2C Specifications (CY8C24093/293/393/693) The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and -40 C TA 85 C, 2.4 V to 3.0 V and -40 C TA 85 C, or 1.71 V to 2.4 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 46. DC I2C Specifications Symbol VILI2C VIHI2C Description Input low level Input high level Conditions 3.1 V VDD 5.5 V Min - Typ - Max Units 0.25 x VDD V 2.5 V VDD 3.0 V - - 0.3 x VDD V 1.71 V VDD 2.4 V - - 0.3 x VDD V 1.71 V VDD 5.5 V 0.65 x VDD - - V DC Reference Buffer Specifications (CY8C24093/293/393/693) The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and -40 C TA 85 C, 2.4 V to 3.0 V and -40 C TA 85 C, or 1.71 V to 2.4 V and -40 C TA 85 C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 C and are for design guidance only. Table 47. DC Reference Buffer Specifications Symbol VRef Description Reference buffer output Conditions 1.7 V VDD 5.5 V Min 1 Typ - Max 1.05 Units V VRefHi Reference buffer output 1.7 V VDD 5.5 V 1.2 - 1.25 V DC IDAC Specifications (CY8C24093/293/393/693) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 48. DC IDAC Specifications Symbol IDAC_DNL IDAC_INL IDAC_Gain (Source) Description Differential nonlinearity Integral nonlinearity Range = 0.5x Range = 1x Range = 2x Range = 4x Range = 8x Document Number: 001-86894 Rev. *B Min -4.5 -5 6.64 14.5 42.7 91.1 184.5 Typ - - - - - - - Max +4.5 +5 22.46 47.8 92.3 170 426.9 Units Notes LSB LSB A DAC setting = 128 dec A A A DAC setting = 128 dec A DAC setting = 128 dec Page 38 of 65 CY8C24X93 AC Chip-Level Specifications (CY8C24093/293/393/693) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 49. AC Chip-Level Specifications Min Typ Max Units FIMO24 Symbol IMO frequency at 24 MHz Setting - 22.8 24 25.2 MHz FIMO12 IMO frequency at 12 MHz setting - 11.4 12 12.6 MHz FIMO6 IMO frequency at 6 MHz setting - 5.7 6.0 6.3 MHz FCPU CPU frequency - 0.75 - 25.20 MHz F32K1 ILO frequency - 15 32 50 kHz F32K_U ILO untrimmed frequency - 13 32 82 kHz DCIMO Duty cycle of IMO - 40 50 60 % DCILO ILO duty cycle - 40 50 60 % SRPOWER_UP Power supply slew rate VDD slew rate during power-up - - 250 V/ms tXRST External reset pulse width at power-up After supply voltage is valid 1 - - ms tXRST2 External reset pulse width after power-up[50] Applies after part has booted 10 - - s Startup time of ECO - - 1 - s N=32 6 MHz IMO cycle-to-cycle jitter (RMS) - 0.7 6.7 ns 6 MHz IMO long term N (N = 32) cycle-to-cycle jitter (RMS) - 4.3 29.3 ns 6 MHz IMO period jitter (RMS) - 0.7 3.3 ns 12 MHz IMO cycle-to-cycle jitter (RMS) - 0.5 5.2 ns 12 MHz IMO long term N (N = 32) cycle-to-cycle jitter (RMS) - 2.3 5.6 ns tOS tJIT_IMO [51] Description Conditions 12 MHz IMO period jitter (RMS) - 0.4 2.6 ns 24 MHz IMO cycle-to-cycle jitter (RMS) - 1.0 8.7 ns 24 MHz IMO long term N (N = 32) cycle-to-cycle jitter (RMS) - 1.4 6.0 ns 24 MHz IMO period jitter (RMS) - 0.6 4.0 ns Notes 50. The minimum required XRES pulse length is longer when programming the device (see Table 55 on page 42). 51. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products - AN5054 for more information. Document Number: 001-86894 Rev. *B Page 39 of 65 CY8C24X93 AC GPIO Specifications (CY8C24093/293/393/693) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 50. AC GPIO Specifications Symbol FGPIO tRISE23 tRISE23L tRISE01 tRISE01L tFALL tFALLL Description GPIO operating frequency Conditions Normal strong mode Port 0, 1 Rise time, strong mode, Cload = 50 pF Port 2 or 3 or 4 pins Rise time, strong mode low supply, Cload = 50 pF, Port 2 or 3 or 4 pins Rise time, strong mode, Cload = 50 pF Ports 0 or 1 Rise time, strong mode low supply, Cload = 50 pF, Ports 0 or 1 Fall time, strong mode, Cload = 50 pF all ports Fall time, strong mode low supply, Cload = 50 pF, all ports Min 0 Typ - Max Units 6 MHz for MHz 1.71 V <VDD < 2.40 V MHz 12 MHz for 2.40 V < VDD< 5.50 V 80 ns 0 - VDD = 3.0 to 3.6 V, 10% to 90% 15 - VDD = 1.71 to 3.0 V, 10% to 90% 15 - 80 ns VDD = 3.0 to 3.6 V, 10% to 90% LDO enabled or disabled VDD = 1.71 to 3.0 V, 10% to 90% LDO enabled or disabled VDD = 3.0 to 3.6 V, 10% to 90% 10 - 50 ns 10 - 80 ns 10 - 50 ns VDD = 1.71 to 3.0 V, 10% to 90% 10 - 70 ns Figure 16. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% tRISE23 tRISE01 tRISE23L tRISE01L Document Number: 001-86894 Rev. *B tFALL tFALLL Page 40 of 65 CY8C24X93 Table 51. AC Characteristics - USB Data Timings Min Typ tDRATE Symbol Full speed data rate Description Average bit rate Conditions 12 - 0.25% 12 Max Units tJR1 Receiver jitter tolerance To next transition -18.5 - 18.5 ns tJR2 Receiver jitter tolerance To pair transition -9.0 - 9 ns tDJ1 FS Driver jitter To next transition -3.5 - 3.5 ns tDJ2 FS Driver jitter To pair transition -4.0 - 4.0 ns tFDEOP Source jitter for differential transition To SE0 transition -2.0 - 5 ns 12 + 0.25% MHz tFEOPT Source SE0 interval of EOP - 160.0 - 175 ns tFEOPR Receiver SE0 interval of EOP - 82.0 - - ns tFST Width of SE0 interval during differential transition - - - 14 ns Min Typ Max Units Table 52. AC Characteristics - USB Driver Symbol Description Conditions tFR Transition rise time 50 pF 4 - 20 ns tFF Transition fall time 50 pF 4 - 20 ns tFRFM[52] Rise/fall time matching - 90 - 111 % VCRS Output signal crossover voltage - 1.30 - 2.00 V AC Comparator Specifications (CY8C24093/293/393/693) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 53. AC Low Power Comparator Specifications Symbol tLPC Description Comparator response time, 50 mV overdrive Conditions 50 mV overdrive does not include offset voltage. Min Typ Max Units - - 100 ns AC External Clock Specifications (CY8C24093/293/393/693) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 54. AC External Clock Specifications Symbol FOSCEXT Description Frequency (external oscillator frequency) Conditions - Min Typ Max Units 0.75 - 25.20 MHz High period - 20.60 - 5300 ns Low period - 20.60 - - ns Power-up IMO to switch - 150 - - s Note 52. TFRFM is not met under all conditions. There is a corner case at lower supply voltages, such as those under 3.3 V. This condition does not affect USB communications. Signal integrity tests show an excellent eye diagram at 3.15 V. Document Number: 001-86894 Rev. *B Page 41 of 65 CY8C24X93 AC Programming Specifications (CY8C24093/293/393/693) Figure 17. AC Waveform SCLK (P1[1]) T FSCLK T RSCLK SDATA (P1[0]) TSSCLK T HSCLK TDSCLK The following table lists the guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 55. AC Programming Specifications Symbol tRSCLK tFSCLK tSSCLK tHSCLK FSCLK tERASEB tWRITE tDSCLK tDSCLK3 tDSCLK2 tXRST3 Description Rise time of SCLK Fall time of SCLK Data setup time to falling edge of SCLK Data hold time from falling edge of SCLK Frequency of SCLK Flash erase time (block) Flash block write time Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK External reset pulse width after power-up Conditions - - - - - - - 3.6 VDD 3.0 VDD 3.6 1.71 VDD 3.0 Required to enter programming mode when coming out of sleep tXRES tVDDWAIT tVDDXRES tPOLL tACQ XRES pulse length VDD stable to wait-and-poll hold off VDD stable to XRES assertion delay SDATA high pulse time "Key window" time after a VDD ramp acquire event, based on 256 ILO clocks. tXRESINI "Key window" time after an XRES event, based on 8 ILO clocks Document Number: 001-86894 Rev. *B Min 1 1 40 40 0 - - - - - 300 Typ - - - - - - - - - - - Max 20 20 - - 8 18 25 60 85 130 - Units ns ns ns ns MHz ms ms ns ns ns s - - - - - 300 0.1 14.27 0.01 3.20 - - - - - - 1 - 200 19.60 s ms ms ms ms - 98 - 615 s Page 42 of 65 CY8C24X93 AC I2C Specifications (CY8C24093/293/393/693) The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 56. AC Characteristics of the I2C SDA and SCL Pins Symbol fSCL tHD;STA tLOW tHIGH tSU;STA tHD;DAT tSU;DAT tSU;STO tBUF tSP Description SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH Period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Bus free time between a STOP and START condition Pulse width of spikes are suppressed by the input filter Standard Mode Min Max 0 100 4.0 - 4.7 4.0 4.7 0 250 4.0 4.7 - - - - 3.45 - - - - Fast Mode Min Max 0 400 0.6 - 1.3 0.6 0.6 0 100[53] 0.6 1.3 0 - - - 0.90 - - - 50 Units kHz s s s s s ns s s ns Figure 18. Definition for Timing for Fast/Standard Mode on the I2C Bus Note 53. A Fast-Mode I2C-bus device can be used in a standard mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-86894 Rev. *B Page 43 of 65 CY8C24X93 Table 57. SPI Master AC Specifications Min Typ Max Units FSCLK Symbol SCLK clock frequency Description VDD 2.4 V VDD < 2.4 V Conditions - - - - 6 3 MHz MHz DC SCLK duty cycle - - 50 - % tSETUP MISO to SCLK setup time VDD 2.4 V VDD < 2.4 V 60 100 - - - - ns ns tHOLD SCLK to MISO hold time - 40 - - ns tOUT_VAL SCLK to MOSI valid time - - - 40 ns tOUT_H MOSI high time - 40 - - ns Figure 19. SPI Master Mode 0 and 2 SPI Master, modes 0 and 2 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TSETUP MISO (input) THOLD LSB MSB TOUT_SU TOUT_H MOSI (output) Figure 20. SPI Master Mode 1 and 3 SPI Master, modes 1 and 3 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TSETUP MISO (input) THOLD TOUT_SU MOSI (output) Document Number: 001-86894 Rev. *B LSB MSB TOUT_H MSB LSB Page 44 of 65 CY8C24X93 Table 58. SPI Slave AC Specifications Symbol FSCLK tLOW tHIGH tSETUP tHOLD tSS_MISO tSCLK_MISO tSS_HIGH tSS_CLK tCLK_SS Description SCLK clock frequency SCLK low time SCLK high time MOSI to SCLK setup time SCLK to MOSI hold time SS high to MISO valid SCLK to MISO valid SS high time Time from SS low to first SCLK Time from last SCLK to SS high Conditions Min - 42 42 30 50 - - 50 2/SCLK 2/SCLK - - - - - - - - - - Typ - - - - - - - - - - Max 4 - - - - 153 125 - - - Units MHz ns ns ns ns ns ns ns ns ns Figure 21. SPI Slave Mode 0 and 2 SPI Slave, modes 0 and 2 TCLK_SS TSS_CLK TSS_HIGH /SS 1/FSCLK THIGH TLOW SCLK (mode 0) SCLK (mode 2) TOUT_H TSS_MISO MISO (output) TSETUP MOSI (input) THOLD LSB MSB Figure 22. SPI Slave Mode 1 and 3 SPI Slave, modes 1 and 3 TSS_CLK TCLK_SS /SS 1/FSCLK THIGH TLOW SCLK (mode 1) SCLK (mode 3) TOUT_H TSCLK_MISO TSS_MISO MISO (output) MSB TSETUP MOSI (input) Document Number: 001-86894 Rev. *B LSB THOLD MSB LSB Page 45 of 65 CY8C24X93 Packaging Information This section illustrates the packaging specifications for the CY8C24X93 PSoC device, along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. Figure 23. 32-pin QFN (5 x 5 x 0.55 mm) LQ32 3.5 x 3.5 E-Pad (Sawn) Package Outline, 001-42168 001-42168 *E Document Number: 001-86894 Rev. *B Page 46 of 65 CY8C24X93 Figure 24. 16-pin Chip On Lead (3 x 3 x 0.6 mm) LG16A/LD16A (Sawn) Package Outline, 001-09116 001-09116 *H Figure 25. 48-pin QFN (6 x 6 x 0.6 mm) LQ48A 4.6 x 4.6 E-Pad (Sawn) Package Outline, 001-57280 001-57280 *E Document Number: 001-86894 Rev. *B Page 47 of 65 CY8C24X93 Figure 26. 48-pin QFN (7 x 7 x 1.0 mm) LT48A 5.1 x 5.1 E-Pad (SAWN) Package Outline, 001-13191 001-13191 *G Important Notes For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Pinned vias for thermal conduction are not required for the low power PSoC device. Document Number: 001-86894 Rev. *B Page 48 of 65 CY8C24X93 Thermal Impedances Table 59. Thermal Impedances per Package Typical JA [54] Typical JC 16-pin QFN (No Center Pad) 33 C/W - 32-pin QFN [55] 20 C/W - 25.20 C/W 3.04 C/W 18 C/W - Package 48-pin QFN (6 x 6 x 0.6 mm) [55] 48-pin QFN (7 x 7 x 1.0 mm) [55] Capacitance on Crystal Pins Table 60. Typical Package Capacitance on Crystal Pins Package Package Capacitance 32-pin QFN 3.2 pF 48-pin QFN 3.3 pF Solder Reflow Specifications Table 61 shows the solder reflow temperature limits that must not be exceeded. Table 61. Solder Reflow Specifications Maximum Peak Temperature (TC) Maximum Time above TC - 5 C 16-pin QFN Package 260 C 30 seconds 32-pin QFN 260 C 30 seconds 48-pin QFN (6 x 6 x 0.6 mm) 260 C 30 seconds 48-pin QFN (7 x 7 x 1.0 mm) 260 C 30 seconds Notes 54. TJ = TA + Power x JA. 55. To achieve the thermal impedance specified for the QFN package, the center thermal pad must be soldered to the PCB ground plane. Document Number: 001-86894 Rev. *B Page 49 of 65 CY8C24X93 Development Tool Selection Software PSoC Designer supports the advance emulation features also. The kit includes: PSoC Designer Software CD ICE-Cube In-Circuit Emulator ICE Flex-Pod for CY8C29X66A Family Cat-5 Adapter Mini-Eval Programming Board 110 ~ 240 V Power Supply, Euro-Plug Adapter Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC Programmer is available free of charge at http://www.cypress.com. iMAGEcraft C Compiler (Registration Required) ISSP Cable USB 2.0 Cable and Blue Cat-5 Cable 2 CY8C29466A-24PXI 28-PDIP Chip Samples Development Kits All evaluation tools are sold at the Cypress Online Store. For more information on PSoC 1 kits, visit the link http://www.cypress.com/?rID=63754 PSoC DesignerTM At the core of the PSoC development software suite is PSoC Designer. Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for over half a decade. PSoC Designer is available free of charge at http://www.cypress.com. PSoC Programmer All development kits are sold at the Cypress Online Store. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. Document Number: 001-86894 Rev. *B Evaluation Tools Device Programmers All device programmers are purchased from the Cypress Online Store. Page 50 of 65 CY8C24X93 Ordering Information The following table lists the CY8C24X93 PSoC devices' key package features and ordering codes. Table 62. PSoC Device Key Features and Ordering Information Package Flash (Bytes) Ordering Code SRAM Digital Analog XRES USB (Bytes) I/O Pins Inputs [56] Pin ADC Supported by OCD 16-pin QFN (3 x 3 x 0.6 mm) CY8C24093-24LKXI 8K 1K 13 13 Yes No Yes No 32-pin QFN (5 x 5 x 0.6 mm) CY8C24193-24LQXI 8K 1K 28 28 Yes No Yes Yes 32-pin QFN (5 x 5 x 0.6 mm) CY8C24293-24LQXI 16 K 2K 28 28 Yes No Yes No 48-pin QFN (6 x 6 x 0.6 mm) CY8C24393-24LQXI 16 K 2K 34 34 Yes No Yes No 48-pin QFN (7 x 7 x 1.0 mm) CY8C24493-24LTXI 32 K 2K 36 36 Yes Yes Yes Yes 48-pin QFN (6 x 6 x 0.6 mm) CY8C24693-24LQXI 32 K 2K 34 34 Yes No Yes No 32 K 2K 36 36 Yes Yes Yes - 48-pin QFN (OCD) CY8C240093-24LTXI (7 x 7 x 1.0 mm) Ordering Code Definitions CY 8 C 24 X93 - 24 XX X I X X = blank or T blank = Tube; T = Tape and Reel Temperature range: I = Industrial Pb-free Package Type: LK = 16-pin QFN; LQ = 32-pin QFN or 48-pin QFN Speed Grade: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = PSoC Company ID: CY = Cypress Note 56. Dual-function Digital I/O Pins also connect to the common analog mux. Document Number: 001-86894 Rev. *B Page 51 of 65 CY8C24X93 Acronyms Table 63. Acronyms Used in this Document (continued) Table 63. Acronyms Used in this Document Acronym Description AC Alternating Current ADC Analog-to-Digital Converter API Application Programming Interface CMOS Complementary Metal Oxide Semiconductor CPU Central Processing Unit DAC Digital-to-Analog Converter DC Direct Current EOP End Of Packet FSR Full Scale Range GPIO General Purpose Input/Output GUI Graphical User Interface I2C Inter-Integrated Circuit ICE In-Circuit Emulator IDAC Digital Analog Converter Current ILO Internal Low Speed Oscillator IMO Internal Main Oscillator I/O Input/Output ISSP In-System Serial Programming LCD Liquid Crystal Display LDO Low Dropout (regulator) LSB Least-Significant Bit LVD Low Voltage Detect MCU Micro-Controller Unit MIPS Mega Instructions Per Second MISO Master In Slave Out MOSI Master Out Slave In MSB Most-Significant Bit OCD On-Chip Debugger POR Power On Reset PPOR precision power on reset PSRR Power Supply Rejection Ratio PWRSYS Power System PSoC(R) Programmable System-on-Chip SLIMO Slow Internal Main Oscillator SRAM Static Random Access Memory SNR Signal to Noise Ratio QFN Quad Flat No-lead SCL Serial I2C Clock SDA Serial I2C Data SDATA Serial ISSP Data SPI Serial Peripheral Interface Document Number: 001-86894 Rev. *B Acronym Description SS Slave Select SSOP Shrink Small Outline Package TC Test Controller USB Universal Serial Bus USB D+ USB Data+ USB D- USB Data- WLCSP Wafer Level Chip Scale Package XTAL Crystal Page 52 of 65 CY8C24X93 Document Conventions Reference Documents Units of Measure Technical reference manual for CY8C24x93 devices Table 64. Units of Measure In-system Serial Programming (ISSP) protocol for CY8C24x93 (AN2026C) Host Sourced Serial Programming for CY8C24x93 devices (AN59389) Symbol Unit of Measure C degree Celsius dB decibel fF femtofarad g gram Numeric Naming Hz hertz KB 1024 bytes Kbit 1024 bits KHz kilohertz Ksps kilo samples per second k kilohm Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase `h' (for example, `14h' or `3Ah'). Hexadecimal numbers may also be represented by a `0x' prefix, the C coding convention. Binary numbers have an appended lowercase `b' (for example, 01010100b' or `01000011b'). Numbers not indicated by an `h', `b', or 0x are decimal. MHz megahertz M megaohm A microampere F microfarad H microhenry s microsecond W microwatt mA milliampere ms millisecond mV millivolt nA nanoampere nF nanofarad ns nanosecond nV nanovolt W ohm pA picoampere pF picofarad pp peak-to-peak ppm parts per million ps picosecond sps samples per second s sigma: one standard deviation V volt W watt Document Number: 001-86894 Rev. *B Page 53 of 65 CY8C24X93 Glossary Crosspoint connection Connection between any GPIO combination via analog multiplexer bus. Differential non-linearity Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one LSB apart. Differential non-linearity is a measure of the worst case deviation from the ideal 1 LSB step. Hold time Hold time is the time following a clock event during which the data input to a latch or flip-flop must remain stable in order to guarantee that the latched data is correct. I2C It is a serial multi-master bus used to connect low speed peripherals to MCU. Integral nonlinearity It is a term describing the maximum deviation between the ideal output of a DAC/ADC and the actual output level. Latch-up current Current at which the latch-up test is conducted according to JESD78 standard (at 125 degree Celsius) Power supply rejection ratio (PSRR) The PSRR is defined as the ratio of the change in supply voltage to the corresponding change in output voltage of the device. Setup time Period required to prepare a device, machine, process, or system for it to be ready to function. SPI Serial peripheral interface is a synchronous serial data link standard. Document Number: 001-86894 Rev. *B Page 54 of 65 CY8C24X93 Appendix A: Silicon Errata for the CY8C24093/293/393/693 Family This section describes the errata for the CY8C24093/293/393/693 family. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. CY8C24093/293/393/693 Qualification Status Product Status: Production released. CY8C24093/293/393/693 Errata Summary The following Errata items apply to the CY8C24093/293/393/693 datasheet 001-86894. 1. DoubleTimer0 ISR Problem Definition When programmable timer 0 is used in "one-shot" mode by setting bit 1 of register 0,B0h (PT0_CFG), and the timer interrupt is used to wake the device from sleep, the interrupt service routine (ISR) may be executed twice. Parameters Affected No datasheet parameters are affected. Trigger Condition(S) Triggered by enabling one-shot mode in the timer, and using the timer to wake from sleep mode. Scope of Impact The ISR may be executed twice. Workaround In the ISR, firmware should clear the one-shot bit with a statement such as "and reg[B0h], FDh" Fix Status Will not be fixed Changes None Document Number: 001-86894 Rev. *B Page 55 of 65 CY8C24X93 2. Missed GPIO Interrupt Problem Definition When in sleep mode, if a GPIO interrupt happens simultaneously with a Timer0 or Sleep Timer interrupt, the GPIO interrupt may be missed, and the corresponding GPIO ISR not run. Parameters Affected No datasheet parameters are affected. Trigger Condition(S) Triggered by enabling sleep mode, then having GPIO interrupt occur simultaneously with a Timer 0 or Sleep Timer interrupt. Scope of Impact The GPIO interrupt service routine will not be run. Workaround The system should be architected such that a missed GPIO interrupt may be detected. For example, if a GPIO is used to wake the system to perform some function, the system should detect if the function is not performed, and re-issue the GPIO interrupt. Alternatively, if a GPIO interrupt is required to wake the system, then firmware should disable the Sleep Timer and Timer0. Alternatively, the ISR's for Sleep Timer and Timer0 should manually check the state of the GPIO to determine if the host system has attempted to generate a GPIO interrupt. Fix Status Will not be fixed Changes None 3. Missed Interrupt During Transition to Sleep Problem Definition If an interrupt is posted a short time (within 2.5 CPU cycles) before firmware commands the device to sleep, the interrupt will be missed. Parameters Affected No datasheet parameters are affected. Trigger Condition(S) Triggered by enabling sleep mode just prior to an interrupt. Scope of Impact The relevant interrupt service routine will not be run. Workaround None. Fix Status Will not be fixed Changes None Document Number: 001-86894 Rev. *B Page 56 of 65 CY8C24X93 4. Wakeup from sleep with analog interrupt Problem Definition Device wakes up from sleep when an analog interrupt is trigger Parameters Affected No datasheet parameters are affected. Trigger Condition(S) Triggered by enabling analog interrupt during sleep mode when device operating temperature is 50 C or above Scope of Impact Device unexpectedly wakes up from sleep Workaround Disable the analog interrupt before entering sleep and turn it back on upon wake-up. Fix Status Will not be fixed Changes None Document Number: 001-86894 Rev. *B Page 57 of 65 CY8C24X93 5. Wake-up from Sleep with Hardware I2C Address match on Pins P1[0], P1[1] Problem Definition I2C interface needs 20 ns hold time on SDA line with respect to falling edge of SCL, to wake-up from sleep using I2C hardware address match event. Parameters Affected tHD;DAT increased to 20 ns from 0 ns Trigger Condition(S) This is an issue only when all these three conditions are met: 1) P1.0 and P1.1 are used as I2C pins, 2) Wakeup from sleep with hardware address match feature is enabled, and 3) I2C master does not provide 20 ns hold time on SDA with respect to falling edge of SCL. Scope of Impact These trigger conditions cause the device to never wake-up from sleep based on I2C address match event Workaround For a design that meets all of the trigger conditions, the following suggested circuit has to be implemented as a work-around. The R and C values proposed are 100 ohm and 200 pF respectively. CY8C24093/ 293/393/693 Fix Status Will not be fixed Changes None Document Number: 001-86894 Rev. *B Page 58 of 65 CY8C24X93 6. I2C Port Pin Pull-up Supply Voltage Problem Definition Pull-up resistor on I2C interface cannot be connected to a supply voltage that is greater than 0.7 V of CY8C24093/293/393/693 VDD. Parameters Affected None. Trigger Condition(S) This problem occurs only when the I2C master is powered at a higher voltage than CY8C24093/293/393/693. Scope of Impact This trigger condition will corrupt the I2C communication between the I2C host and the CY8C24093/293/393/693 controller. Workaround I2C master cannot be powered at a supply voltage that is greater than 0.7 V compared to CY8C24093/293/393/693 supply voltage. Fix Status Will not be fixed Changes None 7. Port1 Pin Voltage Problem Definition Pull-up resistor on port1 pins cannot be connected to a voltage that is greater than 0.7 V higher than CY8C24093/293/393/693 VDD. Parameters Affected None. Trigger Condition(S) This problem occurs only when port1 pins are at voltage 0.7 V higher than VDD of CY8C24093/293/393/693. Scope of Impact This trigger condition will not allow CY8C24093/293/393/693 to drive the output signal on port1 pins, input path is unaffected by this condition. Workaround Port1 should not be connected to a higher voltage than VDD of CY8C24093/293/393/693. Fix Status Will not be fixed Changes None Document Number: 001-86894 Rev. *B Page 59 of 65 CY8C24X93 Appendix B: Silicon Errata for the PSoC(R) CY8C24193/493 Families This section describes the errata for the PSoC(R) CY8C24193/493 families. Details include errata trigger conditions, scope of impact, available workarounds, and silicon revision applicability. Contact your local Cypress Sales Representative if you have questions. CY8C24193/493 Qualification Status Product Status: Production released. CY8C24193/493 Errata Summary The following Errata items apply to the CY8C24193/493 datasheet 001-86894. 1. Wakeup from sleep may intermittently fail Problem Definition When the device is put to sleep in Standby or I2C_USB Mode and the bandgap circuit is refreshed less frequently than every 8 ms (default), the device may not come out of sleep when a sleep-ending input is received. Parameters Affected None Trigger Condition(S) By default, when the device is in the Standby or I2C_USB sleep modes, the bandgap circuit is powered-up approximately every 8 ms to facilitate detection of POR or LVD events. This interval can be lengthened or the periodic power-up disabled to reduce sleep current by setting the ALT_BUZZ bits in the SLP_CFG2 register or the Disable Buzz bit in the OSC_CR0 register respectively. If the bandgap circuit refresh interval is set longer than the default 8 ms, the device may fail to wakeup from sleep and enter a locked up state that can only be recovered by Watchdog Reset, XRES, or POR. Scope of Impact The trigger conditions outlined above may cause the device to never wakeup. Workaround Prior to entering Standby or I2C_USB sleep modes, do not lengthen or disable the bandgap refresh interval by manipulating the ALT_BUZZ bits in the SLP_CFG2 register or the Disable Buzz bit in the OSC_CR0 register respectively. Fix Status This issue will not be corrected in the next silicon revision. Document Number: 001-86894 Rev. *B Page 60 of 65 CY8C24X93 2. I2C Errors Problem Definition The I2C block exhibits occasional data and bus corruption errors when the I2C master initiates transactions while the device is transitioning in to or out of sleep mode. Parameters Affected Affects reliability of I2C communication to device, and between I2C master and third party I2C slaves. Trigger Condition(S) Triggered by transitions into and out of the device's sleep mode. Scope of Impact Data errors result in incorrect data reported to the I2C master, or incorrect data received from the master by the device. Bus corruption errors can corrupt data in transactions between the I2C master and third party I2C slaves. Workaround Firmware workarounds are available in firmware. Generally the workaround consists of disconnecting the I2C block from the bus prior to going to sleep modes. I2C transactions during sleep are supported by a protocol in which the master wakes the device prior to the I2C transaction. Fix Status To be fixed in future silicon. Changes None 3. DoubleTimer0 ISR Problem Definition When programmable timer 0 is used in "one-shot" mode by setting bit 1 of register 0,B0h (PT0_CFG), and the timer interrupt is used to wake the device from sleep, the interrupt service routine (ISR) may be executed twice. Parameters Affected No datasheet parameters are affected. Trigger Condition(S) Triggered by enabling one-shot mode in the timer, and using the timer to wake from sleep mode. Scope of Impact The ISR may be executed twice. Workaround In the ISR, firmware should clear the one-shot bit with a statement such as "and reg[B0h], FDh" Fix Status Will not be fixed Changes None Document Number: 001-86894 Rev. *B Page 61 of 65 CY8C24X93 4. Missed GPIO Interrupt Problem Definition When in sleep mode, if a GPIO interrupt happens simultaneously with a Timer0 or Sleep Timer interrupt, the GPIO interrupt may be missed, and the corresponding GPIO ISR not run. Parameters Affected No datasheet parameters are affected. Trigger Condition(S) Triggered by enabling sleep mode, then having GPIO interrupt occur simultaneously with a Timer 0 or Sleep Timer interrupt. Scope of Impact The GPIO interrupt service routine will not be run. Workaround The system should be architected such that a missed GPIO interrupt may be detected. For example, if a GPIO is used to wake the system to perform some function, the system should detect if the function is not performed, and re-issue the GPIO interrupt. Alternatively, if a GPIO interrupt is required to wake the system, then firmware should disable the Sleep Timer and Timer0. Alternatively, the ISR's for Sleep Timer and Timer0 should manually check the state of the GPIO to determine if the host system has attempted to generate a GPIO interrupt. Fix Status Will not be fixed Changes None 5. Missed Interrupt During Transition to Sleep Problem Definition If an interrupt is posted a short time (within 2.5 CPU cycles) before firmware commands the device to sleep, the interrupt will be missed. Parameters Affected No datasheet parameters are affected. Trigger Condition(S) Triggered by enabling sleep mode just prior to an interrupt. Scope of Impact The relevant interrupt service routine will not be run. Workaround None. Fix Status Will not be fixed Changes None Document Number: 001-86894 Rev. *B Page 62 of 65 CY8C24X93 6. Wakeup from sleep with analog interrupt Problem Definition Device wakes up from sleep when an analog interrupt is trigger Parameters Affected No datasheet parameters are affected. Trigger Condition(S) Triggered by enabling analog interrupt during sleep mode when device operating temperature is 50 C or above Scope of Impact Device unexpectedly wakes up from sleep Workaround Disable the analog interrupt before entering sleep and turn it back on upon wakeup. Fix Status Will not be fixed Changes None Document Number: 001-86894 Rev. *B Page 63 of 65 CY8C24X93 Document History Page Document Title: CY8C24X93, PSoC(R) Programmable System-on-Chip Document Number: 001-86894 Orig. of Submission Revision ECN Description of Change Change Date 3947416 AMKA 04/02/2013 New data sheet. ** 3971208 AMKA 04/30/2013 Changed status from Preliminary to Final. *A Updated Features. Updated PSoC(R) Functional Overview (Updated Analog system (Updated IDAC), updated Additional System Resources). *B 4009884 AMKA 05/24/2013 Updated Ordering Information (Updated part numbers). Updated Logic Block Diagram. Updated Getting Started (Updated Silicon Errata). Updated Development Tool Selection (Updated Evaluation Tools (Removed CY3210-PSoCEval1)). Updated Reference Documents. Added Appendix A: Silicon Errata for the CY8C24093/293/393/693 Family. Added Appendix B: Silicon Errata for the PSoC(R) CY8C24193/493 Families. Document Number: 001-86894 Rev. *B Page 64 of 65 CY8C24X93 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer's representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control cypress.com/go/automotive PSoC Solutions cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing PSoC Touch Sensing cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless (c) Cypress Semiconductor Corporation, 2013. The information contained herein is subject to change without notice. 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