TSA1401 14-BIT, 20MSPS, 85mW A/D CONVERTER APPLICATIONS TSA1401IF -40C to +85C TQFP48 TSA1401IFT -40C to +85C TQFP48 DR D0 (LSB) VCCBE GNDBE VCCBI NC 34 D3 AGND 4 33 D4 VIN 5 32 D5 TSA1401 AGND 6 31 D6 VINB 7 30 D7 AGND 8 29 D8 INCM 9 28 D9 AGND 10 27 D10 AVCC 11 26 D11 25 D12 AVCC 12 D13(MSB) OR DVCC VCCBE 13 14 15 16 17 18 19 20 21 22 23 24 t e l o s b O SRC 35 D2 VREFM 3 GNDBE o r P e 36 D1 IPOL 1 VREFP 2 GNDBI Typically designed for multi-channel applications and high-end imaging equipment, where low consumption is a must, the TSA1401 only dissipates 85mW at 20Msps when using external references, 110mW using internal references. Its power consumption adapts relative to sampling frequency. Differential signals are applied on the inputs for optimum performance. The TSA1401 reaches an SFDR of -90.5dBc and an SNR of 73.1dBc at Fin=10MHz when increasing the input dynamic range to 2.5V by using the voltage reference, TS431 (1.24V). SA1401 SA1401 48 47 46 45 44 43 42 41 40 39 38 37 DGND du index corner OEB P e let so b O - ct Tray Tape & Reel PIN CONNECTIONS (top view) NC (s) uc Marking Evaluation board DESCRIPTION The TSA1401 is a 14-bit, 20MHz sampling frequency Analog to Digital Converter using deep submicron CMOS technology combining high performances with very low power consumption.The TSA1401 is based on a pipeline structure with digital error correction to provide excellent static linearity and dynamic performances. ) s t( Conditioning d o r EVAL1401/AB DFSB 1) OPTIMWATT(TM) is a ST deposited trademark for products features allowing optimization of power efficiency at chip/application level. Package DGND Temperature Range Part Number AVCC ORDER CODES CLK Single supply voltage: 2.5V Digital I/O supply voltage: 2.5V/3.3V compatible -90.5dBc SFDR and 73.1dBc SNR at Fin=10MHz when using external references (VINpp=2.5V) Differential analog input-driving Built-in reference voltage with external bias capabilities Digital output high impedance mode High-end infra-red imaging X-Ray medical imaging High-end CCD cameras Scanners and digital copiers Test instrumentation Wireless communication AVCC l Adjustable consumption versus speed. DGND OPTIMWATTTM features 1 l Ultra low power consumption: 85mW at 20Msps (using external references). AGND DVCC FEATURES PACKAGE 7 x 7 mm TQFP48 A tri-state capability is available on the output buffers, enabling a Chip Select.The TSA1401 is available in the industrial temperature range of 40C to +85C and in a small 48-lead TQFP package. December 2003 1/19 1/19 TSA1401 1 ABSOLUTE MAXIMUM RATINGS ABSOLUTE MAXIMUM RATINGS Symbol Parameter AVCC, DVCC, VCCBI VCCBE Analog, digital, digital buffer Supply voltage Digital buffer Supply voltage Analog inputs VIN, VINB, VREFP, VREFM, VINCM IDout Tstg ESD Values Unit -0.3V to 3.3V V 0V to 3.6V V -0.3V to AVCC+0.3V V -100mA to 100mA +150 mA C 2000 700 V 1 1 Digital output current Storage temperature Electrical Static Discharge - HBM: Human Body Model2 - CDM-JEDEC Standard Latch-up Class3 A 1) All voltage values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not exceed -0.3V or VCC 2) ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5k 3) ST Microelectronics Corporate procedure number 0018695 OPERATING CONDITIONS Symbol Parameter Test conditions Min Unit 2.7 V 2.5 2.7 V 2.25 2.5 2.7 V 2.25 2.5 3.3 V Analog Supply voltage 2.25 DVCC Digital Supply voltage 2.25 VCCBI Digital buffer Supply voltage VCCBE Digital buffer Supply voltage e t le BLOCK DIAGRAM +2.5V VIN ct stage 1 INCM VINB o r P e t e l o CLK (s) du stage 2 o s b O stage n Pr od GNDA IPOL VREFM DFSB Sequencer-phase shifting OEB Timing s b O Digital data correction DR DO Buffers TO D13 OR GND 2/19 2.5 VREFP REFMODE Reference circuit uc Max AVCC Typ ) s t( ABSOLUTE MAXIMUM RATINGS TSA1401 PIN DESCRIPTIONS Pin Name I/O IPOL VREFP VREFM AGND VIN VINB INCM AVCC DVCC DGND CLK NC GNDBI GNDBE VCCBE OR D13(MSB)D0(LSB) DR VCCBI I No Pin Description 1 Analog bias current input - adjusts polarization current versus Fs. Top Reference Voltage - may be used as a voltage generator output or used as an I/O 2 input to adjust the input dynamic range (VIN-VINB=2x(VREFP-VREFM)). I 3 Bottom Reference Voltage. Usually connected to GND (see AN p12 for details) I 4, 6, 8, 10, 48 Analog ground. I 5 Positive Analog input. I 7 Negative Analog Input. Internal Common Mode - may be used as a voltage generator output for input sigI/O 9 nal common mode or used as an input to force the internal common mode (see AN p12 for more details). I 11, 12, 46, 47 Analog Power Supply (2.5V). I 13, 14 Digital Power Supply (2.5V) (Clock). I 15, 17,19 Digital Ground (Clock). I 16 CMOS Clock Input. NA 18, 42 Non Connected Pin. I 20 Digital Ground (Internal Buffer). I 21,40 Digital Ground (External Buffer). I 22, 39 Digital Power Supply (External Buffer, 2.5V/3.3V). O 23 Over Range Indicator, if D0-D13='1' or `0', OR='1'. Data CMOS Outputs (2.5V/3.3V). O 24-37 c u d O I 38 41 REFMODE I 43 OEB I 44 DFSB I 45 ) s t( o r P Data Ready Signal (2.5V/3.3V). Digital Power Supply (Internal Buffers 2.5V). REFMODE='VIL', internal references active. REFMODE=`VIH', external references must be applied. Output Enable Input. If OEB='VIH' then D0-D13 in `High Z' state. Data Format Select Input - If DFSB='VIH' then D13 is standard binary output coding; if DFSB='VIL' then D13 is two's complemented. e t le ) s ( ct o s b O - u d o r P e t e l o s b O 3/19 TSA1401 2 ELECTRICAL CHARACTERISTICS ELECTRICAL CHARACTERISTICS AVCC = DVCC = VCCBI =VCCBE = 2.5V, Fs= 20MHz, Fin= 10MHz, VIN-VINB@ -1.0dBFS, VREFM= 0V, VREFP=1V, INCM=0.5V (external references), Tamb = 25C (unless otherwise specified) Timing Characteristics Symbol Parameter Test conditions Min Typ 0.5 Max Unit 20 MHz FS Sampling Frequency DC Clock Duty Cycle 50 % TC1 Clock pulse width (high) 25 ns TC2 Clock pulse width (low) 25 ns Tod Data Output Delay (Fall of Clock 10pF load capacitance to Data Valid) Tpd Data Pipeline delay Ton Falling edge of OEB to digital output valid data 1 Toff Rising edge of OEB to digital output tri-state 1 6 P e let N+4 N+5 N+6 so N+2 N-1 N+1 N ) s ( ct CLK OEB Tod o r P e t e l o s b O 4/19 du N-8 N-7 N-6 N+7 b O - N+8 8.5 clk cycles Ton Toff N-5 N-4 N-1 N-3 HZ state N ns cycles ) s t( ns uc d o r N+3 DR 11 8.5 Timing Diagram DATA OUT 7.5 ns ELECTRICAL CHARACTERISTICS TSA1401 Dynamic Characteristics Symbol SFDR1 Parameter Test conditions Min Spurious Free Dynamic Range Fin=10MHz, VREFP=1V Fin=10MHz, VREFP=1.24V (TS431) Signal to Noise Ratio Fin=10MHz, VREFP=1V Total Harmonic Distortion 68 ENOB1 Effective Number of Bits 71.5 70 Fin=10MHz, VREFP=1V -85 Fin=10MHz, VREFP=1V 72.85 Fin=10MHz, internal references 69.9 10.9 11.7 OE Offset Error GE Gain Error DNL Differential Non Linearity INL Integral Non Linearity - Monotonicity and no missing codes Analog Inputs Symbol ) s ( ct t e l o Parameter VIN-VINB Analog Input Voltage, Differential Cin Analog Input capacitance s b O Zin BW bits d o r P e let Min b O - Typ Max Unit -3 LSB 0.04 % 0.8 LSB 2 LSB Guaranteed u d o r P e ) s t( 11.5 1) Typical values have been measured using the evaluation board on a dedicated test bench. so dBc uc 12 Fin=10MHz, internal references Parameter dBc 71 Fin=10MHz, VREFP=1.24V (TS431) Symbol -71 -86 Fin=10MHz, VREFP=1.24V (TS431) Accuracy dBc -85.9 66 Fin=10MHz, VREFP=1V dBFS 73.1 Fin=10MHz, internal references Signal to Noise and Distortion Ratio -74 Fin=10MHz, internal references Fin=10MHz, VREFP=1.24V (TS431) SINAD1 -89 Unit -91 Fin=10MHz, VREFP=1.24V (TS431) THD1 Max -91.5 Fin=10MHz, internal references SNR1 Typ Test conditions Analog Input impedance Fs=20MHz Analog Input Bandwidth (-3dB) Full power, VIN-VINB=2.0Vpp, Fs=20MHz Min Typ Max Unit 2 Vpp 4.0 pF 3.3 k 1000 MHz Internal Reference Voltage Symbol Parameter REFP Top internal reference voltage REFM Bottom internal reference voltage INCM Internal common mode voltage Test conditions Min Typ Max Unit 0.75 0.84 0.9 V 0 0.4 0.44 V 0.5 V 5/19 TSA1401 ELECTRICAL CHARACTERISTICS Symbol RrefO Parameter Test conditions Reference output impedance Min REFMODE='0': int references Typ Max Unit 18.7 External Reference Voltage Symbol Parameter VREFP Forced Top reference voltage VREFM Bottom reference voltage VINCM Forced common mode voltage RrefI Reference input impedance Vpol Analog bias voltage Test conditions REFMODE='1' Min Typ Max Unit 0.8 1.3 V 0 0.2 V 0.4 1 V 7.5 REFMODE='1' k 1.22 1.27 1.34 Min Typ Max Power Consumption Symbol ICCA Parameter Test conditions Analog Supply current ICCD Digital Supply Current ICCBI Digital Buffer Supply Current ICCBE Digital Buffer Supply Current ICCBEZ Digital Buffer Supply Current in High Impedance Mode Pd Power consumption in normal opera- REFMODE='0' tion mode REFMODE='1' e t le (s) PdZ Power consumption in High Impedance mode t c u Rthja c u d REFMODE='0' REFMODE='1' so b O - REFMODE='0' REFMODE='1' Thermal resistance (TQFP48) d o r P e 1) Typical values have been measured using the evaluation board on a dedicated test bench. t e l o s b O 6/19 V ) s t( Unit 40 30 37 595 700 A 1 1.5 mA 2.3 6 mA 10 150 A o r P 110 851 110 104 791 80 96 mA mW mW C/W ELECTRICAL CHARACTERISTICS TSA1401 Digital Inputs and Outputs Symbol Parameter Test conditions Min Typ Max Unit 0.8 V Clock inputs VIL Logic "0" voltage DVCC=2.5V VIH Logic "1" voltage IIL Low input current TBD A IIH High input current TBD A 2.0 V Digital inputs VIL Logic "0" voltage VCCBE=2.5V 0.25 VCCBE VIH Logic "1" voltage IIL Low input current TBD IIH High input current TBD 0.75 VCCBE V Logic "0" voltage VCCBE=2.5V, Iol=10A VOH Logic "1" voltage VCCBE=2.5V, Ioh=10A ) s ( ct P e let ro 2.45 ) s t( A c u d Digital Outputs VOL V 0.1 A V V o s b O - u d o r P e t e l o s b O 7/19 TSA1401 3 DEFINITIONS OF SPECIFIED PARAMETERS DEFINITIONS OF SPECIFIED PARAMETERS 3.1 Static Parameters Signal to Noise and Distortion Ratio (SINAD) Static measurements are performed through the method of histograms on a 2MHz input signal, sampled at 20Msps, which is high enough to fully characterize the test frequency response. An input level of +1dBFS is used to saturate the signal. Similar ratio as for SNR but including the harmonic distortion components in the noise figure (not DC signal). It is expressed in dB. Differential Non Linearity (DNL) When the applied signal is not Full Scale (FS), but has an A0 amplitude, the SINAD expression becomes: The average deviation of any output code width from the ideal code width of 1LSB. Integral Non linearity (INL) 3.2 Dynamic Parameters Dynamic measurements are performed by spectral analysis, applied to an input sine wave of various frequencies and sampled at 20Msps. Spurious Free Dynamic Range (SFDR) (s) u d o ct The ratio of the rms sum of the first five harmonic distortion components to the rms value of the fundamental line. It is expressed in dB. r P e Signal to Noise Ratio (SNR) The ratio of the rms value of the fundamental component to the rms sum of all other spectral components in the Nyquist band (Fs/2) excluding DC, fundamental and the first five harmonics. SNR is reported in dB. s b O 8/19 SINAD= 6.02 x ENOB + 1.76 dB + 20 log (2A0/FS) Analog Input Bandwidth ) s t( The maximum analog input frequency at which the spectral response of a full power signal is reduced by 3dB. Higher values can be achieved with smaller input levels. c u d o r P Effective Resolution Bandwidth (ERB) e t le The band of input signal frequencies that the ADC is intended to convert without loosing linearity i.e. the maximum analog input frequency at which the SINAD is decreased by 3dB or the ENOB by 1/2 bit. o s b O - The ratio between the amplitude of fundamental tone (signal power) and the power of the worst spurious signal (not always an harmonic) over the full Nyquist band. It is expressed in dBc. t e l o SINAD= 6.02 x ENOB + 1.76 dB. The ENOB is expressed in bits. An ideal converter presents a transfer function as being the straight line from the starting code to the ending code. The INL is the deviation for each transition from this ideal curve. Total Harmonic Distortion (THD) From the SINAD, the Effective Number of Bits (ENOB) can easily be deduced using the formula: Pipeline delay Delay between the initial sample of the analog input and the availability of the corresponding digital data output, on the output bus. Also called data latency. It is expressed as a number of clock cycles. TYPICAL PERFORMANCE CHARACTERISTICS TYPICAL PERFORMANCE CHARACTERISTICS Fig. 1: Linearity vs. Fin, Internal References Fig. 4: Linearity vs. Fin, External References (REFP=1V) Fs=20MHz; Icca=28mA Fs=20MHz; Icca=40mA Dynamic parameters (dB) 12 11.9 77 11.8 11.7 74 11.6 ENOB 11.5 71 11.4 SNR ENOB (Bits) Dynamic parameters (dB) 80 11.3 SINAD 68 11.2 11.1 65 77 5 10 15 20 Fin (Mhz) 25 11.8 ENOB 74 11.6 SINAD 71 11.4 SNR 68 11.2 65 11 5 10 15 30 20 25 30 Fin (Mhz) Fig. 2: Distortion vs. Fin, Internal References Fs=20MHz; Icca=40mA; Internal references -70 -70 -75 -75 -80 THD c u d e t le -80 SFDR -90 o r P THD o s b O - -85 ) s t( Fig. 5: Distortion vs. Fin, External References (RefP=1V) Fs=20MHz; Icca=28mA Distortion (dBc) Distortion (dBc) 12 11 0 -85 -90 SFDR -95 -95 -100 0 5 10 15 Fin (Mhz) o r P e 20 c u d (t s) 25 -100 5 t e l o -60 -65 -70 Distortion (dB) Distortion (dB) 30 -60 -65 -80 H2 -90 -95 -75 -80 H3 -85 -90 H2 -95 -100 H3 -100 25 Icca=28mA -75 -85 15 20 Fin (Mhz) Fig. 6: 2nd. and 3rd. harmonic vs. Fin, External References (REFP=1V) Fs=20MHz; -70 bs 10 30 Fig. 3: 2nd. and 3rd. harmonic vs. Fin, Internal References, Fs=20MHz; Icca=40mA O 80 ENOB (Bits) 4 TSA1401 -105 -105 -110 0 5 10 15 Fin (Mhz) 20 25 30 -110 5 10 15 20 Fin (Mhz) 25 30 9/19 TSA1401 TYPICAL PERFORMANCE CHARACTERISTICS Fig. 7: SFDR vs. input amplitude (FS=2x0.86V) Fs=20Msps; Fin=5Mhz;Icca=40mA, -20 SFDR(dBc and dBFS) -30 -40 -50 -60 SFDR(dBc) -70 -80 -90 SFDR(dBFS) -100 -110 -30 -25 -20 -15 SFSR(dB) -10 -5 0 Fig. 8: Single-tone 16K FFT at Fs=20 Msps, Internal references c u d ) s t( Fin=5MHz, Icca=40mA,Vin@-1dBFS, SFDR=-89.3dBc, THD=-84.5dBc, SNR=70.5dB, SINAD=70.3dB, ENOB=11.5 bits 0 -2 0 -4 0 e t le -6 0 -8 0 -1 0 0 -1 2 0 -1 4 0 ) s ( ct -1 6 0 -1 8 0 0 u d o o r P o s b O 5 F (M h z) Fig. 9: Single-tone 16K FFT at Fs=20Msps, External References TS4041 r P e Fin=5MHz, Icca=40mA, Vin@-1dBFS, VREFP=1.225V SFDR=-87.5dBc, THD=-85.4dBc, SNR=73.3dB, SINAD=73dB, ENOB=11.84 bits t e l o 20 0 O Power spectrum bs -2 0 -4 0 -6 0 -8 0 -1 0 0 -1 2 0 -1 4 0 -1 6 0 0 5 F (M h z) 10/19 10 TYPICAL PERFORMANCE CHARACTERISTICS TSA1401 Static parameter: Differential Non Linearity Fs=20MSPS; Fin=1MHz; Icc=40mA;N=524288pts 1 .2 1 0 .8 0 .6 0 .4 0 .2 0 -0 . 2 -0 . 4 -0 . 6 -0 . 8 Static parameter: Integral Non Linearity Fs=20MSPS; Fin=1MHz; Icc=40mA; N=524288pts 2 .5 c u d 2 1 .5 1 0 .5 e t le 0 -0 . 5 -1 -1 . 5 -2 -2 . 5 ) s ( ct ) s t( o r P o s b O - u d o r P e t e l o s b O 11/19 TSA1401 5 APPLICATION INFORMATION APPLICATION INFORMATION The TSA1401 is a High Speed Analog to Digital converter based on a pipeline architecture and the latest deep sub micron CMOS process to achieve the best performances in terms of linearity and power consumption. The pipeline structure consists of 14 internal conversion stages in which the analog signal is fed and sequentially converted into digital data. Each of the 14 stages consists of an Analog to Digital converter, a Digital to Analog converter, a Sample and Hold and an amplifier (gain=2). A 1.5bit conversion resolution is achieved in each stage. Each resulting LSB-MSB couple is then time-shifted to recover from the delay caused by conversion. Digital data correction completes the processing by recovering from the redundancy of the (LSB-MSB) couple for each stage. The corrected data are outputted through the digital buffers. Signal input is sampled on the rising edge of the clock while digital outputs are delivered on the falling edge of the clock. t c u 5.1 Analog Input Configuration When REFMODE is set to VIL level, TSA1401 operates with its own reference voltage generated by its internal bandgap. VREFM pin is connected externally to the Analog Ground while VREFP is set to its internal voltage (0.86V). The full scale of the ADC when using internal references is 1.8Vpp (to reduce the full scale if desired, VREFM may be forced externally). In this case VREFP and INCM are low impedance outputs. INCM pin (voltage generator 0.46V) may be used to supply the common mode, CM of the analog input signal. ) s t( External references, common mode: In applications requiring a different full scale magnitude, it is possible to force externally VREFP and INCM (REFM must be connected to analog ground or forced externally). c u d o r P REFMODE set to VIH level will put in standby mode the internal references. In this case, VREFP, INCM are high impedance inputs and have to be forced by external references. TSA1401 shows better performances when the full scale is increased by the use of external references (see Figure 10 and 11). e t le o s b O - The advantages of such a converter reside in the combination of pipeline architecture and the most advanced technologies. The highest dynamic performances are achieved while consumption remains at the lowest level. (s) Internal references, common mode: od Fig. 10: Linearity vs. VREFP Fin=5MHz;Fs=20Mhz;Icca=26mA;INCM=0.45V 80 12.4 r P e To maximize the TSA1401's high-resolution and speed, it is advisable to drive the analog input differentially. The full scale of TSA1401 is adjusted through the voltage value of VREFP and VREFM: t e l o bs VIN-VINB=2(VREFP-VREFM) O The differential analog input signal always presents a common mode voltage, CM: CM=(VIN+VINB)/2 In order for the user to select the right full scale according to the application, a control pin, REFMODE, allows to switch from internal to external references. 12/19 Dynamic parameters (dB) 5.1.1 Analog input level and references 12.2 77 12 ENOB 74 SINAD 11.8 SNR 71 11.6 11.4 68 11.2 65 11 0.8 0.9 1 1.1 1.2 REFP (V) 1.3 1.4 APPLICATION INFORMATION TSA1401 Fig. 11: Distortion vs. VREFP Fin=5MHz;Fs=20Mhz;Icca=26mA;INCM=0.46V Fig. 13: Linearity vs. Fs at Fin=5MHz, using TS4041 Icca optimised; VREFP=1.225V; VREFM=GND; INCM=0.65V, -70 80 THD -85 -90 SFDR -95 -100 0.8 0.9 1 1.1 REFP (V) 1.2 1.3 1.4 An external reference voltage device may be used for specific applications requiring even better linearity, accuracy or enhanced temperature behavior. Using the STMicroelectronics TS821, TS4041-1.2 or TS431 Voltage Reference devices leads to optimum performances when configured as shown in Figure 12. The full scale is increased to 2.5Vpp differential and SNR and SINAD are enhanced as shown in Figure 13 . Fig. 12: External reference setting ) s ( ct 1k VREFP TSA1401 r P e VINB t e l o VREFM 100 u d o VIN TS4041 TS821 external reference In multi-channel applications, the high impedance input of the references permits to drive several ADCs with only one Voltage Reference device. O bs 12 ENOB 77 11.9 11.8 74 11.7 SNR 11.6 SINAD 71 11.5 11.4 68 11.3 11.2 65 11.1 3 5 7 9 11 13 Fs (Mhz) 15 17 19 21 ) s t( Fig. 14: Distortion vs. Fs at Fin=5MHz, using TS4041 Icca optimised; VREFP=1.225V; c u d VREFM=GND; INCM=0.65V -70 -75 e t le -80 o s b O - 330pF 10nF 4.7F REFMODE AVCC 12.1 ENOB (Bits) Dynamic parameters (dB) -80 Distortion (dBc) Distortion (dBc) -75 -85 o r P THD -90 SFDR -95 -100 3 5 7 9 11 13 Fs (Mhz) 15 17 19 21 The magnitude of the analog input common mode, CM should stay close to VREFP/2. Higher level will introduce more distortion. 5.1.2 - Driving the analog input The TSA1401 has been designed to be differentially driven for better noise immunity. Some measurements have been done with single-ended signals. It degrades a little bit the performances, with an SFDR of -75dBc and an ENOB of 11.2 bits at 20Msps, Fin at 10MHz. The switch-capacitor input structure of TSA1401, presents a high input impedance (3.3k at Fs=20MHz) but not constant in time (see equivalent input circuit Figure 15). Indeed at the end of each conversion, the charge update of the 13/19 TSA1401 APPLICATION INFORMATION sampling capacitor will draw/inject a small current transient on the input signal. One method to mask this transient current is a low-pass RC filter as shown on Figures 16 and Figure 17. A larger capacitor value compared to the sampling capacitor (appoximately 2pF) mounted in parallel of the two analog inputs signals will absorb the transient glitches. configuration. Both inputs VIN and VINB are centered around the common mode voltage CM, that can be forced through INCM or supplied externally (in this case the internal common mode of the TSA1401 may be left internal at 0.45V, different from the input common mode value). Fig. 17: AC-coupled differential input Fig. 15: ADC input equivalent circuit VIN 10nF 50 AVcc 100k 33pF common mode 100k Zin =1/(2Cs.Fs)=3.3k (Fs=20MHz) VIN c u d 5.2 - Clock management Single-ended signal with transformer: Using an RF transformer is a good means to achieve high performance. Figures 16 describes the schematics. The input signal is fed to the primary of the transformer, while the secondary drives both ADC inputs. Fig. 16: Differential input configuration with transformer ) s ( ct ADT1-1 1:1 du t e l o o r P e 100pF 330pF TSA1401 VINB 10nF INCM 4.7F bs The internal common mode voltage of the ADC (INCM) is connected to the center-tap of the secondary of the transformer in order to bias the input signal around this common voltage, internally set to 0.46V. The INCM is decoupled to maintain a low noise level on this node. O AC coupled differential input: Figure 17 represents the biasing of a differential input signal in AC-coupled differential input 14/19 ) s t( o r P The converter performances are very dependant on clock input accuracy, in terms of aperture delay and jitter. The voltage error induced by the jitter of the clock is: e t le Verror=SR.Tj, o s b O - VIN 50 VINB INCM AGND Analog source TSA1401 10nF 50 Cin=4pF INCM where Tj is the jitter of the clock (system clock and ADC) and, SR is the slew rate of the input signal: SR max=2.Fin.FS (FS full scale, Fin input signal frequency) Verror should be less than an LSB to guarantee no missing codes. At the end we have: Verror=2.Fin.FS.Tj and Verror< FS/2n Tj <FS/(2.Fs.Fin.2n). For TSA1401 at 10MHz input frequency, we have Tj <1ps. Consequently to target the maximum performances of the TSA1401, the clock applied should have a jitter below 1ps. The clock power supplies must be separated from the ADC output ones to avoid digital noise modulation at the output. It is strongly advised not to switch off the clock when the circuit is active (power supply on). APPLICATION INFORMATION TSA1401 5.3 - Power consumption optimization The internal architecture of the TSA1401 enables the optimization of the power consumption according to the sampling frequency of the application. For this purpose, a resistor (value Rpol) is placed between IPOL and the analog Ground pins. At 20MHz sampling frequency, the Rpol for optimized consumption is equal to 41k. Optimized power consumption of the circuit versus the sampling frequency are shown in two configurations (Figure 18): l REFMODE=0 internal references l REFMODE=1 external references Fig. 18: Analog Current consumption vs. Fs According value of Rpol polarization resistances: internal references 45 120 100 35 80 30 60 40 25 Ipol_extref 20 20 0 5 10 15 20 Fs (Mhz) ) s ( ct 5.4 - Digital outputs Rpol (ohm) Ipol (mA) Rpol Ipol_intref Out of Range (OR) This function is implemented on the output stage in order to set up an "Out of Range" flag whenever the digital data is over the full scale range. Typically, there is a detection of all the data being at '0' or all the data being at '1'. This ends up with an output signal OR which is in low level state (VOL) when the data stay within the range, or in high level state (VOH) when the data are out of the range. c u d ) s t( The Data Ready output is an image of the clock being synchronized on the output data (D0 to D13). This is a very helpful signal that simplifies the synchronization of the measurement equipment or the controlling DSP. e t le o r P As digital output, DR goes in high impedance state when OEB is asserted to High level as described in the timing diagram page 4. o s b O - u d o Data Format Select (DFSB) The timing diagram page 4 summarizes this operating cycle. Data Ready (DR) 140 40 When OEB is set to low level again, the data is then valid on the output with a very short Ton delay(1ns). 5.5 - Layout precautions To use the TSA1401 circuit in the best manner at high frequencies, some precautions have to be taken for power supplies: When set to low level (VIL), the digital input DFSB provides a two's complement digital output MSB. This can be of interest when performing some further signal processing. - The separation of the analog signal from the digital part and from the buffers power supply is essential to prevent noise from coupling onto the input signal. When set to high level (VIH), DFSB provides a standard binary output coding. - Power supply bypass capacitors must be placed as close as possible to the IC pins in order to improve high frequency bypassing and reduce harmonic distortion. r P e t e l o s b O Output Enable (OEB) When set to low level (VIL), all digital outputs remain active and are in low impedance state. When set to high level (VIH), all digital outputs buffers are in high impedance state. It results in lower consumption while the converter goes on sampling. - Proper termination of all inputs and outputs is needed; with output termination resistors, the amplifier load will be only resistive and the stability of the amplifier will be improved. All leads must be wide and as short as possible especially for the analog input in order to decrease parasitic capacitance and inductance. 15/19 TSA1401 APPLICATION INFORMATION - To keep the capacitive loading as low as possible at digital outputs, short lead lengths when routing are essential to minimize currents when the output changes. To minimize this output capacitance, buffers or latches close to the output pins can relax this constraint. It is also helpful to use 47 to 56 ohms series resistors at the ADC output pins, located as close to the ADC output pins as possible. - Choose component sizes as small as possible (SMD). EVAL1401 evaluation board The characterization of the board has been made with a fully ADC devoted test bench. The schematic of the evaluation board is shown on figure 19. The analog signal must be filtered to be very pure. The dataready signal is the acquisition clock of the logic analyzer. All characterization measurement has been made with an input amplitude of +0.2dB for static parameters and -0.5dB for dynamic parameters c u d ) s ( ct u d o r P e t e l o s b O 16/19 o s b O - e t le o r P ) s t( AGND 1 AGND AVDD INCM VINM VINP IPOL REFP REFM GNDBUF 5 1 2 3 4 5 6 7 8 9 10 11 12 C13 470nF SM/C_0603 1 2 3 4 5 6 7 8 9 10 11 12 C14 10nF SM/C_0603 C3 330pF SM/C_0603 C4 470nF SM/C_0603 C15 330pF SM/C_0603 U1 TQFP48 TQFP48 36 35 34 33 32 31 30 29 28 27 26 25 36 35 34 33 32 31 30 29 28 27 26 25 C16 470nF SM/C_0603 C17 10nF SM/C_0603 C5 10nF SM/C_0603 4 + + C6 330pF SM/C_0603 C18 330pF SM/C_0603 4 VDDBUF PT2 PICOT/2pts 2 1 PT3 PICOT/2pts 2 1 PT4 PICOT/2pts 2 1 PT5 PICOT/2pts 2 1 R2 100 SM/R_0603 R3 100 SM/R_0603 R4 100 SM/R_0603 R5 100 SM/R_0603 C20 47F 16V CAPA/POL/5.08 PT1 PICOT/2pts 2 1 + C19 47F 16V CAPA/POL/5.08 AVDD C8 47F 16V CAPA/POL/5.08 R1 100 SM/R_0603 + C7 47F 16V CAPA/POL/5.08 PT14 PICOT/2pts 2 1 PT15 PICOT/2pts 2 1 R19 100 SM/R_0603 R20 100 SM/R_0603 GNDBUF PT13 PICOT/2pts 2 1 R17 100 SM/R_0603 PT10 PICOT/2pts 2 1 R13 100 SM/R_0603 PT12 PICOT/2pts 2 1 PT9 PICOT/2pts 2 1 R11 100 SM/R_0603 R16 100 SM/R_0603 PT8 PICOT/2pts 2 1 R8 100 SM/R_0603 PT11 PICOT/2pts 2 1 PT7 PICOT/2pts 2 1 R7 100 SM/R_0603 R15 100 SM/R_0603 PT6 PICOT/2pts 2 1 R6 100 SM/R_0603 3 AGND SMB_TRANCHE J7 2 SMB INCM AGND SMB_TRANCHE J6 2 SMB VCMO AGND SMB_TRANCHE J5 2 SMB REFM AGND SMB_TRANCHE J4 2 SMB REFP DGND SMB_TRANCHE J2 2 SMB DVDD 3 e t le A B C 1 SMB_TRANCHE J3 2 SMB VDDBUF CLK D C2 10nF SM/C_0603 AGND D VDD C1 470nF SM/C_0603 GNDBUF VDDBUF 1 1 1 1 1 5 AVDD VCMO NO DI PWD DGND C26 470nF SM/C_0603 C30 470nF SM/C_0603 C34 470nF SM/C_0603 C25 47F 16V CAPA/POL/5.08 C29 47F 16V CAPA/POL/5.08 C33 47F 16V CAPA/POL/5.08 + + + 2 C22 470nF SM/C_0603 C21 47F 16V CAPA/POL/5.08 + R9 50K R_VARIABLE C35 10nF SM/C_0603 C31 10nF SM/C_0603 C27 10nF SM/C_0603 C23 10nF SM/C_0603 C11 10nF SM/C_0603 IPOL R12 1K SM/R_0603 AGND C10 470nF SM/C_0603 C9 47F 16V CAPA/POL/5.08 + 2 2 DVDD C36 330pF SM/C_0603 INCM C32 330pF SM/C_0603 VCMO C28 330pF SM/C_0603 REFM C24 330pF SM/C_0603 REFP C12 330pF SM/C_0603 1 1 1 1 1 Date: Size B Title 1 1 CALE DE PLACEMENT CALE_MPG 2 AGND AGND CLK R18 47 SM/R_0603 50 ohms R14 47 SM/R_0603 50 ohms R10 47 SM/R_0603 50 ohms AGND AVDD Tuesday, October 08, 2002 Document Number 1 1 Sheet 1 of 1 C38 0pF SM/C_0603 Willy Beule STMicroelectronics Crolles 2 SM/C_0603 C37 10nF 2 DGND 2 DGND AGND TP3 picot picot/1pts GNDBUF 3 2 AGND AVDD CALE DE PLACEMENT CALE_MPG 3 SW1 inverseur SW2 1 CALE DE PLACEMENT CALE_MPG inverseur B3 B2 B1 TP2 picot picot/1pts CVT_TQFP48_MB_V1 J10 SMA SMA_TRANCHE VINM J9 SMA SMA_TRANCHE VINP J8 SMA SMA_TRANCHE CLOCK TP1 picot picot/1pts PWD N ODI F4 FIXATION CARTE TROU FIXATION 3MM 1 F3 FIXATION CARTE TROU FIXATION 3MM 1 F2 FIXATION CARTE TROU FIXATION 3MM 1 F1 FIXATION CARTE TROU FIXATION 3MM 1 VDDBUF 48 47 46 45 44 43 42 41 40 39 38 37 GNDBUF 1 1 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 13 14 15 16 17 18 19 20 21 22 23 24 VDDBUF 3 2 2 1 1 o s b O - 1 1 1 1 1 2 2 2 2 1 1 1 1 1 t e l o r P e u d o ) s ( ct 1 s b O SMB_TRANCHE J1 2 SMB AVDD Rev A VINM VINP A B C D APPLICATION INFORMATION TSA1401 Fig. 19: TSA1401 Evaluation board schematic c u d ) s t( o r P 17/19 TSA1401 APPLICATION INFORMATION Printed circuit board - List of components R e fe re n c e B 1 ,B 2 ,B 3 C 1 ,C 4 ,C 1 0 ,C 1 3 ,C 1 6 ,C 2 2 , C 2 6 ,C 3 0 ,C 3 4 C 2 ,C 5 ,C 1 1 ,C 1 4 ,C 1 7 ,C 2 3 , C 2 7 ,C 3 1 ,C 3 5 ,C 3 7 C 3 ,C 6 ,C 1 2 ,C 1 5 ,C 1 8 ,C 2 4 , C 2 8 ,C 3 2 ,C 3 6 C 7 ,C 8 ,C 9 ,C 1 9 ,C 2 0 ,C 2 1 ,C 2 5 , C 2 9 ,C 3 3 C38 J 1 ,J 2 ,J 3 ,J 4 ,J 5 ,J 6 ,J 7 J 8 ,J 9 ,J 1 0 P T 1 ,P T 2 ,P T 3 ,P T 4 ,P T 5 ,P T 6 , P T 7 ,P T 8 ,P T 9 ,P T 1 0 ,P T 1 1 , P T 1 2 ,P T 1 3 ,P T 1 4 ,P T 1 5 R 1 ,R 2 ,R 3 ,R 4 ,R 5 ,R 6 ,R 7 ,R 8 , R 1 1 ,R 1 3 ,R 1 5 ,R 1 6 ,R 1 7 ,R 1 9 , R20 R9 R 1 0 ,R 1 4 ,R 1 8 R12 S W 1 ,S W 2 T P 1 ,T P 2 ,T P 3 P a rt C ALE D E P LA C EM EN T 470nF P C B F o o tp r in t CALE_M PG S M /C _ 0 6 0 3 10nF S M /C _ 0 6 0 3 330pF S M /C _ 0 6 0 3 100 F 16V C A P A /P O L /5 .0 8 0pF SMB SMA p ic o t S M /C _ 0 6 0 3 SM B_TRANCHE SM A_TRANCHE P IC O T /2 p ts 100 S M /R _ 0 6 0 3 200K 4 9 .9 1K m ic ro s w itc h 1 p ic o t R _ V A R IA B L E S M /R _ 0 6 0 3 S M /R _ 0 6 0 3 in v e rs e u r p ic o t/1 p ts c u d e t le ) s ( ct u d o r P e t e l o s b O 18/19 o s b O - o r P ) s t( PACKAGE MECHANICAL DATA 6 TSA1401 PACKAGE MECHANICAL DATA TQFP48 MECHANICAL DATA mm. inch DIM. MIN. TYP A MAX. MIN. TYP. 1.6 A1 0.05 0.15 0.002 A2 1.35 1.40 1.45 0.053 0.055 B 0.17 0.22 0.27 0.007 0.009 C 0.09 0.20 0.0035 0.006 D 9.00 0.354 7.00 0.276 D3 5.50 0.216 e 0.50 0.020 E 9.00 0.354 E1 7.00 0.276 5.50 L 0.45 0.60 L1 0 3.5 0.018 7 0 0.024 0.030 c u d 0.039 3.5 e t le ) s ( ct 0.011 0.216 0.75 1.00 K 0.057 0.0079 D1 E3 MAX. 0.063 ) s t( 7 o r P o s b O - u d o r P e t e l o 0110596/C s b O Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. 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