1/19
FEATURES
■OPTIMWATTTM fea tures 1
l
Ultra low power consumption: 85mW at
20Msps (using external references).
l
Adjustable cons ump tion versus speed.
■Single sup ply volt age: 2.5V
■Digital I/ O suppl y voltage: 2.5V/3.3V com-
patible
■-90.5dBc SFDR and 73.1dBc SNR at
Fin=10M Hz when usi ng external refer-
ences (V INpp=2 .5V)
■Differ e ntial a nalo g in put -driv in g
■Built-in reference voltage with external
bias capabilities
■Digit al output high im ped a nce mo de
1) OPTIMWATT(TM) is a ST deposited trademark for products features allowing
optimization of po we r efficiency at chip/application level.
DESCRIPTION
The TSA1401 is a 14-bit, 20MHz sampling
frequen cy Analog to Digital Converter using de ep
submicron CMOS technology combining high
performances with very low power
cons umption.The TSA1401 is based on a pipeline
structure with digital error correction to provide
excellent static linearity and dynamic
performances.
Typically designed for multi-channel applications
and high-end imaging equipment, where low
consumption is a must, the TSA1401 only
dissipat es 85 mW at 20Msps when u sing ex ternal
references, 110mW using internal references. Its
power consumption adapts relative to sampling
frequency. Differential signals are applied on the
inputs for optimum performance. The TSA1401
reaches an SFDR of -90.5dBc and an SNR of
73.1d Bc at Fin= 10MHz when increasing the input
dynamic range to 2.5V by using the voltage
reference, TS431 (1. 24V).
A tri-state capability is available on the output
buffers, enabling a Chip Select.The TSA1401 is
available in the industrial temperature range of -
40°C to +85°C and in a small 48-lead TQFP
package.
APPLICATIONS
■Hi gh - end infra -r ed im aging
■X-Ray medical imaging
■High-end CCD cameras
■Sca n ne rs and digital copi e rs
■Test instrumentation
■Wireless comm u nicati on
ORDER CO DES
PIN CONNECT IONS (top view)
PACKAGE
Part Number Temperat ure
Range Package Conditioning Marking
TSA1401IF -40°C to +85°C TQFP48 Tray SA1401
TSA1401IFT -40°C to +85°C TQFP48 Tape & Reel SA1401
EVAL1 401 / A B Eva lu ation boa r d
index
corner
1
2
3
4
5
6
7
8
9
10
11
32
31
30
29
28
27
26
13 14 15 16 17 18 19 20 21 22
47
25
33
12
23 24
35
34
36
48 44 43 42 41 40 39 38 3746 45
TSA1401
VREFM
VREFP
VINB
AGND
AGND
AGND
VIN
AVCC
AVCC
AGND
IPOL
INCM
D0 (LSB)
AVCC
DR
SRC
OEB
AGND
AVCC
DFSB
VCCBI
GNDBE
NC
VCCBE
GNDBE
GNDBI
DGND
DVCC
CLK
DGND
VCCBE
NC
OR
DGND
DVCC
D13(MSB)
D1
D2
D3
D4
D5
D6
D7
D8
D11
D9
D10
D12
index
corner
1
2
3
4
5
6
7
8
9
10
11
32
31
30
29
28
27
26
13 14 15 16 17 18 19 20 21 22
47
25
33
12
23 24
35
34
36
48 44 43 42 41 40 39 38 3746 45
TSA1401
VREFM
VREFP
VINB
AGND
AGND
AGND
VIN
AVCC
AVCC
AGND
IPOL
INCM
D0 (LSB)
AVCC
DR
SRC
OEB
AGND
AVCC
DFSB
VCCBI
GNDBE
NC
VCCBE
GNDBE
GNDBI
DGND
DVCC
CLK
DGND
VCCBE
NC
OR
DGND
DVCC
D13(MSB)
D1
D2
D3
D4
D5
D6
D7
D8
D11
D9
D10
D12
7 x 7 mm TQFP48
TSA1401
14-BIT, 20MSPS, 85mW A/D CONVERTER
1/19
December 2003
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
TSA1401 ABSOLUTE MAXIMUM RATINGS
2/19
1 ABSOLUTE MAXIMUM RATINGS
OPERATING CONDITIONS
BLOCK DIAGRAM
Symbol Parameter Values Unit
AVCC, DVCC, VCCBI Analog, digital, digital buffer Supply voltage 1
1) All voltage values, except differential voltage, are with respect to network ground terminal. The magnitude of input and output voltages must not e xceed -0 .3V or VCC
-0.3V to 3.3V V
VCCBE Digital buffer Supply voltage 1 0V to 3.6V V
VIN, VINB, VREFP,
VREFM, VINCM Analog inputs -0.3V to AVCC+0.3V V
IDout Digital output current -100mA to 100mA mA
Tstg Storage temperature +150 °C
ESD Electrical Static Discharge
- HBM: Human Body Model2
- CDM-JEDEC Standard
2) ElectroStatic Discharge pulse (ESD pulse) simulating a human body discharge of 100 pF through 1.5kΩ
2000
700 V
Latch-up Class3
3) ST Microelectronics Corporate procedure number 0018695
A
Symb ol Para m eter Test condit ions Min Typ Max Unit
AVCC Analog Supply voltage 2.25 2.5 2.7 V
DVCC Digital Supply voltage 2.25 2.5 2.7 V
VCCBI Digital buffer Supply voltage 2.25 2.5 2.7 V
VCCBE Digital buffer Supply voltage 2.25 2.5 3.3 V
stage stage stage
1 2 n
Reference
Timing
circuit
Sequencer-phase shifting
Digi tal dat a co rrection
Buffers
IPOL
VREFM
VREFP
CLK
+2.5V
VIN
VINB
DFSB
OEB
DR
DO
TO
D13
OR
INCM
GND
GNDA
REFMODE
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ABSOLUTE MA XIM UM RATINGS TSA 1401
3/19
PIN DESCRIPTIONS
Pin Name I/O No Pin Description
IPOL I 1 Analog bias current input - adjusts polarization current versus Fs.
VREFP I/O 2 Top Reference Voltage - may be used as a voltage generator output or used as an
input to adjust the input dynamic range (VIN-VINB=2x(VREFP-VREFM)).
VREFM I 3 Bottom Reference Voltage. Usually connected to GND (see AN p12 for details)
AGND I 4, 6, 8, 10, 48 Analog ground.
VIN I 5 Positive Analog input.
VINB I 7 Negative Analog Input.
INCM I/O 9 Internal Common Mode - may be used as a voltage generator output for input sig-
nal common mode or used as an input to force the internal common mode (see AN
p12 for more details).
AVCC I 11, 12, 46, 47 Analog Power Supply (2.5V).
DVCC I 13, 14 Digital Power Supply (2.5V) (Clock).
DGND I 15, 17,19 Digital Ground (Clock).
CLK I 16 CMOS Clock Input.
NC NA 18, 42 Non Connected Pin.
GNDBI I 20 Digital Ground (Internal Buffer).
GNDBE I 21,40 Digital Ground (External Buffer).
VCCBE I 22, 39 Digital Power Supply (External Buffer, 2.5V/3.3V).
OR O 23 Over Range Indicator, if D0-D13=’1’ or ‘0’, OR=’1’.
D13(MSB)-
D0(LSB) O 24-37 Data CMOS Outputs (2.5V/3.3V).
DR O 38 Data Ready Signal (2.5V/3.3V).
VCCBI I 41 Digital Power Supply (Internal Buffers 2.5V).
REFMODE I 43 REF MODE =’VIL’, internal refere nces active .
REFMODE=‘VIH’, external references must be applied.
OEB I 44 Output Enable Input. If OEB=’VIH’ then D0-D13 in ‘High Z’ state.
DFSB I 45 Data Format Select Input - If DFSB=’VIH’ then D13 is standard binary output cod-
ing; if DFSB=’VIL’ then D13 is two’s complemented.
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TSA1401 ELECTRICAL CHARACTERISTICS
4/19
2 ELECTRICAL CHARACTERISTICS
AVCC = DVCC = VCCBI =VCCBE = 2.5V, Fs= 20MHz, Fin= 10MHz, VIN-VINB@ -1.0dBFS, VREFM=
0V, VREFP=1V, INCM=0. 5V (external references), Tamb = 25°C (unless otherwise specified)
Timing Characteristics
Timing Diagram
Symbol Parameter Test conditions Min Typ Max Unit
FS Sampling Frequency 0.5 20 MHz
DC Clock Duty Cycle 50 %
TC1 Clock pulse width (high) 25 ns
TC2 Clock pulse width (low) 25 ns
Tod Data Output Delay (Fall of Clock
to Data Valid) 10pF load capacitance 6 7.5 11 ns
Tpd Data Pipeline delay 8.5 cycles
Ton Falling edge of OEB to digital
output valid data 1ns
Toff Rising edge of OEB to digital
output tri-state 1ns
N-1 NN+1
N+6
N+7
N+2
N+5
N+3
N+4
N+8
N-3 N-1N-4N-5N-6N-7N-8
CLK
OEB
DR
Tod Ton
Toff
8.5 clk cyc les
HZ state
N
DATA
OUT
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ELECTRICAL CHARACTERISTICS TSA1401
5/19
Dynamic Characteristics
Accuracy
An alog Inputs
Internal Reference Voltage
Symbol Parameter Test conditions Min Typ Max Unit
SFDR1Spurious Free Dynamic Range Fin=10MHz, VREFP=1V
Fin=10MHz, VREFP=1.24V (TS431)
Fin=10MHz, internal references
-89
-91.5
-91
-74 dBFS
SNR1Signal to Noise Ratio Fin=10MHz, VREFP=1V
Fin=10MHz, VREFP=1.24V (TS431)
Fin=10MHz, internal references
68 71.5
73.1
70 dBc
THD1Total Harmonic Distortion Fin=10MHz, VREFP=1V
Fin=10MHz, VREFP=1.24V (TS431)
Fin=10MHz, internal references
-85
-85.9
-86
-71 dBc
SINAD1Signal to Noise and Distortion
Ratio Fin=10MHz, VREFP=1V
Fin=10MHz, VREFP=1.24V (TS431)
Fin=10MHz, internal references
66 71
72.85
69.9 dBc
ENOB1Effective Number of Bits Fin=10MHz, VREFP=1V
Fin=10MHz, VREFP=1.24V (TS431)
Fin=10MHz, internal references
10.9 11.7
12
11.5 bits
1) T ypical v al ues have b een meas ured usi ng the evalua tion boa rd on a dedi cated te st bench.
Symbol Parameter Min Typ Max Unit
OE Offset Error -3 LSB
GE Gain Error 0.04 %
DNL Differential Non Linearity ±0.8 LSB
INL Integral Non Linearity ±2LSB
-Monotonicity and no missing codes Guaranteed
Symbol Parameter Test conditions Min Typ Max Unit
VIN-VINB Analog Input Voltage, Differential 2 Vpp
Cin Analog Input capacitance 4.0 pF
Zin Analog Input impedance Fs=20MHz 3.3 kΩ
BW Analog Input Bandwidth (-3dB) Full power, VIN-VINB=2.0Vpp,
Fs=20MHz 1000 MHz
Symbo l Parameter Test condit ions Mi n Typ M ax Unit
REFP Top internal reference voltage 0.75 0.84 0.9 V
REFM Bottom internal reference voltage 0 V
INCM Internal common mode voltage 0.4 0.44 0.5 V
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TSA1401 ELECTRICAL CHARACTERISTICS
6/19
External R e fer ence Voltage
Power Consumption
RrefO Reference output impedance REFM ODE =’0’: int referenc es 18.7 Ω
Symbol Parameter Test conditions Min Typ Max Unit
Symbol Parameter Test conditions Min Typ Max Unit
VREFP Forced Top reference voltage REFMODE=’1’ 0.8 1.3 V
VREFM Bottom reference voltage 0 0.2 V
VINCM Forced common mode voltage 0.4 1 V
RrefI Reference input impedance 7.5 kΩ
Vpol Analog bias voltage REFMODE=’1’ 1.22 1.27 1.34 V
Symbol Parameter Test conditions Min Typ Max Unit
ICCA Analog Supply current REFMODE=’0’
REFMODE=’1’ 40
30 37 mA
ICCD Digital Supply Current 595 700 µA
ICCBI Digital Buffer Supply Current 1 1.5 mA
ICCBE Digital Buffer Supply Current 2.3 6 mA
ICCBEZ Digital Buffer Supply Current in High
Impedance Mode 10 150 µA
Pd Power consumption in normal opera-
tion mode REFMODE=’0’
REFMODE=’1’ 110
851110 mW
PdZ Power consumption in High Imped-
ance mode REFMODE=’0’
REFMODE=’1’ 104
79196 mW
Rthja Thermal resistance (TQFP48) 80 °C/W
1) Typical values have been measured using the evaluation board on a dedicated test bench.
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ELECTRICAL CHARACTERISTICS TSA1401
7/19
Digital Inputs and Outputs
Symbol Parameter Test conditions Min Typ Max Unit
Clock inputs
VIL Logic "0" voltage DVCC=2.5V 0.8 V
VIH Logic "1" voltage 2.0 V
IIL Low input current TBD µA
IIH High input current TBD µA
Digital inputs
VIL Logic "0" voltage VCCBE=2.5V 0.25
VCCBE V
VIH Logic "1" voltage 0.75
VCCBE V
IIL Low input current TBD µA
IIH High input current TBD µA
Digital Outputs
VOL Logic "0" voltage VCCBE=2.5V, Iol=10µA 0.1 V
VOH Logic "1" voltage VCCBE=2.5V, Ioh=10µA 2.45 V
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TSA1401 DEFINITIONS OF SPECIFIED PARAMETERS
8/19
3 DEFINITIONS OF SPECIFIED PARAM ETERS
3.1 Static Param et ers
Static measurements are performed through the
method of histograms on a 2MHz input signal,
sample d at 20Msps, which is high e nough to fully
characterize the test frequency response. An
input level of +1dBFS is used to saturate the
signal.
Dif f erential N on Li n e ari ty (DNL)
The average deviation of any output code width
from the ideal code widt h of 1LSB.
Integral Non linearity (INL)
An ide al c onverter pres ent s a transfer f unct ion as
being the straight li ne from the starti ng code to the
ending code. The INL is the deviation for each
transition from this ideal curve.
3.2 Dynamic Parameters
Dynamic measurements are performed by
spe ctral analysi s, applied to an input sine wave of
various frequencies and sampled at 20Msps.
Spurious Free Dynamic Range (SFDR)
The ratio between the amplitude of fundamental
tone (signal power) and the power of the worst
spur ious signal (not always an harmonic) over the
full Nyquist band. It is expressed in dB c.
Total Harmonic Distortio n (THD)
The ratio of the rm s sum of the f irst five harmonic
distortion components to the rms value of the
fundamental line. It is ex pressed in dB.
Signal to Noise Ratio (SNR)
The ratio of the rms value of the fundamental
component to the rms sum of all other spectral
components in the Nyquist band (Fs/2) excluding
DC, fundamental and the first five harmonics.
SNR is reported in dB.
Signal to Noise and Distortion Ratio (SINAD)
Similar ratio as for SNR but including the
harmonic distortion components in the noise
figure (not DC signal). It is expressed in dB.
From the SINAD, the Effective Number of Bits
(ENOB ) can easily be deduced using the formula:
SINAD= 6.02 × ENOB + 1.76 dB.
When t he applied signal is not Full Scale (FS), but
has an A0 amplitude, the SINAD expression
becomes:
SINAD= 6.02 × ENOB + 1.76 dB + 20 log (2A0/FS)
The E NOB is expressed in bits.
Analog Input Bandwidth
The maximum analog input frequency at which
the spectral response of a full power signal is
reduced by 3dB. Higher values can be achieved
wi th s maller in put leve ls .
Effective Resolution Bandw idth (ERB)
The band of input signal frequencies that the ADC
is intended t o convert without loosin g linearity i.e.
the maximum analog input frequency at which the
SINAD is decreased by 3dB or the ENOB by 1/2
bit.
Pipeline delay
Delay between the initial sample of the analog
input and the availability of the corresponding
digital data output, on the o utput bus. Also called
data l atenc y. It is expressed as a num ber of clock
cycles.
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TYPICAL PERFORMANCE CHARACTERISTICS TSA1401
9/19
4 TYPICAL PERFORMANCE CHARACTERISTICS
Fig. 1: Linearity vs. Fin, Internal References
Fs=20MHz; Icca=40mA
Fig. 2: Distortion vs. Fin, Internal References
Fs=20MHz; Icca=40mA; Internal references
Fig. 3: 2nd. and 3rd. harmonic vs. Fin, Internal
References, Fs=20MHz; Icca=40mA
Fig. 4: Linearity vs. F in, Externa l References
(REFP=1V) Fs=20MHz; Icca=28mA
Fig. 5: Disto rtion vs. Fin, External References
(RefP=1V) Fs=20MHz; Icca=28mA
Fig. 6: 2nd. and 3rd. harmonic vs. Fin, External
References (REFP=1V) Fs=20MHz;
Icca=28mA
65
68
71
74
77
80
0 5 10 15 20 25 30
F in (Mhz)
Dynam ic param ete rs (dB)
11
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
12
ENOB (Bits)
SINAD
SNR
ENOB
-100
-95
-90
-85
-80
-75
-70
0 5 10 15 20 25 30
F in (Mhz)
Distorti on (dBc)
THD
SFDR
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
0 5 10 15 20 25 30
Fin (Mhz)
Distorti on (d B)
H2
H3
65
68
71
74
77
80
5 1015202530
Fin (Mhz)
Dynamic parameters (dB)
11
11.2
11.4
11.6
11.8
12
ENOB (Bits
)
ENOB
SINAD
SNR
-100
-95
-90
-85
-80
-75
-70
5 1015202530
Fin (Mhz)
Distortion (dBc)
THD
SFDR
-110
-105
-100
-95
-90
-85
-80
-75
-70
-65
-60
51015202530
F in (M hz)
Distortion (dB)
H3
H2
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TSA1401 TYPICAL PERFORMANCE CHARACTERISTICS
10/19
Fig. 7: SFDR vs. input amplitude (FS=2x0.86V)
Fs=20Msps; Fin=5Mhz;Icca=40mA,
Fig. 8: Single-tone 16K FFT at Fs=20 Msps, Internal references
Fin=5MHz, Icca=40mA,Vin@-1dBFS, SFDR=-89.3dBc, THD=-84.5dBc, SNR=70.5dB, SINAD=70.3dB, ENOB=11.5 bits
Fig. 9: Single-tone 16K FFT at Fs=20Msps, External References TS4041
Fin=5MHz, Icca=40mA, Vin@-1dBFS, VREFP=1.225V
SFDR=-87.5dBc, THD=-85.4dBc, SNR=73.3dB, SINAD=73dB, ENOB=11.84 bits
-110
-100
-90
-80
-70
-60
-50
-40
-30
-20
-30 -25 -20 -15 -10 -5 0
SFSR(dB)
SFDR (dB c and dBFS )
SFDR(dBc)
SFDR(dBFS)
-180
-160
-140
-120
-100
-80
-60
-40
-20
0
F(Mhz)
05
-160
-140
-120
-100
-80
-60
-40
-20
0
20
F (M hz)
Power spect rum
5 10
0
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TYPICAL PERFORMANCE CHARACTERISTICS TSA1401
11/19
Static parameter: Differential Non Linearity
Fs=20MSPS; Fin=1MHz; Icc=40mA;N=524288pts
Static parameter: Integral Non Linearity
Fs=20MSPS; Fin=1M Hz; Icc=40m A; N=5 24288pts
-0 .8
-0 .6
-0 .4
-0 .2
0
0.2
0.4
0.6
0.8
1
1.2
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
2
2.5
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TSA 1401 APPL ICATION INF ORMATION
12/19
5 APPLICATION INFOR MATION
The TSA1401 is a High Speed Analog to Digital
conv er ter based on a pipeline architecture and the
latest deep sub m icron CMO S process to achiev e
the best performances in terms of linearity and
power consumption.
The pipeline structure consists of 14 internal
conversion stages in which the analog signal is
fed and sequentially con verted into digital data.
Each of the 14 stages consists of an Analog to
Digital converter, a Digital to Analog converter, a
Sample and Hold and an amplifier (gain=2). A 1.5-
bit conversion resolution is achieved in each
stage. Each resulting LSB-MSB couple is then
time-shifted to recover from the delay caused by
conversion. Digital data correction completes the
proce ssin g by recov ering from the redunda ncy of
the (LSB-MSB) couple for each stage. The
corrected data are outputted through the digital
buffers.
Signal input is sampled on the rising edge of the
clock while digital outputs are delivered on the
falling edge of the clock.
The ad vantages of such a convert er reside in the
combin ation of pipeline archit ecture and the most
advanced technologies. The highest dynamic
performances are achieved while consumption
remains at the lowest level.
5.1 Analog Input Configuration
5.1.1 Analog input level and references
To maximize the TSA1401’s high-resolution and
speed, it is advisable to drive the analog input
differentially. The full scale of TSA1401 is
adjust ed throug h the voltage value of VREFP and
VREFM:
VIN-VINB=2(VREFP-VREFM)
The differential analog input signal always
prese nts a common mo de voltage, CM:
CM=(VIN+VINB)/2
In order for the user to select the right full scale
according to the application, a control pin,
REFMODE, allows to switch from internal to
external references.
Internal references, common mode:
When REFMODE is set to VIL level, TSA1401
operates wi th its own reference voltage generated
by its internal bandg ap. VREFM pin is connected
externally to the Analog Ground while VREFP is
set to its internal voltage (0. 86V ). The full scale of
the ADC when using i nternal references is 1.8Vpp
(to reduc e t he full scale if desired, VREFM may be
forced externally).
In this case VREFP and INCM are low impedance
outpu ts. INCM pin (voltage g enerator 0.46V) may
be used to supply the common mode, CM of the
analog inp ut signal.
External references, common mode:
In applications requiring a different full scale
magnitude, it is possible to force externally
VREFP and INCM (REFM must be connected to
analog groun d or forced externally).
REFMODE set to VIH level will put in standby
mode the internal references. In this case,
VREFP, INCM are high impedance inputs and
have to be forced by external references.
TSA1401 shows better performances when the
full scale is increased by the use of external
references (see
Figure 10
and
11
).
Fig. 10: Linearity vs. VREFP
Fin=5MHz;Fs=20Mhz;Icca=26mA;INCM=0.45V
65
68
71
74
77
80
0.8 0.9 1 1.1 1.2 1.3 1.4
REFP
(
V
)
Dynamic parameters (dB)
11
11.2
11.4
11.6
11.8
12
12.2
12.4
ENOB
SNR
SINAD
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APPLICATIO N INFORMATION TSA1401
13/19
Fi g. 11: D i stortion vs . VR E FP
Fin=5MHz;Fs=20Mhz;Icca=26mA;INCM=0.46V
An external reference voltage device may be used
for specific applications requiring even better
linearity, accuracy or enhanced temperature
behavior.
Using the STMicroelectronics TS821, TS4041-1. 2
or TS431 Voltage Reference devices leads to
optimum performances when configured as
shown in
Figure 12
. The full scal e is increased to
2.5Vpp differential and SNR and SINAD are
enhanced as shown in
Figure 13
.
Fig. 12: External reference setting
In m ulti-channel applications, the high im pedance
input of the references permits to drive several
ADCs with only one Voltage Reference device.
Fig. 13: Linear ity vs. Fs a t Fin=5MHz, using
TS404 1 Icca optimised; VREFP=1.225V;
VREFM=G ND; INCM =0.65 V,
Fig. 14: Distortion vs. Fs a t Fin=5MHz, using
TS4041 Icca optimised; VREFP=1.225V;
VREFM=G ND; INCM =0.65 V
The magnitude of the analog input common
mode, CM should stay close to VREFP/2. Higher
level will introduce more distortion.
5.1.2 - Driving t he an alog input
The TSA1401 has been designed to be
differentially driven for better noise immunity.
Some measurements have been done with
single-ended signals. It degrades a little bit the
performances, with an SFDR of -75dBc and an
ENOB of 11.2 bits at 20Msps, Fin at 10MHz.
The switch-capacitor input structure of TSA1401,
presents a high input impedance (3.3kΩ at
Fs=20MHz) but not constant in time (see
equivalent input circuit
Figure 15
). Indeed at the
end of each conv ersion, the charge upda te of the
-100
-95
-90
-85
-80
-75
-70
0.8 0.9 1 1.1 1.2 1.3 1.4
RE F P (V)
Distortion (dBc
)
THD
SFDR
1k
Ω
TSA1401
VIN
VINB VREFM
VREFP
external
reference
AVCC
330pF 4.7µF
10nF
TS821
TS4041
REFMODE
100
Ω
65
68
71
74
77
80
3579111315171921
Fs (Mhz)
Dy namic para m eters (dB)
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
12
12.1
ENOB (Bits
)
ENOB
SINAD
SNR
-100
-95
-90
-85
-80
-75
-70
3579111315171921
Fs (Mhz)
Distortion (dBc
)
THD
SFDR
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
TSA 1401 APPL ICATION INF ORMATION
14/19
sampli ng capaci tor will dra w/inject a sma ll current
transien t on the input signal.
One method to mask this transient current is a
low-pass RC filter as shown on
Figures 16
and
Figure 17
. A larger capacitor value compared to
the sampling capacitor (appoximately 2pF)
mounted in parallel of the two analog inputs
signals w ill ab so r b the trans ie nt g lit c he s .
Fig. 15: ADC input equivalent circuit
Single-ended signal wi th transformer:
Using an RF transformer is a good means to
ach ieve high performance .
Figures 16
describes the schematics. The input
signal is fed to the primary of the transformer,
while the secondary drives both ADC inputs.
Fig. 16: Differential input configuration with
transformer
The internal common mode voltage of the ADC
(INCM) is connected to the center-tap of the
secondary of the transformer in order to bias the
input signal around this common voltage,
inte rnally set to 0. 46V. The INCM is decoup led to
maintain a low noise level on this node.
AC coupled differential input:
Figure 17
represents the biasing of a differential
input signal in AC-coupled differential input
configuration. Both inputs VIN and VINB are
centered around the common mode voltage CM,
that can be forced through INCM or supplied
external ly (in thi s case the internal common mo de
of the TSA1401 may be left internal at 0.45V,
different from the input common m ode value).
Fig. 17: AC -couple d diffe rential inp ut
5.2 - Clo ck man agement
The converter performances are very dependant
on clock input accuracy, in terms of aperture delay
and jit ter. The voltage error induced by the jitter of
the clock is:
Verror=SR.Tj,
where Tj is th e j itter of the clock (s ystem clock and
ADC) and,
SR is the slew rate of the inpu t signal:
SR max=2Π.Fin.FS (FS full scale, Fin input signal
frequency)
Verror s hould be less t han an LSB to guarantee no
missing codes. At the end we have:
Verror=2Π.Fin.FS.Tj a nd Verror< FS/2n
Tj <FS/(2Π.Fs.Fin.2n).
For TSA1401 at 10MHz input frequency, we have
Tj <1ps. Consequently to target the maximum
performances of the TSA1401, the clock applied
sho uld have a jitter below 1ps.
The clock power supplies must be separated from
the ADC output ones to avoid digital noise
modu lat ion at the output.
It is strongly advised not to switch off the clock
when the circuit is active (power supply on).
Zin=1/(2ΠCs.Fs)=3.3kΩ (Fs=20MHz)
Cin=4pF
VIN
AVcc
AGND
INCM
TSA1401
VIN
VINB INCM
50Ω100pF
330pF 4.7µF
10nF
Analog source 1:1
ADT1-1
50Ω10nF
TSA1401
VIN
VINB
INCM
33pF 100kΩ
100kΩ
50Ω10nF
common
mode
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
APPLICATIO N INFORMATION TSA1401
15/19
5.3 - Power consump tion optimization
The internal architecture of the TSA1 401 enables
the optimization of the power consumption
according to the sampling frequency of the
application. For this purpose, a resistor (value
Rpol) is placed between IPOL and the analog
Ground pins. At 20MHz sampling frequency, the
Rpol for optimized consump tion is equal to 41kΩ.
Optimized power consumption of the circuit
versus the sampling frequency are shown in two
conf igurations (
Figure 18
):
l
REFMODE =0 internal references
l
REFMODE =1 external reference s
Fig. 18: Analog Current c onsumption vs. Fs
According value of Rpol polarization
resistances: internal references
5.4 - Digital outputs
Data Format Select (DFSB)
When set to low level (VIL), the digital input DFSB
provides a two’s complement d igital output MSB.
This can be of interest when performing some
further signal processing.
When set to high level (VIH), DFSB provides a
standard bin ary output coding.
Output Enable (OEB)
When set to low level (VIL), all digital outputs
remain active and are in low impedance state.
When set to high level (VIH), all digital outputs
buffers are in high impedance state. It results in
lower consumption while the converter goes on
sampling.
When OEB is set to low level again, the data is
then valid on the output with a very short Ton
delay(1ns).
The timing diagram page 4 summarizes this
operati ng cycle.
O ut of R ange (OR )
This function is implemented on the output stage
in order to set up an "Out of Range" flag whenever
the digital data is over the full scale range.
Typicall y, there is a det ecti on of all the dat a bei ng
at ’0’ or all the data being at ’1’. This ends up with
an output signal OR which is in low level state
(VOL) when the data stay within the range, or in
high level state (VOH) when the data are out of
the range.
Data Ready (DR)
The Data Ready output is an image of the clock
being synchronized on the output data (D0 to
D13). This is a very helpful signal that simplifies
the synchronization of the measurement
equipm ent or the controlling DSP.
As digital output, DR goes in high impedance
state when OEB is asserted to High level as
des cribed in the timing diagram page 4.
5.5 - Layout precaut ions
To use the T SA1401 circuit in the best manne r at
high frequencies, some precautions have to be
taken for power supplies:
- The separation of the analog signal from the
digital part and from the buffers power supply is
essen tial to prevent noise from coupl ing onto the
input signal.
- Power supply bypass capac itors must be placed
as close as possible to the IC pins in order to
improve high frequency bypassing and reduce
harmonic distortion.
- Proper termination of all inputs and outputs is
needed; with output termination resistors, the
amplifier load will be only resistiv e and the stability
of the amplifier will be improved. All leads must be
wide and as short as possible especially for the
analog input in order to decrease parasitic
capacit ance and inductance.
20
25
30
35
40
45
5101520
Fs (Mhz)
Ipol (mA)
0
20
40
60
80
100
120
140
Rpol (ohm)
Ipol_intref
Ipol_extref
Rpol
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
TSA 1401 APPL ICATION INF ORMATION
16/19
- To keep the capacitive loading as low as
possible at digital outputs, short lead lengths
when routing are essential to minimize currents
when the output changes. To minimi ze this output
cap acitance , buffers or latches close to the output
pins can relax this constraint. It is also helpful to
use 47 to 56 ohms series resistors at the ADC
output pins, located as close to the ADC output
pins as possible.
- Choose com ponent size s as small as possible
(SMD).
EVA L1 401 evaluati on board
The charac terization of t he bo ard has been made
with a fully ADC devoted test bench.
The schematic of the evaluation board is shown
on figure 19. The analog signal must be filtered to
be very pure.
The dataready signal is the acquisition clock of the
logic analyzer.
All characterization measurement has been made
with an input amplitude of +0.2dB for static
parame ters and -0.5dB for dynamic paramete rs
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
APPLICATIO N INFORMATION TSA1401
17/19
Fig. 19: TSA1401 Evaluation board schematic
5
5
4
4
3
3
2
2
1
1
D D
C C
B B
A A
DVDD
AVDD
DGND
AGND
DGND
CLK
CLK
VINP
VINM
AVDD
AVDD
VCMO
VDDBUF
REFP
GNDBUF
VDDBUF
AGND
INCM
AGND
REFM
AGND
AVDD
AGND
VCMO
DGND
DVDD
VDDBUF
GNDBUF
GNDBUF
GNDBUF DGNDAGND
VINP
AGND
VINM
AGND
NODI
NODI
IPOL
REFP
REFM
AGND
INCM
AGND
VDDBUF
GNDBUF
IPOL
AGND
PWD
AVDD
AGND
PWD
AGND
Title
Size Document Number R e v
Da te: Sheet of
1 A
CVT_TQFP48_MB_V1
B
11Tuesday, October 08, 2002
CLOCK
Willy Beule STMicroelectronics Crolles
REFPVDDBUF
INCM
REFM
AVDD
VCMO
DVDD
VINP
VINM
50 ohms
50 ohms
50 ohms
C28
330pF
SM/C_0603
C17
10nF
SM/C_0603
PT3
PICOT/2pts
12
+
C25
47µF 16V
CAPA/POL/5.08
C23
10nF
SM/C_0603
R6 100
SM/R_0603
J3
SMB
SMB_T RANCHE
2
1
R4 100
SM/R_0603
J1
SMB
SMB_T RANCHE
2
1
+
C7
47µF 16V
CAPA/POL/5.08
PT11
PICOT/2pts
12
PT9
PICOT/2pts
12
TP3
picot
picot/1pts
1
1
R2 100
SM/R_0603
C35
10nF
SM/C_0603
+
C29
47µF 16V
CAPA/POL/5.08
J5
SMB
SMB_T RANCHE
2
1
U1
TQFP48
TQFP48
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12
12
13
13
14
14
15
15
16
16
17
17
18
18
19
19
20
20
21
21
22
22
23
23
24
24
25 25
26 26
27 27
28 28
29 29
30 30
31 31
32 32
33 33
34 34
35 35
36 36
37 37
38 38
39 39
40 40
41 41
42 42
43 43
44 44
45 45
46 46
47 47
48 48
+
C20
47µF 16V
CAPA/POL/5.08
F3
FIXATION CARTE
TROU FIXATION 3MM
11
SW1
inverseur
1
2
3
C6
330pF
SM/C_0603
C1
470nF
SM/C_0603
R8 100
SM/R_0603
B1 CALE DE PLACEMENT
CALE_MPG
11
22
C31
10nF
SM/C_0603
+
C21
47µF 16V
CAPA/POL/5.08
PT13
PICOT/2pts
12
C26
470nF
SM/C_0603
R14
47
SM/R_0603
+
C33
47µF 16V
CAPA/POL/5.08
C15
330pF
SM/C_0603
R16 100
SM/R_0603
PT4
PICOT/2pts
12
R13 100
SM/R_0603
J2
SMB
SMB_T RANCHE
2
1
PT2
PICOT/2pts
12
PT15
PICOT/2pts
12
R12
1K
SM/R_0603
C24
330pF
SM/C_0603
J10
SMA
SMA_T RANCHE
2
1
+
C9
47µF 16V
CAPA/POL/5.08
C11
10nF
SM/C_0603
+
C8
47µF 16V
CAPA/POL/5.08
C4
470nF
SM/C_0603
C2
10nF
SM/C_0603
PT8
PICOT/2pts
12
PT6
PICOT/2pts
12
R19 100
SM/R_0603
C18
330pF
SM/C_0603
R9
50K
R_VARIABLE
1 3
2
TP2
picot
picot/1pts
1
1
C38
0pF
SM/C_0603
F4
FIXATION CARTE
TROU FIXATION 3MM
11
C27
10nF
SM/C_0603
R5 100
SM/R_0603
C13
470nF
SM/C_0603
R3 100
SM/R_0603
PT10
PICOT/2pts
12
J7
SMB
SMB_T RANCHE
2
1
C10
470nF
SM/C_0603
R1 100
SM/R_0603
C36
330pF
SM/C_0603
C22
470nF
SM/C_0603
J9
SMA
SMA_T RANCHE
2
1
R11 100
SM/R_0603
C32
330pF
SM/C_0603
R7 100
SM/R_0603
C5
10nF
SM/C_0603
R18
47
SM/R_0603
PT14
PICOT/2pts
12
PT12
PICOT/2pts
12
C16
470nF
SM/C_0603
C12
330pF
SM/C_0603
B3 CALE DE PLACEMENT
CALE_MPG
11
22
J6
SMB
SMB_T RANCHE
2
1
TP1
picot
picot/1pts
1
1
J8
SMA
SMA_T RANCHE
2
1
J4
SMB
SMB_T RANCHE
2
1
SW2
inverseur
1
2
3
+
C19
47µF 16V
CAPA/POL/5.08
F1
FIXATION CARTE
TROU FIXATION 3MM
11
PT5
PICOT/2pts
12
R15 100
SM/R_0603
C37 10nF
SM/C_0603
C14
10nF
SM/C_0603
F2
FIXATION CARTE
TROU FIXATION 3MM
11
PT1
PICOT/2pts
12
C34
470nF
SM/C_0603
C3
330pF
SM/C_0603
R10
47
SM/R_0603
C30
470nF
SM/C_0603
R20 100
SM/R_0603
PT7
PICOT/2pts
12
R17 100
SM/R_0603
B2 CALE DE PLACEMENT
CALE_MPG
11
22
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
TSA 1401 APPL ICATION INF ORMATION
18/19
Pr i nted circui t board - Li st of c om ponents
Reference Part
PCB F ootprint
B1,B2,B 3 CALE D E PLAC EM ENT C ALE_M PG
C1,C4,C10,C13,C16,C22, 470nF SM/C_0603
C26,C30,C34
C2,C5,C11,C14,C17,C23, 10nF SM/C_0603
C27,C31,C35,C37
C3,C6,C12,C15,C18,C24, 330pF SM/C_0603
C28,C32,C36
C7,C8,C9,C19,C20,C21,C25, 100 µF 16 V CAP A/POL/5 .08
C29,C33
C38 0pF SM/C_0603
J1,J2,J3,J4,J5,J6,J7 SMB SMB_TRANCHE
J8,J9,J10 SMA SMA_TRANCHE
PT1,PT2,PT3,PT4,PT5,PT6, picot PICOT/2pts
PT7,PT8,PT9,PT10,PT11,
PT12,PT13,PT14,PT15
R1,R2,R3,R4,R5,R6,R7,R8, 100 SM/R_0603
R11,R13,R15,R16,R17,R19,
R20
R9 200K R_VARIABLE
R10,R14,R18 49.9 SM/R_0603
R12 1K SM/R_0603
SW 1 ,SW 2 mic ro sw itch 1 in v ers eu r
TP1,TP2,TP3 picot picot/1pts
Obsolete Product(s) - Obsolete Product(s) Obsolete Product(s) - Obsolete Product(s)
PACKAGE MECHANICAL DATA TSA1401
19/19
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No li cense is granted by impl ication or otherw ise under any pa tent or patent rights of STMicroelectronics. Specifica tions
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without expre ss written approval of STMicroelectronics.
The ST logo is a registered tradem ark of STMicroelectroni cs
All o th er names are th e p r o p erty of th ei r r espective owners.
© 2003 STM icroe lectro n ics - All Rights Reserved
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6 PACKAGE MECHANICAL DATA
DIM. mm. inch
MIN. TYP MAX. MIN. TYP. MAX.
A 1.6 0.063
A1 0.05 0.15 0.002 0.006
A2 1.35 1.40 1.45 0.053 0.055 0.057
B 0.17 0.22 0.27 0.007 0.009 0.011
C 0.09 0.20 0.0035 0.0079
D 9.00 0.354
D1 7.00 0.276
D3 5.50 0.216
e 0.50 0.020
E 9.00 0.354
E1 7.00 0.276
E3 5.50 0.216
L 0.45 0.60 0.75 0.018 0.024 0.030
L1 1.00 0.039
K 0˚3.5˚7˚ 0˚3.5˚7˚
TQFP48 MECHANICAL DATA
0110596/C
