Semiconductor Components Industries, LLC, 2002
September, 2002 – Rev. 5 1Publication Order Number:
MC33363/D
MC33363
High Voltage Switching
Regulator
The MC 33363 i s a m onolithic h igh v oltage s witching r egulator t hat i s
specifically designed to operate from a rectified 240 Vac line source.
This integrated circuit features an on–chip 700 V/1.0 A SENSEFET
power switch, 450 V active off–line startup FET, duty cycle controlled
oscillator, current limiting comparator with a programmable threshold
and leading edge blanking, latching pulse width modulator for double
pulse suppression, high gain error amplifier, and a trimmed internal
bandgap reference. Protective features include cycle–by–cycle current
limiting, input undervoltage l ockout w ith h ysteresis, o utput o vervoltage
protection, and thermal shutdown. This device is available in a 16–lead
dual–in–line and wide body surface mount packages.
•On–Chip 700 V, 1.0 A SENSEFET Power Switch
•Rectified 240 Vac Line Source Operation
•On–Chip 450 V Active Off–Line Startup FET
•Latching PWM for Double Pulse Suppression
•Cycle–By–Cycle Current Limiting
•Input Undervoltage Lockout with Hysteresis
•Output Overvoltage Protection Comparator
•Trimmed Internal Bandgap Reference
•Internal Thermal Shutdown
This device contains 221 active transistors.
Startup
Reg
Osc
Thermal
LEB
PWM
DC Output
Startup Input
Gnd 4, 5, 12, 13
Mirror
7
AC Input
Regulator
Output
6
8
CT
RT
PWM Latch
EA
Ipk
VCC
3
11
16
9
10
1
Compensation
Voltage
Feedback
Input
Power Switch
Drain
Overvoltage
Protection
Input
Driver
OVP
UVLO
S
R
Q
Figure 1. Simplified Application
Device Package Shipping
ORDERING INFORMATION
MC33363DW SO–16W 47 Units/Rail
MC33363P PDIP–16 25 Units/Rail
MC33363DWR2 SO–16W 1000 Tape & Reel
MARKING
DIAGRAMS
A = Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
1
16
PDIP–16
P SUFFIX
CASE 648E
1
16
SO–16W
DW SUFFIX
CASE 751N
MC33363P
AWLYYWW
MC33363DW
AWLYYWW
http://onsemi.com
116
13
12
11
10
9
3
4
5
6
7
8
(Top View)
Startup Input
VCC
Gnd
RT
CT
Regulator Output
Power Switch
Drain
Gnd
Compensation
PIN CONNECTIONS
Overvoltage
Protection Input
Voltage Feedback
Input
MC33363
http://onsemi.com
2
MAXIMUM RATINGS (Note 1)
Rating Symbol Value Unit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Power Switch (Pin 16)
Drain Voltage
Drain Current
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
VDS
IDS
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
700
1.0
ÁÁÁ
Á
Á
Á
ÁÁÁ
V
A
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Startup Input Voltage (Pin 1, Note 2)
Pin 3 = Gnd
Pin 3 ≤ 1000 µF to ground
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Vin
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
400
500
ÁÁÁ
Á
Á
Á
ÁÁÁ
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Power Supply Voltage (Pin 3)
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC
ÁÁÁÁ
ÁÁÁÁ
40
ÁÁÁ
ÁÁÁ
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Voltage Range
Voltage Feedback Input (Pin 10)
Compensation (Pin 9)
Overvoltage Protection Input (Pin 11)
RT (Pin 6)
CT (Pin 7)
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
VIR
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
–1.0 to Vreg
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Thermal Characteristics
P Suffix, Dual–In–Line Case 648E
Thermal Resistance, Junction–to–Air
Thermal Resistance, Junction–to–Case
(Pins 4, 5, 12, 13)
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
RθJA
RθJC
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
80
15
ÁÁÁ
Á
Á
Á
Á
Á
Á
ÁÁÁ
°C/W
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DW Suffix, Surface Mount Case 751N
Thermal Resistance, Junction–to–Air
Thermal Resistance, Junction–to–Case
(Pins 4, 5, 12, 13)
Refer to Figures 15 and 16 for additional thermal information.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
RθJA
RθJC
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
95
15
ÁÁÁ
Á
Á
Á
Á
Á
Á
Á
Á
Á
ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Operating Junction Temperature
ÁÁÁÁÁ
ÁÁÁÁÁ
TJ
ÁÁÁÁ
ÁÁÁÁ
– 25 to +150
ÁÁÁ
ÁÁÁ
°C
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Storage Temperature
ÁÁÁÁÁ
ÁÁÁÁÁ
Tstg
ÁÁÁÁ
ÁÁÁÁ
– 55 to +150
ÁÁÁ
ÁÁÁ
°C
ELECTRICAL CHARACTERISTICS (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 µF, for typical values TJ = 25°C,
for min/max values TJ is the operating junction temperature range that applies (Note 3), unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
REGULATOR (Pin 8)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output Voltage (IO = 0 mA, TJ = 25°C)
ÁÁÁÁÁ
ÁÁÁÁÁ
Vreg
ÁÁÁÁ
ÁÁÁÁ
5.5
ÁÁÁÁ
ÁÁÁÁ
6.5
ÁÁÁÁ
ÁÁÁÁ
7.5
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Line Regulation (VCC = 20 V to 40 V)
ÁÁÁÁÁ
ÁÁÁÁÁ
Regline
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
30
ÁÁÁÁ
ÁÁÁÁ
500
mV
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Load Regulation (IO = 0 mA to 10 mA)
ÁÁÁÁÁ
ÁÁÁÁÁ
Regload
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
44
ÁÁÁÁ
ÁÁÁÁ
200
mV
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Total Output Variation over Line, Load, and Temperature
ÁÁÁÁÁ
ÁÁÁÁÁ
Vreg
ÁÁÁÁ
ÁÁÁÁ
5.3
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
8.0
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
OSCILLATOR (Pin 7)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Frequency
CT = 390 pF
TJ = 25°C (VCC = 20 V)
TJ = Tlow to Thigh (VCC = 20 V to 40 V)
CT = 2.0 nF
TJ = 25°C (VCC = 20 V)
TJ = Tlow to Thigh (VCC = 20 V to 40 V)
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
fOSC
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
260
255
60
59
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
285
–
67.5
–
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
310
315
75
76
Á
Á
Á
Á
kHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Frequency Change with Voltage (VCC = 20 V to 40 V)
ÁÁÁÁÁ
ÁÁÁÁÁ
∆fOSC/∆V
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
0.1
ÁÁÁÁ
ÁÁÁÁ
2.0
kHz
1. This device series contains ESD protection and exceeds the following tests:
Human Body Model 2000 V per MIL–STD–883, Method 3015.
Machine Model Method 200 V.
2. Maximum power dissipation limits must be observed.
3. Tested junction temperature range for the MC33363:
Tlow = –25°CT
high = +125°C
MC33363
http://onsemi.com
3
ELECTRICAL CHARACTERISTICS (continued) (VCC = 20 V, RT = 10 k, CT = 390 pF, CPin 8 = 1.0 µF, for typical values
TJ = 25°C, for min/max values TJ is the operating junction temperature range that applies (Note 4), unless otherwise noted.)
Characteristic Symbol Min Typ Max Unit
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ERROR AMPLIFIER (Pins 9, 10)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Voltage Feedback Input Threshold
ÁÁÁÁÁ
ÁÁÁÁÁ
VFB
ÁÁÁÁ
ÁÁÁÁ
2.52
ÁÁÁÁ
ÁÁÁÁ
2.6
ÁÁÁÁ
ÁÁÁÁ
2.68
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Line Regulation (VCC = 20 V to 40 V, TJ = 25°C)
ÁÁÁÁÁ
ÁÁÁÁÁ
Regline
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
0.6
ÁÁÁÁ
ÁÁÁÁ
5.0
mV
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Bias Current (VFB = 2.6 V)
ÁÁÁÁÁ
ÁÁÁÁÁ
IIB
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
20
ÁÁÁÁ
ÁÁÁÁ
500
nA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Open Loop Voltage Gain (TJ = 25°C)
ÁÁÁÁÁ
ÁÁÁÁÁ
AVOL
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
82
ÁÁÁÁ
ÁÁÁÁ
–
dB
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Gain Bandwidth Product (f = 100 kHz, TJ = 25°C)
ÁÁÁÁÁ
ÁÁÁÁÁ
GBW
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
1.0
ÁÁÁÁ
ÁÁÁÁ
–
MHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Output Voltage Swing
High State (ISource = 100 µA, VFB < 2.0 V)
Low State (ISink = 100 µA, VFB > 3.0 V)
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
VOH
VOL
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
4.0
–
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
5.3
0.2
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
–
0.35
Á
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
OVERVOLTAGE DETECTION (Pin 11)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Threshold Voltage
ÁÁÁÁÁ
ÁÁÁÁÁ
Vth
ÁÁÁÁ
ÁÁÁÁ
2.47
ÁÁÁÁ
ÁÁÁÁ
2.6
ÁÁÁÁ
ÁÁÁÁ
2.73
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Input Bias Current (Vin = 2.6 V)
ÁÁÁÁÁ
ÁÁÁÁÁ
IIB
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
100
ÁÁÁÁ
ÁÁÁÁ
500
nA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PWM COMPARATOR (Pins 7, 9)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Duty Cycle
Maximum (VFB = 0 V)
Minimum (VFB = 2.7 V)
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
DC(max)
DC(min)
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
48
–
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
50
0
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
52
0
Á
%
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
POWER SWITCH (Pin 16)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Drain–Source On–State Resistance (ID = 200 mA)
TJ = 25°C
TJ = Tlow to Thigh
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
RDS(on)
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
–
–
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
14
–
ÁÁÁÁ
Á
ÁÁ
Á
ÁÁÁÁ
17
32
Á
Ω
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Drain–Source Off–State Leakage Current (VDS = 700 V)
ÁÁÁÁÁ
ÁÁÁÁÁ
ID(off)
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
0.2
ÁÁÁÁ
ÁÁÁÁ
50
µA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Rise Time
ÁÁÁÁÁ
ÁÁÁÁÁ
tr
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
50
ÁÁÁÁ
ÁÁÁÁ
–
ns
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Fall Time
ÁÁÁÁÁ
ÁÁÁÁÁ
tf
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
50
ÁÁÁÁ
ÁÁÁÁ
–
ns
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
OVERCURRENT COMPARATOR (Pin 16)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Current Limit Threshold (RT = 10 k)
ÁÁÁÁÁ
ÁÁÁÁÁ
Ilim
ÁÁÁÁ
ÁÁÁÁ
0.5
ÁÁÁÁ
ÁÁÁÁ
0.72
ÁÁÁÁ
ÁÁÁÁ
0.9
A
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
STARTUP CONTROL (Pin 1)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Peak Startup Current (Vin = 400 V)
VCC = 0 V
VCC = (Vth(on) – 0.2 V)
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
Istart
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
–
–
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
20
6.0
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
–
–
Á
Á
mA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Off–State Leakage Current (Vin = 50 V, VCC = 20 V)
ÁÁÁÁÁ
ÁÁÁÁÁ
ID(off)
ÁÁÁÁ
ÁÁÁÁ
–
ÁÁÁÁ
ÁÁÁÁ
40
ÁÁÁÁ
ÁÁÁÁ
200
µA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
UNDERVOLTAGE LOCKOUT (Pin 3)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Startup Threshold (VCC Increasing)
ÁÁÁÁÁ
ÁÁÁÁÁ
Vth(on)
ÁÁÁÁ
ÁÁÁÁ
11
ÁÁÁÁ
ÁÁÁÁ
15.2
ÁÁÁÁ
ÁÁÁÁ
18
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Minimum Operating Voltage After Turn–On
ÁÁÁÁÁ
ÁÁÁÁÁ
VCC(min)
ÁÁÁÁ
ÁÁÁÁ
7.5
ÁÁÁÁ
ÁÁÁÁ
9.5
ÁÁÁÁ
ÁÁÁÁ
11.5
V
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
TOTAL DEVICE (Pin 3)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Power Supply Current
Startup (VCC = 10 V, Pin 1 Open)
Operating
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
ICC
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
–
–
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
0.25
3.2
ÁÁÁÁ
Á
ÁÁ
Á
Á
ÁÁ
Á
ÁÁÁÁ
0.5
5.0
Á
Á
mA
4. Tested junction temperature range for the MC33363:
Tlow = –25°CT
high = +125°C
MC33363
http://onsemi.com
4
RT, TIMING RESISTOR (kΩ)
1.0
7.0
1.0 M
IPK, POWER SWITCH PEAK DRAIN CURRENT (A)
VCC = 20 V
CT = 1.0 µF
TA = 25°C
fOSC, OSCILLATOR FREQUENCY (Hz)
Figure 1. Oscillator Frequency
versus Timing Resistor
RT, TIMING RESISTOR (kΩ)
Figure 2. Power Switch Peak Drain Current
versus Timing Resistor
500 k
200 k
100 k
50 k
20 k
10 k
0.8
0.6
0.4
0.2
0.1
10 15 20 30 50 7.0 10 15 20 30 40 70
VCC = 20 V
TA = 25°C
CT = 100 pF
CT = 200 pF
CT = 500 pF
CT = 1.0 nF
CT = 2.0 nF
CT = 5.0 nF
CT = 10 nF
Inductor supply voltage and inductance value are
adjusted so that Ipk turn-off is achieved at 5.0 µs.
70 50
1.0
70
7.0
0.8
Dmax, MAXIMUM OUTPUT DUTY CYCLE (%)
TIMING RESISTOR RATIO
Ichg , OSCILLATOR
Figure 3. Oscillator Charge/Discharge
Current versus Timing Resistor
RT, TIMING RESISTOR (kΩ)
Figure 4. Maximum Output Duty Cycle
versus Timing Resistor Ratio
/I dscg
CHARGE/DISCHARGE CURRENT (mA)
0.5
0.3
0.2
0.15
0.1
0.08
60
50
40
30
10 15 20 30 70 2.0 3.0 5.0 7.0 10
RD/RT Ratio
Discharge Resistor
Pin 6 to Gnd
VCC = 20 V
CT = 2.0 nF
TA = 25°C
RC/RT Ratio
Charge Resistor
Pin 6 to Vreg
VCC = 20 V
TA = 25°C
50
0
0
10
100
Vsat, OUTPUT SATURATION VOLTAGE (V)
IO, OUTPUT LOAD CURRENT (mA)
AVOL, OPEN LOOP VOLTAGE GAIN (dB)
f, FREQUENCY (Hz)
Figure 5. Error Amp Open Loop Gain and
Phase versus Frequency Figure 6. Error Amp Output Saturation
Voltage versus Load Current
θ, EXCESS PHASE (DEGREES)
80
60
40
20
0
-20
-1.0
-2.0
2.0
1.0
0
100 1.0 k 10 k 100 k 1.0 M 10 M 0.2 0.4 0.6 0.8 1.0
0
30
60
90
120
150
180
VCC = 20 V
VO = 1.0 to 4.0 V
RL = 5.0 MΩ
CL = 2.0 pF
TA = 25°C
Gain
Phase
Source Saturation
(Load to Ground)
Sink Saturation
(Load to Vref)VCC = 20 V
TA = 25°C
Gnd
Vref
MC33363
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5
1.80 V
0.5 V/DIV
1.0 µs/DIV
20 mV/DIV
1.0 µs/DIV
VCC = 20 V
AV = -1.0
CL = 10 pF
TA = 25°C
Figure 7. Error Amplifier Small Signal
Transient Response Figure 8. Error Amplifier Large Signal
Transient Response
VCC = 20 V
AV = -1.0
CL = 10 pF
TA = 25°C
1.75 V
1.70 V
3.00 V
1.75 V
0.50 V
0
20
0
0
Ipk, PEAK STARTUP CURRENT (mA)
VCC, POWER SUPPLY VOLTAGE (V)
VPin 1 = 400 V
TA = 25°C
Vreg, REGULATOR VOLTAGE CHANGE (mV)
Figure 9. Regulator Output Voltage
Change versus Source Current
Ireg, REGULATOR SOURCE CURRENT (mA)
Figure 10. Peak Startup Current
versus Power Supply Voltage
VCC = 20 V
RT = 10 k
CPIN 8 = 1.0 µF
TA = 25°C
Pulse tested with an on-time of 20 µs to 300 µs
at < 1.0% duty cycle. The on-time is adjusted at
Pin 1 for a maximum peak current out of Pin 3.
∆
-20
-40
-60
-80
10
0
4.0 8.0 12 16 20 2.0 4.0 6.0 8.0 10 12 14
1.0
160
-50
32
COSS, DRAIN-SOURCE CAPACITANCE (pF)
VDS, DRAIN-SOURCE VOLTAGE (V)
VCC = 20 V
TA = 25°C
RDS(on), DRAIN-SOURCE ON-RESISTANCE ( )Ω
TA, AMBIENT TEMPERATURE (°C)
ID = 200 mA
Figure 11. Power Switch Drain–Source
On–Resistance versus Temperature Figure 12. Power Switch
Drain–Source Capacitance versus Voltage
Pulse tested at 5.0 ms with < 1.0% duty cycle
so that TJ is as close to TA as possible. COSS measured at 1.0 MHz with 50 mVpp.
24
16
8.0
0
120
40
80
0
-25 0 25 50 75 150100 10 100 1000125
MC33363
http://onsemi.com
6
0
3.2
ICC, SUPPLY CURRENT (mA)
VCC, SUPPLY VOLTAGE (V)
CT = 390 pF
Figure 13. Supply Current versus Supply Voltage
CT = 2.0 nF
RT = 10 k
Pin 1 = Open
Pin 4, 5, 10, 11,
12, 13 = Gnd
TA = 25°C
2.4
1.6
0.8
010 20 30 40 0.01
100
RJA , THERMAL RESISTANCE
t, TIME (s)
Figure 14. DW and P Suffix Transient
Thermal Resistance
θ
JUNCTION-TO-AIR ( C/W)°
0.1 1.0 10 100
10
1.0
L = 12.7 mm of 2.0 oz.
copper. Refer to Figures
15 and 16.
0
100
RJA , THERMAL RESISTANCE
L, LENGTH OF COPPER (mm)
PD(max) for TA = 50°C
Figure 15. DW Suffix (SOP–16L) Thermal Resistance and
Maximum Power Dissipation versus P.C.B. Copper Length
θ
JUNCTION-TO-AIR ( C/W)°
PD, MAXIMUM POWER DISSIPATION (W)
RθJA
90
70
60
80
50
10 20 30 40 50
2.8
2.4
1.6
1.2
2.0
0.8
0.4
0
40
30 00
Figure 16. P Suffix (DIP–16) Thermal Resistance and
Maximum Power Dissipation versus P.C.B. Copper Length
ÏÏÏ
ÏÏÏ
Graphs represent symmetrical layout
3.0 mm
Printed circuit board heatsink example
L
L
100
80
60
40
20
10 20 30 40 50
L, LENGTH OF COPPER (mm)
PD, MAXIMUM POWER DISSIPATION (W)
5.0
4.0
3.0
2.0
1.0
0
PD(max) for TA = 70°C
2.0 oz
Copper
ÏÏÏ
ÏÏÏ
RθJA
R , THERMAL RESISTANCE
JAθ
JUNCTION-TO-AIR ( C/W)°
ÏÏÏ
ÏÏÏ
ÏÏÏ
Graphs represent symmetrical layout
3.0 mm
L
L2.0 oz
Copper
ÏÏ
ÏÏ
ÏÏ
Printed circuit board heatsink example
MC33363
http://onsemi.com
7
PIN FUNCTION DESCRIPTION
Pin Function Description
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
1
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Startup Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This pin connects directly to the rectified ac line voltage source. Internally Pin 1 is tied to the
drain of a high voltage startup MOSFET. During startup, the MOSFET supplies internal bias, and
charges an external capacitor that connects from the VCC pin to ground.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
2
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This pin has been omitted for increased spacing between the rectified ac line voltage on Pin 1
and the VCC potential on Pin 3.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
3
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
VCC
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This is the positive supply voltage input. During startup, power is supplied to this input from
Pin 1. When VCC reaches the UVLO upper threshold, the startup MOSFET turns off and power is
supplied from an auxiliary transformer winding.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
4, 5, 12, 13
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Ground
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
These pins are the control circuit grounds. They are part of the IC lead frame and provide a
thermal path from the die to the printed circuit board.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
6
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
RT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Resistor RT connects from this pin to ground. The value selected will program the Current Limit
Comparator threshold and affect the Oscillator frequency.
ÁÁÁÁÁ
ÁÁÁÁÁ
7
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
CT
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Capacitor CT connects from this pin to ground. The value selected, in conjunction with resistor
RT, programs the Oscillator frequency.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
8
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Regulator Output
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This 6.5 V output is available for biasing external circuitry. It requires an external bypass
capacitor of at least 1.0 µF for stability.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
9
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Compensation
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This pin is the Error Amplifier output and is made available for loop compensation. It can be used
as an input to directly control the PWM Comparator.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
10
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Voltage Feedback
Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This is the inverting input of the Error Amplifier. It has a 2.6 V threshold and normally connects
through a resistor divider to the converter output, or to a voltage that represents the converter
output.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
Á
ÁÁÁ
Á
ÁÁÁÁÁ
11
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
Overvoltage
Protection Input
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This input provides runaway output voltage protection due to an external component or
connection failure in the control loop feedback signal path. It has a 2.6 V threshold and normally
connects through a resistor divider to the converter output, or to a voltage that represents the
converter output.
ÁÁÁÁÁ
Á
ÁÁÁ
Á
ÁÁÁÁÁ
14, 15
ÁÁÁÁÁÁ
Á
ÁÁÁÁ
Á
ÁÁÁÁÁÁ
–
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Á
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
These pins have been omitted for increased spacing between the high voltages present on the
Power Switch Drain, and the ground potential on Pins 12 and 13.
ÁÁÁÁÁ
ÁÁÁÁÁ
16
ÁÁÁÁÁÁ
ÁÁÁÁÁÁ
Power Switch Drain
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
This pin is designed to directly drive the converter transformer and is capable of switching a
maximum of 700 V and 1.0 A.
MC33363
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8
Figure 17. Representative Block Diagram
Oscillator
PWM
PWM Latch
Current Limit
Thermal
Shutdown
Error
Startup
Control
Band Gap
Regulator UVLO
14.5 V/
9.5 V
OVP 2.6 V
Current
2.6 V
Regulator Output
6.5 V
R
C
8
6
7
4, 5, 12, 13Gnd
11
16
9
10
1
Voltage
Compensation
Power Switch
Overvoltage
AC Input
DC Output
2.25 I
I
9.0
R
S
Q
Driver
3
Startup Input
450
T
T
Comparator
Leading Edge
Blanking
Mirror
4 I
270 µA
VCC
Comparator
Protection
Input
Drain
Feedback Input
Amplifier
Figure 18. Timing Diagram
Capacitor C
Compensation
PWM
Comparator
Output
Oscillator Output
PWM Latch
Q Output
Power Switch
Gate Drive
Leading Edge
Blanking Input
(Power Switch
Drain Current)
Normal PWM Operating Range Output Overload
Current
Limit
Threshold
0.6 V
2.6 V
Current Limit
Propagation
Delay
T
MC33363
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9
OPERATING DESCRIPTION
Introduction
The MC33363 represents a new higher level of integration
by providing all the active high voltage power, control, and
protection circuitry required for implementation of a
flyback or forward converter on a single monolithic chip.
This device is designed for direct operation from a rectified
240 Vac line source and requires a minimum number of
external components to implement a complete converter. A
description of each of the functional blocks is given below,
and the representative block and timing diagrams are shown
in Figures 17 and 18.
Oscillator and Current Mirror
The oscillator frequency is controlled by the values
selected for the timing components RT and CT. Resistor RT
programs the oscillator charge/discharge current via the
Current Mirror 4 I output, Figure 3. Capacitor CT is char ged
and discharged by an equal magnitude internal current
source and sink. This generates a symmetrical 50 percent
duty cycle waveform at Pin 7, with a peak and valley
threshold of 2.6 V and 0.6 V respectively. During the
discharge o f CT, the oscillator generates an internal blanking
pulse that holds the inverting input of the AND gate Driver
high. This causes the Power Switch gate drive to be held in
a low state, thus producing a well controlled amount of
output deadtime. The amount of deadtime is relatively
constant with respect to the oscillator frequency when
operating below 1.0 MHz. The maximum Power Switch
duty cycle at Pin 16 can be modified from the internal 50%
limit by providing an additional charge or discharge current
path t o C T, Figure 19. In order to increase the maximum duty
cycle, a discharge current resistor RD is connected from
Pin 7 to ground. To decrease the maximum duty cycle, a
charge current resistor RC is connected from Pin 7 to the
Regulator Output. Figure 4 shows an obtainable range of
maximum output duty cycle versus the ratio of either R C or
RD with respect to RT.
Figure 19. Maximum Duty Cycle Modification
PWM
Current
Regulator Output
1.0
R
C
8
6
2.25 I
I
T
T
Mirror
4 I
Oscillator
Comparator
RD
RC
7
Current
Limit
Reference
Blanking
Pulse
The formula for the charge/discharge current along with
the oscillator frequency are given below. The frequency
formula is a first order approximation and is accurate for C T
values greater than 500 pF. For smaller values of CT, refer to
Figure 1. Note that resistor RT also programs the Current
Limit Comparator threshold.
Ichgdscg 5.4
RTf
Ichgdscg
4CT
PWM Comparator and Latch
The pulse width modulator consists of a comparator with
the oscillator ramp voltage applied to the non–inverting
input, while the error amplifier output is applied into the
inverting input. The Oscillator applies a set pulse to the
PWM Latch while CT is dischar ging, and upon reaching t h e
valley voltage, Power Switch conduction is initiated. When
CT charges to a voltage that exceeds the error amplifier
output, the PWM Latch is reset, thus terminating Power
Switch conduction for the duration of the oscillator ramp–up
period. This PWM Comparator/Latch combination
prevents multiple output pulses during a given oscillator
clock cycle. The timing diagram shown in Figure 18
illustrates the Power Switch duty cycle behavior versus the
Compensation voltage.
Current Limit Comparator and Power Switch
The MC33363 uses cycle–by–cycle current limiting as a
means of protecting the output switch transistor from
overstress. Each on–cycle is treated as a separate situation.
Current limiting is implemented by monitoring the output
switch current buildup during conduction, and upon sensing
an overcurrent condition, immediately turning off the switch
for the duration of the oscillator ramp–up period.
The Power Switch is constructed as a SENSEFET
allowing a virtually lossless method of monitoring the drain
current. It consists of a total of 1780 cells, of which 46 are
connected to a 9.0 Ω ground–referenced sense resistor. The
Current Sense Comparator detects if the voltage across the
sense resistor exceeds the reference level that is present at
the inverting input. If exceeded, the comparator quickly
resets the PWM Latch, thus protecting the Power Switch.
The current limit reference level is generated by the 2.25 I
output of the Current Mirror. This current causes a reference
voltage to appear across the 450 Ω resistor. This voltage
level, as well as the Oscillator charge/discharge current are
both set by resistor RT. Therefore when selecting the values
for RT and CT, RT must be chosen first to set the Power
Switch peak drain current, while CT is chosen second to set
the desired Oscillator frequency. A graph of the Power
Switch peak drain current versus RT is shown in Figure 2
with the related formula below.
Ipk 8.8 RT
1000– 1.077
MC33363
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10
The Power Switch is designed to directly drive the converter
transformer and is capable of switching a maximum of
700 V and 1.0 A. Proper device voltage snubbing and
heatsinking are required for reliable operation.
A Leading Edge Blanking circuit was placed in the current
sensing signal path. This circuit prevents a premature reset
of the PWM Latch. The premature reset is generated each
time the Power Switch is driven into conduction. It appears
as a narrow voltage spike across the current sense resistor,
and is due to the MOSFET gate to source capacitance,
transformer interwinding capacitance, and output rectifier
recovery time. The Leading Edge Blanking circuit has a
dynamic behavior in that it masks the current signal until the
Power Switch turn–on transition is completed. The current
limit propagation delay time is typically 233 ns. This time is
measured from when an overcurrent appears at the Power
Switch drain, to the beginning of turn–off.
Error Amplifier
An fully compensated Error Amplifier with access to the
inverting input a nd o utput i s p rovided f or p rimary s ide v oltage
sensing, Figure 17 . It features a typical dc voltage gain of 82
dB, and a u nity g ain b andwidth o f 1 .0 MHz w ith 7 8 d egrees o f
phase margin, Figure 5. The noninverting input is internally
biased at 2.6 V ±3.1% and is not pinned out. The Error
Amplifier output is p inned out f or external loop c ompensation
and as a m eans f or directly d riving t he P WM C omparator. T he
output was designed with a limited sink current capability of
270 µA, allowing it to be easily overridden with a pull–up
resistor. This is d esirable i n a pplications t hat r equire s econdary
side voltage s ensing, F igure 20. In t his a pplication, t he Voltage
Feedback Input is connected to the Regulator Output. This
disables the Error Amplifier by p lacing its o utput into t he s ink
state, a llowing t he o ptocoupler t ransistor to d irectly c ontrol t he
PWM Comparator.
Overvoltage Protection
An Overvoltage Protection Comparator is included to
eliminate the possibility of runaway output voltage. This
condition can occur if the control loop feedback signal path
is broken due to an external component or connection
failure. The comparator is normally used to monitor the
primary side VCC voltage. When the 2.6 V threshold is
exceeded, i t will immediately turn of f the Power Switch, and
protect the load from a severe overvoltage condition. This
input can also be driven from external circuitry to inhibit
converter operation.
Undervoltage Lockout
An Undervoltage Lockout comparator has been
incorporated to guarantee that the integrated circuit has
sufficient voltage to be fully functional before the output
stage is enabled. The UVLO comparator monitors the VCC
voltage at Pin 3 and when it exceeds 14.5 V, the reset signal
is removed from the PWM Latch allowing operation of the
Power Switch. To prevent erratic switching as the threshold
is crossed, 5.0 V of hysteresis is provided.
Startup Control
An internal Startup Control circuit with a high voltage
enhancement mode MOSFET is included within the
MC33363. This circuitry allows for increased converter
efficiency b y eliminating the external startup resistor, and its
associated power dissipation, commonly used in most
off–line converters that utilize a UC3842 type of controller.
Rectified ac line voltage is applied to the Startup Input,
Pin 1. This causes the MOSFET to enhance and supply
internal bias as well as charge current to the VCC bypass
capacitor that connects from Pin 3 to ground. When VCC
reaches the UVLO upper threshold of 15.2 V, the IC
commences operation and the startup MOSFET is turned
off. Operating bias is now derived from the auxiliary
transformer winding, and all of the device power is
efficiently converted down from the rectified ac line.
The startup MOSFET will provide an initial peak current
of 20 mA, Figure 10, which decreases rapidly as VCC and
the die temperature rise. The steady state current will self
limit in the range of 8.0 mA with VCC shorted to ground. The
startup MOSFET is rated at a maximum of 400 V with V CC
shorted to ground, and 500 V when charging a VCC
capacitor of 1000 µF or less.
Regulator
A low current 6.5 V regulated output is available for
biasing the Error Amplifier and any additional control
system circuitry. It is capable of up to 10 mA and has
short–circuit protection. This output requires an external
bypass capacitor of at least 1.0 µF for stability.
Thermal Shutdown and Package
Internal thermal circuitry is provided to protect the Power
Switch in the event that the maximum junction temperature
is exceeded. W hen a ctivated, typically a t 1 55°C, the Latch is
forced into a ‘reset’ state, disabling the Power Switch. The
Latch is allowed t o ‘set’ when the Power Switch t emperature
falls below 145°C. This feature is provided to prevent
catastrophic f ailures f rom a ccidental d evice o verheating. I t i s
not intended t o b e u sed as a s ubstitute f or p roper h eatsinking.
The MC33363 is contained in a heatsinkable plastic
dual–in–line p ackage i n w hich t he d ie i s m ounted o n a s pecial
heat tab c opper a lloy l ead f rame. T his t ab consists o f the f our
center ground pins that are specifically designed to improve
thermal conduction from the die to the circuit board.
Figures 15 and 16 show a simple and effective method of
utilizing the p rinted c ircuit b oard medium as a h eat d issipater
by s oldering t hese p ins t o a n a dequate area o f c opper f oil. T his
permits the use of standard layout and mounting practices
while having the ability to halve the junction to air thermal
resistance. The examples are for a symmetrical layout on a
single–sided board w ith t wo o unce per square f oot o f c opper.
Figure 2 2 s hows a p ractical e xample o f a p rinted circuit b oard
layout that utilizes the copper foil as a heat dissipater. Note
that a jumper was added to the layout from Pins 8 to 10 in
order t o enhance t he c opper a rea near t he d evice f or i mproved
thermal conductivity. The application circuit requires two
ounce copper foil in order to obtain 8.0 watts of continuous
output power at room temperature.
MC33363
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11
Figure 20. 8.0 W Off–Line Converter
Osc
PWM
PWM Latch
Thermal
EA
Startup
Reg
UVLO
14.5 V/
9.5 V
OVP
2.6 V
2.6 V
R1
8
6
7
4, 5, 12, 13
11
16
9
10
1
92 to 276
5.05 V/1.6
A
R
S
Q
Driver
3
LEB
Mirror
270 µA
15 k
Vac Input
C3
820 pF
C4
1.0
R2
2.7 k
IC1 MC33363
5
4
R4
5.1 k
R3
1.0 k
C2
10
C1
33
C6
47 pF
C5
4.0 nF
R6
180 k
1.0 W
DC Output
C12
1.0
C11
220
R8
220
R9
2.80 k
C7
100 nF
1
2
31
2
R10
2.74 k
IC3
TL431B
C8
330
C9
330
C10
330
T1
D6
MUR
120
R5
39
D5
MUR
1100E
L1
5.0 µH
R7
2.2 k
1.0 W
IC2
MOC
8103
1N4006
D3
D4
D2 D1
F1
1.0 A
ILimit
D7
MBR
1635
Test Conditions Results
Line Regulation Vin = 92 Vac to 276 Vac, IO 1.6 A ∆ = 1.0 mV
Load Regulation Vin = 115 Vac, IO = 0.4 A to 1.6 A ∆ = 4.0 mV
g
Vin = 230 Vac, IO = 0.4 A to 1.6 A ∆ = 4.0 mV
Output Ripple Vin = 115 Vac, IO = 1.6 A Triangular = 2.0 mVpp, Spike = 12 mVpp
Vin = 230 Vac, IO = 1.6 A Triangular = 2.0 mVpp, Spike = 12 mVpp
Efficiency Vin = 115 Vac, IO = 1.6 A 78.6%*
y
Vin = 230 Vac, IO = 1.6 A 75.6%
This data was taken with the components listed below mounted on the printed circuit board shown in Figure 22.
* With MBR2535CTL, 79.8% efficiency. PCB layout modification is required to use this rectifier.
For high efficiency and small circuit board size, the Sanyo Os–Con capacitors are recommended for C8, C9, C10 and C11.
C8, C9, C10 = Sanyo Os–Con #6SA330M, 330 µF 6.3 V.
C11 = Sanyo Os–Con #10SA220M, 220 µF 10 V.
L1 = Coilcraft S5088–A, 5.0 µH, 0.11 Ω.
T1 = Coilcraft S5502–A
Primary: 77 turns of # 28 AWG, Pin 1 = start, Pin 8 = finish.
Two layers 0.002″ Mylar tape.
Secondary: 5 turns of # 22 AWG, 2 strands bifiliar wound, Pin 5 = start, Pin 4 = finish.
Two layers 0.002″ Mylar tape.
Auxiliary: 13 turns of # 28 AWG wound in center of bobbin, Pin 2 = start, Pin 7 = finish.
Two layers 0.002″ Mylar tape.
Gap: 0.006″ total for a primary inductance (LP) of 1.0 mH.
Core and Bobbin: Coilcraft PT1950, E187, 3F3 material.
Figure 21. Converter Test Data
MC33363
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12
Figure 22. Printed Circuit Board and Component Layout (Circuit of Figure 20)
MC33363
(Top View)
(Bottom View)
2.25"
2.75"
Caution!
High
Voltages
D1
D2
F1
T1
C1 R6
C5
C6
D6
IC2
D4
D3
AC
Line
Input
R4
R1
R2
J1
R3
C9
C10
IC3
DC Output
C4
R8 L1
D7
C3
C7
R10
C8
R9
C11
R7
D5
C2
R3
IC1
C12
R5
1
MC33363
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13
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
CASE 648E–01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION A AND B DOES NOT INCLUDE MOLD
PROTRUSION.
5. MOLD FLASH OR PROTRUSIONS SHALL NOT
EXCEED 0.25 (0.010).
6. ROUNDED CORNER OPTIONAL.
–A–
–B–
16 9
18
D
GH
S
C
13 PL
S
B
M
0.25 (0.010) T
–T–
SEATING
PLANE
J
M
L
R
PF
K
S
A
DIM MIN MAX MIN MAX
MILLIMETERSINCHES
A0.740 0.760 18.80 19.30
B0.245 0.260 6.23 6.60
C0.145 0.175 3.69 4.44
D0.015 0.021 0.39 0.53
F0.050 0.070 1.27 1.77
G0.100 BSC 2.54 BSC
H0.050 BSC 1.27 BSC
J0.008 0.015 0.21 0.38
K0.120 0.140 3.05 3.55
L0.295 0.305 7.50 7.74
M0 10 0 10
P0.200 BSC 5.08 BSC
R0.300 BSC 7.62 BSC
S0.015 0.035 0.39 0.88
 
SO–16W
DW SUFFIX
CASE 751N–01
ISSUE O
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A10.15 10.45 0.400 0.411
B7.40 7.60 0.292 0.299
C2.35 2.65 0.093 0.104
D0.35 0.49 0.014 0.019
F0.50 0.90 0.020 0.035
G1.27 BSC 0.050 BSC
J0.25 0.32 0.010 0.012
K0.10 0.25 0.004 0.009
M0 7 0 7
P10.05 10.55 0.395 0.415
R0.25 0.75 0.010 0.029
M
B
M
0.010 (0.25)
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER
SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN
EXCESS OF D DIMENSION AT MAXIMUM
MATERIAL CONDITION.
–A–
–B– P
G
9X
D13X
SEATING
PLANE
–T–
S
A
M
0.010 (0.25) B S
T
16 9
81
F
J
RX 45

M
T
S
S2.54 BSC 0.100 BSC
T3.81 BSC 0.150 BSC
C
K
MC33363
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14
Notes
MC33363
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15
Notes
MC33363
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16
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changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any
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2–9–1 Kamimeguro, Meguro–ku, Tokyo, Japan 153–0051
Phone: 81–3–5773–3850
Email: r14525@onsemi.com
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For additional information, please contact your local
Sales Representative.
MC33363/D
The product described herein (MC33363), may be covered by one or more of the following U.S. patents: 4,553,084; 5,418,410;
5,477,175. There may be other patents pending.
SENSEFET is a trademark of Semiconductor Components Industries, LLC (SCILLC)
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