2013/3/1 Evaluation Evaluation board board circuit circuit diagram diagram and and implementation implementation <MN63Y1208> <MN63Y1208> Ver 1.2 2013/3/1 Semiconductor Business Group Industrial Devices Company Panasonic Corporation 2 List of pin placement / pins of the NFC tag 2013/3/1 Fig. List of pin placement Tab. Pins of the NFC tag PIN Number Terminal name Input/output 1 VB I/O 2 VDDEX 3 VSS 4 VA I/O 5 N.C. 6 VDDD 7 TEST1 input 8 N.C. 9 NIRQ output 10 TEST3 input 11 SCL input 12 SDA I/O 13 N.C. 14 TEST4 input 15 TEST2 input 16 VDDA Input and output type Power GND Power Open Drain Open Drain Power function Coil terminal Power supply for contact (Input 1.7V 3.6V) Ground Coil terminal Unconnected pin Digital internal power supply (Connect capacitance between VSS) Test control (Normally connected to VSS) Unconnected pin Interrupt request output Test control (Normally connected to VSS) HOST I/F (I2C 100kHz) HOST I/F (I2C 100kHz) Unconnected pin Test control (Normally connected to VSS) Test control (Normally connected to VSS) Analog internal power supply (Connect capacitance between VSS) Figure of pattern of the evaluation board Chip and Parts are implemented by the antenna board surface Connect with the other board R0 C2 VDD VDDEX MN63Y1208 R NIRQ R2 SDA SCL R VSS C3 C4 3 External part Recommendation Value Detailed explanation R1,R2 3.3k It is pulling up resistance for I2C signal lines.Please decide the resistance level in consideration of transmission rate, wiring capacity, current ability. In our NFC tag board "ANT4030_02_0505_B0_L ," it is not implemented. R3 3.3k It is pulling up resistance for interrupt signal lines. Please decide the resistance level in consideration of wiring capacity, current ability. In our NFC tag board "ANT4030_02_0505_B0_L ," it is not implemented. C2C3C4 0.1F It is a fixed value at the capacity between the power supply for operation stabilization of the tag LSI. C2 is connected to VDDD, and C3 is connected to VDDA and C4 is connected to VDDEX R0 100k It is pulling up resistance to prevent an uncertainty state of SCL causing the malfunction. When NFC tag LSI has the terms of use that R1 is not connected to, I am necessary. I connect pulling up resistance (R,R2,R3) to the microcomputer board of our offer. 2013/3/1 Connection example with the MCU board 2013/3/1 NFC tag system constitution Antenna Board Control Board TAG circuit Antenna MN63Y1208 Antenna ANT4030_02_0505_B0_L Antenna Board 3.3V R3 SCL SCL SDA C2 SDA NIRQ NIRQ IRQ TEST3 R1 SCL R2 SDA VDDEX 9 8 7 6 5 VA 11 C0 4 10 MN63Y1208 3 2 1213 14 15 16 1 NC R0 GPIO Antenna TAG circuit VSS TEST1 MCU Board VDDD NC Host Controller Host Controller RF I2C NC 4 VSS VB VDDA TEST4 TEST2 C4 VDDEX C3 5 Implementation of the evaluation board Chip and Parts are implemented by the board surface R0 C2 C0 MN63Y1208 C3 C4 Antenna is implemented by the board back side 2013/3/1 6 Connector specifications 2013/3/1 Connection image Micon Board [BTPB101-B] Antenna Board [ANT4030_02_0505_B0_L] MCU Board DF11CZ-8DP-2V(27) [BTPB-101B] ( Hirose Electric ) VSS SDA SCL NIRQ VDDEX VDDEX HRS DF11CZ- 8DS-2V NIRQ ( Hirose Electric ) SDA SCL VSS Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed. 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