TECHNICAL NOTE
High-performance Regulator IC Series for PCs
Ultra Low Dropout
Linear Regulators(4A) for Desktop PC
BD3522EFV, BD35221EFV, BD35222EFV
● Description
BD3522EFV / BD35221EFV / BD35222EF V ultra lo w-dropo ut linear chipset regulator operates from a very lo w input supply,
and offers ideal performance in low input voltage to low output voltage applications. It incorporates a built-in N-MOSFET
power transistor to minimize the input-to-output voltage differential to the ON resistance (RON=50mΩ) level. By lowering the
dropout voltage in this way, the regulator realizes high current output (Iomax=4.0A) with reduced conversion loss, and
thereby obviates the switching regulator and its power transistor, choke coil, and rectifier diode. Thus, BD3522EFV /
BD35221EFV / BD35222EFV designed to enable significant package profile downsizing and cost reduction. In BD3522EFV,
an external resistor allows the entire range of output voltage configurations between 0.65 and 2.7V, while the NRCS (soft
start) function enables a controlled output voltage ramp-up, which can be programmed to whatever power supply sequ ence
is required.
● Features
1) Internal high-precision referenc e voltage circ uit(0.65V±1%)
2) Internal high-precision out put voltage circuit < B D35221EFV/BD35222EFV>
3) Built-in VCC undervoltage lockout circuit (VC C=3.80V)
4) NRCS (soft start) function reduces the magnitude of in-rush current
5) Internal Nch MOSFET driver offers low ON resistance (28mΩ typ)
6) Built-in short circuit protection (SCP)
7) Built-in current limit circuit (4.0A min)
8) Built-in thermal shutdown (TSD) circuit
9) Variable output (0.65～2.7V) <BD3522EFV>
10) High-po wer package HTSSOP-B20 : 6.5mm x 6.4mm x 1.0mm
11) Tracking function
● Applications
Notebook computers, Desktop computers, LCD-TV, DVD, Digital appliances
● Line-up
Maximum Output Voltage Package Product name
Adjustable (0.65～2.7V) HTSSOP-B20 BD3522EFV
1.2V (fixed) BD35221EFV
1.5V (fixed) BD35222EFV
Oct. 2008
2/20
●Absolute maximum ratings
Parameter Symbol Limit Unit
BD3522EFV BD35221EFV BD35222EFV
Input Voltage 1 VCC 6.0 *1 V
Input Voltage 2 VIN 6.0 *1 V
Maximum Output Current IO 4*1 A
Enable Input Voltage Ven 6.0 V
Power Dissipation 1 Pd1 1.00 *2 W
Power Dissipation 2 Pd2 1.45 *3 W
Power Dissipation 3 Pd3 2.31 *4 W
Power Dissipation 4 Pd4 3.20 *5 W
Operating Temperature Range Topr -10～+100 ℃
Storage Temperature Range Tstg -55～+125 ℃
Maximum Junction Temperature Tjmax +150 ℃
*1 Should not exceed Pd.
*2 Reduced by 8mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, no coppe r foil area)
*3 Reduced by 11.6mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 2-layer,
copper foil area : 15mm×15mm)
*4 Reduced by 18.5mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 2-layer,
copper foil area : 70mm×70mm)
*5 Reduced by 25.6mW/℃ for each increase in Ta≧25℃ (when mounted on a 70mm×70mm×1.6mm glass-epoxy board, 4-layer,
copper foil area : 70mm×70mm)
●Operating Voltage(Ta=25℃)
Parameter Symbol
BD3522EFV BD35221EFV BD35222EFV
Unit
Min. Max. Min. Max. Min. Max.
Input Voltage 1 VCC 4.3 5.5 4.3 5.5 4.3 5.5 V
Input Voltage 2 VIN 0.7 VCC-1 *61.25 VCC-1 *61.55 VCC-1 *6 V
Output Voltage Setting Range Vo VFB 2.7 1.2 (fixed) 1.5 (fixed) V
Enable Input Voltage Ven -0.3 5.5 -0.3 5.5 -0.3 5.5 V
NRCS Capacity CNRCS 0.001 1 0.001 1 0.001 1 μF
*6 VCC and VIN do not have to be implemented in the order listed.
★This product is not designed for use in radioactive environments.
3/20
●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VCC=5V, VEN=3V, VIN=1.7V, R1=3.9kΩ, R2=3.3kΩ)
BD3522EFV
Parameter Symbol Limit Unit Condition
Min. Typ. Max.
Bias Current ICC - 1.4 2.2 mA
VCC Shutdown Mode Current IST - 0 10 μA VEN=0V
Output Voltage IO 4.0 - - A
Feedback Voltage 1 VFB1 0.643 0.650 0.657 V
Feedback Voltage 2 VFB2 0.637 0.650 0.663 V Tj=-10 to 100℃
Line Regulation 1 REG.l1 - 0.1 0.5 %/V VCC=4.3V to 5.5V
Line Regulation 2 REG.l2 - 0.1 0.5 %/V VIN=1.2V to 3.3V
Load Regulation REG.L - 0.5 10 mV IO=0 to 4A
Output ON Resistance Ron - 28 50 mΩ IO=4A,VIN=1.2V
Tj=-10 to 100℃
Standby Discharge Current IDEN 1 - - mA VEN=0V, VO=1V
[ENABLE]
Enable Pin
Input Voltage High ENHIGH 2 - - V
Enable Pin
Input Voltage Low ENLOW -0.2 - 0.8 V
Enable Input Bias Current IEN - 6 10 μA VEN=3V
[FEEDBACK]
Feedback Pin Bias Current IFB -100 0 100 nA
[NRCS]
NRCS Charge Current INRCS 12 20 28 μA
NRCS Standby Voltage VSTB - 0 50 mV VEN=0V
[UVLO]
VCC Undervoltage Lockout
Threshold Voltage VCCUVLO 3.5 3.8 4.1 V VCC:Sweep-up
VCC Undervoltage Lockout
Hysteresis Voltage VCCHYS 100 160 220 mV VCC:Sweep-down
VD Undervoltage Lockout
Threshold Voltage VDUVLO VREF×0.6 VREF×0.7 VREF×0.8 V VD:Sweep-up
[SCP]
SCP Start up Voltage VOSCP V
O×0.3 VO×0.4 VO×0.5 V VFB=0, VGATE=2.5V
SCP Threshold Vo ltage VSCPTH 1.05 1.15 1.25 V
VFB=VCC, VGATE=2.5V
Charge Current ISCP 2 4 6 μA
Standby Voltag e VSCPSTBY - - 50 mV
4/20
●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VCC=5V, VEN=3V, VIN=1.7V)
BD35221EFV
Parameter Symbol Limit Unit Condition
Min. Typ. Max.
Bias Current ICC - 1.4 2.2 mA
VCC Shutdown Mode Current IST - 0 10 μA VEN=0V
Output Voltage IO 4.0 - - A
Feedback Voltage 1 VOS1 1.188 1.200 1.212 V
Feedback Voltage 2 VOS2 1.176 1.200 1.224 V Tj=-10 to 100℃
Line Regulation 1 REG.l1 - 0.1 0.5 %/V VCC=4.3V to 5.5V
Line Regulation 2 REG.l2 - 0.1 0.5 %/V VIN=1.25V to 3.3V
Load Regulation REG.L - 0.5 10 mV IO=0 to 4A
Output ON Resistance Ron - 28 50 mΩ IO=4A,VIN=1.2V
Tj=-10 to 100℃
Standby Discharge Current IDEN 1 - - mA VEN=0V, VO=1V
[ENABLE]
Enable Pin
Input Voltage High ENHIGH 2 - - V
Enable Pin
Input Voltage Low ENLOW -0.2 - 0.8 V
Enable Input Bias Current IEN - 6 10 μA VEN=3V
[NRCS]
NRCS Charge Current INRCS 12 20 28 μA
NRCS Standby Voltage VSTB - 0 50 mV VEN=0V
[UVLO]
VCC Undervoltage Lockout
Threshold Voltage VCCUVLO 3.5 3.8 4.1 V VCC:Sweep-up
VCC Undervoltage Lockout
Hysteresis Voltage VCCHYS 100 160 220 mV VCC:Sweep-down
VD Undervoltage Lockout
Threshold Voltage VDUVLO VO×0.6 VO×0.7 VO×0.8 V VD:Sweep-up
[SCP]
SCP Start up Voltage VOSCP V
O×0.3 VO×0.4 VO×0.5 V VFB=0, VGATE=2.5V
SCP Threshold Vo ltage VSCPTH 1.05 1.15 1.25 V
VFB=VCC, VGATE=2.5V
Charge Current ISCP 2 4 6 μA
Standby Voltag e VSCPSTBY - - 50 mV
5/20
●Electrical Characteristics (Unless otherwise specified, Ta=25℃, VCC=5V, VEN=3V, VIN=1.7V)
BD35222EFV
Parameter Symbol Limit Unit Condition
Min. Typ. Max.
Bias Current ICC - 1.4 2.2 mA
VCC Shutdown Mode Current IST - 0 10 μA VEN=0V
Output Voltage IO 4.0 - - A
Feedback Voltage 1 VOS1 1.485 1.500 1.515 V
Feedback Voltage 2 VOS2 1.470 1.500 1.530 V Tj=-10 to 100℃
Line Regulation 1 REG.l1 - 0.1 0.5 %/V VCC=4.3V to 5.5V
Line Regulation 2 REG.l2 - 0.1 0.5 %/V VIN=1.55V to 3.3V
Load Regulation REG.L - 0.5 10 mV IO=0 to 4A
Output ON Resistance Ron - 28 50 mΩ IO=4A,VIN=1.5V
Tj=-10 to 100℃
Standby Discharge Current IDEN 1 - - mA VEN=0V, VO=1V
[ENABLE]
Enable Pin
Input Voltage High ENHIGH 2 - - V
Enable Pin
Input Voltage Low ENLOW -0.2 - 0.8 V
Enable Input Bias Current IEN - 6 10 μA VEN=3V
[NRCS]
NRCS Charge Current INRCS 12 20 28 μA
NRCS Standby Voltage VSTB - 0 50 mV VEN=0V
[UVLO]
VCC Undervoltage Lockout
Threshold Voltage VCCUVLO 3.5 3.8 4.1 V VCC:Sweep-up
VCC Undervoltage Lockout
Hysteresis Voltage VCCHYS 100 160 220 mV VCC:Sweep-down
VD Undervoltage Lockout
Threshold Voltage VDUVLO VO×0.6 VO×0.7 VO×0.8 V VD:Sweep-up
[SCP]
SCP Start up Voltage VOSCP V
O×0.3 VO×0.4 VO×0.5 V VFB=0, VGATE=2.5V
SCP Threshold Vo ltage VSCPTH 1.05 1.15 1.25 V
VFB=VCC, VGATE=2.5V
Charge Current ISCP 2 4 6 μA
Standby Voltag e VSCPSTBY - - 50 mV
6/20
●Reference Data
BD3522EFV
Fig.3 Transient Response
(0→4A)
Co=100μF, Cfb=1000
p
F
Fig.2 Transient Response
(0→4A)
Co=100μF
Io=0A→4A/4μsec T(10μsec/div)
59mV
Vo
50mV/di
v
2A/div
Io
Fig.1 Transient Response
(0→4A)
Co=22μF, Cfb=1000
p
F
Fig.4 Transient Response
(4→0A)
Co=22μF, Cfb=1000
p
F
Fig.5 Transient Response
(4→0A)
Co=100μF
Fig.6 Transient Response
(4→0A)
Co=100μF, Cfb=1000pF
Fig.7 Waveform at output start
T(20μsec/div)
Ven
2V/di
v
VNRCS
2V/di
v
Vo
1V/di
v
Fig.8 Wavefor m at output OFF
T(2msec/div) VCC→VIN→Ven
VIN→VCC→Ven
Fig.10 Input sequence Fig.12 Input sequence
VCC→Ven→VIN
Ven→VCC→VIN
Fig.11 Input sequence
VCC
5V/di
v
Ven
2V/div
VIN
2V/di
v
1V/di
v
Vo
Fig.9 Input sequence
49mV 46mV
4.0A
Io=0A→4A/4μsec T(10μsec/div)
Io=0A→4A/4μsec T(10μsec/div)
42mV 41mV 41mV
T(100μsec/div)Io=4A→0A/4μsec T(100μsec/div)
Io=4A→0A/4μsec T(100μsec/div)Io=4A→0A/4μsec
4.0A 4.0A
4.0A 4.0A 4.0A
Vo
50mV/di
v
2A/div
Io
Vo
50mV/di
v
2A/di
v
Io
Vo
50mV/di
v
2A/di
v
Io
Vo
50mV/di
v
2A/di
v
Io
Vo
50mV/di
v
2A/di
v
Io
Ven
2V/di
v
VNRCS
2V/di
v
Vo
1V/di
v
VCC
5V/di
v
Ven
2V/di
v
VIN
2V/di
v
1V/di
v
Vo
VCC
5V/di
v
Ven
2V/div
VIN
2V/di
v
1V/di
v
Vo
VCC
5V/di
v
Ven
2V/div
VIN
2V/di
v
1V/di
v
Vo
7/20
●Reference Data
BD3522EFV
1.17
1.18
1.19
1.20
1.21
1.22
1.23
-50 -25 0 25 50 75 100 125 150
Tj [℃]
Vo [V]
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
-50 -25 0 25 50 75 100 125 150
Tj [℃]
ISTB [μA]
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.9
2.0
-50 -25 0 25 50 75 100 125 150
Tj [℃]
Icc [mA]
20
22
24
26
28
30
357
Vcc [V]
RON[mΩ]
Fig.13 Input sequence
VCC
Ven
VIN
Vo
VIN→Ven→VCC
Fig.14 Input sequence
Ven→VIN→VCC
Fig.17 Tj-ISTB
Fig.19 Tj-INRCS Fig.20 Tj-IEN
Fig.23 VCC-RON
Fig.21 Tj-RON
(VCC=5V/VO=1.2V)
Fig.22 Tj-RON
(VCC=5V/VO=1.5V)
Fig.15 Tj-V o
Vo=2.5V
Vo=1.8V
Vo=1.5V
Vo=1.2V
Fig.16 Tj-ICC
12
14
16
18
20
22
24
-50 -25 0 25 50 75 100 125 150
Tj [℃]
INRCS [μA]
0
5
10
15
20
25
30
35
40
45
50
-50 -25 0 25 50 75 100 125 150
Tj [℃]
IINSTB [μA]
0
1
2
3
4
5
6
7
8
9
10
-50 -25 0 25 50 75 100 125 150
Tj [℃]
IEN[μA]
0
5
10
15
20
25
30
35
40
-50 -25 0 25 50 75 100 125 150
Tj [℃]
RON[mΩ]
Fig.18 Tj-IINSTB
0
5
10
15
20
25
30
35
40
-50 -25 0 25 50 75 100 125 150
Tj [℃]
RON[mΩ]
VCC
Ven
VIN
Vo
8/20
●Block Diagram
BD3522EFV
BD35221EFV/BD35222EFV
Reference
Block
VIN
UVLO LATCH
Current
Limit
EN
VCC
VCC
VCC
VCC
EN
UVLO1
UVLO2
VREF
GND
CL
UVLO1
UVLO2
TSD
SCP
EN
UVLO1 CL
VCC VREF
×0.7
SCP
NRCS
11
12
13
8
10
NRCS
TSD
NRCS×0.3
VREF×0.4
FB
SCP/TSD
LATCH LATCH
EN
UVLO1
EN/UVLO
NRCS
VD
VIN
VO
FB
VIN
VO
R2
R1
R2
R1
7
6
5
4
3
2
1
20
19
18
17
16
15
14
C1
C2
C3
CNRCS
CSCP
9
CFB
VOS
Reference
Block
VIN
UVLOLATCH
Current
Limit
EN
VCC
VCC
VCC
VCC
EN
UVLO1
UVLO2
VREF
GND
CL
UVLO1
UVLO2
TSD
SCP
EN
UVLO1 CL
VCC VREF
×0.7
SCP
NRCS
11
12
13
8
10
NRCS
TSD
NRCS×0.3
VREF×0.4
FB
SCP/TSD
LATCH LATCH
EN
UVLO1
EN/UVLO
NRCS
VD
VIN
VO
FB
VIN
VO
R2
R1
R2
R1
7
6
5
4
3
2
1
20
19
18
17
16
15
14
C1
C2
C3
CNRCS
CSCP
9
CFB
9/20
●Pin Layout
●Pin Function Table
PIN
No. PIN name PIN Function PIN
No. PIN name PIN Function
1 VO Output Voltage Pin 1 VO Output Voltage Pin
2 VO Output Voltage Pin 2 VO Output Voltage Pin
3 VO Output Voltage Pin 3 VO Output Voltage Pin
4 VO Output Voltage Pin 4 VO Output Voltage Pin
5 VO Output Voltage Pin 5 VO Output Voltage Pin
6 VO Output Voltage Pin 6 VOS Output Voltage Control Pin
7 FB Reference Voltage Feedback Pin 7 FB Reference Voltage Feedback Pin
8 NRCS
In-rush Current Protection (NRCS)
Capacitor Connection Pin 8 NRCS
In-rush Current Protection (NRCS)
Capacitor Connection Pin
9 GND Ground Pin 9 GND Ground Pin
10 GND Ground Pin 10 GND Ground Pin
11 VCC Power supply pin 11 VCC Power supply pin
12 EN Enable input pin 12 EN Enable input pin
13 SCP
SCP Delay Time Setting Capacitor
Connection Pin 13 SCP
SCP Delay Time Setting Capacitor
Connection Pin
14 VD VIN Input Voltage Detect Pin 14 VD VIN Input Voltage Detect Pin
15 VIN Input Voltage Pin 15 V IN Input Voltage Pin
16 VIN Input Voltage Pin 16 V IN Input Voltage Pin
17 VIN Input Voltage Pin 17 V IN Input Voltage Pin
18 VIN Input Voltage Pin 18 V IN Input Voltage Pin
19 VIN Input Voltage Pin 19 V IN Input Voltage Pin
20 VIN Input Voltage Pin 20 V IN Input Voltage Pin
- FIN Connected to heatsink and GND - FIN Connected to heatsink and GND
BD3522EFV BD35221EFV/BD35222EFV
20 19 18 17 16 15 14 13 12 1120 19 18 17 16 15 14 13 12 11
1
VO
FIN
2
VO
3
VO
4
VO
5
VO
6
VO
7
FB
8
NRCS
9
GND
10
GND
VIN VIN V
IN V
IN V
IN V
IN VD SCP EN VCC
1
VO
FIN
2
VO
3
VO
4
VO
5
VO
6
VOS
7
FB
8
NRCS
9
GND
10
GND
VIN VIN VIN VIN VIN V
IN VD SCP EN VCC
BD3522EFV BD35221EFV/BD35222EFV
10/20
●Operation of Each Block
・AMP
This is an error amp compares the reference voltage (0.65V ) with VO to driv e the output N ch FE T (Ron=50mΩ). F reque ncy
optimization helps to realize rapid transient response, and to support the use of ceramic capacitors on the output. AMP input
voltage ranges from GND to 2.7V, while the AMP output ranges from GND to VCC. When EN is OFF, or when UVLO is
active, output goes LOW and the output of the NchFET switches OFF.
・EN
The EN block controls the regulator’s ON/OFF state via the EN logic input pin. In the OFF position, circuit voltage is
maintained at 0μA, thus minimizing current consumption at standby. The F ET is switched ON to enable discharge of the
NRCS pin VO, thereby draining the excess charge and preventing the IC on the load side from malfunctioning. Since no
electrical connection is required (e.g. between the VCC pin and the ESD prevention diode), module operation is
independent of the input sequence.
・VCCUVLO
To prevent malfunctions that can occur during a momentary decrease in VCC, the UVLO circuit switches the output OFF,
and (like the EN bl ock) disch arges NRCS a nd V O. Once the UVLO threshold voltage (TYP3.80V) is reached, the po wer-on
reset is triggered and output continues.
・VDUVLO
VD pin is the VIN voltage detect pin. When VD voltage exceeds the threshold voltage, VDUVLO becomes active. Once active,
the status of output voltage remains ON even if VD voltage drops. (When VIN voltage drops, SCP engages and output
switches OFF.) Unl ike EN and VCC, it is effective at output startup. VDUVLO can be rest ored eith er by rec onnecting the EN
pin or VCC pin.
・CURRENT LIMIT
When output is ON, the current limit function monitors the internal IC output current against the parameter value. When
current exceeds this level, the current limit modu le lowers the output current to protect the load IC. When the overcurren t
state is eliminated, output voltage is restored to the parameter value. However when output voltage falls to or below the
SCP startup voltage, the SCP function becomes active and the output switches OFF.
・NRCS (Non Rush Current on Start-up)
The soft start function enabled by connecting an external capacitor between the NRCS pin and ground. Output ramp-up
can be set for any period up to the time the NRCS pin reaches VFB (0.65V). During startup, the NRCS pin serves as a 20μ
A (TYP) constant current source to charge the external capacitor. Output start time is calculated via the formula below.
・TSD (Thermal Shut down)
The shutdown (TSD) circuit automatically is latched OFF when the chip temperature exceeds the threshold temperature
after the programmed time period elapses, thus serving to protect the IC against “thermal runaway” and heat damage.
Because the TSD circuit is intend ed to shut down the IC only in the prese n ce of extreme heat, it is crucial that the Tj (max)
parameter not be exceeded in the thermal design, in order to avoid pote ntial problems with the TSD.
・VIN
The VIN line acts as the major current supply line, and is connected to the output NchFET drain. Since no electrical
connection (such as between the VCC pin and the ESD protection diode) is necessary, VIN operates independent of the input
sequence. However, since an output Nc h FET body diode exi sts between VIN and VO, a VIN-VO electric (diode) connection is
present. Note, therefore, that when output is switched ON or OFF, reverse current may flow to VIN from VO.
・SCP
When output voltage (Vo) drops, the IC assumes that VO pin is shorted to GND and switched the output voltage OFF. After
the GND short has been detected and the pr ogramm ed dela y time has elapsed, output is latched OFF. It is also effective
during output startup. SCP can be cleared either by reconnecting the EN pin or VCC pin. Delay time is calculated via the
formula below.
TNRCS (typ.) = CNRCS×VFB
INRCS
TTSD (typ.) = CSCP×VSCPTH
20uA
TSCP (typ.) = CSCP×VSCPTH
ISCP
11/20
●Timing Chart
EN ON/OFF
VCC ON/OFF
VIN
VCC
EN
NRCS
Vo
VIN
VCC
EN
NRCS
Vo
t
t
Startup
Hysteresis
UVLO
Startup
0.65V(typ)
0.65V(typ)
12/20
●Timing Chart
VD ON
SCP OFF
VIN
VCC
EN
NRCS
Vo
VDUVLO
VD
VIN
VCC
EN
NRCS
Vo
SCP threshold voltage
VD
SCP
SCP delay time
SCP startup voltage
13/20
●Evaluation Board
*1 provision for supply impedance of instruments
Component Rating Manufacturer Product Name Component Rating Manufacturer Product Name
U1 - ROHM BD3522EFV CFB 1000pF MURATA GRM188B11H102KD
C6 22uF KYOCERA CM316B226M06A R6 (@VOUT=1.2V) 3.3kΩROHM MCR03EZPF3301
C8 0.01uF
MURATA GRM188B11H103KD R7 3.9Ω ROHM MCR03EZPF3901
C11 1uF
MURATA GRM188B11A105KD R121 0kΩ - jumper
C13 330pF
MURATA GRM188B11H331KD R14 3.9kΩROHM MCR03EZPF3901
C15 10uF KYOCERA CM21B106M06A R15(@VOUT=1.2V) 3.3kΩROHM MCR03EZPF3301
C18(*1) 150uF SANYO 6TPB150M
■
■
BD3522EFV Evaluation Board Schematic
■
■
BD3522EFV Evaluation Board Layout
■
■
BD3522EFV Evaluation Board List
Silk Screen (Bottom)
Bottom Layer
Silk Screen (Top)
Middle Layer_1 Middle Layer_2
TOP Layer
U1
BD3522EFV
VO
120
VIN
VO
219
VIN
VO
318
VIN
VO
417
VIN
VO
516
VIN
VO
615
VIN
FB
714
VD
NRCS
813
SCP
GND
912
EN
GND
10 11
VCC
VIN_S
C15 C16 C17 C18
VIN
R15
VD
R14
C13
R6
R7
C8 SCP
VCC
C12
R12
C11
JP15
JP6
C6 C5
R4
C4
VO_S
VO
RLD
CFB
FB
NRCS
SGND
GND1GND GND2
VCC
SW1
H
L
VCC
U2
INF RF1
RF2
JP10
JPF1
JPF2
VCC
IN
V
RF3
U3
CF
EN
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
14/20
●Recommended Circuit Example (BD 3522EFV)
Component Recommended
Value Programming Notes and Precautions
R6/R7 3.3k /3.9k IC output voltage can be set with a configuration formula VFB×(R6+R7)/R7 using the
values for the internal reference output voltage (VFB) and the output voltage resistors (R6,
R7). Select resistance values that will avoid the impact of the FB bias current (±100nA).
The recommended total resistance value is 10KΩ.
C1 22μF To assure output voltage stability, please be certain the output capacitors are connected
between Vo pin and GN D. Output capacitors play a role in loop gai n phase compensation
and in mitigating output fluctuation during rapid changes in load level. Insufficient
capacitance may cause oscillation, while high equivalent series reisistance (ESR) will
exacerbate output voltage fluctuation under rapid load change conditions. While a 22μF
ceramic capacitor is recomended, actual stability is highly dependent on temperature an d
load conditions. Also, note that connecting different types of capacitors in series may result
in insufficient total phase compensation, thus causing oscillation. In light of this information,
please confirm operation acro ss a variety of temperature and load conditions.
C11/C20 1μF/10μF Input capacitors reduce the output impedance of the voltage supply source connected to
the (VCC, VIN) input pins. If the impedance of this power supply were to increase, input
voltage (VCC, VIN) could become unstable, lead ing to oscillation or lo wered ripple rejection
function. While a low-ESR 1 μF/10μF capacitor with minimal susc epti bilit y to temperature
is recommended, stability is highly dependent on the input power supply characteristics
and the substrate wiring pattern. In light of this information, please confirm operation
across a variety of temperature and l oa d conditions.
C8 0.01μF The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush
current from going through the loa d (VIN to VO ) and impacting output capacitors at power
supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the
UVLO function is deactivated. The temporary reference voltage is proportionate to time,
due to the current charge of the NRCS pin capacitor, and output voltage start-up is
proportionate to this reference voltage. Capacitors with low susceptibility to temperature
are recommended, in order to assure a stable soft-start time.
C6
1000pF This component is employe d when the C16 capacitor causes, or ma y cause, oscil lation. It
provides more precise internal phase correction.
C13 330pF The Short Circuit Protection (SCP) function and the Thermal Shut Down (TSD) function
are built into the IC. Constant current comes from the SCP pin when SCP function or TSD
function is operated. (SCP:4μA, TSD:20μA TYP.) The voltage occurred in SCP pin by
this current overstep the threshold voltage, the status of voltage becomes OFF. Capacitors
with low susceptibility to temperature (330pF or more) are recommended, in order to
assure a stable TSD delay setting time. In light of this information, please confirm the
capacitor value to prevent startup defective.
R6
20 19 18 17 16 15 14 13 12 11
1 2 3 45678910
C6
C1
R7 C8
C13
VIN C20
R15 R14
C12 EN
Vcc C11
Vo Vo Vo Vo Vo Vo FB NRCS GND GND
VccEN SCPVD VIN VIN VIN VIN VIN VIN
15/20
●Recommended Circuit Example (BD 35221EFV/BD35222EFV)
Component Recommended
Value Programming Notes and Precautions
C1 22μF To assure output voltage stability, please be certain the output capacitors are connected
between Vo pin and GN D. Output capacitors play a role in loop gai n phase compensation
and in mitigating output fluctuation during rapid changes in load level. Insufficient
capacitance may cause oscillation, while high equivalent series reisistance (ESR) will
exacerbate output voltage fluctuation under rapid load change conditions. While a 22μF
ceramic capacitor is recomended, actual stability is highly dependent on temperature an d
load conditions. Also, note that connecting different types of capacitors in series may result
in insufficient total phase compensation, thus causing oscillation. In light of this information,
please confirm operation acro ss a variety of temperature and load conditions.
C11/C20 1μF/10μF Input capacitors reduce the output impedance of the voltage supply source connected to
the (VCC, VIN) input pins. If the impedance of this power supply were to increase, input
voltage (VCC, VIN) could become unstable, lead ing to oscillation or lo wered ripple rejection
function. While a low-ESR 1 μF/10μF capacitor with minimal susc epti bilit y to temperature
is recommended, stability is highly dependent on the input power supply characteristics
and the substrate wiring pattern. In light of this information, please confirm operation
across a variety of temperature and l oa d conditions.
C8 0.01μF The Non Rush Current on Startup (NRCS) function is built into the IC to prevent rush
current from going through the load (VIN to VO) and impacting output capacitors at power
supply start-up. Constant current comes from the NRCS pin when EN is HIGH or the
UVLO function is deactivated. The temporary reference voltage is proportionate to time,
due to the current charge of the NRCS pin capacitor, and output voltage start-up is
proportionate to this reference voltage. Capacitors with low susceptibility to temperature
are recommended, in order to assure a stable soft-start time.
C6
1000pF This component is employed when the C16 capacitor causes, or may cause, oscil lation. It
provides more precise internal phase correction.
C13 330pF The Short Circuit Protection (SCP) function and the Thermal Shut Down (TSD) function
are built into the IC. Constant current comes from the SCP pin when SCP function or TSD
function is operated. (SCP:4μA, TSD:20μA TYP.) The voltage occurred in SCP pin by
this current overstep the threshold voltage, the status of voltage becomes OFF. Capacitors
with low susceptibility to temperature (330pF or more) are recommended, in order to
assure a stable TSD delay setting time. In light of this information, please confirm the
capacitor value to prevent startup defective.
20 19 18 17 16 15 14 13 12 11
1 2 3 45678910
C8
C13
VIN C20
R15 R14
C12 EN
Vcc C11
FIN
Vo Vo Vo Vo Vo Vos FB NRCS GND GND
VccEN SCPVD VIN VIN VIN VIN VIN VIN
C6
C1
16/20
●Heat Loss
Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed
temperature limits, and thermal design sh ould allow sufficient margin from the limits.
1. Ambient temperature Ta can be no higher than 10 0℃.
2. Chip junction temperature (Tj) can be no higher than 150℃.
Chip junction temperature can be determined as follo ws:
It is recommended to layout the VIA for heat radiation in the GND pattern of reverse (of IC) when there is the GND pattern in
the inner layer (in using multiplayer substrate). This package is so small (size: 6.5mm×6.4mm) that it is not available to
layout the VIA in the bottom of IC. Spreading the pattern and being increased the number of VIA like the figure below enabl e
to get the superior heat radiation characteristic. (This figure is the image. It is recommended that the VIA size and the
number is designed suitable for the actual situation.).
Most of the heat loss that occurs in the BD3522EFV is generated from the output Nc h FET. Power loss is determined by the
total VIN-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current
conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in mind that heat
dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the
BD3522EFV) make certain to factor conditions such as substrate size into the thermal design.
Power consumption (W) = Input voltage (VIN)- Output voltage (Vo) ×Io(Ave)
Example) Where VIN=1.7V, VO=1.2V, Io(Ave) = 4A,
Power consumption (W) = 1.7(V)-1.2(V) ×4.0(A)
= 2.0(W)
① Calculation based on ambient temperature (Ta)
Tj=Ta+θj-a×W
1-layer substrate (no copp er foil area)
1-layer substrate (copper foil area : 15mm×15mm)
2-layer substrate (copper foil area : 70mm×70mm)
2-layer substrate (copper foil area : 70mm×70mm)
Substrate size: 70×70×1.6mm3 (substrate with thermal via)
<Reference values>
θj-a: HTSSOP-B20 125℃/W
86.2℃/W
54.1℃/W
39.1℃/W
17/20
●Input-Output Equivalent Circuit Diagram (BD3522EFV)
400kΩ
EN
VCC
FB 1kΩ
1kΩ
VIN
VIN
VIN
VIN
VIN
VIN
NRCS
VCC
1kΩ
1kΩ
1kΩ
90kΩ
210kΩ
1kΩ
VCC
1kΩ 1kΩ
VCC
Vo
Vo 50kΩ
10kΩ
1kΩ
Vo
Vo
Vo
Vo
1kΩ
VD 1kΩ
SCP
VCC
1kΩ 1kΩ
1kΩ
1kΩ 1kΩ
5PF
18/20
●Operation Notes
1. Absolute maximum ratings
An excess in the absolute maximum ratings, such as suppl y vo ltage, temperature range of operati ng conditions, etc., can
break down the devices, thus making impossible to identif y breakin g mode, such as a short circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consid er adding circuit protection devices, such as
fuses.
2. Connecting the power supply co nnector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction di ode can be added.
3. Power supply lines
Design PCB layout pattern to provi de lo w impedanc e GND and s uppl y lines. To obtain a lo w noise gro und and su pply line,
separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to
ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the
circuit, not that capacitance characteristic values are reduced at low temperatures.
4. GND voltage
The potential of GND pin mus t be minimum potential in all operating conditions.
5. Thermal design
Use a thermal design that allows for a sufficient margin in light of the po wer dissipation (Pd) in actual operating conditions.
6. Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
7. Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
8. ASO
When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.
9. Thermal shutdown circuit
The IC incorporates a built-in thermal shutdown circuit (T SD circuit). T he thermal shutdown circuit (TSD circuit) is desig ned
only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not
continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is
assumed. TSD on temperature [°C] (typ.)
BD3522EFV/BD35221EFV/BD35222EFV 175
10. Testing on application boards
When testing the IC on a n application board, conn ecting a capacit or to a pin with low impedance subj ects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.
19/20
11. Regardi ng input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adj acent elements in order to keep them isolated.
P-N junctions are formed at th e intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N j unction operates as a parasitic diode.
When GND > Pin B, the P-N junction operat es as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes operate,
such as applying a voltage that is lo wer than the GND (P substrate) voltage to an input pin, should not be used.
12. Ground Wiring Pattern.
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing
a single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations
caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND
wiring pattern of any external components, either.
●Heat Dissipation Characteristics
◎HTSSOP-B20
Example of IC structure
Resistor Transistor (NPN)
N
N N P+ P
+
P
P substrate
GND
Parasitic element
Pin A
N
N P+ P+
P
P substrate
GND
Parasitic element
Pin B C B
E
N
GND
Pin A
P
aras
iti
c
element
Pin B
Other adjacent elements
E
B C
GND
aras
c
element
(HTSSOP-B20)
25
Power Dissipation :Pd [W]
Ambient Temperature:Ta [℃]
①1W
70mm×70mm×1.6mm (PCB with Thermal Via)
① 1 layer substrate (s ubstrate surface copper foil area:0mm×0mm)
θj-a=125℃/W
② 2 layer substrate (substrat e surface copper foil area:15mm×15mm)
θj-a=86.2℃/W
③ 2 layer substrate (substrat e surface copper foil area:15mm×15mm)
θj-a=54.1℃/W
④ 4 layer substrate (substrat e surface copper foil area:70mm×70mm)
θj-a=39.1℃/W
0 50 75 100 150
1
2
3
4
125
②1.45W
③2.31W
④3.2W
20/20
●Type Designations (Orderin g Information)
Product Name Package Type E2:Emboss tape reel opposite draw-out side: 1 pin
・BD3522
・BD35221
・BD35222
・EFV: HTSSOP-B20
B D 3 5 2 2―E 2 E F V
<Tape and Reel information>
Tape
Quantity
Direction
of feed
Embossed carrier ta
p
e
2500pcs
E2
(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)
(Unit:mm)
HTSSOP-B20
<Dimension>
1.0Max.
101
20 11
0.17
1.0
±
0.2
0.5
±
0.15
0.65 S
0.08
+0.05
−0.04
+0.05
−0.03
0.2
6.4
±
0.2
0.85
±
0.05
0.08
±
0.05 4.4
±
0.1
0.325
6.5
±
0.1
S
Reel Direction of feed
1pin
1234
1234
1234
1234
1234
1234
1234
1234
※When you order , please order in times the amount of pa ckage quantity.
Catalog No.08T427A '08.10 ROHM ©
Appendix1-Rev3.0
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FAX : +81-75-315-0172
Appendix
Notes
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CO.,LTD.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter "Products"). If you
wish to use any such Product, please be sure to refer to the specifications, which can be obtained from ROHM
upon request.
Examples of application circuits, circuit constants and any other information contained herein illustrate the
standard usage and operations of the Products. The peripheral conditions must be taken into account when
designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document. However, should
you incur any damage arising from any inaccuracy or misprint of such information, ROHM shall bear no respon-
sibility for such damage.
The technical information specified herein is intended only to show the typical functions of and examples of
application circuits for the Products. ROHM does not grant you, explicitly or implicitly, any license to use or
exercise intellectual property or other rights held by ROHM and other parties. ROHM shall bear no responsibility
whatsoever for any dispute arising from the use of such technical information.
The Products specified in this document are intended to be used with general-use electronic equipment or
devices (such as audio visual equipment, office-automation equipment, communication devices, electronic
appliances and amusement devices).
The Products are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a Product may fail or
malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard against the
possibility of physical injury, fire or any other damage caused in the event of the failure of any Product, such as
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