IDT71024S70 CMOS STATIC RAM 1 MEG (128K x 8-BIT) Integrated Device Technology, Inc. FEATURES: DESCRIPTION: * 128K x 8 CMOS static RAM * Equal access and cycle times -- Commercial: 70ns * Two Chip Selects plus one Output Enable pin * Bidirectional inputs and outputs directly TTL-compatible * Low power consumption via chip deselect * Available in 300 and 400 mil Plastic SOJ packages The IDT71024 is a 1,048,576-bit medium-speed static RAM organized as 128K x 8. It is fabricated using IDT's highperformance, high-reliability CMOS technology. This stateof-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for your memory needs. The IDT71024 has an output enable pin which operates as fast as 30ns, with address access times as fast as 70ns available. All bidirectional inputs and outputs of the IDT71024 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used; no clocks or refreshes are required for operation. The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ and 32-pin 400 mil Plastic SOJ packages. FUNCTIONAL BLOCK DIAGRAM A0 * * * ADDRESS DECODER * * * 1,048,576-BIT MEMORY ARRAY A16 8 I/O0 - I/O7 I/O CONTROL 8 8 WE OE CONTROL LOGIC CS1 CS2 3568 drw 01 The IDT logo is a registered trademark of Integrated Device Technology, Inc. COMMERCIAL TEMPERATURE RANGE 1996 Integrated Device Technology, Inc. MAY 1996 DSC-3568/- 1 IDT71024S70 CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1) PIN CONFIGURATION Symbol 1 32 2 31 3 30 4 29 5 28 6 S032-3 27 7 SO32-3 26 8 25 24 9 23 10 22 11 21 12 13 20 14 19 15 18 16 17 NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 GND Com'L. Unit -0.5 to +7.0 V Operating Temperature 0 to +70 C TBIAS Temperature Under Bias -55 to +125 C TSTG StorageTemperature -55 to +125 C PT Power Dissipation 1.25 W IOUT DC Output Current 50 mA (2) Rating VCC A15 CS2 VTERM Terminal Voltage with Respect to GND WE TA A13 A8 A9 A11 OE A10 CS1 I/O7 I/O6 I/O5 I/O4 I/O3 NOTES: 3568 tbl 02 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V. 3568 drw 02 SOJ TOP VIEW TRUTH TABLE(1,2) CAPACITANCE (TA = +25C, f = 1.0MHz, SOJ package) INPUTS CS1 CS2 OE I/O FUNCTION X H X X High-Z Deselected-Standby (ISB) X VHC(3) X X High-Z Deselected-Standby (ISB1) X X L X High-Z Deselected-Standby (ISB) X X VLC(3) X High-Z Deselected-Standby (ISB1) H L H H High-Z Outputs Disabled H L H L DATAOUT Read Data L L H X DATAIN Write Data NOTES: 1. H = VIH, L = VIL, X = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC. Parameter(1) Conditions Max. Unit CIN Input Capacitance VIN = 3dV 8 pF CI/O I/O Capacitance VOUT = 3dV 8 pF Symbol WE NOTE: 3568 tbl 03 1. This parameter is guaranteed by device characterization, but is not production tested. RECOMMENDED DC OPERATING CONDITIONS Symbol 3568 tbl 01 Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V GND Supply Voltage 0 0 0 V VIH Input High Voltage 2.2 -- VIL Input Low Voltage -0.5(1) -- Vcc+0.5 0.8 V V NOTE: 3568 tbl 04 1. VIL (min.) = -1.5V for pulse width less than 10ns, once per cycle. DC ELECTRICAL CHARACTERISTICS VCC = 5.0V 10% IDT71024 Symbol Min. Max. Unit |ILI| Input Leakage Current Parameter VCC = Max., VIN = GND to VCC Test Condition -- 5 A |ILO| Output Leakage Current VCC = Max., CS1 = VIH, CS2 = VIL, VOUT = GND to VCC -- 5 A VOL Output LOW Voltage IOL = 8mA, VCC = Min. -- 0.4 V VOH Output HIGH Voltage IOH = -4mA, VCC = Min. 2.4 -- V 3568 tbl 05 . 2 IDT71024S70 CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE DC ELECTRICAL CHARACTERISTICS(1) (VCC = 5.0V 10%, VLC = 0.2V, VHC = VCC - 0.2V) 71024S70 Symbol Parameter Com'l. Mil. Unit ICC Dynamic Operating Current, CS2 VIH and CS2 VIH and CS1 VIL, Outputs Open, VCC = Max., f = fMAX(2) 140 -- mA ISB Standby Power Supply Current (TTL Level) CS1 V IH or CS2 VIL, Outputs Open, VCC = Max., f = fMAX(2) 35 -- mA ISB1 Full Standby Power Supply Current (CMOS Level) CS1 VHC, or CS2 VLC Outputs Open, VCC = Max., f = 0(2), VIN VLC or VIN VHC 10 -- mA NOTES: 1.All values are maximum guaranteed values. 2.fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing. 3568 tbl 06 AC TEST CONDITIONS Input Pulse Levels GND to 3.0V Input Rise/Fall Times 3ns Input Timing Reference Levels 1.5V Output Reference Levels 1.5V AC Test Load See Figures 1 and 2 3568 tbl 07 5V 5V 480 480 DATA OUT DATA OUT 30pF 255 5pF* 255 3568 drw 04 3568 drw 03 Figure 1. AC Test Load *Including jig and scope capacitance. Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ) 3 IDT71024S70 CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V 10%, Commercial Temperature Range) Symbol Parameter 71024S70 Min. Max. Unit Read Cycle tRC Read Cycle Time 70 -- ns tAA Address Access Time -- 70 ns tACS Chip Select Access Time -- 70 ns (2) Chip Select to Output in Low-Z 3 -- ns (2) Chip Deselect to Output in High-Z 0 30 ns tCLZ tCHZ tOE tOLZ Output Enable to Output Valid -- 30 ns (2) Output Enable to Output in Low-Z 0 -- ns (2) Output Disable to Output in High-Z 0 30 ns tOHZ tOH Output Hold from Address Change 4 -- ns tPU (2) Chip Select to Power-Up Time 0 -- ns tPD (2) Chip Deselect to Power-Down Time -- 70 ns Write Cycle tWC Write Cycle Time 70 -- ns tAW Address Valid to End-of-Write 60 -- ns tCW Chip Select to End-of-Write 60 -- ns tAS Address Set-up Time 0 -- ns tWP Write Pulse Width 45 -- ns tWR Write Recovery Time 0 -- ns tDW Data Valid to End-of-Write 30 -- ns tDH Data Hold Time 0 -- ns tOW(2) Output Active from End-of-Write 5 -- ns tWHZ(2) Write Enable to Output in High-Z 0 30 ns NOTES: 1. 0C to +70C temperature range only. 2. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested. 3568 tbl 08 4 IDT71024S70 CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF READ CYCLE NO. 1(1) t RC ADDRESS t AA OE t OE t OLZ CS1 (5) CS2 t ACS (3) t OHZ (5) t CHZ (5) t CLZ (5) HIGH IMPEDANCE DATA OUT Vcc SUPPLY CURRENT Icc DATA OUT VALID t PD t PU Isb 3568 drw 05 TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4) tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID 3568 drw 06 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is HIGH. 3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured 200mV from steady state. 5 IDT71024S70 CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED TIMING)(1, 2, 5, 7) tWC ADDRESS tAW tCW CS1 CS2 tWR (3) tWP (7) tAS WE tWHZ DATAOUT (6) tOW HIGH IMPEDANCE (4) tCHZ (6) (6) (4) tDH tDW DATAIN DATAIN VALID 3568 drw 07 TIMING WAVEFORM OF WRITE CYCLE NO. 2 (CS1 AND CS2 CONTROLLED TIMING)(1, 2, 5) tWC ADDRESS tAW CS1 CS2 tAS tWR tCW (3) WE tDW DATAIN tDH DATAIN VALID 3568 drw 08 NOTES: 1. WE must be HIGH, CS1 must be HIGH, or CS2 must be LOW during all address transitions. 2. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE. 3. tWR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle. 4. During this period, I/O pins are in the output state, and input signals must not be applied. 5. If the CS1 LOW transition or the CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS1 and CS2 must both be active during the tCW write period. 6. Transition is measured 200mV from steady state. 7. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP. 6 IDT71024S70 CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE ORDERING INFORMATION IDT 71024 S XX Device Type Power Speed X Package X Process/ Temperature Range Blank Commercial (0C to +70C) TY Y 300-mil SOJ (SO32-2) 400-mil SOJ (SO32-3) 70 Speed in nanoseconds 3568 drw 09 7