FEATURES:
• 128K x 8 CMOS static RAM
• Equal access and cycle times
— Commercial: 70ns
• Two Chip Selects plus one Output Enable pin
• Bidirectional inputs and outputs directly TTL-compatible
• Low power consumption via chip deselect
• Available in 300 and 400 mil Plastic SOJ packages
Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE MAY 1996
1996 Integrated Device Technology, Inc. DSC-3568/-
CMOS STATIC RAM
1 MEG (128K x 8-BIT)
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
IDT71024S70
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION:
The IDT71024 is a 1,048,576-bit medium-speed static
RAM organized as 128K x 8. It is fabricated using IDT’s high-
performance, high-reliability CMOS technology. This state-
of-the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for your memory
needs.
The IDT71024 has an output enable pin which operates as
fast as 30ns, with address access times as fast as 70ns
available. All bidirectional inputs and outputs of the IDT71024
are TTL-compatible and operation is from a single 5V supply.
Fully static asynchronous circuitry is used; no clocks or
refreshes are required for operation.
The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ
and 32-pin 400 mil Plastic SOJ packages.
1
ADDRESS
DECODER 1,048,576-BIT
MEMORY ARRAY
I/O CONTROL
•
•
•
A0
A16
3568 drw 01
8
8
I/O0 – I/O7¥
8
•
•
•
CONTROL
LOGIC
WE
OE
CS1
CS2
2
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE
TRUTH TABLE(1,2)
INPUTS
WE
WE CS1
CS1
CS2
OE
OE
I/O FUNCTION
X H X X High-Z Deselected–Standby (ISB)
XV
HC(3) X X High-Z Deselected–Standby (ISB1)
X X L X High-Z Deselected–Standby (ISB)
XXV
LC(3) X High-Z Deselected–Standby (ISB1)
H L H H High-Z Outputs Disabled
H L H L DATAOUT Read Data
L L H X DATAIN Write Data
NOTES: 3568 tbl 01
1. H = VIH, L = VIL, X = Don't care.
2. VLC = 0.2V, VHC = VCC -0.2V.
3. Other inputs ≥VHC or ≤VLC.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Com'L. Unit
VTERM(2) Terminal Voltage with –0.5 to +7.0 V
Respect to GND
TAOperating Temperature 0 to +70 °C
TBIAS Temperature Under Bias –55 to +125 °C
TSTG StorageTemperature –55 to +125 °C
PTPower Dissipation 1.25 W
IOUT DC Output Current 50 mA
NOTES: 3568 tbl 02
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VTERM must not exceed VCC + 0.5V.
PIN CONFIGURATION
SOJ
TOP VIEW
CAPACITANCE
(TA = +25°C, f = 1.0MHz, SOJ package)
Symbol Parameter(1) Conditions Max. Unit
CIN Input Capacitance VIN = 3dV 8 pF
CI/O I/O Capacitance VOUT = 3dV 8 pF
NOTE: 3568 tbl 03
1. This parameter is guaranteed by device characterization, but is not prod-
uction tested.
RECOMMENDED DC OPERATING
CONDITIONS
Symbol Parameter Min. Typ. Max. Unit
VCC Supply Voltage 4.5 5.0 5.5 V
GND Supply Voltage 0 0 0 V
VIH Input High Voltage 2.2 — Vcc+0.5 V
VIL Input Low Voltage –0.5(1) — 0.8 V
NOTE: 3568 tbl 04
1. VIL (min.) = –1.5V for pulse width less than 10ns, once per cycle.
DC ELECTRICAL CHARACTERISTICS
VCC = 5.0V ± 10% IDT71024
Symbol Parameter Test Condition Min. Max. Unit
|ILI| Input Leakage Current VCC = Max., VIN = GND to VCC — 5 µA
|ILO| Output Leakage Current VCC = Max.,
CS1
= VIH, CS2 = VIL, VOUT = GND to VCC — 5 µA
VOL Output LOW Voltage IOL = 8mA, VCC = Min. — 0.4 V
VOH Output HIGH Voltage IOH = –4mA, VCC = Min. 2.4 — V
3568 tbl 05
.
5
6
7
8
9
10
11
12
NC
A16
A14
1
2
3
4
32
31
30
29
28
27
26
25
24
23
22
21
A15
A12
A7
A6
A5
A4
CS2
A13
A8
A9
A11
WE
A10
3568 drw 02
A3
13 20
OE
14 19
15 18
16GND 17
A2
A1
A0
I/O0
I/O1
I/O2
VCC
CS1
I/O7
I/O6
I/O5
I/O4
I/O3
S032-3
SO32-3
3
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC – 0.2V) 71024S70
Symbol Parameter Com'l. Mil. Unit
ICC Dynamic Operating Current, CS2 ≥ VIH and 140 — mA
CS2 ≥ VIH and
CS1
≤ VIL, Outputs Open,
VCC = Max., f = fMAX(2)
ISB Standby Power Supply Current (TTL Level) 35 — mA
CS1
≥ VIH or CS2 ≤ VIL, Outputs Open,
VCC = Max., f = fMAX(2)
ISB1 Full Standby Power Supply Current 10 — mA
(CMOS Level)
CS1
≥ VHC,
or CS2 ≤ VLC Outputs Open,
VCC = Max., f = 0(2), VIN ≤ VLC or VIN ≥ VHC
NOTES: 3568 tbl 06
1.All values are maximum guaranteed values.
2.fMAX = 1/t RC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing.
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
Figure 1. AC Test Load
AC TEST CONDITIONS
Input Pulse Levels GND to 3.0V
Input Rise/Fall Times 3ns
Input Timing Reference Levels 1.5V
Output Reference Levels 1.5V
AC Test Load See Figures 1 and 2
3568 tbl 07
3568 drw 04
480Ω
255Ω
5pF*
DATAOUT
5V
3568 drw 03
480Ω
255Ω
30pF
DATAOUT
5V
4
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS (VCC = 5.0V ± 10%, Commercial Temperature Range)
71024S70
Symbol Parameter Min. Max. Unit
Read Cycle
tRC Read Cycle Time 70 — ns
tAA Address Access Time —70 ns
tACS Chip Select Access Time —70 ns
tCLZ(2) Chip Select to Output in Low-Z 3 — ns
tCHZ(2) Chip Deselect to Output in High-Z 0 30 ns
tOE Output Enable to Output Valid — 30 ns
tOLZ(2) Output Enable to Output in Low-Z 0 — ns
tOHZ(2) Output Disable to Output in High-Z 0 30 ns
tOH Output Hold from Address Change 4 — ns
tPU(2) Chip Select to Power-Up Time 0 — ns
tPD(2) Chip Deselect to Power-Down Time — 70 ns
Write Cycle
tWC Write Cycle Time 70 — ns
tAW Address Valid to End-of-Write 60 — ns
tCW Chip Select to End-of-Write 60 — ns
tAS Address Set-up Time 0— ns
tWP Write Pulse Width 45 — ns
tWR Write Recovery Time 0— ns
tDW Data Valid to End-of-Write 30 — ns
tDH Data Hold Time 0— ns
tOW(2) Output Active from End-of-Write 5 — ns
tWHZ(2) Write Enable to Output in High-Z 0 30 ns
NOTES: 3568 tbl 08
1. 0°C to +70°C temperature range only.
2. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
5
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS1
is LOW, CS2 is HIGH.
3. Address must be valid prior to or coincident with the later of
CS1
transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter.
4.
OE
is LOW.
5. Transition is measured ±200mV from steady state.
TIMING WAVEFORM OF READ CYCLE NO. 1(1)
TIMING WAVEFORM OF READ CYCLE NO. 2(1, 2, 4)
ADDRESS
3568 drw 05
OE
CS1
(5) (5)
(5)
(5)
CS2
DATA VALID
HIGH IMPEDANCE
AA
RC
OE
ACS
OLZ
CHZ
CLZ
(3)
OHZ
DATA OUT OUT
PU PD
Vcc
SUPPLY
CURRENT
Icc
Isb
t
tt
t
t
t
t
t
t
t
DATA
OUT
ADDRESS
3568 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALIDPREVIOUS DATA
OUT
VALID
6
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (
WE
WE
CONTROLLED TIMING)(1, 2, 5, 7)
TIMING WAVEFORM OF WRITE CYCLE NO. 2 (
CS1
CS1
AND CS2 CONTROLLED TIMING)(1, 2, 5)
NOTES:
1.
WE
must be HIGH,
CS1
must be HIGH, or CS2 must be LOW during all address transitions.
2. A write occurs during the overlap of a LOW
CS1
, HIGH CS2, and a LOW
WE
.
3. tWR is measured from the earlier of either
CS1
or
WE
going HIGH or CS2 going LOW to the end of the write cycle.
4. During this period, I/O pins are in the output state, and input signals must not be applied.
5. If the
CS1
LOW transition or the CS2 HIGH transition occurs simultaneously with or after the
WE
LOW transition, the outputs remain in a high impedance
state.
CS1
and CS2 must both be active during the tCW write period.
6. Transition is measured ±200mV from steady state.
7.
OE
is continuously HIGH. During a
WE
controlled write cycle with
OE
LOW, tWP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to
turn off and data to be placed on the bus for the required tDW. If
OE
is HIGH during a
WE
controlled write cycle, this requirement does not apply and the
minimum write pulse is the specified tWP.
ADDRESS
CS1
WE
CS2
DATAOUT
DATAIN 3568 drw 07
(6)
(7)
(6) (6)
DATAIN VALID
HIGH IMPEDANCE
tWC
tAW
tAS
tWHZ
tWP
tCHZ
tOW
tDW tDH
tCW
(3)
tWR
(4)(4)
CS1
ADDRESS
WE
CS2
DATAIN 3568 drw 08
tAW
tWC
tCW
tAS tWR
tDW tDH
(3)
DATAIN VALID
7
IDT71024S70
CMOS STATIC RAM 1MEG (128K x 8-BIT) COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
S
Power
XX
Speed
X
Package
X
Process/
Temperature
Range
Blank Commercial (0°C to +70°C)
TY
Y300-mil SOJ (SO32-2)
400-mil SOJ (SO32-3)
70
Device
Type
IDT
Speed in nanoseconds
3568 drw 09
71024
