IDT71P71604S300BQ8 - Integrated Device Technology

MAY 2004

DSC-6112/00

1

18Mb Pipelined

DDR™II SRAM

Burst of 2

Advance

Information

IDT71P71204

IDT71P71104

IDT71P71804

IDT71P71604

Features

◆18Mb Density (2Mx8, 2Mx9, 1Mx18, 512kx36)

◆Common Read and Write Data Port

◆Dual Echo Clock Output

◆2-Word Burst on all SRAM accesses

◆Multiplexed Address Bus

- One Read or One Write request per clock cycle

◆DDR (Double Data Rate) Data Bus

- Two word bursts data per clock

◆Depth expansion through Control Logic

◆HSTL (1.5V) inputs that can be scaled to receive signals

from 1.4V to 1.9V .

◆Scalable output drivers

- Can drive HSTL, 1.8V TTL or any voltage level

from 1.4V to 1.9V .

- Output Impedance adjustable from 35 ohms to 70

ohms

◆1.8V Core V oltage (VDD)

◆165-ball, 1.0mm pitch, 13mm x 15mm fBGA Package

Description

The IDT DDRIITM Burst of two SRAMs are high-speed synchronous

memories with a double-data-rate (DDR), bidirectional data port. This

scheme allows maximization of the bandwidth on the data bus by pass-

ing two data items per clock cycle. The address bus operates at single

data rate speeds, allowing the user to fan out addresses and ease

system design while maintaining maximum performance on data trans-

fers.

The DDRII has scalable output impedance on its data output bus and

echo clocks, allowing the user to tune the bus for low noise and high

performance.

All interfaces of the DDRII SRAM are HSTL, allowing speeds be-

yond SRAM devices that use any form of TTL interface. The interface

can be scaled to higher voltages (up to 1.9V) to interface with 1.8V

systems if necessary. The device has a VDDQ and a separate Vref,

allowing the user to designate the interface operational voltage, indepen-

dent of the device core voltage of 1.8V VDD. The output impedance

control allows the user to adjust the drive strength to adapt to a wide

range of loads and transmission lines.

Clocking

The DDRII SRAM has two sets of input clocks, namely the K, K clocks

and the C, C clocks. In addition, the DDRII has an output “echo” clock,

CQ, CQ.

The K and K clocks are the primary device input clocks. The K clock

is used to clock in the control signals (LD, R/W and BWx or NWx), the

address, and the first word of the data burst during a write operation.

Functional Block Diagram

Notes

1) Represents 8 data signal lines for x8, 9 signal lines for x9, 18 signal lines for x18, and 36 signal lines for x36

2) Represents 20 address signal lines for x8 and x9, 19 address signal lines for x18, and 18 address signal lines for x36.

3) Represents 1 signal line for x9, 2 signal lines for x18, and four signal lines for x36. On x8 parts, the BW is a “nibble write” and there are 2

signal lines.

4) Represents 16 data signal lines for x8, 18 signal lines for x9, 36 signal lines for x18, and 72 signal lines for x36.

◆ JT AG Interface

DATA

REG

ADD

REG

CTRL

LOGIC

CLK

GEN

(Note2)

A

LD

R/W (Note3)

BWx

K

C

SELECT OUTPUT CONTROL

WRITE/READDECODE

SENSEAMPS

OUTPUTREG

OUTPUTSELECT

WRITE DRIVER

(Note2)

CQ

DQ

(Note1)

(Note4)

18M

MEMORY

ARRAY

CQ

6112 drw 16

S

(Note1)

SA0

(Note 1)

6.422

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

signals can be used to prevent writing any byte or individual nibbles,

or combined to prevent writing one word of the burst. The x18 and

x36 DDRll devices have the ability to address to the individual word

level using the SA0 address, but the burst will continue in a linear

sequence and wrap back on itself. The address will not increment to

the next higher burst address location, but instead will return to it’s

own lower words within the burst location. Similarly when reading x18

and x36 DDRll devices, the read burst will begin at the designated

address, but if the burst is started at any other position than the first

word of the burst, the burst will wrap back on itself and read the first

locations before completing.

Output Enables

The DDRII SRAM automatically enables and disables the DQ[X:0]

outputs. When a valid read is in progress, and data is present at the

output, the output will be enabled. If no valid data is present at the output

(read not active), the output will be disabled (high impedance). The

echo clocks will remain valid at all times and cannot be disabled or turned

off. During power-up the DQ outputs will come up in a high impedance

state.

Programmable Impedance

An external resistor , RQ, must be connected between the ZQ pin on

the SRAM and Vss to allow the SRAM to adjust its output drive imped-

ance. The value of RQ must be 5X the value of the intended drive

impedance of the SRAM. The allowable range of RQ to guarantee

impedance matching with a tolerance of +/- 10% is between 175 ohms

and 350 ohms, with VDDQ = 1.5V. The output impedance is adjusted

every 1024 clock cycles to correct for drifts in supply voltage and tem-

perature. If the user wishes to drive the output impedance of the SRAM

to it’s lowest value, the ZQ pin may be tied to VDDQ.

The C and C clocks may be used to clock the data out of the output

register during read operations and to generate the echo clocks. C and

C must be presented to the SRAM within the timing tolerances. The

output data from the DDRII will be closely aligned to the C and C input,

through the use of an internal DLL. When C is presented to the DDRII

SRAM, the DLL will have already internally clocked the first data word to

arrive at the device output simultaneously with the arrival of the C clock.

The C and second data word of the burst will also correspond.

Single Clock Mode

The DDRII SRAM may be operated with a single clock pair . C and C

may be disabled by tying both signals high, forcing the outputs and echo

clocks to be controlled instead by the K and K clocks.

DLL Operation

The DLL in the output structure of the DDRII SRAM can be used to

closely align the incoming clocks C and C with the output of the data,

generating very tight tolerances between the two. The user may disable

the DLL by holding Doff low . With the DLL off, the C and C (or K and K

if C and C are not used) will directly clock the output register of the SRAM.

With the DLL off, there will be a propagation delay from the time the clock

enters the device until the data appears at the output.

Echo Clock

The echo clocks, CQ and CQ, are generated by the C and C clocks

(or K, K if C, C are disabled). The rising edge of C generates the rising

edge of CQ, and the falling edge of CQ. The rising edge of C generates

the rising edge of CQ and the falling edge of CQ. This scheme improves

the correlation of the rising and falling edges of the echo clock and will

improve the duty cycle of the individual signals.

The echo clock is very closely aligned with the data, guaranteeing that

the echo clock will remain closely correlated with the data, within the

tolerances designated.

Read and Write Operations

Read operations are initiated by holding Read/Write control input

(R/W) high, the load control input (LD) low and presenting the read

address to the address port during the rising edge of K, which will latch

the address. The data will then be read and will appear at the device

output at the designated time in correspondence with the C and C clocks.

Write operations are initiated by holding the Read/Write control input

(R/W) low, the load control input ( LD) low and presenting the write

address to the address port during the rising edge of K, which will latch

the address. On the following rising edge of K, the first word of the two

word burst must be present on the data input bus DQ[x:O], along with the

appropriate byte write or nibble write (BW or NW) inputs. On the follow-

ing rising edge of K, the second half of the data write burst will be

accepted at the device input with the designated (BW or NW) inputs.

DDRII devices internally store two words of the burst as a single,

wide word and will retain their order in the burst. The x8 and x9

DDRII devices do not have the ability to address to the single word

level or reverse the burst order; however the byte and nibble write

The K clock is used to clock in the control signals (BWx or NWx), and the

second word of the data burst during a write operation. The K and K

clocks are also used internally by the SRAM. In the event that the user

disables the C and C clocks, the K and K clocks will also be used to clock

the data out of the output register and generate the echo clocks.

6.42

3

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

Symbol

Pi n Function

Description

DQ[X:0] Input/Output

Synchronous

Data I/O signals. Data inputs are sampled on the rising edge of K and K during valid write operations. Data

outputs are driven during a valid read operation. The outputs are aligned with the rising edge of both C and C

during normal operation. When operating in a single clock mode (C and C tied high), the outputs are aligned

with the rising edge of both K and K. When a Read operation is not initiated or LD is high (deselected) during

the rising edge of K, DQ[X:O] are automatically driven to high impedance after any previous read operation in

progress completes.

2M x 8 -- DQ[7:0]

2M x 9 -- DQ[8:0]

1M x 18 -- DQ[17: 0]

512K x 36 -- DQ[35:0]

BW0, BW1,

BW2, BW3Input

Synchronous

Byte Write Sele ct 0, 1, 2, and 3 are activ e LOW. Samp le d o n the ris ing e dg e o f the K and again on the rising

edge of K clocks d uring write operations. Used to select which byte is written into the device during the

current portion of the write operations. Bytes not written remain unaltered. All the byte writes are sampled on

the same edge as the d ata. Deselecting a Byte Write Select will cause the corre spo nd ing byte of data to be

ignored and not written in to the device.

2M x 9 -- BW0 controls DQ[8:0]

1M x 18 -- BW0 controls DQ[8:0] and BW1 co ntro ls DQ[17:9]

512K x 36 -- BW0 controls DQ[8:0], BW1 co ntro ls DQ[17:9] , BW2 c ontro ls DQ[26:18] and BW3 co ntro ls DQ[35:27]

NW0, NW1Input

Synchronous

Nibble Write Select 0 and 1 are active LOW. Available only on x8 bit parts instead of Byte Write Selects.

Sampled on the rising edge of the K and K clocks during write operations. Used to select which nibble is

written into the device during the current portion of the write operations. Nibbles not written remain unaltered.

All the nibble writes are sampled on the same edge as the data. Deselecting a Nibble Write Select will cause

the corresponding nibble of data to be ignored and not written in to the device.

SA Input

Synchronous Address Inputs. Addresses are sampled on the rising edge of K clock during active read or write operations.

SA0Input

Synchronous Burst count address bit on x18 and x36 DDRll devices. This bit allows reversing the burst order in read or

write operations, or addressing to the individual word of a burst.

LD

Input

Synchronous

Lo ad Contro l Log ic: Samp led on the rising ed ge o f K. If LD is low, a two word burst read or write operation

will initiate as designated by the R/ W i n put. If LD is high during the rising edge of K, operations in progress

will complete, but new operations will not be initiated.

R/W

Input

Synchronous

Read or Write Control Logic. If LD is low during the rising edge of K, the R/W indicates whether a new

operation should be a read or write. If R/W is high, a read operation will be initiated, if R/W is low, a write

operation will be initiated. If the LD input is high during the rising edge of K, the R/W input will be ig nored.

CInput Clock

P o sitiv e Outp ut Cl o ck Inp ut. C i s us e d in c onj unc tio n wi th C to c lo ck o ut the Re ad d ata from the d e vic e . C

and C can be used toge ther to deskew the flight times of various devices on the board back to the controller.

See app licatio n example fo r further de tails .

CInp ut Clo c k Neg a tive O utpu t C l ock In pu t. C is used in conjunction with C to clock out the Read data fro m the device. C

and C can be used toge ther to deskew the flight times of various devices on the board back to the controller.

See app licatio n example fo r further de tails .

KInput Clock

Positive Input Clock. The rising ed ge of K is used to capture synchronous inputs to the device and to drive

out data through DQ[X:0] when in single clock mode. All accesses are initiated on the rising edge of K.

KInp ut Clo c k Ne gative Input Clock. K is used to capture synchronous inputs being presented to the device and to drive out

data through DQ[X:0] when in single clock mode.

CQ, CQ Output Cloc k

Synchronous Echo clock outputs. The rising edges of these outputs are tightly matched to the synchronous

data outputs and can be used as a data valid indication. These signals are free running and do not stop when

the outp ut d ata is thre e s tate d .

ZQ Input Output Impedance Matching Input. This input is used to tune the device outputs to the system data bus

impedance. DQ[X:0] output impedance is set to 0.2 x RQ, where RQ is a resistor connected between ZQ and

ground. Alternately, this pin can be connected directly to VDDQ, which enables the minimum impedance mode.

This pin cannot be connec ted directly to GND or left unconnected.

6112 tb l 02a

Pin Definitions

6.424

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

Symbol Pin Function Description

Doff Input

DL L Tu rn O ff. Whe n lo w this i np ut will turn o ff t he DLL ins id e the d e v i ce . The A C ti mi ng s wi th

the DLL turned o ff will be diffe re nt from tho se lis ted in this d ata sheet. There will be an

increas ed propagation delay from the incidence o f C and C to DQ, or K and K to DQ as

configured. The propagation delay is not a tes ted parameter, but will be similar to the

propagation delay of other SRAM devices in this speed grade.

TDO Output TDO pin for JTAG

TCK Inp ut TCK pi n fo r J TA G.

TDI Input TDI pin for JTAG. An internal resistor will p ull TDI to V

DD

when the pi n is unconnec ted.

TMS Input TMS p in for JTA G. An internal resistor will pull TMS to V

DD

when the pi n is unconnec ted.

NC No Connect No connects inside the package. Can be tied to any voltag e level

VREF Input

Reference Refe renc e Vo ltag e i np ut . Sta tic in p ut us e d to se t th e refe renc e lev e l fo r HS TL inp uts and

o utp uts as we l l as A C me as ure me nt p o i nts .

VDD Power

Supply Power supp ly inputs to the co re o f the device. Should be connected to a 1.8V powe r

supply.

VSS Gr ound Gr ound fo r the device. Shoul d be c onnected to gr ound of the system.

VDDQ Power

Supply Power supp ly for the outputs of the d evice. Should be co nnected to a 1.5V power supply

for HSTL or scaled to the desired output voltag e.

6112 tb l 0 2b

Pin Definitions continued

6.42

5

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

Pin Configuration 2M x 8

1234567891011

ACQ V

SS

/

SA (2) SA R/W NW

1

KNC LD SA V

SS

/

SA (1) CQ

BNC NC NC SA NC K NW

0

SA NC NC DQ

3

CNC NC NC V

SS

SA SA SA V

SS

NC NC NC

DNC NC NC V

SS

V

SS

V

SS

V

SS

V

SS

NC NC NC

ENC NC DQ

4

V

DDQ

V

SS

V

SS

V

SS

V

DDQ

NC NC DQ

2

FNC NC NC V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC NC

GNC NC DQ

5

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC NC

HDoff V

REF

V

DDQ

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

V

DDQ

V

REF

ZQ

JNC NC NC V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC DQ

1

NC

KNC NC NC V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC NC

LNC DQ

6

NC V

DDQ

V

SS

V

SS

V

SS

V

DDQ

NC NC DQ

0

MNC NC NC V

SS

V

SS

V

SS

V

SS

V

SS

NC NC NC

NNC NC NC V

SS

SA SA SA V

SS

NC NC NC

PNC NC DQ

7

SA SA C SA SA NC NC NC

RTDO TCK SA SA SA CSA SA SA TMS TDI

6 112 t bl 12

165-ball FBGA Pinout

TOP VIEW

NOTES:

1. A10 is reserved for the 36Mb expansion address.

2. A2 is reserved for the 72Mb expansion address.

6.426

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

Pin Configuration 2M x 9

1234567891011

ACQ V

SS

/

SA (2) SA R/WNC KNC LD SA V

SS

/

SA (1) CQ

BNC NC NC SA NC K BW SA NC NC DQ

3

CNC NC NC V

SS

SA SA SA V

SS

NC NC NC

DNC NC NC V

SS

V

SS

V

SS

V

SS

V

SS

NC NC NC

ENC NC DQ

4

V

DDQ

V

SS

V

SS

V

SS

V

DDQ

NC NC DQ

2

FNC NC NC V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC NC

GNC NC DQ

5

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC NC

HDoff V

REF

V

DDQ

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

V

DDQ

V

REF

ZQ

JNC NC NC V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC DQ

1

NC

KNC NC NC V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC NC

LNC DQ

6

NC V

DDQ

V

SS

V

SS

V

SS

V

DDQ

NC NC DQ

0

MNC NC NC V

SS

V

SS

V

SS

V

SS

V

SS

NC NC NC

NNC NC NC V

SS

SA SA SA V

SS

NC NC NC

PNC NC DQ

7

SA SA C SA SA NC NC DQ

8

RTDO TCK SA SA SA CSA SA SA TMS TDI

6112 tb l 12a

165-ball FBGA Pinout

TOP VIEW

NOTES:

1. A10 is reserved for the 36Mb expansion address.

2. A2 is reserved for the 72Mb expansion address.

6.42

7

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

Pin Configuration 1M x 18

1234567891011

ACQ V

SS

/

SA (2) SA R/W BW

1

KNC LD SA V

SS

/

SA (1) CQ

BNC DQ9NC SA NC K BW

0

SA NC NC DQ8

CNC NC NC V

SS

SA SA

0

SA V

SS

NC DQ7NC

DNC NC DQ10 V

SS

V

SS

V

SS

V

SS

V

SS

NC NC NC

ENC NC DQ11 V

DDQ

V

SS

V

SS

V

SS

V

DDQ

NC NC DQ6

FNC DQ12 NC V

DDQ

VDD VSS V

DD

V

DDQ

NC NC DQ5

GNC NC DQ13 V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC NC NC

HDoff V

REF

V

DDQ

V

DDQ

V

DD

V

SS

V

DD

V

DDQ

V

DDQ

V

REF

ZQ

JNC NC NC V

DDQ

V

DD

V

SS

V

DD

V

DDQ

NC DQ4NC

KNC NC DQ14 V

DDQ

V

DD

VSS V

DD

V

DDQ

NC NC DQ3

LNC DQ15 NC V

DDQ

VSS VSS V

SS

V

DDQ

NC NC DQ2

MNC NC NC V

SS

V

SS

V

SS

V

SS

V

SS

NC DQ

1

NC

NNC NC DQ16 V

SS

SA SA SA V

SS

NC NC NC

PNC NC DQ17 SA SA C SA SA NC NC DQ0

RTDO TCK SA SA SA CSA SA SA TMS TDI

6112 tbl 12b

165-ball FBGA Pinout

TOP VIEW

NOTES:

1. A10 is reserved for the 36Mb expansion address. This must be tied or driven to Vss on the 1M x 18 DDRII Burst of 2 (71P71804) devices.

2. A2 is reserved for the 72Mb expansion address. This must be tied or driven to VSS on the 1M x 18 DDRII Burst of 2 (71P7180 4) devices.

6.428

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

Pin Configuration 512K x 36

165-ball FBGA Pinout

TOP VIEW

1234567891011

ACQ VSS/

SA (3) NC/

SA (1 ) R/W BW2KBW

1LD SA VSS/

SA (2) CQ

BNC DQ

27

DQ

18

SA BW3KBW0SA NC NC DQ

8

CNC NC DQ

28

VSS SA SA

0

SA VSS NC DQ

17

DQ

7

DNC DQ

29

DQ

19

VSS VSS VSS VSS VSS NC NC DQ

16

ENC NC DQ

20

VDDQ VSS VSS VSS VDDQ NC DQ

15

DQ

6

FNC DQ

30

DQ

21

VDDQ VDD VSS VDD V

DDQ

NC NC DQ

5

GNC DQ

31

DQ

22

VDDQ V

DD

VSS VDD VDDQ NC NC DQ

14

HDoff V

REF

V

DDQ

VDDQ V

DD

VSS VDD VDDQ V

DDQ

V

REF

ZQ

JNC NC DQ

32

VDDQ V

DD

VSS VDD VDDQ NC DQ

13

DQ

4

KNC NC DQ

23

VDDQ V

DD

VSS VDD VDDQ NC DQ

12

DQ

3

LNC DQ

33

DQ

24

VDDQ VSS VSS VSS VDDQ NC NC DQ

2

MNC NC DQ

34

VSS VSS VSS VSS VSS NC DQ

11

DQ

1

NNC DQ

35

DQ

25

VSS SA SA SA V

SS

NC NC DQ

10

PNC NC DQ

26

SA SA C SA SA NC DQ

9

DQ

0

RTDO TCK SA SA SA CSA SA SA TMS TDI

6112 tbl 12c

NOTES:

1. A3 is reserved for the 36Mb expansion address.

2. A10 is reserved for the 72Mb expansion address.

3. A2 is reserved for the 144Mb expansion address

6.42

9

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

NOTES:

1) All byte write (BWx) and nibble write (NWx) signals are sampled on the

rising edge of K and again on K. The data that is present on the data bus in the

designated byte/nibble will be latched into the input if the corresponding BWx or

NWx is held low. The rising edge of K will sample the first byte/nibble of the

two word burst and the rising edge of K will sample the second byte/nibble of

the two word burst.

2) The availability of the BWx or NWx on designated devices is described in

the pin description table.

3) The DDRII Burst of two SRAM has data forwarding. A read request that is

initiated on the cycle following a write request to the same address will produce

the newly written data.

Signal

BW0BW1BW2BW3NW0NW1

Write Byte 0 LXXXXX

Write By te 1 X L X X X X

Write By te 2 X X L X X X

Write Byte 3 XXX LXX

Write Nibble 0 X X X X L X

Write Nibble 1 XXXXXL

6112 tbl 09

Write Descriptions(1,2) Linear Burst Sequence Table (1,2)

NOTE:

1. SA0 is the address presented giving the burst sequence a,b.

2. SA0 is only available on the x18 and x36-bit devices.

SA

0

ab

0

01

1

10

6112 tbl 22

6.4210

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

Application Example

SRAM #1

ALD R/WBW

0

BW1CCKK

DQ

ZQ

ALD BW0BW1CCKK

DQ

ZQ

R=250 R=250

Vt

Data Bus

Address

LD

R/W

MEMORY

CONTROLLER

Return CLK

Source CLK

Return CLK

Source CLK R=50

Vt

R

Ω

Vt =VREF

Vt

R

6112 drw 20

SRAM #4

BWx/NWx

R/W

SS

Vt

t

V

R

6.42

11

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

Absolute Maximum Ratings(1) (2) Capacitance (TA = +25°C, f = 1.0MHz)(1)

Symbol

Rating

Value

Unit

V

TERM

Supply Voltage on V

DD

with

Re sp ect to GND –0.5 to +2.9 V

V

TERM

Supply Voltage on V

DDQ

with

Re sp ect to GND –0.5 to V

DD

+0.3 V

V

TERM

Vo lta g e o n Inp ut te rm inals with

respec t to GN D –0.5 to V

DD

+0.3 V

V

TERM

Voltage on Output and I/O

term in als w ith res pect to GN D. –0.5 to V

DDQ

+0.3 V

T

BIAS

Temperature Under Bias –55 to +125 °C

T

STG

Storage Temperature –65 to +150 °C

I

OUT

Continuous Current into Outputs + 20 mA

6112 tbl 05

Symbol

Parameter

Conditions

Max.

Unit

C

IN

Inp ut Cap ac itance V

DD

= 1.8V

V

DDQ

= 1.5V

5pF

C

CLK

Clock Input Capacitance 6 pF

C

O

Output Capacitance 7 pF

6112 tbl 06

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those

indicated in the operational sections of this specification is not implied. Exposure

to absolute maximum rating conditions for extended periods may affect

reliability.

2. VDDQ must not exceed VDD during normal operation.

NOTE:

1 . Tested at characterization and retested after any design or process change that

may affect these parameters.

Recommended DC Operating and

Temperature Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

VDD Power Supply

Voltage 1.7 1.8 1.9 V

VDDQ I/O Supp ly Vo ltage 1.4 1.5 1.9 V

VSS Ground 0 0 0 V

VREF Input R e fer e n c e

Voltage 0.68 VDDQ/2 0.95 V

TAAmbient

Temperature (1) 0

_

+70 o

c

6 112 tb l 04

NOTE:

1. During production testing, the case temperature equals the ambient

temperature.

6.4212

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

DC Electrical Characteristics Over the Operating Temperature and

Supply Voltage Range (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V)

Parameter

Symbol

Test Conditions

Min

Max

Unit

Note

Input Leakage Current

I

IL

V

DD

= Max V

IN

= V

SS

to V

DDQ

-10

+10

µ

A

Output Leakage Current

I

OL

Output Disabled

-10

+10

µ

A

Operating Current

(x36,x18,x9,x8): DDR

I

DD

V

DD

= Max,

I

OUT

= 0mA (outputs open),

Cycle Time

>

t

KHKH

Min

333MH

Z

-

TBD

mA

1

300MH

Z

-

TBD

250MH

Z

-

TBD

200MHz

-

TBD

167MHz

-

TBD

Standb y Current: NOP

I

SB1

Device Deselected (in NOP state),

I

OUT

= 0mA (outputs open),

f=Max,

All Inputs

<

0.2V or

>

VDD -0.2V

333MH

Z

-

TBD

mA

2

300MH

Z

-

TBD

250MH

Z

-

TBD

200MHz

-

TBD

167MHz

-

TBD

Output High Voltage

V

OH1

RQ = 250

Ω,

I

OH

= -15mA

V

DDQ

/2-0.12

V

DDQ

/2+0.12

V

3,7

Output Low Voltage

V

OL1

RQ = 250

Ω,

I

OH

= 15mA

V

DDQ

/2-0.12

V

DDQ

/2+0.12

V

4,7

Output High Voltage

V

OH2

I

OH

= -0.1mA

V

DDQ

-0.2

V

DDQ

V

5

Output Low Voltage

V

OL2

I

OL

= 0.1mA

V

SS

0.2

V

6

6112 tb l 10 c

NOTES:

1. Operating Current is measured at 100% bus utilization.

2. Standby Current is only after all pending read and write burst operations are completed.

3. Outputs are impedance-controlled. IOH = -(VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This

parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.

4. Outputs are impedance-controlled. IOL = (VDDQ/2)/(RQ/5) and is guaranteed by device characterization for 175Ω < RQ < 350Ω. This

parameter is tested at RQ = 250Ω, which gives a nominal 50Ω output impedance.

5. This measurement is taken to ensure that the output has the capability of pulling to the VDDQ rail, and is not intended to be used as an

impedance measurement point.

6. This measurement is taken to ensure that the output has the capability of pulling to Vss, and is not intended to be used as an impedance

measurement point.

7. Programmable Impedance Mode.

6.42

13

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

AC Test Load

Device R

L

=50

Ω

Z

0

=50

Ω

V

DDQ

/2

Under

Test

V

REF

OUTPUT

6112 drw 04

ZQ R

Q

=250

Ω

DDQ

/2

V

Parameter

Symbol

Value

Unit

Core P owe r S up ply Vo l ta g e V DD 1.7-1.9 V

Output Power Supply Voltage VDDQ 1.4-1.9 V

Input High/Low Level VIH/VIL 1.25/0.25 V

Inp u t Refe r e nc e L e v e l V RE F V DDQ/2 V

Inp ut Ris e/ Fall Time TR/TF 0.3/0.3 ns

Outp ut Timing Reference Level VDDQ/2 V

6112 tbl 11 a

AC Test Conditions

NOTE:

1. Parameters are tested with RQ=250Ω

1.25V

0.25V

6112 drw 06

0.75V

PARAMETER SYMBOL MIN MAX UNIT NOTES

Input High Voltage, DC V

IH

(DC

)V

REF

+0.1 V

DDQ

+0.3 V 1,2

In p ut L o w Vo l ta g e , DC V

IL

(DC)

-0.3 V

REF

-0.1 V 1, 3

Input High Voltage, AC V

IH

(AC)

V

REF

+0.2 - V 4,5

Input Low Voltag e, AC V

IL

(AC)

-V

REF

-0.2 V 4,5

6112 tbl 10d

Input Electrical Characteristics Over the Operating Temperature and

Supply Voltage Range (VDD = 1.8 ± 100mV , VDDQ = 1.4V to 1.9V)

1. These are DC test criteria. DC design criteria is VREF + 50mV. The AC VIH/VIL levels are defined separately for measuring timing parameters.

2. VIL (Min) DC = -0.3V, VIL (Min) AC = -0.5V (pulse width <20% tKHKH (min))

3. VIH (Max) DC = VDDQ+0.3, VIH (Max) AC = VDD +0.5V (pulse width <20% tKHKH (min))

4. This conditon is for AC function test only, not for AC parameter test.

5. To maintain a valid level, the transitioning edge of the input must:

a) Sustain a constant slew rate from the current AC level through the target AC level, VIL(AC) or VIH(AC)

b) Reach at leaset the target AC level.

c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC)

NOTES:

V

I

L

V

D

V

D

+0.25

V

D

+0.5

20% tKHKH (MIN)

6112 drw 21

VSS

V

IH

VSS-0.25V

VSS-0.5V

20% tKHKH (MIN)

6112 drw 22

Overshoot Timing Undershoot Timing

6.4214

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

AC Electrical Characteristics (VDD = 1.8 ± 100mV, VDDQ = 1.4V to 1.9V, TA =0 to 70°C) (3,8)

Symbol Parameter

333MHz 300MHz 250MHz 200MHz 167MHz

Unit Notes

Min. Max Min. Max Min. Max Min. Max Min. Max

Clock P arameters

tKHKH Average clock cycle time (K,K,C,C) 3.00 3.47 3.30 5.25 4.00 6.30 5.00 7.88 6.00 8.40 ns

tKC va r Cycle to Cycle Period Jitter (K,K,C,C) - 0.20 - 0.20 - 0.20 - 0.20 - 0.20 ns 1,5

tKHKL Clo c k Hig h Ti me (K, K,C,C) 1.20 - 1.32 - 1.60 - 2.00 - 2.40 - ns 9

tKLKH Clo c k LOW Ti me (K, K,C,C) 1.20 - 1.32 - 1.60 - 2.00 - 2.40 - ns 9

tKHKHClo ck to clock (K→K,C→C) 1.35 - 1.49 - 1.80 - 2.20 - 2.70 - ns 10

tKHKH Clock to c l o c k (K→K,C→C) 1.35 - 1.49 - 1.80 - 2.20 - 2.70 - ns 10

tKHCH Clock to data clock (K→C,K→C) 0.00 1.30 0.00 1.45 0.00 1.80 0.00 2.30 0.00 2.80 ns

tKC loc k DLL lock time (K, C) 1024 - 1024 - 1024 - 1024 - 1024 - cycl es 2

tKC res et K stati c to DLL reset 30 - 30 - 30 - 30 - 30 - ns

Output P aram eters

tCHQV C,C HIGH to outp ut vali d - 0.45 - 0.45 - 0.45 - 0.45 - 0. 50 ns 3

tCHQX C,C HIGH to ou tp ut ho ld -0. 45 - -0 .45 - -0. 45 - -0.45 - -0. 50 - ns 3

tCHCQV C,C HIGH to e cho cloc k valid - 0.45 - 0.45 - 0.45 - 0.45 - 0. 50 ns 3

tCHCQX C,C HIGH to echo clock hold -0.45 - -0.45 - -0.45 - -0.45 - -0.50 - ns 3

tCQHQV CQ,CQ HIGH to outp ut val id - 0.25 - 0.27 - 0.30 - 0.35 - 0. 40 ns

tCQHQX CQ,CQ HIGH to o utp ut ho ld -0. 25 - -0. 27 - -0.3 0 - -0.35 - -0. 40 - ns

tCHQZ C HIGH to o utput Hig h-Z - 0. 45 - 0.45 - 0.45 - 0.45 - 0.50 ns 3,4, 5

tCHQX1 C HIGH to outp ut Low-Z -0.45 - -0. 45 - -0.45 - -0.45 - -0. 50 - ns 3,4, 5

Set-Up Tim es

tAVKH Address valid to K,K rising edge 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 6

tIVKH Control inputs valid to K,K rising edge 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 7

tDVKH D ate-i n val id to K, K rising edge 0.30 - 0.30 - 0.35 - 0.40 - 0.50 - ns

Hol d T i mes

tKHAX K,K rising edge to address hold 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 6

tKHIX K,K ris ing edge to contro l inputs ho ld 0.40 - 0.40 - 0.50 - 0.60 - 0.70 - ns 7

tKHDX K, K ri sing edge to data-in hol d 0.30 - 0.30 - 0.35 - 0.40 - 0.50 - ns

6112 tbl 11

NOTES:

1. Cycle to cycle period jitter is the variance from clock rising edge to the next expected clock rising edge, as defined per JEDEC Standard No.65 (EIA/JESD65) pg.10

2. Vdd slew rate must be less than 0.1V DC per 50 ns for DLL lock retention. DLL lock time begins once Vdd and input clock are stable.

3. If C,C are tied High, K,K become the references for C,C timing parameters.

4. To avoid bus contention, at a given voltage and temperature tCHQX1 is bigger than tCHQZ.

The specs as shown do not imply bus contention because tCHQX1 is a MIN parameter that is worse case at totally different test conditions

(0°C, 1.9V) than tCHQZ, which is a MAX parameter (worst case at 70°C, 1.7V)

It is not possible for two SRAMs on the same board to be at such different voltage and temperature.

5. This parameter is guaranteed by device characterization, but not production tested.

6. All address inputs must meet the specified setup and hold times for all latching clock edges.

7. Control signals are R, W,BW0,BW1 and (NW0,NW1, for x8) and (BW2,BW3 also for x36)

8. During production testing, the case temperature equals TA.

9. Clock High Time (tKHKL) and Clock Low Time (tKLKH) should be within 40% to 60% of the cycle time (tKHKH).

10. Clock to clock time (tKHKH) and Clock to clock time (tKHKH) should be within 45% to 55% of the cycle time (tKHKH).

6.42

15

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

Timing Waveform of Combined Read and Write Cycles

NOTE:

1. If a R/W is low on the next rising edge of K after a read request, the device automatically performs a NOP (No Operation.)

2. The second NOP cycle is not necessary for correct device operation; however , at high clock frequencies, it may be required to

prevent the bus contention.

6112 drw09

K

123

LD

SA

t

K

H

C

H

t

K

H

K

L

t

K

H

I

X

t

I

V

K

H

t

K

H

A

X

t

A

V

K

H

C

CQ

t

C

H

Q

X

t

C

H

Q

X

1

t

D

V

K

H

t

K

H

D

X

t

K

H

D

X

D20 D21 D30 D31

t

D

V

K

H

t

K

L

K

H

t

C

H

C

Q

V

t

C

H

C

Q

X

R

/

W

DQ

4567

t

K

L

K

H

t

K

H

K

H

t

K

H

K

H

A2A1

A0 A3

t

C

H

Q

V

t

C

H

Q

X

t

C

H

Q

V

t

C

Q

H

Q

V

t

K

H

C

H

t

K

H

K

L

NOP Read A0

(burst of 2) Read A1

(burst of 2) NOP

(Note 1) WriteA2

(burst of 2) Read A4

(burst of 2)

Q00 Q01 Q10 Q11 Q40 Q41

8

NOP

A4

Qx1

t

C

H

Q

Z

t

K

H

K

H

t

K

H

K

H

t

C

H

C

Q

X

t

C

H

C

Q

V

WriteA3

(burst of 2)

910

t

C

Q

H

Q

X

(

N

O

T

E

1

)

(

N

O

T

E

2

)

6.4216

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

IEEE 1149.1 TEST ACCESS PORT AND BOUNDARY SCAN-JTAG

This part contains an IEEE standard 1 149.1 Compatible T est Access Port (T AP). The package pads are monitored by the Serial Sca n circuitry

when in test mode. This is to support connectivity testing during manufacturing and system diagnostics. In conformance with IEEE 1 149.1, the

SRAM contains a T AP controller , Instruction register, Bypass Register and ID register. The T AP controller has a standard 16-st ate machine that

resets internally upon power-up; therefore, the TRST signal is not required. It is possible to use this device without utilizi ng the T AP. T o disable

the T AP controller without interfacing with normal operation of the SRAM, TCK must be tied to VSS to preclude a mid level input. TMS and TDI

are designed so an undriven input will produce a response identical to the application of a logic 1, and may be left unconnected, but they may

also be tied to VDD through a resistor . TDO should be left unconnected.

JTAG Block Diagram JTAG Instruction Coding

IR2

IR1

IR0

Instruction

TDO Output

Notes

0

EXTEST

Boundary Scan Register

0

IDCODE

Identification register

2

0

1

0

SAMPLE-Z

Boundary Scan Register

1

0

1

RESERVED

Do Not Use

5

1

0

SAMPLE/PRELOAD

Boundary Scan register

4

1

0

1

RESERVED

Do Not Use

5

1

0

RESERVED

Do Not Use

5

1

BYPASS

Bypass Register

3

6112 tbl 13

TAP Controller State Diagram

SRAM

CORE

BYPASS Re

g

.

Identification Re

g

.

Instruction Re

g

.

ControlSi

g

nal

s

TAP Controller

TDI

TMS

TCK

TDO

6112 drw 18

Test Logic Reset

Run Test Idle Select DR

Capture DR

Pause DR

Exit 2 DR

Update DR

Shift DR

Exit 1 DR

Select IR

Capture IR

Pause IR

Exit 2 IR

Update IR

Shift IR

Exit 1 IR

0

1

0

6112 drw 17

0

1

0

1

0

NOTE:

1. Places DQs in Hi-Z in order to sample all input data regardless of other

SRAM inputs.

2. TDI is sampled as an input to the first ID register to allow for the serial shift

of the external TDI data.

3. Bypass register is initialized to Vss when BYP ASS instruction is invoked.

The Bypass Register also holds serially loaded TDI when exiting the Shift DR

states.

4. SAMPLE instruction does not place output pins in Hi-Z.

5. This instruction is reserved for future use.

6.42

17

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

Part

Instrustion Register

Bypass Register

ID Register

Boundary Scan

512K x36 3 b its 1 b it 32 bi ts 107 bits

1Mx18 3 b its 1 bit 32 bits 107 bits

2Mx8/x 9 3 bits 1 b it 32 bits 107 bits

6112 tbl 14

Scan Register Definition

Identification Register Definitions

INSTRUCTION FIELD

ALL DE V ICE S

DESCRIPTION

PART NUMBER

Revision Number (31:29) 000 Revision Number

De vi ce ID (28: 12) 0 0000 0010 0101 0100

0 0000 0010 0101 0101

0 0000 0010 0101 0110

0 0000 0010 0100 0111

51 2K x36 DDRII BURS T OF 2

1Mx18

2Mx9

2Mx8

71P71604S

71P71804S

71P71104S

71P71204S

IDT J EDEC ID CODE (11: 1) 000 0011 0011 Allo ws uniq ue id e nti fic ati on o f S RAM

vendor.

ID Register Presence

Ind ic ato r (0) 1 Indicates the presence of an ID register.

6112 tbl 15

6.4218

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

ORDER PI N ID

16R

26P

36N

47P

57N

67R

78R

88P

99R

10 11P

11 10P

12 10N

13 9P

14 10M

15 11N

16 9M

17 9N

18 11L

19 11M

20 9L

21 10L

22 11K

23 10K

24 9J

25 9K

26 10J

27 11J

28 11H

29 10G

30 9G

31 11F

32 11G

33 9F

34 10F

35 11E

36 10E

6112 tbl 16a

ORDER PI N ID

37 10D

38 9E

39 10C

40 11D

41 9C

42 9D

43 11B

44 11C

45 9B

46 10B

47 11A

48 Internal

49 9A

50 8B

51 7C

52 6C

53 8A

54 7A

55 7B

56 6B

57 6A

58 5B

59 5A

60 4A

61 5C

62 4B

63 3A

64 2A

65 1A

66 2B

67 3B

68 1C

69 1B

70 3D

71 3C

72 2D

6112 tb l 17 a

ORDER PIN ID

73 3E

74 2C

75 1D

76 2E

77 1E

78 2F

79 3F

80 2G

81 3G

82 1F

83 1G

84 1J

85 2J

86 3K

87 3J

88 3L

89 2L

90 1K

91 2K

92 1M

93 1L

94 3N

95 3M

96 2N

97 3P

98 2M

99 1N

100 2P

101 1P

102 3R

103 4R

104 4P

105 5P

106 5N

107 5R

6112 tb l 18 a

Boundary Scan Exit Order (2M x 8-Bit, 2M x 9-Bit)

6.42

19

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

Boundary Scan Exit Order (1M x 18-Bit)

ORDER PI N ID

16R

26P

36N

47P

57N

67R

78R

88P

99R

10 11P

11 10P

12 10N

13 9P

14 10M

15 11N

16 9M

17 9N

18 11L

19 11M

20 9L

21 10L

22 11K

23 10K

24 9J

25 9K

26 10J

27 11J

28 11H

29 10G

30 9G

31 11F

32 11G

33 9F

34 10F

35 11E

36 10E

6112 tbl 16

ORDER PI N ID

37 10D

38 9E

39 10C

40 11D

41 9C

42 9D

43 11B

44 11C

45 9B

46 10B

47 11A

48 Internal

49 9A

50 8B

51 7C

52 6C

53 8A

54 7A

55 7B

56 6B

57 6A

58 5B

59 5A

60 4A

61 5C

62 4B

63 3A

64 1H

65 1A

66 2B

67 3B

68 1C

69 1B

70 3D

71 3C

72 1D

6112 tbl 17

ORDER PIN ID

73 2C

74 3E

75 2D

76 2E

77 1E

78 2F

79 3F

80 1G

81 1F

82 3G

83 2G

84 1J

85 2J

86 3K

87 3J

88 2K

89 1K

90 2L

91 3L

92 1M

93 1L

94 3N

95 3M

96 1N

97 2M

98 3P

99 2N

100 2P

101 1P

102 3R

103 4R

104 4P

105 5P

106 5N

107 5R

6112 tbl 18

6.4220

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

ORDER PI N ID

16R

26P

36N

47P

57N

67R

78R

88P

99R

10 11P

11 9P

12 10N

13 10P

14 11M

15 9N

16 9M

17 11N

18 11L

19 10L

20 9L

21 10M

22 11K

23 9K

24 9J

25 10K

26 11J

27 9G

28 11H

29 10G

30 10J

31 11F

32 10F

33 9F

34 11G

35 11E

36 9E

6112 tbl 16b

ORDER PI N ID

37 10D

38 10E

39 11C

40 9D

41 9C

42 11D

43 11B

44 10B

45 9B

46 10C

47 11A

48 Internal

49 9A

50 8B

51 7C

52 6C

53 8A

54 7A

55 7B

56 6B

57 6A

58 5B

59 5A

60 4A

61 5C

62 4B

63 3A

64 1H

65 1A

66 3B

67 1B

68 1C

69 2B

70 3D

71 2C

72 1D

6112 tbl 17b

ORDER PIN ID

73 3C

74 3E

75 1E

76 2E

77 2D

78 3F

79 1F

80 1G

81 2F

82 3G

83 2J

84 1J

85 2G

86 3K

87 1K

88 2K

89 3J

90 3L

91 1L

92 1M

93 2L

94 3N

95 2M

96 1N

97 3M

98 3P

99 1P

100 2P

101 2N

102 3R

103 4R

104 4P

105 5P

106 5N

107 5R

6112 tbl 18b

Boundary Scan Exit Order (512K x 36-Bit)

6.42

21

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

Parameter Symbol Min Typ Max Unit Note

Outp ut Po wer Supply V

DDQ

1.4 - 1.9 V

Power Supply Voltage V

DD

1.7 1.8 1.9 V

Inp ut Hig h Le v e l V

IH

1.3 - V

DD

+0.3 V

Inp ut Lo w Le ve l V

IL

-0.3 - 0.5 V

Output High Voltage (I

OH

= -1mA) V

OH

V

DDQ -

0.2 - V

DDQ

V1

Output Low Voltage (I

OL

= 1mA) V

OL

V

SS

-0.2V

1

6112 tbl 19

Parameter Symbol Min Unit Note

Input High/Low Level VIH/VIL 1.3/0.5 V

Input Rise/Fall Time TR/TF 1.0/1.0 ns

Input and Output Timing Refere nce Leve l VDDQ/2 V 1

6112 tbl 20

JTAG DC Operating Conditions

JTAG AC Test Conditions

Parameter Symbol Min Max Unit Note

TCK Cy cle Ti m e t

CHCH

50 - ns

TCK High Pulse Width t

CHCL

20 - ns

TCK Low Pulse Width t

CLCH

20 - ns

TMS Input Setup Time t

MVCH

5-ns

TM S In p u t H o l d Ti m e t

CHMX

5-ns

TDI Input S etup Tim e t

DVCH

5-ns

TDI Input Hol d Tim e t

CHDX

5-ns

SRAM Input Setup Time t

SVCH

5-ns

SRAM Input Hold Time t

CHSX

5-ns

Clo ck Lo w to Outp ut Valid t

CLQV

010ns

6112 tbl.2 1

JTAG AC Characteristics

JTAG Timing Diagram

NOTE:

1. The output impedance of TDO is set to 50 ohms (nominal process) and does not vary with the external resistor connected to ZQ.

TC

K

TM

S

t

C

H

C

H

TD

I

/

SR

A

M

Inp

u

t

s

T

D

O

t

M

V

C

H

t

D

V

C

H

t

S

V

C

H

t

C

H

C

L

t

C

H

M

X

t

C

H

D

X

t

C

H

S

X

t

C

L

C

H

t

C

L

Q

V

6112drw 19

SRA

M

Out

p

u

t

s

NOTE:

1. See AC test load on page 12.

6.4222

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

Package Diagram Outline for 165-Ball Fine Pitch Grid Array

6.42

23

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18-Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

Ordering Information

CORPORA TE HEADQUARTERS for SALES: for T ech Support:

2975 Stender Way 800-345-7015 or 408-727-6116 sramhelp@idt.com

Santa Clara, CA 95054 fax: 408-492-8674 800-544-7726

www.idt.com

“QDR SRAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress Semiconductor, IDT, and Micron Technology, Inc. “

S

Power

XXX

Speed

BQ

Package

BQ

IDT 71P71XXX

333

300

250

200

167

6112 drw 15

Device

Type

165 Fine Pitch Ball Grid Array (fBGA)

Clock Frequency in MegaHertz

IDT71P71204 2M x 8 DDR II SRAM Burst of 2

IDT71P71104 2M x 9 DDR II SRAM Burst of 2

IDT71P71804 1M x 18 DDR II SRAM Burst of 2

IDT71P71604 512K x 36 DDR II SRAM Burst of 2

Revision History

IDT71P71204 (2M x 8-Bit), 71P71104 (2M x 9-Bit), 71P71804 (1M x 18 x -Bit) 71P71604 (512K x 36-Bit)

Advance Information

18 Mb DDR II SRAM Burst of 2 Commercial Temperature Range

REVISION DATE PAGES DESCRIPTION

0 05/31/04 1-23 Initial Advance Information Data Sheet Release