6-1
March 1997
HM-6642
512 x 8 CMOS PROM
Features
• Low Power Standby and Operating Power
- ICCSB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100µA
- ICCOP . . . . . . . . . . . . . . . . . . . . . . . . . .20mA at 1MHz
• Fast Access Time. . . . . . . . . . . . . . . . . . . . . . 120/200ns
• Industry Standard Pinout
• Single 5.0V Supply
• CMOS/TTL Compatible Inputs
• Field Programmable
• Synchronous Operation
• On-Chip Address Latches
• Separate Output Enable
Description
The HM-6642 is a 512 x 8 CMOS NiCr fusible link
Programmable Read Only Memory in the popular 24 pin,
byte wide pinout. Synchronous circuit design techniques
combine with CMOS processing to give this device high
speed performance with very low power dissipation.
On-chip address latches are provided, allowing easy
interfacing with recent generation microprocessors that use
multiplexed address/data bus structures, such as the 8085.
The output enable controls, both active low and active high,
further simplify microprocessor system interfacing by
allowing output data bus control independent of the chip
enable control. The data output latches allow the use of the
HM-6642 in high speed pipelined architecture systems, and
also in synchronous logic replacement functions.
Applications for the HM-6642 CMOS PROM include low
power handheld microprocessor based instrumentation and
communications systems, remote data acquisition and
processing systems, processor control store, and synchro-
nous logic replacement.
All bits are manufactured storing a logical “0” and can be
selectively programmed for a logical “1” at any bit location.
Ordering Information
PACKAGE TEMPERATURE RANGE 120ns 200ns PKG. NO.
SBDIP -40oC to +85oC HM1-6642B-9 HM1-6642-9 D24.6
SMD# -55oC to +125oC 5962-8869002JA 5962-8869001JA D24.6
SLIM SBDIP -40oC to +85oC HM6-6642B-9 HM6-6642-9 D24.3
SMD# -55oC to +125oC 5962-8869002LA 5962-8869001LA D24.3
CLCC -40oC to +85oC - HM4-6642-9 J28.A
SMD# -55oC to +125oC 5962-88690023A 5962-88690013A J28.A
File Number 3012.1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
6-2
Functional Diagram
Pinouts
HM-6642 (SBDIP)
TOP VIEW HM-6642 (CLCC)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
A7
A6
A5
A4
A3
A2
A1
A0
Q0
Q1
Q2
GND
16
17
18
19
20
21
22
23
24
15
14
13
VCC
G1
G2
G3
E
Q7
Q5
Q4
Q3
A8
P
Q6
23
24
25
22
21
20
19
11
3 2 14
14 15 16 17 1812 13
28 27 26
10
5
6
7
8
9
A4
A3
A2
A1
A0
NC
Q0
G2
G3
E
P
NC
Q7
Q6
Q1
Q2
GND
NC
Q3
Q5
Q4
A5
A6
A7
NC
VCC
G1
A8
PIN DESCRIPTION
PIN DESCRIPTION
NC No Connect
A0-A8 Address Inputs
E Chip Enable
Q Data Output
VCC Power (+5V)
G1, G2, G3 Output Enable
P (Note) Program Enable
NOTE: P should be hardwired to GND
except during programming.
88
8 8 8 8
64 x 64
MATRIX
64
6
E
LATCHED
REGISTER
ADDRESS
6
3
A
3
A
A3
A4
A5
A6
A7
A8
A0
A1
A2
8 8
A
A
D
GATED COLUMN
DECODER
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
LATCHED
ADDRESS
REGISTER
GATED
ROW
DECODER
8-BIT DATA LATCH
ADDRESS LATCHES AND GATED DECODERS:
GATE ON FALLING EDGE OF E
LATCH ON FALLING EDGE OF E
ALL LINES POSITIVE LOGIC - ACTIVE HIGH
A HIGH
DATA LATCHES:
Q LATCHES ON RISING EDGE OF E
L HIGH
THREE STATE BUFFERS:
P SHOULD BE HARDWIRED TO GND EXCEPT
DURING PROGRAMMING
G1
G2
G3
Q = D
OUTPUT ACTIVE
HM-6642
6-3
Programming
Introduction
The HM-6642 is a 512 word by 8-bit field Programmable
Read Only Memory utilizing nicrome fusible links as pro-
grammable memory elements. Selected memory locations
are permanently changed from their manufactured state, of
all low (VOL) to a logical high (VOH), by the controlled
application of programming potentials and pulses. Careful
adherence to the following programming specifications will
result in high programming yield. Both high VCC (6.0V) and
low VCC (4.0V) verify cycles are specified to assure the
integrity of the programmed fuse. This programming
specification, although complete, does not preclude rapid
programming. The worst case programming time required is
37.4 seconds, and typical programming time can be
approximately 4 seconds per device.
The chip (E) and output enable (G) are used during the
programming procedure. On PROMs which have more than
one output enable control G3 is to be used. The other output
enables must be held in the active, or enabled, state
throughout the entire programming sequence. The program-
mer designer is advised that all pins of the programmer’s
socket should be at ground potential when the PROM is
inser ted into the socket. VCC must be applied to the PROM
before any input or output pin is allowed to rise (See Note).
Overall Programming Procedure
1. The address of the first bit to be programmed is
presented, and latched by the chip enable (E) falling
edge. The output is disabled by taking the output enable
G Low: The programming pin is enabled by taking (P)
high.
2. VCC is raised to the programming voltage level, 12.5V.
3. All data output pins are pulled up to VCC program. Then
the data output pin corresponding to the bit to be
programmed is pulled low for 100ms. Only one bit should
be programmed at a time.
4. The data output pin is returned to VCC, and the VCC pin
is returned to 6.0V.
5. The address of the bit is again presented, and latched by
a second chip enable falling edge.
6. The data outputs are enabled, and read, to verify that the
bit was successfully programmed.
a). If verified, the next bit to be programmed is addressed
and programmed.
b). If not verified, the programs v erify sequence is
repeated up to 8 times total.
7. After all bits to be programmed have been verified at 6.0V,
the VCC is lowered to 4.0V and all bits are verified.
a). If all bits verify, the device is properly programmed.
b). If any bit fails to verify, the device is rejected.
Programming System Requirements
1. The power supply f or the de vice to be programmed must
be able to be set to three v oltages: 4.0V, 6.0V, 12.5V. This
supply must be able to supply 500mA average, and 1A
dynamic, currents to the PROM during programming. The
power supply rise f all times when s witching between v olt-
ages must be no quicker than 1ms.
2. The address drivers must be able to supply a VIH of 4.0V
and 6.0V and VIL when the system is at programming
voltages. (See Note)
3. The control input buffers must be able to maintain input
voltage levels of ≥ 70% and ≤ 20% VCC for VIH and VIL
levels, respectively. Notice that chip enable (E) and G
does not require a pull up to programming voltage levels.
The program control (P) must switch from ground to VIH
and from VIH to the VCC PGM level. (See Note)
4. The data input buffers must be able to sink up to 3mA
from the PROM’s output pins without rising more than
0.7V above ground, be able to hold the other outputs high
with a current source capability of 0.5mA to 2.0mA, and
not interfere with the reading and verifying of the data
output of the PROM. Notice that a bit to be programmed
is changed from a low state (VOL) to high (VOH) by pulling
low on the output pin. A suggested implementation is
open collector TTL buffers (or inverters) with 4.7kΩ pull
up resistors to VCC. (See Note)
NOTE: Never allow any input or output pin to rise more than 0.3V
above VCC, or fall more than 0.3V below ground.
HM-6642
6-4
Background Information HM-6642 Programming
PROGRAMMING SPECIFICATIONS
SYMBOL PARAMETER
LIMITS
UNITSMIN TYP MAX
VCC PROG Programming VCC 12.0 12.0 12.5 V
VCCN Operating VCC 4.5 5.5 5.5 V
VCC LV Special Verify VCC 4.0 - 6.0 V
ICC System ICC Capability 500 - - mA
ICC Peak Transient ICC Capability 1.0 - - A
PROM INPUT PINS
VOL Output Low Voltage (To PROM) -0.3 GND 20% VCC V
VOH Output High Voltage (To PROM) 70% VCC VCC VCC +0.3 V
IOL Output Sink Current (At VOL) 0.01 - - mA
IOH Output Source Current (At VOH) 0.01 - - mA
PROM DATA OUTPUT PINS
VOL Output Low Voltage (To PROM) -0.3 GND 0.7 V
VOH Output High Voltage (To PROM) 70% VCC VCC VCC +0.3 V
IOL Output Sink Current (At VOL) 3.0 - - mA
IOH Output Source Current (At VOH) 0.5 1.0 2.0 mA
tD Delay Time 1.0 1.0 - µs
tR Rise Time 1.0 10.0 10.0 µs
tF Fall Time 1.0 10.0 10.0 µs
TEHEL Chip Enable Pulse Width 500 - - ns
TAVEL Address Valid to Chip Enable Low Time 500 - - ns
TELQV Chip Enable Low to Output Valid Time - - 500 ns
tpw Programming Pulse Width 90 100 110 µs
tIP Input Leakage at VCC = VCC PROG -10 +1.0 10 µA
TA Ambient Temperature - 25 - oC
HM-6642
6-5
FIGURE 1. HM-6642 PROGRAMMING CYCLE
FIGURE 2. HM-6642 POST PROGRAMMING VERIFY CYCLE
TEHEL
tD
VERIFY
VALID
PROGRAMMING
VALID
tD
tD
tD
tD
tR tD tD tF
tPW
READ DATA
VCC PROG
VIH
VIL
VIH
VIL
VCC PROG
VIH
VIL
VCC PROG
VIH
VIL
VCC PROG
VCC
GND
VCC PROG
VIH/VOH
VIL/VOL
A
E
G
P
VCC
Q
VALID
TAVEL
TEHEL
TEHEL
VIH
VIL
VIH
VIL
6.0V
5.0V
4.0V
0.0V
VOH
VOL
TELQV
READ
TELQV
READ READ
TELQV
TEHEL
tDtD
A
E
VCC
Q
HM-6642
6-6
Absolute Maximum Ratings Thermal Information
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7.0V
Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V
Typical Derating Factor. . . . . . . . . . . . 5mA/MHz Increase in ICCOP
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1
Operating Conditions
Operating Voltage Range. . . . . . . . . . . . . . . . . . . . . +4.5V to +5.5V
Operating Temperature Range
HM-6642B-9, HM-6642-9 . . . . . . . . . . . . . . . . . . . -40oC to +85oC
Thermal Resistance θJA θJC
SBDIP Package. . . . . . . . . . . . . . . . . . 52oC/W 14oC/W
Slim SBDIP . . . . . . . . . . . . . . . . . . . . . 70oC/W 19oC/W
CLCC Package . . . . . . . . . . . . . . . . . . 58oC/W 14oC/W
Maximum Storage Temperature Range . . . . . . . . .-65oC to +150oC
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . .+175oC
Maximum Lead Temperature (Soldering 10s)+300oC
Die Characteristics
Gate Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1680 Gates
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
DC Electrical Specifications VCC = 5V ± 10%; TA = -40oC to +85oC (HM-6642B-9, HM-6642-9)
SYMBOL PARAMETER
LIMITS
UNITS TEST CONDITIONSMIN MAX
ICCSB Standby Supply Current - 100 µA IO = 0, VI = VCC or GND, VCC = 5.5V
ICCOP Operating Supply Current (Note 3) - 20 mA f = 1MHz, IO = 0, VI = VCC or GND, VCC = 5.5V
II Input Leakage Current -1.0 +1.0 µA GND ≤ VI ≤ VCC, VCC = 5.5V
IOZ Output Leakage Current -1.0 +1.0 µA GND ≤ VO ≤ VCC, VCC = 5.5V
VIL Input Low Voltage -0.3 0.8 V VCC = 4.5V
VIH Input High Voltage 2.4 VCC + 0.3 V VCC = 5.5V
VOL Output Low Voltage - 0.4 V IOL = 3.2mA, VCC = 4.5V
VOH1 Output High Voltage 2.4 - V IOH = -1.0mA, VCC = 4.5V
VOH2 Output High Voltage (Note 2) VCC - 1.0 - V IOH = -100µA, VCC = 4.5V
AC Electrical Specifications
SYMBOL PARAMETER
LIMITS
UNITS TEST
CONDITIONS
HM-6642B-9 HM-6642-9
MIN MAX MIN MAX
(1) TELQV Chip Enable Access Time - 120 - 200 ns Notes 1, 4
(2) TAVQV Address Access Time
(TAVQV = TELQV + TAVEL) - 140 - 220 ns Notes 1, 4
(3) TGVQV Output Enable Access Time - 50 - 150 ns Notes 1, 4
(4) TGVQX Output Enable Time 5 50 5 150 ns Notes 2, 4
(5) TGXQZ Output Disable Time - 50 - 150 ns Notes 2, 4
(6) TELEH Chip Enable Pulse Negative Width 120 - 200 - ns Notes 1, 4
(7) TELEL Read Cycle Time 160 - 350 - ns Notes 1, 4
(8) TEHEL Chip Enable Pulse Positive Width 40 - 150 - ns Notes 1, 4
(9) TAVEL Address Setup Time 20 - 20 - ns Notes 1, 4
(10) TELAX Address Hold Time 25 - 60 - ns Notes 1, 4
HM-6642
6-7
Test Load Circuit
Capacitance TA = +25oC
SYMBOL PARAMETER
LIMITS
UNITS TEST CONDITIONSMIN MAX
CI Input Capacitance (Note 2) - 10.0 pF f = 1MHz, All Measurements Reference Device
Ground
CO Output Capacitance (Note 2) - 12.0 pF
NOTES:
1. Input pulse lev els: 0 to 3.0V; Input rise and fall times: 5ns (max); Input and output timing reference level: 1.5V ; Output load: 1 TTL gate
equivalent CL = 50pF (min) - for CL greater than 50pF, access time is derated by 0.15ns per pF.
2. Tested at initial design and after major design changes.
3. Typical derating 5mA/MHz increase in ICCOP.
4. VCC = 4.5V and 5.5V.
Switching Waveform
NOTE: G has the same timing as G except signal is inverted.
FIGURE 3. READ CYCLE
TGXQZ (5)
TEHEL (8)
TAVEL (9)
TELEL (7)
TELEH
TELQV
TGVQV
TGVQX
(2)
TELAX
(9)
TEHEL
TGXQZ
A
E
Q
G
TIME
(NOTE)
REFERENCE
TAVEL
TAVQV
(10)
(5)
(8)
ADD VALID
(3)
(4)
(1)
(6)
DATA VALID
NEXT ADD
-1 0 1 2 3 456
DUT
EQUIVALENT CIRCUIT
1.5V IOLIOH
CL
NOTE:
CAPACITANCE,
INCLUDES STRAY
AND JIG CAPACITANCE
±
(NOTE)
TEST HEAD
HM-6642
6-8
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate
and reliable . However, no responsibility is assumed by Intersil or its subsidiaries f or its use; nor for any infringements of patents or other rights of third parties which
may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see w eb site http://www.intersil.com
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HM-6642
