Intel(R) Advanced Boot Block Flash Memory (B3) 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Datasheet Product Features * Flexible SmartVoltage Technology -- 2.7 V - 3.6 V read/program/erase -- 12 V V PP fast production programming * 1.65 V - .5 V or 2.7 V - 3.6 V I/O option -- Reduces overall system power * High Performance -- 2.7 V - 3.6 V: 70 ns max access time * Optimized Block Sizes -- Eight 8-KB blocks for data, top or bottom locations -- Up to 127 x 64-KB blocks for code * Block Locking -- VCC-level control through Write Protect WP# * Low Power Consumption -- 9 mA typical read current * Absolute Hardware-Protection -- VPP = GND option -- VCC lockout voltage * Extended Temperature Operation -- -40 C to +85 C * Automated Program and Block Erase -- Status registers * Intel(R) Flash Data Integrator Software --Flash Memory Manager --System Interrupt Manager --Supports parameter storage, streaming data (for example, voice) * Extended Cycling Capability --Minimum 100,000 block erase cycles * Automatic Power Savings Feature --Typical ICCS after bus inactivity * Standard Surface Mount Packaging --48-Ball CSP packages --40-Lead and 48-Lead TSOP packages * Density and Footprint Upgradeable for common package --8-, 16-, 32-, and 64-Mbit densities * ETOXTM VIII (0.13 m) Flash Technology --16-Mbit and 32-Mbit densities * ETOXTM VII (0.18 m) Flash Technology --16-, 32-, and 64-Mbit densities * ETOX TM VI (0.25m) Flash Technology --8-, 16-, and 32-Mbit densities * Bo not use the x8 option for new designs The Intel(R) Advanced Boot Block Flash Memory (B3) device, manufactured on the Intel 0.13 m and 0.18 m technologies, is a feature-rich solution at a low system cost. The B3 device in x16 is available in 48-lead TSOP and 48-ball CSP packages. The x8 option of this product family is available only in 40-lead TSOP and 48-ball BGA* packages. For additional information about this product family, see the Intel website: http://www.intel.com/design/flash. Notice: This specification is subject to change without notice. Verify with your local Intel sales office that you have the latest datasheet before finalizing a design. Order Number: 290580, Revision: 020 18 Aug 2005 INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL (R) PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications. Intel may make changes to specifications and product descriptions at any time, without notice. The Intel(R) Advanced Boot Block Flash Memory (B3) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800 548-4725 or by visiting Intel's website at http://www.intel.com. Intel, the Intel logo, and ETOX are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. *Other names and brands may be claimed as the property of others. Copyright (c) 2005, Intel Corporation. 18 Aug 2005 2 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Contents 1.0 Introduction ............................................................................................................................... 7 1.1 1.2 Nomenclature ....................................................................................................................... 7 Conventions .......................................................................................................................... 8 2.0 Functional Overview .............................................................................................................. 8 3.0 Functional Overview .............................................................................................................. 9 3.1 3.2 Architecture Diagram .......................................................................................................... 10 Memory Maps and Block Organization ............................................................................... 11 3.2.1 Parameter Blocks .................................................................................................. 11 3.2.2 Main Blocks ........................................................................................................... 11 3.2.3 4-Mbit, 8-Mbit, 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Maps ............. 11 3.2.4 4-Mbit, 8-Mbit, and 16-Mbit Byte-Wide Memory Maps........................................... 20 4.0 Package Information ............................................................................................................ 24 4.1 4.2 4.3 mBGA* and Very Thin Profile Fine Pitch Ball Grid Array (VF BGA) Package .................... 24 TSOP Package ................................................................................................................... 25 Easy BGA Package ............................................................................................................ 26 5.0 Pinout and Signal Descriptions ....................................................................................... 27 5.1 5.2 Signal Pinouts ..................................................................................................................... 27 5.1.1 40-Lead and 48-Lead TSOP Packages ................................................................. 27 Signal Descriptions ............................................................................................................. 30 6.0 Maximum Ratings and Operating Conditions ...........................................................32 6.1 6.2 Absolute Maximum Ratings ................................................................................................ 32 Operating Conditions .......................................................................................................... 33 7.0 Electrical Specifications ..................................................................................................... 34 7.1 7.2 DC Current Characteristics .................................................................................................34 DC Voltage Characteristics.................................................................................................36 8.0 AC Characteristics ................................................................................................................ 37 8.1 8.2 8.3 8.4 8.5 AC Read Characteristics .................................................................................................... 37 AC Write Characteristics..................................................................................................... 41 Erase and Program Timing .................................................................................................45 AC I/O Test Conditions ....................................................................................................... 46 Device Capacitance ............................................................................................................ 46 9.0 Power and Reset Specifications .....................................................................................47 9.1 9.2 9.3 Datasheet Power-Up/Down Characteristics ......................................................................................... 47 9.1.1 RP# Connected to System Reset .......................................................................... 47 9.1.2 VCC, VPP, and RP# Transitions..............................................................................47 Reset Specifications ........................................................................................................... 48 Power Supply Decoupling................................................................................................... 49 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 3 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 9.4 Power Consumption ........................................................................................................... 49 9.4.1 Active Power.......................................................................................................... 49 9.4.2 Automatic Power Savings (APS) ........................................................................... 49 9.4.3 Standby Power ...................................................................................................... 49 9.4.4 Deep Power-Down Mode....................................................................................... 50 10.0 Operations Overview ........................................................................................................... 50 10.1 Bus Operations ................................................................................................................... 51 10.1.1 Read ...................................................................................................................... 51 10.1.2 Output Disable ....................................................................................................... 52 10.1.3 Standby.................................................................................................................. 52 10.1.4 Deep Power-Down / Reset .................................................................................... 52 10.1.5 Write ...................................................................................................................... 53 11.0 Operating Modes ................................................................................................................... 53 11.1 11.2 11.3 11.4 11.5 Read Array.......................................................................................................................... 54 Read Identifier .................................................................................................................... 56 Read Status Register.......................................................................................................... 56 11.3.1 Clearing the Status Register.................................................................................. 57 Program Mode .................................................................................................................... 57 11.4.1 Suspending and Resuming Programming ............................................................. 58 Erase Mode ........................................................................................................................ 58 11.5.1 Suspending and Resuming Erase ......................................................................... 59 12.0 Block Locking ......................................................................................................................... 62 12.1 12.2 WP# = VIL for Block Locking............................................................................................... 62 WP# = VIH for Block Unlocking........................................................................................... 62 13.0 VPP Program and Erase Voltages ................................................................................... 63 13.1 VPP = VIL for Complete Protection...................................................................................... 63 14.0 Additional Information ........................................................................................................ 63 Appendix A Write State Machine Current/Next States ................................................. 64 Appendix B Program and Erase Flowcharts .................................................................... 66 Appendix C Ordering Information ......................................................................................... 70 18 Aug 2005 4 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Revision History Revision Number Description -001 Original version -002 Section 3.4, VPP Program and Erase Voltages, added Updated Figure 9: Automated Block Erase Flowchart Updated Figure 10: Erase Suspend/Resume Flowchart (added program to table) Updated Figure 16: AC Waveform: Program and Erase Operations (updated notes) IPPR maximum specification change from 25 A to 50 A Program and Erase Suspend Latency specification change Updated Appendix A: Ordering Information (included 8 M and 4 M information) Updated Figure, Appendix D: Architecture Block Diagram (Block info. in words not bytes) Minor wording changes -003 Combined byte-wide specification (previously 290605) with this document Improved speed specification to 80 ns (3.0 V) and 90 ns (2.7 V) Improved 1.8 V I/O option to minimum 1.65 V (Section 3.4) Improved several DC characteristics (Section 4.4) Improved several AC characteristics (Sections 4.5 and 4.6) Combined 2.7 V and 1.8 V DC characteristics (Section 4.4) Added 5 V VPP read specification (Section 3.4) Removed 120 ns and 150 ns speed offerings Moved Ordering Information from Appendix to Section 6.0; updated information Moved Additional Information from Appendix to Section 7.0 Updated figure Appendix B, Access Time vs. Capacitive Load Updated figure Appendix C, Architecture Block Diagram Moved Program and Erase Flowcharts to Appendix E Updated Program Flowchart Updated Program Suspend/Resume Flowchart Minor text edits throughout -004 Added 32-Mbit density Added 98H as a reserved command (Table 4) A 1-A20 = 0 when in read identifier mode (Section 3.2.2) Status register clarification for SR3 (Table 7) VCC and VCCQ absolute maximum specification = 3.7 V (Section 4.1) Combined IPPW and ICCW into one specification (Section 4.4) Combined IPPE and ICCE into one specification (Section 4.4) Max Parameter Block Erase Time (tWHQV2/tEHQV2) reduced to 4 sec (Section 4.7) Max Main Block Erase Time (tWHQV3/tEHQV3) reduced to 5 sec (Section 4.7) Erase suspend time @ 12 V (tWHRH2/tEHRH2) changed to 5 s typical and 20 s maximum (Section 4.7) Ordering Information updated (Section 6.0) Write State Machine Current/Next States Table updated (Appendix A) Program Suspend/Resume Flowchart updated (Appendix F) Erase Suspend/Resume Flowchart updated (Appendix F) Text clarifications throughout -005 BGA package diagrams corrected (Figures 3 and 4) IPPD test conditions corrected (Section 4.4) 32-Mbit ordering information corrected (Section 6) BGA package top side mark information added (Section 6) -006 VIH and VILSpecification change (Section 4.4) ICCS test conditions clarification (Section 4.4) Added Command Sequence Error Note (Table 7) Data sheet renamed from Smart 3 Advanced Boot Block 4-Mbit, 8-Mbit, 16-Mbit Flash Memory Family. Added device ID information for 4-Mbit x8 device Removed 32-Mbit x8 to reflect product offerings Minor text changes Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 5 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Revision Number Description -007 Corrected RP# pin description in Table 2, 3 Volt Advanced Boot Block Pin Descriptions Corrected typographical error fixed in Ordering Information -008 4-Mbit packaging and addressing information corrected throughout document -009 Corrected 4-Mbit memory addressing tables in Appendices D and E -010 Max ICCD changed to 25 A VCC Max on 32 M (28F320B3) changed to 3.3 V -011 Added 64-Mbit density and faster speed offerings Removed access time vs. capacitance load curve -012 Changed references of 32Mbit 80ns devices to 70ns devices to reflect the faster product offering. Changed VccMax=3.3V reference to indicate the affected product is the 0.25m 32Mbit device. Minor text edits throughout document. -013 Added New Pin-1 indicator information on 40 and 48Lead TSOP packages. Minor text edits throughout document. -014 Added specifications for 0.13 micron product offerings throughout document -015 Minor text edits throughout document. Adjusted ordering information. Adjusted specifications for 0.13 micron product offerings. -016 Revised and corrected DC Characteristics Table. Adjusted package diagram information. Minor text edits throughout document. Updated ordering information. Adjusted specifications for 0.13 micron product offerings. -017 Updated AC/DC Characteristics Table. Added TSOP and BGA* package diagram information. Minor text edits throughout document. -018 Updated the layout of the datasheet. -019 Added line items to Table 34 "Ordering Information: Valid Combinations" on page 70. -020 Removed all x8 products from ordering information, page 70 18 Aug 2005 6 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 1.0 Introduction This datasheet describes the specifications for the Intel(R) Advanced Boot Block Flash Memory (B3) device (hereafter referred to as the B3 flash memory device). The B3 flash memory device is optimized for portable, low-power, systems. This family of products features 1.65 V to 2.5 V or 2.7 V to 3.6 V I/Os, and a low VCC/V PP operating range of 2.7 V to 3.6 V for Read, Program, and Erase operations. The B3 device is also capable of fast programming at 12 V. Throughout this document: * 2.7 V refers to the full voltage range 2.7 V to 3.6 V (except where noted otherwise). * VPP = 12 V refers to 12 V 5%. 1.1 Nomenclature Table 1. Nomenclature Term Datasheet Definition 0x Hexadecimal prefix 0b Binary prefix Byte 8 bits Word 16 bits KW or Kword 1024 words Mword 1,048,576 words Kb 1024 bits KB 1024 bytes Mb 1,048,576 bits MB 1,048,576 bytes APS Automatic Power Savings CSP Chip Scale Package CUI Command User Interface OTP One Time Programmable PR Protection Register PRD Protection Register Data PLR Protection Lock Register RFU Reserved for Future Use SR Status Register SRD Status Register Data WSM Write State Machine Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 7 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 1.2 Conventions Table 2. Conventions Convention Description Used interchangeably to refer to the external signal connections on the package. Pin or signal Note: 2.0 For a chip scale package (CSP), the term ball is used in place of pin. Group Membership Brackets Square brackets designate group membership or define a group of signals with similar function (for example, A[21:1], SR[4:1]) Set When referring to registers, the term set means the bit is a logical 1. Clear: When referring to registers, the term clear means the bit is a logical 0. Block A group of bits (or words) that erase simultaneously using one block erase instruction. Main Block A block that contains 32 Kwords. Parameter Block A block that contains 4 Kwords. Functional Overview The B3 flash memory device features the following: * Enhanced blocking for easy segmentation of code and data or additional design flexibility. * Program Suspend to Read command. * VCCQ input of 1.65 V to 2.5 V or 2.7 V to 3.6 V on all I/Os. See Figure 1 through Figure 4 for pinout diagrams and VCCQ location. * Maximum program and erase time specification for improved data storage. Table 3. B3 Device Feature Summary (Sheet 1 of 2) Feature VCC Read Voltage VPP Program/Erase Voltage Speed Memory Arrangement 18 Aug 2005 8 Reference Section 6.2, Section 7.2 2.7 V- 3.6 V VCCQ I/O Voltage Bus Width 28F800B3, 28F160B3, 28F320B3(3), 28F640B3 28F008B3, 28F016B3 1.65 V-2.5 V or 2.7 V- 3.6 V Section 4.2, 4.4 2.7 V- 3.6 V or 11.4 V- 12.6 V Section 4.2, 4.4 8 bit 16 bit 70 ns, 80 ns, 90 ns, 100 ns, 110 ns 1024 Kbit x 8 (8 Mbit), 2048 Kbit x 8 (16 Mbit) 512 Kbit x 16 (8 Mbit), 1024 Kbit x 16 (16 Mbit), 2048 Kbit x 16 (32 Mbit), 4096 Kbit x 16 (64 Mbit) Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Table 27 Section 8.1 Section 3.2 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 3. B3 Device Feature Summary (Sheet 2 of 2) Feature 28F008B3, 28F016B3 Blocking (top or bottom) 28F800B3, 28F160B3, 28F320B3(3), 28F640B3 Eight 8-Kbyte parameter blocks and Fifteen 64-Kbyte blocks (8 Mbit) or Thirty-one 64-Kbyte main blocks (16 Mbit) Sixty-three 64-Kbyte main blocks (32 Mbit) One hundred twenty-seven 64-Kbyte main blocks (64 Mbit) WP# locks/unlocks parameter blocks All other blocks protected using VPP Locking Reference Section 3.2, "Memory Maps and Block Organization" on page 11 Section 12.0 Table 32 Operating Temperature Extended: -40 C to +85 C Section 6.2, Section 7.2 Program/Erase Cycling 100,000 cycles Section 6.2, Section 7.2 Packages 40-lead TSOP(1), 48-Ball BGA* CSP (2) 48-Lead TSOP, 48-Ball BGA CSP(2), 48-Ball VF BGA Figure 8, Figure 9 Notes: 1. 32-Mbit and 64-Mbit densities not available in 40-lead TSOP. 2. 8-Mbit densities not available in BGA* CSP. 3. VCC Max is 3.3 V on 0.25m 32-Mbit devices. 3.0 Functional Overview Intel provides the most flexible voltage solution in the flash industry, providing three discrete voltage supply pins: * VCC for Read operation * VCCQ for output swing * VPP for Program and Erase operation. All B3 flash memory devices provide program/erase capability at 2.7 V or 12 V (for fast production programming), and read with V CC at 2.7 V. Because many designs read from the flash memory a large percentage of the time, 2.7 V VCC operation can provide substantial power savings. The B3 flash memory device family is available in either x8 or x16 packages in the following densities (see Appendix C, "Ordering Information," for availability): * 8-Mbit (8, 388, 608-bit) flash memory organized as 512 Kwords of 16 bits each or 1024 Kbytes of 8-bits each. * 16-Mbit (16, 777, 216-bit) flash memory organized as 1024 Kwords of 16 bits each or 2048 Kbytes of 8-bits each. * 32-Mbit (33, 554, 432-bit) flash memory organized as 2048 Kwords of 16 bits each. * 64-Mbit (67, 108, 864-bit) flash memory organized as 4096 Kwords of 16 bits each. The parameter blocks are located at either the top (denoted by -T suffix) or the bottom (-B suffix) of the address map, to accommodate different microprocessor protocols for kernel code location. The upper two (or lower two) parameter blocks can be locked to provide complete code security for system initialization code. Locking and unlocking is controlled by Write Protect WP# (see Section 12.0, "Block Locking" on page 62 for details). Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 9 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 * The Command User Interface (CUI) is the interface between the microprocessor or microcontroller and the internal operation of the flash memory. * The internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for Program and Erase operations (including verification), which unburdens the microprocessor or microcontroller. * To indicate the status of the WSM, the Status Register signifies block erase or word program completion and status. The B3 flash memory device also provides Automatic Power Savings (APS), which minimizes system current drain and allows for very low power designs. This mode is entered following the completion of a read cycle (approximately 300 ns later). The RP# pin provides additional protection against unwanted command writes that might occur during system reset and power-up/down sequences due to invalid system bus conditions (see "Power and Reset Specifications" on page 47). * Section 10.0, "Operations Overview" on page 50 explains the different modes of operation. * Section 7.0, "Electrical Specifications" on page 34 and Section 8.0, "AC Characteristics" on page 37 provide complete current and voltage specifications. * Section 8.1, "AC Read Characteristics" on page 37 provides read, program, and erase performance specifications. 3.1 Architecture Diagram Figure 1. B3 Architecture Block Diagram DQ0-DQ15 VCCQ Input Buffer Identifier Register Status Register Power Reduction Control Data Comparator Y-Decoder Y-Gating/Sensing Data Register Output Multiplexer Output Buffer I/O Logic CE# WE# OE# RP# Command User Interface WP# A0-A19 Write State Machine Address Counter 18 Aug 2005 10 32-KWord Main Block X-Decoder 4-KWord Parameter Block 32-KWord Main Block Address Latch 4-KWord Parameter Block Input Buffer Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Program/Erase Voltage Switch VPP VCC GND Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 3.2 Memory Maps and Block Organization The B3 flash memory device uses an asymmetrically blocked architecture, enabling system integration of code and data within a single flash memory device. Each block can be erased independently of other blocks up to 100,000 times. For the address locations of each block, see the following memory maps: * * * * * 3.2.1 Table 4 "16-Mbit and 32-Mbit Word-Wide Memory Addressing Map" on page 11 Table 5 "4-Mbit and 8-Mbit Word-Wide Memory Addressing Map" on page 14 Table 6 "16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map" on page 15 Table 7 "8-Mbit and 16-Mbit Byte-Wide Memory Addressing Map" on page 20 Table 8 "4-Mbit Byte Wide Memory Addressing Map" on page 23 Parameter Blocks The B3 flash memory device architecture includes parameter blocks to facilitate storing frequently updated small parameters (such as data traditionally stored in an EEPROM). The word-rewrite functionality of EEPROMs can be emulated using software techniques. Each flash memory device contains eight parameter blocks of 8 Kbytes/4 Kwords (8192 bytes/4,096 words) each. 3.2.2 Main Blocks After the parameter blocks, the remainder of the flash memory array is divided into equal-size main blocks (65,536 bytes/32,768 words) for data or code storage. * * * * The 8-Mbit flash memory device contains 15 main blocks. The 16-Mbit flash memory device contains 31 main blocks. The 32-Mbit memory device contains 63 main blocks. The 64-Mbit memory device contains 127 main blocks. 3.2.3 4-Mbit, 8-Mbit, 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Maps Table 4. 16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 1 of 4) 16-Mbit and 32-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot Size (KW) 16 Mbit 32 Mbit Size (KW) 4 FF000-FFFFF 1FF000-1FFFFF 32 1F8000-1FFFFF 4 FE000-FEFFF 1FE000-1FEFFF 32 1F0000-1F7FFF 4 FD000-FDFFF 1FD000-1FDFFF 32 1E80001EFFFF 4 FC000-FCFFF 1FC000-1FCFFF 32 1E00001E7FFF Datasheet 8 Mbit Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 16 Mbit 32 Mbit 18 Aug 2005 11 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 4. 16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 2 of 4) 16-Mbit and 32-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot Size (KW) 16 Mbit 32 Mbit Size (KW) 4 FB000-FBFFF 1FB000-1FBFFF 32 1D80001DFFFF 4 FA000-FAFFF 1FA000-1FAFFF 32 1D00001D7FFF 4 F9000-F9FFF 1F9000-1F9FFF 32 1C80001CFFFF 4 F8000-F8FFF 1F8000-1F8FFF 32 1C00001C7FFF 32 F0000-F7FFF 1F0000-1F7FFF 32 1B80001BFFFF 32 E8000-EFFFF 1E8000-1EFFFF 32 1B00001B7FFF 32 E0000-E7FFF 1E0000-1E7FFF 32 1A80001AFFFF 32 D8000-DFFFF 1D8000-1DFFFF 32 1A00001A7FFF 32 D0000-D7FFF 1D0000-1D7FFF 32 198000-19FFFF 32 C8000-CFFFF 1C8000-1CFFFF 32 190000-197FFF 32 C0000-C7FFF 1C0000-1C7FFF 32 188000-18FFFF 32 B8000-BFFFF 1B8000-1BFFFF 32 180000-187FFF 32 B0000-B7FFF 1B0000-1B7FFF 32 178000-17FFFF 32 A8000-AFFFF 1A8000-1AFFFF 32 170000-177FFF 32 A0000-A7FFF 1A0000-1A7FFF 32 168000-16FFFF 32 98000-9FFFF 198000-19FFFF 32 160000-167FFF 32 90000-97FFF 190000-197FFF 32 158000-15FFFF 32 88000-8FFFF 188000-18FFFF 32 150000-157FFF 32 80000-87FFF 180000-187FFF 32 148000-14FFFF 32 78000-7FFFF 178000-17FFFF 32 140000-147FFF 32 70000-77FFF 170000-177FFF 32 138000-13FFFF 32 68000-6FFFF 168000-16FFFF 32 130000-137FFF 32 60000-67FFF 160000-167FFF 32 128000-12FFFF 32 58000-5FFFF 158000-15FFFF 32 120000-127FFF 32 50000-57FFF 150000-157FFF 32 118000-11FFFF 32 48000-4FFFF 148000-14FFFF 32 110000-117FFF 32 40000-47FFF 140000-147FFF 32 108000-10FFFF 32 38000-3FFFF 138000-13FFFF 32 32 30000-37FFF 130000-137FFF 32 F8000-FFFFF 0F8000-0FFFFF 32 28000-2FFFF 128000-12FFFF 32 F0000-F7FFF 0F0000-0F7FFF 18 Aug 2005 12 8 Mbit Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 16 Mbit 32 Mbit 100000-107FFF Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 4. 16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 3 of 4) 16-Mbit and 32-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot Size (KW) 16 Mbit 32 Mbit Size (KW) 32 20000-27FFF 120000-127FFF 32 18000-1FFFF 32 16 Mbit 32 Mbit 32 E8000-EFFFF 0E80000EFFFF 118000-11FFFF 32 E0000-E7FFF 0E00000E7FFF 10000-17FFF 110000-117FFF 32 D8000-DFFFF 0D80000DFFFF 32 08000-0FFFF 108000-10FFFF 32 D0000-D7FFF 0D00000D7FFF 32 00000-07FFF 100000-107FFF 32 C8000-CFFFF 0C80000CFFFF This column continues on next page 8 Mbit This column continues on next page 32 0F8000-0FFFFF 32 C0000-C7FFF 0C00000C7FFF 32 0F0000-0F7FFF 32 B8000-BFFFF 0B80000BFFFF 32 0E8000-0EFFFF 32 B0000-B7FFF 0B00000B7FFF 32 0E0000-0E7FFF 32 A8000-AFFFF 0A80000AFFFF 32 0D8000-0DFFFF 32 A0000-A7FFF 0A00000A7FFF 32 0D0000-0D7FFF 32 98000-9FFFF 098000-09FFFF 32 0C8000-0CFFFF 32 90000-97FFF 090000-097FFF 32 0C0000-0C7FFF 32 88000-8FFFF 088000-08FFFF 32 0B8000-0BFFFF 32 80000-87FFF 080000-087FFF 32 0B0000-0B7FFF 32 78000-7FFFF 78000-7FFFF 32 0A8000-0AFFFF 32 70000-77FFF 70000-77FFF 32 0A0000-0A7FFF 32 68000-6FFFF 68000-6FFFF 32 098000-09FFFF 32 60000-67FFF 60000-67FFF 32 090000-097FFF 32 58000-5FFFF 58000-5FFFF 32 088000-08FFFF 32 50000-57FFF 50000-57FFF 32 080000-087FFF 32 48000-4FFFF 48000-4FFFF 32 078000-07FFFF 32 40000-47FFF 40000-47FFF 32 070000-077FFF 32 38000-3FFFF 38000-3FFFF 32 068000-06FFFF 32 30000-37FFF 30000-37FFF 32 060000-067FFF 32 28000-2FFFF 28000-2FFFF 32 058000-05FFFF 32 20000-27FFF 20000-27FFF 32 050000-057FFF 32 18000-1FFFF 18000-1FFFF 32 048000-04FFFF 32 10000-17FFF 10000-17FFF 32 040000-047FFF 32 08000-0FFFF 08000-0FFFF Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 13 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 le 4. 16-Mbit and 32-Mbit Word-Wide Memory Addressing Map (Sheet 4 of 4) 16-Mbit and 32-Mbit Word-Wide Memory Addressing Top Boot ize W) Bottom Boot 32 Mbit Size (KW) 038000-03FFFF 16 Mbit 32 Mbit 4 07000-07FFF 07000-07FFF 030000-037FFF 4 06000-06FFF 06000-06FFF 028000-02FFFF 4 05000-05FFF 05000-05FFF 020000-027FFF 4 04000-04FFF 04000-04FFF 018000-01FFFF 4 03000-03FFF 03000-03FFF 010000-017FFF 4 02000-02FFF 02000-02FFF 008000-00FFFF 4 01000-01FFF 01000-01FFF 000000-007FFF 4 00000-00FFF 00000-00FFF 16 Mbit Table 5. 8 Mbit 4-Mbit and 8-Mbit Word-Wide Memory Addressing Map (Sheet 1 of 2) 4-Mbit and 8-Mbit Word-Wide Memory Addressing Top Boot Size (KW) Bottom Boot Size (KW) 4 Mbit 4 Mbit 8 Mbit 3F000-3FFFF 7F000-7FFFF 32 78000-7FFFF 3E000-3EFFF 7E000-7EFFF 32 70000-77FFF 3D000-3DFFF 7D000-7DFFF 32 68000-6FFFF 3C000-3CFFF 7C000-7CFFF 32 60000-67FFF 3B000-3BFFF 7B000-7BFFF 32 58000-5FFFF 3A000-3AFFF 7A000-7AFFF 32 50000-57FFF 39000-39FFF 79000-79FFF 32 48000-4FFFF 38000-38FFF 78000-78FFF 32 40000-47FFF 4 30000-37FFF 70000-77FFF 32 38000-3FFFF 38000-3FFFF 4 28000-2FFFF 68000-6FFFF 32 30000-37FFF 30000-37FFF 4 20000-27FFF 60000-67FFF 32 28000-2FFFF 28000-2FFFF 4 18000-1FFFF 58000-5FFFF 32 20000-27FFF 20000-27FFF 4 10000-17FFF 50000-57FFF 32 18000-1FFFF 18000-1FFFF 4 08000-0FFFF 48000-4FFFF 32 10000-17FFF 10000-17FFF 4 00000-07FFF 40000-47FFF 32 08000-0FFFF 08000-0FFFF 4 38000-3FFFF 4 07000-07FFF 07000-07FFF 32 30000-37FFF 4 06000-06FFF 06000-06FFF 32 28000-2FFFF 4 05000-05FFF 05000-05FFF 32 20000-27FFF 4 04000-04FFF 04000-04FFF 32 18000-1FFFF 4 03000-03FFF 03000-03FFF 18 Aug 2005 14 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 5. 4-Mbit and 8-Mbit Word-Wide Memory Addressing Map (Sheet 2 of 2) 4-Mbit and 8-Mbit Word-Wide Memory Addressing Top Boot Size (KW) Bottom Boot 4 Mbit Size (KW) 4 Mbit 8 Mbit 32 10000-17FFF 4 02000-02FFF 02000-02FFF 32 08000-0FFFF 4 01000-01FFF 01000-01FFF 32 00000-07FFF 4 00000-00FFF 00000-00FFF Table 6. 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 1 of 6) 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot Size (KW) 16 Mbit 32 Mbit 64 Mbit Size (KW) 4 FF000-FFFFF 1FF0001FFFFF 3FF000-3FFFFF 32 3F80003FFFFF 4 FE000-FEFFF 1FE0001FEFFF 3FE000-3FEFFF 32 3F00003F7FFF 4 FD000-FDFFF 1FD0001FDFFF 3FD000-3FDFFF 32 3E80003EFFFF 4 FC000-FCFFF 1FC0001FCFFF 3FC000-3FCFFF 32 3E00003E7FFF 4 FB000-FBFFF 1FB0001FBFFF 3FB000-3FBFFF 32 3D80003DFFFF 4 FA000-FAFFF 1FA0001FAFFF 3FA000-3FAFFF 32 3D00003D7FFF 4 F9000-F9FFF 1F90001F9FFF 3F9000-3F9FFF 32 3C80003CFFFF 4 F8000-F8FFF 1F80001F8FFF 3F8000-3F8FFF 32 3C00003C7FFF 32 F0000-F7FFF 1F00001F7FFF 3F0000-3F7FFF 32 3B80003BFFFF 32 E8000-EFFFF 1E80001EFFFF 3E8000-3EFFFF 32 3B00003B7FFF 32 E0000-E7FFF 1E00001E7FFF 3E0000-3E7FFF 32 3A80003AFFFF 32 D8000-DFFFF 1D80001DFFFF 3D8000-3DFFFF 32 3A00003A7FFF 32 D0000-D7FFF 1D00001D7FFF 3D0000-3D7FFF 32 398000-39FFFF 32 C8000-CFFFF 1C80001CFFFF 3C8000-3CFFFF 32 390000-397FFF 32 C0000-C7FFF 1C00001C7FFF 3C0000-3C7FFF 32 388000-38FFFF 32 B8000-BFFFF 1B80001BFFFF 3B8000-3BFFFF 32 380000-387FFF Datasheet 16 Mbit Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 32 Mbit 64 Mbit 18 Aug 2005 15 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 6. 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 2 of 6) 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot Size (KW) 16 Mbit 32 Mbit 64 Mbit Size (KW) 32 B0000-B7FFF 1B00001B7FFF 3B0000-3B7FFF 32 378000-37FFFF 32 A8000-AFFFF 1A80001AFFFF 3A8000-3AFFFF 32 370000-377FFF 32 A0000-A7FFF 1A00001A7FFF 3A0000-3A7FFF 32 368000-36FFFF 32 98000-9FFFF 19800019FFFF 398000-39FFFF 32 360000-367FFF 32 90000-97FFF 190000197FFF 390000-397FFF 32 358000-35FFFF 32 88000-8FFFF 18800018FFFF 388000-38FFFF 32 350000-357FFF 32 80000-87FFF 180000187FFF 380000-387FFF 32 348000-34FFFF 32 78000-7FFFF 17800017FFFF 378000-37FFFF 32 340000-347FFF 32 70000-77FFF 170000177FFF 370000-377FFF 32 338000-33FFFF 32 68000-6FFFF 16800016FFFF 368000-36FFFF 32 330000-337FFF 32 60000-67FFF 160000167FFF 360000-367FFF 32 328000-32FFFF 32 58000-5FFFF 15800015FFFF 358000-35FFFF 32 320000-327FFF 32 50000-57FFF 150000157FFF 350000-357FFF 32 318000-31FFFF 32 48000-4FFFF 14800014FFFF 348000-34FFFF 32 310000-317FFF 32 40000-47FFF 140000147FFF 340000-347FFF 32 308000-30FFFF 32 38000-3FFFF 13800013FFFF 338000-33FFFF 32 300000-307FFF 32 30000-37FFF 130000137FFF 330000-337FFF 32 2F80002FFFFF 32 28000-2FFFF 12800012FFFF 328000-32FFFF 32 2F00002F7FFF 32 20000-27FFF 120000127FFF 320000-327FFF 32 2E80002EFFFF 32 18000-1FFFF 118000-11FFFF 318000-31FFFF 32 2E00002E7FFF 32 10000-17FFF 110000-117FFF 310000-317FFF 32 2D80002DFFFF 18 Aug 2005 16 16 Mbit Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 32 Mbit 64 Mbit Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 6. 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 3 of 6) 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot Size (KW) 16 Mbit 32 Mbit 64 Mbit Size (KW) 32 08000-0FFFF 10800010FFFF 308000-30FFFF 32 2D00002D7FFF 32 00000-07FFF 100000107FFF 300000-307FFF 32 2C80002CFFFF 32 0F80000FFFFF 2F8000-2FFFFF 32 2C00002C7FFF 32 0F00000F7FFF 2F0000-2F7FFF 32 2B80002BFFFF 32 0E80000EFFFF 2E8000-2EFFFF 32 2B00002B7FFF 32 0E00000E7FFF 2E0000-2E7FFF 32 2A80002AFFFF 32 0D80000DFFFF 2D8000-2DFFFF 32 2A00002A7FFF 32 0D00000D7FFF 2D0000-2D7FFF 32 298000-29FFFF 32 0C80000CFFFF 2C8000-2CFFFF 32 290000-297FFF 32 0C00000C7FFF 2C0000-2C7FFF 32 288000-28FFFF 32 0B80000BFFFF 2B8000-2BFFFF 32 280000-287FFF 32 0B00000B7FFF 2B0000-2B7FFF 32 278000-27FFFF 32 0A80000AFFFF 2A8000-2AFFFF 32 270000-277FFF 32 0A00000A7FFF 2A0000-2A7FFF 32 268000-26FFFF 32 09800009FFFF 298000-29FFFF 32 260000-267FFF 32 090000097FFF 290000-297FFF 32 258000-25FFFF 32 08800008FFFF 288000-28FFFF 32 250000-257FFF 32 080000087FFF 280000-287FFF 32 248000-24FFFF 32 07800007FFFF 278000-27FFFF 32 240000-247FFF 32 070000077FFF 270000-277FFF 32 238000-23FFFF 32 06800006FFFF 268000-26FFFF 32 230000-237FFF Datasheet 16 Mbit Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 32 Mbit 64 Mbit 18 Aug 2005 17 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 6. 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 4 of 6) 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 32 Mbit 64 Mbit Size (KW) 32 060000067FFF 260000-267FFF 32 228000-22FFFF 32 05800005FFFF 258000-25FFFF 32 220000-227FFF 32 050000057FFF 250000-257FFF 32 218000-21FFFF 32 04800004FFFF 248000-24FFFF 32 210000-217FFF 32 040000047FFF 240000-247FFF 32 208000-20FFFF 32 03800003FFFF 238000-23FFFF 32 200000-207FFF 32 030000037FFF 230000-237FFF 32 1F80001FFFFF 1F80001FFFFF 32 02800002FFFF 228000-22FFFF 32 1F00001F7FFF 1F00001F7FFF 32 020000027FFF 220000-227FFF 32 1E80001EFFFF 1E80001EFFFF 32 01800001FFFF 218000-21FFFF 32 1E00001E7FFF 1E00001E7FFF 32 010000017FFF 210000-217FFF 32 1D80001DFFFF 1D80001DFFFF 32 00800000FFFF 208000-21FFFF 32 1D00001D7FFF 1D00001D7FFF 32 000000007FFF 200000-207FFF 32 1C80001CFFFF 1C80001CFFFF 32 1F8000-1FFFFF 32 1C00001C7FFF 1C00001C7FFF 32 1F0000-1F7FFF 32 1B80001BFFFF 1B80001BFFFF 32 1E8000-1EFFFF 32 1B00001B7FFF 1B00001B7FFF 32 1E0000-1E7FFF 32 1A80001AFFFF 1A80001AFFFF 32 1D8000-1DFFFF 32 1A00001A7FFF 1A00001A7FFF 32 1D0000-1D7FFF 32 198000-19FFFF 198000-19FFFF 32 1C8000-1CFFFF 32 190000-197FFF 190000-197FFF 32 1C0000-1C7FFF 32 188000-18FFFF 188000-18FFFF 32 1B8000-1BFFFF 32 180000-187FFF 180000-187FFF 32 1B0000-1B7FFF 32 178000-17FFFF 178000-17FFFF 32 1A8000-1AFFFF 32 170000-177FFF 170000-177FFF Size (KW) 16 Mbit 18 Aug 2005 18 16 Mbit 32 Mbit Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 64 Mbit Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 6. 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 5 of 6) 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64 Mbit Size (KW) 32 1A0000-1A7FFF 32 Size (KW) 32 Mbit 64 Mbit 32 168000-16FFFF 168000-16FFFF 198000-19FFFF 32 160000-167FFF 160000-167FFF 32 190000-197FFF 32 158000-15FFFF 158000-15FFFF 32 188000-18FFFF 32 150000-157FFF 150000-157FFF 32 180000-187FFF 32 148000-14FFFF 148000-14FFFF 32 178000-17FFFF 32 140000-147FFF 140000-147FFF 32 170000-177FFF 32 138000-13FFFF 138000-13FFFF 32 168000-16FFFF 32 130000-137FFF 130000-137FFF 32 160000-167FFF 32 128000-12FFFF 128000-12FFFF 32 158000-15FFFF 32 120000-127FFF 120000-127FFF 32 150000-157FFF 32 118000-11FFFF 118000-11FFFF 32 148000-14FFFF 32 110000-117FFF 110000-117FFF 32 140000-147FFF 32 108000-10FFFF 108000-10FFFF 32 138000-13FFFF 32 100000-107FFF 100000-107FFF 32 130000-137FFF 32 F8000-FFFFF F8000-FFFFF 16 Mbit 32 Mbit 16 Mbit F8000-FFFFF 32 128000-12FFFF 32 F0000-F7FFF F0000-F7FFF F0000-F7FFF 32 120000-127FFF 32 E8000-EFFFF E8000-EFFFF E8000-EFFFF 32 118000-11FFFF 32 E0000-E7FFF E0000-E7FFF E0000-E7FFF 32 110000-117FFF 32 D8000-DFFFF D8000-DFFFF D8000-DFFFF 32 108000-10FFFF 32 D0000-D7FFF D0000-D7FFF D0000-D7FFF 32 100000-107FFF 32 C8000-CFFFF C8000-CFFFF C8000-CFFFF 32 0F8000-0FFFFF 32 C0000-C7FFF C0000-C7FFF C0000-C7FFF 32 0F0000-0F7FFF 32 B8000-BFFFF B8000-BFFFF B8000-BFFFF 32 0E8000-0EFFFF 32 B0000-B7FFF B0000-B7FFF B0000-B7FFF 32 0E0000-0E7FFF 32 A8000-AFFFF A8000-AFFFF A8000-AFFFF 32 0D8000-0DFFFF 32 A0000-A7FFF A0000-A7FFF A0000-A7FFF 32 0D0000-0D7FFF 32 98000-9FFFF 98000-9FFFF 98000-9FFFF 32 0C8000-0CFFFF 32 90000-97FFF 90000-97FFF 90000-97FFF 32 0C0000-0C7FFF 32 88000-8FFFF 88000-8FFFF 88000-8FFFF 32 0B8000-0BFFFF 32 80000-87FFF 80000-87FFF 80000-87FFF 32 0B0000-0B7FFF 32 78000-7FFFF 78000-7FFFF 78000-7FFFF 32 0A8000-0AFFFF 32 70000-77FFF 70000-77FFF 70000-77FFF 32 0A0000-0A7FFF 32 68000-6FFFF 68000-6FFFF 68000-6FFFF 32 098000-09FFFF 32 60000-67FFF 60000-67FFF 60000-67FFF 32 090000-097FFF 32 58000-5FFFF 58000-5FFFF 58000-5FFFF Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 19 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 6. 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Map (Sheet 6 of 6) 16-Mbit, 32-Mbit, and 64-Mbit Word-Wide Memory Addressing Top Boot Bottom Boot 64 Mbit Size (KW) 16 Mbit 32 Mbit 64 Mbit 32 088000-08FFFF 32 50000-57FFF 50000-57FFF 50000-57FFF 32 080000-087FFF 32 48000-4FFFF 48000-4FFFF 48000-4FFFF 32 078000-07FFFF 32 40000-47FFF 40000-47FFF 40000-47FFF Size (KW) 16 Mbit 32 Mbit 32 070000-077FFF 32 38000-3FFFF 38000-3FFFF 38000-3FFFF 32 068000-06FFFF 32 30000-37FFF 30000-37FFF 30000-37FFF 32 060000-067FFF 32 28000-2FFFF 28000-2FFFF 28000-2FFFF 32 058000-05FFFF 32 20000-27FFF 20000-27FFF 20000-27FFF 32 050000-057FFF 32 18000-1FFFF 18000-1FFFF 18000-1FFFF 32 048000-04FFFF 32 10000-17FFF 10000-17FFF 10000-17FFF 32 040000-047FFF 32 08000-0FFFF 08000-0FFFF 08000-0FFFF 32 038000-03FFFF 4 07000-07FFF 07000-07FFF 07000-07FFF 32 030000-037FFF 4 06000-06FFF 06000-06FFF 06000-06FFF 32 028000-02FFFF 4 05000-05FFF 05000-05FFF 05000-05FFF 32 020000-027FFF 4 04000-04FFF 04000-04FFF 04000-04FFF 32 018000-01FFFF 4 03000-03FFF 03000-03FFF 03000-03FFF 32 010000-017FFF 4 02000-02FFF 02000-02FFF 02000-02FFF 32 008000-00FFFF 4 01000-01FFF 01000-01FFF 01000-01FFF 32 000000-007FFF 4 00000-00FFF 00000-00FFF 00000-00FFF 3.2.4 4-Mbit, 8-Mbit, and 16-Mbit Byte-Wide Memory Maps Table 7. 8-Mbit and 16-Mbit Byte-Wide Memory Addressing Map (Sheet 1 of 3) 8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing Top Boot Bottom Boot Size (KB) 8 Mbit 16 Mbit Size (KB) 8 FE000-FFFFF 1FE000-1FFFFF 64 8 FC000-FDFFF 1FC000-1FDFFF 64 8 FA000-FBFFF 1FA000-1FBFFF 64 8 F8000-F9FFF 1F8000-1F9FFF 64 8 F6000-F7FFF 1F6000-1F7FFF 64 8 F4000-F5FFF 1F4000-1F5FFF 64 8 F2000-F3FFF 1F2000-1F3FFF 64 8 F0000-F1FFF 1F0000-1F1FFF 64 18 Aug 2005 20 8 Mbit Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 16 Mbit Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 7. 8-Mbit and 16-Mbit Byte-Wide Memory Addressing Map (Sheet 2 of 3) 8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing Top Boot Bottom Boot Size (KB) 8 Mbit 16 Mbit Size (KB) 64 E0000-EFFFF 1E0000-1EFFFF 64 64 D0000-DFFFF 1D0000-1DFFFF 64 64 C0000-CFFFF 1C0000-1CFFFF 64 64 B0000-BFFFF 1B0000-1BFFFF 64 64 A0000-AFFFF 1A0000-1AFFFF 64 64 90000-9FFFF 190000-19FFFF 64 64 80000-8FFFF 180000-18FFFF 64 64 70000-7FFFF 170000-17FFFF 64 64 60000-6FFFF 160000-16FFFF 64 64 50000-5FFFF 150000-15FFFF 64 64 40000-4FFFF 140000-14FFFF 64 64 30000-3FFFF 130000-13FFFF 64 64 20000-2FFFF 120000-12FFFF 64 64 10000-1FFFF 110000-11FFFF 64 64 00000-0FFFF 8 Mbit 16 Mbit 100000-10FFFF 64 64 0F0000-0FFFFF 64 64 0E0000-0EFFFF 64 64 0D0000-0DFFFF 64 64 0C0000-0CFFFF 64 64 0B0000-0BFFFF 64 64 0A0000-0AFFFF 64 64 090000-09FFFF 64 64 080000-08FFFF 64 64 070000-07FFFF 64 64 060000-06FFFF 64 1F0000-1FFFFF 64 050000-05FFFF 64 1E0000-1EFFFF 64 040000-04FFFF 64 1D0000-1DFFFF 64 030000-03FFFF 64 1C0000-1CFFFF 64 020000-02FFFF 64 1B0000-1BFFFF 64 010000-01FFFF 64 1A0000-1AFFFF 64 000000-00FFFF 64 190000-19FFFF 64 64 180000-18FFFF 64 64 170000-17FFFF 64 64 160000-16FFFF 64 64 150000-15FFFF Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 21 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 7. 8-Mbit and 16-Mbit Byte-Wide Memory Addressing Map (Sheet 3 of 3) 8-Mbit and 16-Mbit Byte-Wide Byte-Wide Memory Addressing Top Boot Size (KB) 8 Mbit Bottom Boot 16 Mbit Size (KB) 8 Mbit 16 Mbit 64 64 140000-14FFFF 64 64 130000-13FFFF 64 64 120000-12FFFF 64 64 110000-11FFFF 64 64 100000-10FFFF 64 64 64 64 E0000-EFFFF 0E0000-0EFFFF 64 64 D0000-DFFFF 0D0000-0DFFFF 64 64 C0000-CFFFF 0C0000-0CFFFF 64 64 B0000-BFFFF 0B0000-0BFFFF 64 64 A0000-AFFFF 0A0000-0AFFFF 64 64 90000-9FFFF 090000-09FFFF 64 64 80000-8FFFF 080000-08FFFF 64 64 70000-7FFFF 070000-07FFFF 64 64 60000-6FFFF 060000-06FFFF 64 64 50000-5FFFF 050000-05FFFF 64 64 40000-4FFFF 040000-04FFFF 64 64 30000-3FFFF 030000-03FFFF 64 64 20000-2FFFF 020000-02FFFF 64 64 10000-1FFFF 010000-01FFFF 64 8 0E000-0FFFF 00E000-00FFFF 64 8 0C000-0DFFF 00C000-00DFFF 64 8 0A000-0BFFF 00A000-00BFFF 64 8 08000-09FFF 008000-009FFF 64 8 06000-07FFF 006000-007FFF 64 8 04000-05FFF 004000-005FFF 64 8 02000-03FFF 002000-003FFF 64 8 00000-01FFF 000000-001FFF 18 Aug 2005 22 F0000-FFFFF Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 0F0000-0FFFFF Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 8. 4-Mbit Byte Wide Memory Addressing Map 4-Mbit Byte-Wide Memory Addressing Top Boot Bottom Boot Size (KB) 4 Mbit Size (KB) 4 Mbit 8 7E000-7FFFF 64 70000-7FFFF 8 7C000-7DFFF 64 60000-6FFFF 8 7A000-7BFFF 64 50000-5FFFF 8 78000-79FFF 64 40000-4FFFF 8 76000-77FFF 64 30000-3FFFF 8 74000-75FFF 64 20000-2FFFF 8 72000-73FFF 64 10000-1FFFF 8 70000-71FFF 8 0E000-0FFFF 64 60000-6FFFF 8 0C000-0DFFF 64 50000-5FFFF 8 0A000-0BFFF 64 40000-4FFFF 8 08000-09FFF 64 30000-3FFFF 8 06000-07FFF 64 20000-2FFFF 8 04000-05FFF 64 10000-1FFFF 8 02000-03FFF 64 00000-0FFFF 8 00000-01FFF Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 23 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 4.0 Package Information 4.1 BGA* and Very Thin Profile Fine Pitch Ball Grid Array (VF BGA) Package Figure 2. BGA* and VF BGA Package Drawing Ball A1 Corner D 1 E 2 3 4 S1 5 6 7 8 8 A A B B C C D D E E F F 7 6 5 4 3 2 Ball A1 Corner S2 1 e b Bottom View -Bump side up Top View - Bump Side down A 1 A2 A Seating Y Plan Side View Note: Drawing not to scale Dimensions Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Length 8M (.25) Package Body Length 16M (.25/.18/.13) 32M (.25/.18/.13) Package Body Length 64M (.18) Package Body Width 8M (.25) Package Body Width 16M (.25/.18/.13) 32M (.18/.13) Package Body Width 32M (.25) Package Body Width 64M (.18) Pitch Ball (Lead) Count 8M, 16M Ball (Lead) Count 32M Ball (Lead) Count 64M Seating Plane Coplanarity Corner to Ball A1 Distance Along D 8M (.25) Corner to Ball A1 Distance Along D 16M (.25/.18/.13) 32M (.18/.13) Corner to Ball A1 Distance Along D 64M (.18) Corner to Ball A1 Distance Along E 8M (.25) Corner to Ball A1 Distance Along E 16M (.25/.18/.13) 32M (.18/.13) Corner to Ball A1 Distance Along E 32M (.25) Corner to Ball A1 Distance Along E 64M (.18) 18 Aug 2005 24 Symbol A A1 A2 b D D D E E E E e N N N Y S1 S1 S1 S2 S2 S2 S2 Min Millimeters Nom Max 1.000 0.150 0.325 7.810 7.186 7.600 6.400 6.864 10.750 8.900 1.230 0.918 1.125 1.275 1.507 3.450 2.525 Min Inches Nom Max 0.0394 0.0059 0.665 0.375 7.910 7.286 7.700 6.500 6.964 10.850 9.000 0.750 46 47 48 1.330 1.018 1.225 1.375 1.607 3.550 2.625 0.2829 0.2992 0.2520 0.2702 0.4232 0.3504 0.2868 0.3031 0.2559 0.2742 0.4272 0.3543 0.0295 46 47 48 0.100 1.430 1.118 1.325 1.475 1.707 3.650 2.725 0.0484 0.0361 0.0443 0.0502 0.0593 0.1358 0.0994 0.0524 0.0401 0.0482 0.0541 0.0633 0.1398 0.1033 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 0.0128 0.0262 0.0148 0.425 8.010 7.386 7.800 6.600 7.064 10.860 9.100 0.0167 0.2908 0.3071 0.2598 0.2781 0.4276 0.3583 0.0039 0.0563 0.0440 0.0522 0.0581 0.0672 0.1437 0.1073 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 4.2 TSOP Package Figure 3. TSOP Package Drawing Z A2 See Notes 1, 2, 3 and 4 Pin 1 e See Detail B E Y D1 A1 D Seating Plane See Det ail A A Det ail A Detail B C b 0 L A5568- 02 Dimensions Family: Thin Small Out -Line Package Symbol Millimeters Min Nom Inches Max Notes Min Nom 1.200 Max Package Height A Standoff A1 0.050 Package Body Thickness A2 0.950 1.000 1.050 0.037 0.039 0.041 Lead Width b 0.150 0.200 0.300 0.006 0.008 0.012 0.100 0.150 0.047 0.002 Lead Thickness c 0.200 0.004 0.006 0.008 Plastic Body Length D1 18.200 18.400 18.600 0.717 0.724 0.732 Package Body Width E 11.800 12.000 12.200 0.465 0.472 0.480 Lead Pitch e 0.500 Terminal Dimension D 19.800 20.000 20.200 Lead Tip Length L Lead Count N Lead Tip Angle O Seating Plane Coplanarity Y Lead to Package Offset Z 0.500 0.600 0.0197 0.780 0.787 0.795 0.700 0.020 0.024 0.028 5 0 48 0 3 48 3 0.100 0.150 Notes 0.250 0.350 5 0.004 0.006 0.010 0.014 Notes: 1. One dimple on package denotes Pin 1. 2. If two dimples, then the larger dimple denotes Pin 1. 3. Pin 1 is in the upper left corner of the package, in reference to the product mark. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 25 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 4.3 Easy BGA Package Figure 4. Easy BGA Package Drawing Ball A1 Corner D 1 E 2 3 4 Ball A1 Corner S1 5 6 7 8 8 A A B B C C D D E E F F G G H H 7 6 5 4 3 2 1 S2 b e Top View - Ball side down Bottom View - Ball Side Up A1 A2 A Seating Y Plane Side View Note: Drawing not to scale Dimensions Table Package Height Ball Height Package Body Thickness Ball (Lead) Width Package Body Width Package Body Length Pitch Ball (Lead) Count Seating Plane Coplanarity Corner to Ball A1 Distance Along D Corner to Ball A1 Distance Along E Symbol A A1 A2 b D E [e] N Y S1 S2 Millimeters Min Nom Max 1.200 Notes 0.250 0.330 9.900 12.900 1.400 2.900 Inches Min Nom Max 0.0472 0.0098 0.780 0.430 10.000 13.000 1.000 64 1.500 3.000 0.530 10.100 13.100 1 1 0.0130 0.3898 0.5079 0.100 1.600 3.100 1 1 0.0551 0.1142 0.0307 0.0169 0.3937 0.5118 0.0394 64 0.0591 0.1181 0.0209 0.3976 0.5157 0.0039 0.0630 0.1220 Note: (1) Package dimensions are for reference only. These dimensions are estimates based on die size, and are subject to change. 18 Aug 2005 26 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 5.0 Pinout and Signal Descriptions This section explains the package pinout and signal descriptions. 5.1 Signal Pinouts The B3 flash memory device is available in the following packages: * * * * 40-lead TSOP (x8, Figure 5). 48-lead TSOP (x16, Figure 6). 48-ball BGA (x8 in Figure 8 and x16 in Figure 9). 48-ball VF BGA (x16, Figure 9). 5.1.1 40-Lead and 48-Lead TSOP Packages Figure 5. 40-Lead TSOP Package for x8 Configurations 4M A16 A15 A14 A13 A12 A11 A9 A8 WE# RP# VPP WP# A18 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Advanced Boot Block 40-Lead TSOP 10 mm x 20 mm TOP VIEW 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 A17 GND A20 A19 A10 DQ7 DQ6 DQ5 DQ4 VCCQ VCC NC DQ3 DQ2 DQ1 DQ0 OE# GND CE# A0 16 M 8M Notes: 1. 40-Lead TSOP available for 8-Mbit and 16-Mbit densities only. 2. Lower densities have NC on the upper address pins. For example, an 8-Mbit device has NC on Pin 38. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 27 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Figure 6. 48-Lead TSOP Package for x16 Configurations 64 M 32 M 16 M Figure 7. A15 A14 A13 A12 A11 A10 A9 A8 A21 A20 WE# RP# VPP WP# A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Advanced Boot Block 48-Lead TSOP 12 mm x 20 mm TOP VIEW 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 VCCQ GND DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# GND CE# A0 New Mark for Pin-1 Indicator: 40-Lead 8/16 Mb TSOP and 48-Lead 8/16/32 Mb TSOP New Mark: Note: 18 Aug 2005 28 The topside marking on 8-Mb, 16-Mb, and 32-Mb Intel(R) Advanced Boot Block 40L and 48L TSOP products changed to a white ink triangle as a Pin-1 indicator. Products without the white triangle continue to use a dimple as a Pin-1 indicator. No other changes were made in package size, materials, functionality, customer handling, or manufacturability. The product continues to meet stringent Intel quality requirements. Table 9 lists the ordering codes of the affected products. See also Table 34 "Ordering Information: Valid Combinations" on page 70. Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 9. B3 Flash Memory Device Ordering Information Ordering Information Valid Combinations 40-Lead TSOP 48-Lead TSOP Ext. Temp. 64 Mbit Ext. Temp. 32 Mbit Ext. Temp. 16 Mbit Ext. Temp. 8 Mbit Figure 8. TE28F640B3TC70 TE28F640B3BC70 TE28F320B3TD70 TE28F320B3BD70 TE28F320B3TC70 TE28F320B3BC70 TE28F320B3TC90 TE28F320B3BC90 TE28F320B3TA100 TE28F320B3BA100 TE28F320B3TA110 TE28F320B3BA110 TE28F160B3TC70 TE28F160B3BC70 TE28F160B3TC80 TE28F160B3BC80 TE28F016B3TA90 TE28F016B3BA90 TE28F160B3TA90 TE28F160B3BA90 TE28F016B3TA110 TE28F016B3BA110 TE28F160B3TA110 TE28F160B3BA110 TE28F008B3TA90 TE28F008B3BA90 TE28F800B3TA90 TE28F800B3BA90 TE28F008B3TA110 TE28F008B3BA110 TE28F800B3TA110 TE28F800B3BA110 x8 48-Ball BGA* Chip Size Package (Top View, Ball Down) 1 2 3 4 5 6 7 8 A A14 A12 A8 V PP W P# A20 A7 A4 B A15 A10 WE# RP# A19 A18 A5 A2 C A16 A13 A9 A6 A3 A1 D A17 NC D5 NC D2 NC CE# A0 E VCCQ A11 D6 NC D3 NC D0 GND D7 NC D4 V CC NC D1 OE# 16M 8M F GND Notes: 1. A19 and A20 indicate the upgrade address connections. Lower density devices do not have the upper address solder balls. Do not route is not done in this area. A20 is the upgrade address for the 16-Mbit device. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 29 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Figure 9. x16 48-Ball VF BGA and BGA* Chip Size Package (Top View, Ball Down) 1 2 3 4 5 6 7 8 16M A A13 A11 A8 VPP WP# A19 A7 A4 B A14 A10 WE# RP# A18 A17 A5 A2 64M 32M C A15 A12 A9 A21 A20 A6 A3 A1 D A16 D14 D5 D11 D2 D8 CE# A0 E VCCQ D15 D6 D12 D3 D9 D0 Vss F Vss D7 D13 D4 VCC D10 D1 OE# Notes: 1. A19, A20, and A21 indicate the upgrade address connections. Lower density devices do not have the upper address solder balls. Do not route in this area. - A19 is the upgrade address for the 16-Mbit device. - A20 is the upgrade address for the 32-Mbit device. - A21 is the upgrade address for the 64-Mbit device. 2. Table 10 "B3 Flash memory Device Signal Descriptions" on page 31 details the usage of each device pin. 5.2 Signal Descriptions Table 10 describes the active signals. 18 Aug 2005 30 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 10. Symbol A0-A21 DQ0-DQ7 B3 Flash memory Device Signal Descriptions (Sheet 1 of 2) Type Description Input ADDRESS INPUTS for memory addresses. Addresses are internally latched during a program or erase cycle. 28F008B3: A[0-19], 28F016B3: A[0-20], 28F800B3: A[0-18], 28F160B3: A[0-19], 28F320B3: A[0-20], 28F640B3: A[0-21] Input/ Output DATA INPUTS/OUTPUTS: Inputs array data on the second CE# and WE# cycle during a Program command. * Inputs commands to the Command User Interface when CE# and WE# are active. Data is internally latched. * Outputs array, identifier and Status Register data. The data pins float to tristate when the chip is deselected or the outputs are disabled. DATA INPUTS/OUTPUTS: * Inputs array data on the second CE# and WE# cycle during a Program command. Data is internally latched. * Outputs array and identifier data. The data pins float to tristate when the chip is de-selected. Not included on x8 products. DQ8-DQ15 Input/ Output CE# Input CHIP ENABLE: Activates the internal control logic, input buffers, decoders, and sense amplifiers. CE# is active low. CE# high de-selects the memory device and reduces power consumption to standby levels. OE# Input OUTPUT ENABLE: Enables the flash memory device outputs through the data buffers during a Read operation. OE# is active low. WE# Input WRITE ENABLE: Controls writes to the Command Register and memory array. WE# is active low. Addresses and data are latched on the rising edge of the second WE# pulse. Input RESET/DEEP POWER-DOWN: Uses two voltage levels (VIL, VIH) to control reset/deep powerdown mode. * When RP# is at logic low, the flash memory device is in reset/deep power-down mode, which drives the outputs to High-Z, resets the Write State Machine, and minimizes current levels (ICCD). * When RP# is at logic high, the flash memory device is in standard operation. When RP# transitions from logic-low to logic-high, the flash memory device defaults to the read array mode. RP# WRITE PROTECT: Locks and unlocks the two lockable parameter blocks. WP# Input VCCQ Input VCC Power Datasheet * When WP# is at logic low, the lockable blocks are locked, preventing Program and Erase operations to those blocks. If a Program or Erase operation is attempted on a locked block, SR.1 and either SR.4 [program] or SR.5 [erase] are set to indicate the operation failed. * When WP# is at logic high, the lockable blocks are unlocked and can be programmed or erased. See Section 12.0, "Block Locking" on page 62 for details on write protection. OUTPUT V CC: Enables all outputs to be driven to 1.8 V to 2.5 V while the VCC is at 2.7 V to 3.3 V. If the VCC is regulated to 2.7 V to 2.85 V, VCCQ can be driven at 1.65 V to 2.5 V to achieve lowest power operation (see Section 7.2, "DC Voltage Characteristics" on page 36). This input can be tied directly to VCC (2.7 V to 3.6 V). DEVICE Power Supply: 2.7 V to 3.6 V Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 31 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 10. Symbol B3 Flash memory Device Signal Descriptions (Sheet 2 of 2) Type Description VPP Power PROGRAM/ERASE Power Supply: Supplies power for Program and Erase operations. VPP can be the same as VCC (2.7 V to 3.6 V) for single supply voltage operation. For fast programming at manufacturing, 11.4 V to 12.6 V can be supplied to VPP. This pin cannot be left floating. 11.4 V to 12.6 V can be applied to VPP only for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP can be connected to 12 V for a total of 80 hours maximum (see Section 13.0, "VPP Program and Erase Voltages" on page 63 for details). VPP < VPPLK protects memory contents against inadvertent or unintended program and erase commands. GND -- Ground: For all internal circuitry. All ground inputs must be connected. NC -- No Connect: Pin can be driven or left floating. 6.0 Maximum Ratings and Operating Conditions 6.1 Absolute Maximum Ratings Warning: Stressing the flash memory device beyond the Absolute Maximum Ratings in Table 11 can cause permanent damage. These ratings are stress ratings only. NOTICE: Specifications are subject to change without notice. Verify with your local Intel Sales office that you have the latest datasheet before finalizing a design. Table 11. Absolute Maximum Ratings Parameter Maximum Rating Notes Extended Operating Temperature During Read -40 C to +85 C During Block Erase and Program -40 C to +85 C Temperature under Bias -40 C to +85 C Storage Temperature -65 C to +125 C Voltage On Any Pin (except VCC and VPP) with Respect to GND -0.5 V to +3.7 V 1 VPP Voltage (for Block Erase and Program) with Respect to GND -0.5 V to +13.5 V 1,2,3 VCC and VCCQ Supply Voltage with Respect to GND -0.2 V to +3.6 V Output Short Circuit Current 100 mA 4 Notes: 1. Minimum DC voltage is -0.5 V on input/output pins. During transitions, this level might undershoot to -2.0 V for periods <20 ns. Maximum DC voltage on input/output pins is VCC +0.5 V which, during transitions, might overshoot to VCC +2.0 V for periods <20 ns. 2. Maximum DC voltage on VPP might overshoot to +14.0 V for periods <20 ns. 3. VPP Program voltage is typically 1.65 V to 3.6 V. Connection to a 11.4 V to 12.6 V supply can be done for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks during program/erase. VPP can be connected to 12 V for a total of 80 hours maximum. 4. Output shorted for no more than one second. No more than one output shorted at a time. 18 Aug 2005 32 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 6.2 Operating Conditions Do not operate the flash memory device beyond the Operating Conditions in Table 12. Extended exposure beyond the Operating Conditions can affect device reliability. Table 12. Temperature and Voltage Operating Conditions Symbol TA VCC1 Parameter Min Max Units Operating Temperature -40 +85 C VCC Supply Voltage 2.7 3.6 Volts 3.0 3.6 VCC2 VCCQ1 VCCQ2 I/O Supply Voltage VCCQ3 VPP1 Supply Voltage VPP2 Cycling Block Erase Cycling 2.7 3.6 1.65 2.5 1.8 2.5 1.65 3.6 11.4 12.6 100,000 Notes 1, 2 1, 2 1 Volts Volts 1 Volts 1, 3 Cycles 3 Notes: 1. VCC and VCCQ must share the same supply when they are in the VCC1 range. 2. VCCMax = 3.3 V for 0.25m 32-Mbit devices. 3. VPP = 11.4 V-12.6 V can be applied during a program/erase only for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP can be connected to 12 V for a total of 80 hours maximum. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 33 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 7.0 Electrical Specifications 7.1 DC Current Characteristics Table 13. DC Current Characteristics (Sheet 1 of 2) Sym Parameter VCC 2.7 V-3.6 V 2.7 V-2.85 V 2.7 V-3.3 V VCCQ 2.7 V-3.6 V 1.65 V-2.5 V 1.8 V-2.5 V Note Typ Typ Typ Max Max Unit Test Conditions Max ILI Input Load Current 1,2 1 1 1 A VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND ILO Output Leakage Current 1,2 10 10 10 A VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND VCC Standby Current for 0.13 and 0.18 Micron Product 1 7 15 20 50 150 250 A VCC Standby Current for 0.25 Micron Product 1 10 25 20 50 150 250 A VCC Power-Down Current for 0.13 and 0.18 Micron Product 1,2 7 15 7 20 7 20 A VCC Power-Down Current for 0.25 Product 1,2 7 25 7 25 7 25 A VCC Read Current for 0.13 and 0.18 Micron Product 1,2,3 9 18 8 15 9 15 mA VCC Read Current for 0.25 Micron Product 1,2,3 10 18 8 15 9 15 mA 1 0.2 5 0.2 5 0.2 5 A RP# = GND 0.2 V VPP VCC 18 55 18 55 18 55 mA VPP =VPP1, Program in Progress 8 22 10 30 10 30 mA VPP = VPP2 (12v) Program in Progress 16 45 21 45 21 45 mA VPP = VPP1, Erase in Progress 8 15 16 45 16 45 mA VPP = VPP2 (12v) , Erase in Progress 7 15 50 200 50 200 A ICCS ICCD ICCR IPPD ICCW ICCE ICCES/ ICCWS IPPR VPP Deep Power-Down Current VCC Program Current VCC = VCCMax VCCQ = VCCQMax OE# = VIH, CE# =VIL f = 5 MHz, IOUT=0 mA Inputs = VIL or VIH 1,4 VCC Erase Suspend Current for 0.13 and 0.18 Micron Product CE# = VIH, Erase Suspend in Progress 1,4,5 VCC Erase Suspend Current for 0.25 Micron Product 18 Aug 2005 34 VCC = VCCMax VCCQ = VCCQMax VIN = VCCQ or GND RP# = GND 0.2 V 1,4 VCC Erase Current VPP Read Current VCC = VCCMax CE# = RP# = VCCQ or during Program/ Erase Suspend WP# = VCCQ or GND 10 25 50 200 50 200 A 2 15 2 15 2 15 A VPP VCC 50 200 50 200 50 200 A VPP > VCC 1,4 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 13. Sym IPPW IPPE IPPES/ IPPWS DC Current Characteristics (Sheet 2 of 2) Parameter VPP Program Current VPP Erase Current VCC Erase Suspend Current VCC 2.7 V-3.6 V 2.7 V-2.85 V 2.7 V-3.3 V VCCQ 2.7 V-3.6 V 1.65 V-2.5 V 1.8 V-2.5 V Note Typ Max Typ Max Typ Max 0.05 0.1 0.05 0.1 0.05 0.1 mA VPP =VPP1, Program in Progress 8 22 8 22 8 22 mA VPP = VPP2 (12v) Program in Progress 0.05 0.1 0.05 0.1 0.05 0.1 mA VPP = VPP1, Erase in Progress 8 22 16 45 16 45 mA VPP = VPP2 (12v) , Erase in Progress 0.2 5 0.2 5 0.2 5 A VPP = VPP1, Program or Erase Suspend in Progress 50 200 50 200 50 200 A VPP = VPP2 (12v) , Program or Erase Suspend in Progress Unit Test Conditions 1,4 1,4 1,4 Notes: 1. All currents are in RMS unless otherwise noted. Typical values at nominal VCC, TA = +25 C. 2. The test conditions VCCMax, VCCQMax, VCCMin, and VCCQMin refer to the maximum or minimum VCC or VCCQ voltage listed at the top of each column. VCCMax = 3.3 V for 0.25m 32-Mbit devices. 3. Automatic Power Savings (APS) reduces ICCR to approximately standby levels in static operation (CMOS inputs). 4. Sampled, not 100% tested. 5. ICCES or ICCWS is specified with the flash memory device deselected. - If the device is read while in erase suspend, the current draw is the sum of ICCES and ICCR. - If the device is read while in program suspend, the current draw is the sum of ICCWS and ICCR. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 35 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 7.2 DC Voltage Characteristics Table 14. DC Voltage Characteristics Symbol Parameter VCC 2.7 V-3.6 V 2.7 V-2.85 V 2.7 V-3.3 V VCCQ 2.7 V-3.6 V 1.65 V-2.5 V 1.8 V-2.5 V Note Min Max Min Max Min Max Unit Test Conditions VIL Input Low Voltage -0.4 VCC * 0.22 V -0.4 0.4 -0.4 0.4 V VIH Input High Voltage 2.0 VCCQ +0.3V VCCQ - 0.4V VCCQ +0.3V VCCQ - 0.4V VCCQ +0.3V V VOL Output Low Voltage -0.1 0.1 -0.1 0.1 -0.1 0.1 V VCC = VCCMin VCCQ = VCCQMin IOL = 100 A VOH Output High Voltage VCCQ -0.1V V VCC = VCCMin VCCQ = VCCQMin IOH = -100 A VPPLK VPP LockOut Voltage 1.0 V Complete Write Protection VPP1 VPP2 VPP During Program / Erase Operations 1 VCCQ - 0.1V 1.0 VCCQ - 0.1V 1.0 1 1.65 3.6 1.65 3.6 1.65 3.6 V 1,2 11.4 12.6 11.4 12.6 11.4 12.6 V VLKO VCC Prog/ Erase Lock Voltage 1.5 1.5 1.5 V VLKO2 VCCQ Prog/ Erase Lock Voltage 1.2 1.2 1.2 V Notes: 1. Erase and Program are inhibited when VPP < VPPLK and not guaranteed outside the valid VPP ranges of VPP1 and VPP2. 2. VPP = 11.4 V-12.6 V can be applied during program/erase only for a maximum of 1000 cycles on the main blocks and 2500 cycles on the parameter blocks. VPP can be connected to 12 V for a total of 80 hours maximum. 18 Aug 2005 36 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 8.0 AC Characteristics 8.1 AC Read Characteristics Table 15. Read Operations--8-Mbit Density Density 8 Mbit Product # Sym 90 ns Unit VCC 3.0 V - 3.6 V 2.7 V - 3.6 V 3.0 V - 3.6 V 2.7 V - 3.6 V Note Min Min Min Min 80 Max R1 tAVAV Read Cycle Time 3,4 R2 tAVQV Address to Output Delay 3,4 R3 tELQV CE# to Output Delay 1,3,4 R4 tGLQV OE# to Output Delay 1,3,4 R5 tPHQV RP# to Output Delay 3,4 150 R6 tELQX CE# to Output in Low Z R7 tGLQX R8 tEHQZ R9 R10 Notes: 1. 2. 3. 4. 110 ns Parameter Max 90 80 Max 100 Max 110 ns 90 100 110 ns 80 90 100 110 ns 30 30 30 30 ns 150 150 150 ns 2,3,4 0 OE# to Output in Low Z 2,3,4 0 CE# to Output in High Z 2,3,4 20 20 20 20 ns tGHQZ OE# to Output in High Z 2,3,4 20 20 20 20 ns tOH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 2,3,4 0 0 0 0 0 0 0 0 ns 0 0 ns ns OE# can be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, but not 100% tested. See Figure 10 "Read Operation Waveform" on page 40. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 37 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 16. Read Operations--16-Mbit Density Density # Sym R1 Param eter 16 Mbit Product 70 ns 80 ns VCC 2.7 V-3.6 V 2.7 V-3.6 V 3.0 V-3.6 V 2.7 V-3.6 V Min Min Min Min Max Max Min ns 3,4 Max tAVQV 70 80 80 90 100 110 ns 3,4 R3 tELQV CE# to Output Delay 70 80 80 90 100 110 ns 1,3,4 R4 tGLQV OE# to Output Delay 20 20 30 30 30 30 ns 1,3,4 R5 tPHQV RP# to Output Delay 150 150 150 150 150 150 ns 3,4 R6 tELQX CE# to Output in Low Z 0 0 0 0 0 0 ns 2,3,4 R7 tGLQX OE# to Output in Low Z 0 0 0 0 0 0 ns 2,3,4 R8 tEHQZ CE# to Output in High Z 20 20 20 20 20 20 ns 2,3,4 R9 tGHQZ OE# to Output in High Z 20 20 20 20 20 20 ns 2,3,4 ns 2,3,4 Notes: 1. 2. 3. 4. 0 0 0 100 Notes R2 0 90 Min Unit 2.7 V-3.6V Address to Output Delay tOH 80 Max 3.0 V- 3.6V Read Cycle Time R10 80 Max 110 ns tAVAV Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 70 Max 90 ns 0 110 0 OE# can be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, but not 100% tested. See Figure 10 "Read Operation Waveform" on page 40. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate. 18 Aug 2005 38 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 17. Read Operations--32-Mbit Density Density # Sym R1 Param eter 32 Mbit Product 70 ns 90 ns VCC 2.7 V-3.6 V 2.7 V-3.6 V 3.0 V-3.3 V 2.7 V-3.3 V 3.0 V-3.3 V 2.7 V-3.3 V Min Min Min Min Min Min Max ns 3,4 tAVQV 70 90 90 100 100 110 ns 3,4 R3 tELQV CE# to Output Delay 70 90 90 100 100 110 ns 1,3,4 R4 tGLQV OE# to Output Delay 20 20 30 30 30 30 ns 1,3,4 R5 tPHQV RP# to Output Delay 150 150 150 150 150 150 ns 3,4 R6 tELQX CE# to Output in Low Z 0 0 0 0 0 0 ns 2,3,4 R7 tGLQX OE# to Output in Low Z 0 0 0 0 0 0 ns 2,3,4 R8 tEHQZ CE# to Output in High Z 20 20 20 20 20 20 ns 2,3,4 R9 tGHQZ OE# to Output in High Z 20 20 20 20 20 20 ns 2,3,4 tOH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First ns 2,3,4 Notes: 1. 2. 3. 4. 0 100 Max R2 0 100 Max Notes Address to Output Delay 0 90 Max Unit Read Cycle Time 0 90 Max 110 ns tAVAV R10 70 Max 100 ns 0 110 0 OE# can be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, but not 100% tested. See Figure 10 "Read Operation Waveform" on page 40. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 39 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 18. Read Operations -- 64-Mbit Density Density # Sym Product 70 ns 80 ns VCC 2.7 V-3.6 V 2.7 V-3.6 V Note Min Min 70 Parameter Unit Max Max R1 tAVAV Read Cycle Time 3,4 R2 tAVQV Address to Output Delay 3,4 70 80 ns R3 tELQV CE# to Output Delay 1,3,4 70 80 ns R4 tGLQV OE# to Output Delay 1,3,4 20 20 ns R5 tPHQV RP# to Output Delay 3,4 150 150 ns R6 tELQX CE# to Output in Low Z 2,3,4 0 0 ns R7 tGLQX OE# to Output in Low Z 2,3,4 0 0 ns R8 tEHQZ CE# to Output in High Z 2,3,4 20 20 ns R9 tGHQZ OE# to Output in High Z 2,3,4 20 20 ns R10 tOH Output Hold from Address, CE#, or OE# Change, Whichever Occurs First 2,3,4 Notes: 1. 2. 3. 4. Figure 10. 64 Mbit 0 80 ns 0 ns OE# can be delayed up to tELQV-tGLQV after the falling edge of CE# without impact on tELQV. Sampled, but not 100% tested. See Figure 10 "Read Operation Waveform" on page 40. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate. Read Operation Waveform R1 R2 Address [A] R3 R8 CE# [E] R4 R9 OE# [G] WE# [W] R7 R6 R10 Data [D/Q] R5 RST# [P] 18 Aug 2005 40 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 8.2 AC Write Characteristics Table 19. Write Operations--8-Mbit Density Density 8 Mbit Product # Sym Parameter 90 ns 3.0 V - 3.6 V 110 ns 80 100 Unit VCC 2.7 V - 3.6 V 90 110 Note Min Min Min Min W1 tPHWL / tPHEL RP# High Recovery to WE# (CE#) Going Low 4,5 150 150 150 150 ns W2 tELWL / tWLEL CE# (WE#) Setup to WE# (CE#) Going Low 4,5 0 0 0 0 ns W3 tWLWH / tELEH WE# (CE#) Pulse Width 4,5 50 60 70 70 ns W4 tDVWH / tDVEH Data Setup to WE# (CE#) Going High 2,4,5 50 50 60 60 ns W5 tAVWH / tAVEH Address Setup to WE# (CE#) Going High 2,4,5 50 60 70 70 ns W6 tWHEH / tEHWH CE# (WE#) Hold Time from WE# (CE#) High 4,5 0 0 0 0 ns W7 tWHDX / tEHDX Data Hold Time from WE# (CE#) High 2,4,5 0 0 0 0 ns W8 tWHAX / tEHAX Address Hold Time from WE# (CE#) High 2,4,5 0 0 0 0 ns W9 tWHWL / tEHEL WE# (CE#) Pulse Width High 2,4,5 30 30 30 30 ns W10 tVPWH / tVPEH VPP Setup to WE# (CE#) Going High 3,4,5 200 200 200 200 ns W11 tQVVL VPP Hold from Valid SRD 3,4 0 0 0 0 ns W12 tBHWH / tBHEH WP# Setup to WE# (CE#) Going High 3,4 0 0 0 0 ns W13 tQVBL WP# Hold from Valid SRD 3,4 0 0 0 0 ns W14 tWHGL WE# High to OE# Going Low 3,4 30 30 30 30 ns Notes: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). So tWP = tWLWH = tELEH = tWLEH = tELWH. 2. 3. 4. 5. Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). So tWPH = tWHWL = tEHEL = tWHEL = tEHWL. Refer to Table 27 "Bus Operations(1)" on page 51 for valid AIN or DIN. Sampled, but not 100% tested. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate. See Figure 11 "Write Operations Waveform" on page 45. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 41 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 20. Write Operations--16-Mbit Density Density 16 Mbit Product # Sym Parameter 70 ns 80 ns 3.0 V - 3.6 V 90 ns 110 ns 80 100 Unit VCC 2.7 V - 3.6 V 70 80 90 110 Note Min Min Min Min Min Min W1 tPHWL / tPHEL RP# High Recovery to WE# (CE#) Going Low 4,5 150 150 150 150 150 150 ns W2 tELWL / tWLEL CE# (WE#) Setup to WE# (CE#) Going Low 4,5 0 0 0 0 0 0 ns W3 tWLWH / tELEH WE# (CE#) Pulse Width 1,4,5 45 50 50 60 70 70 ns W4 tDVWH / tDVEH Data Setup to WE# (CE#) Going High 2,4,5 40 40 50 50 60 60 ns W5 tAVWH / tAVEH Address Setup to WE# (CE#) Going High 2,4,5 50 50 50 60 70 70 ns W6 tWHEH / tEHWH CE# (WE#) Hold Time from WE# (CE#) High 4,5 0 0 0 0 0 0 ns W7 tWHDX / tEHDX Data Hold Time from WE# (CE#) High 2,4,5 0 0 0 0 0 0 ns W8 tWHAX / tEHAX Address Hold Time from WE# (CE#) High 2,4,5 0 0 0 0 0 0 ns W9 tWHWL / tEHEL WE# (CE#) Pulse Width High 1,4,5 25 30 30 30 30 30 ns W10 tVPWH / tVPEH VPP Setup to WE# (CE#) Going High 3,4,5 200 200 200 200 200 200 ns W11 tQVVL VPP Hold from Valid SRD 3,4 0 0 0 0 0 0 ns W12 tBHWH / tBHEH WP# Setup to WE# (CE#) Going High 3,4 0 0 0 0 0 0 ns W13 tQVBL WP# Hold from Valid SRD 3,4 0 0 0 0 0 0 ns W14 tWHGL WE# High to OE# Going Low 3,4 30 30 30 30 30 30 ns Notes: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). So tWP = tWLWH = tELEH = tWLEH = tELWH. 2. 3. 4. 5. Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). So tWPH = tWHWL = tEHEL = tWHEL = tEHWL. Refer to Table 27 "Bus Operations(1)" on page 51 for valid AIN or DIN. Sampled, but not 100% tested. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate. See Figure 11 "Write Operations Waveform" on page 45. 18 Aug 2005 42 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 21. Write Operations--32-Mbit Density Density 32 Mbit Product # Sym 70 ns 90 ns 3.0 V - 3.6 V6 Parameter 100 ns 110 ns 90 100 Unit VCC 2.7 V - 3.6 V 70 90 100 110 Note Min Min Min Min Min Min W1 tPHWL / tPHEL RP# High Recovery to WE# (CE#) Going Low 4,5 150 150 150 150 150 150 ns W2 tELWL / tWLEL CE# (WE#) Setup to WE# (CE#) Going Low 4,5 0 0 0 0 0 0 ns W3 tWLWH / tELEH WE# (CE#) Pulse Width 1,4,5 45 60 60 70 70 70 ns W4 tDVWH / tDVEH Data Setup to WE# (CE#) Going High 2,4,5 40 40 50 60 60 60 ns W5 tAVWH / tAVEH Address Setup to WE# (CE#) Going High 2,4,5 50 60 60 70 70 70 ns W6 tWHEH / tEHWH CE# (WE#) Hold Time from WE# (CE#) High 4,5 0 0 0 0 0 0 ns W7 tWHDX / tEHDX Data Hold Time from WE# (CE#) High 2,4,5 0 0 0 0 0 0 ns W8 tWHAX / tEHAX Address Hold Time from WE# (CE#) High 2,4,5 0 0 0 0 0 0 ns W9 tWHWL / tEHEL WE# (CE#) Pulse Width High 1,4,5 25 30 30 30 30 30 ns W10 tVPWH / VPP Setup to WE# (CE#) Going High tVPEH 3,4,5 200 200 200 200 200 200 ns W11 tQVVL VPP Hold from Valid SRD 3,4 0 0 0 0 0 0 ns W12 tBHWH / tBHEH WP# Setup to WE# (CE#) Going High 3,4 0 0 0 0 0 0 ns W13 tQVBL WP# Hold from Valid SRD 3,4 0 0 0 0 0 0 ns W14 tWHGL WE# High to OE# Going Low 3,4 30 30 30 30 30 30 ns Notes: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). So tWP = tWLWH = tELEH = tWLEH = tELWH. 2. 3. 4. 5. 6. Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). So tWPH = tWHWL = tEHEL = tWHEL = tEHWL. Refer to Table 27 "Bus Operations(1)" on page 51 for valid AIN or DIN. Sampled, but not 100% tested. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate. See Figure 11 "Write Operations Waveform" on page 45. VCCMax = 3.3 V for 32-Mbit 0.25 Micron product. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 43 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 22. Write Operations--64-Mbit Density # Symbol Parameter VCC Density 64 Mbit Product 80 ns 2.7 V - 3.6 V Note Min Unit W1 tPHWL / tPHEL RP# High Recovery to WE# (CE#) Going Low 4,5 150 ns W2 tELWL / tWLEL CE# (WE#) Setup to WE# (CE#) Going Low 4,5 0 ns W3 tWLWH / tELEH WE# (CE#) Pulse Width 1,4,5 60 ns W4 tDVWH / tDVEH Data Setup to WE# (CE#) Going High 2,4,5 40 ns W5 tAVWH / tAVEH Address Setup to WE# (CE#) Going High 2,4,5 60 ns W6 tWHEH / tEHWH CE# (WE#) Hold Time from WE# (CE#) High 4,5 0 ns W7 tWHDX / tEHDX Data Hold Time from WE# (CE#) High 2,4,5 0 ns W8 tWHAX / tEHAX Address Hold Time from WE# (CE#) High 2,4,5 0 ns W9 tWHWL / tEHEL WE# (CE#) Pulse Width High 1,4,5 30 ns W10 tVPWH / tVPEH VPP Setup to WE# (CE#) Going High 3,4,5 200 ns VPP Hold from Valid SRD 3,4 0 ns WP# Setup to WE# (CE#) Going High 3,4 0 ns W11 tQVVL W12 tBHWH / tBHEH W13 tQVBL WP# Hold from Valid SRD 3,4 0 ns W14 tWHGL WE# High to OE# Going Low 3,4 30 ns Notes: 1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever goes high first). So tWP = tWLWH = tELEH = tWLEH = tELWH. 2. 3. 4. 5. Similarly, write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). So tWPH = tWHWL = tEHEL = tWHEL = tEHWL. Refer to Table 27 "Bus Operations(1)" on page 51 for valid AIN or DIN. Sampled, but not 100% tested. See Figure 12 "AC Input/Output Reference Waveform" on page 46 for timing measurements and maximum allowable input slew rate. See Figure 11 "Write Operations Waveform" on page 45. 18 Aug 2005 44 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Figure 11. Write Operations Waveform W5 W8 Address [A] W6 CE# [E] W3 W2 W9 WE# [W] OE# [G] W4 W7 Data [D/Q] W1 RP# [P] W10 Vpp [V] 8.3 Erase and Program Timing Table 23. Erase and Program Timing Symbol VPP 1.65 V-3.6 V 11.4 V-12.6 V Note Typ Max Typ Max Unit Parameter tBWPB 4-KW Parameter Block Word Program Time 1, 2, 3 0.10 0.30 0.03 0.12 s tBWMB 32-KW Main Block Word Program Time 1, 2, 3 0.8 2.4 0.24 1 s Word Program Time for 0.13 and 0.18 Micron Product 1, 2, 3 12 200 8 185 s Word Program Time for 0.25 Micron Product 1, 2, 3 22 200 8 185 s tWHQV2 / tEHQV2 4-KW Parameter Block Erase Time 1, 2, 3 0.5 4 0.4 4 s tWHQV3 / tEHQV3 32-KW Main Block Erase Time 1, 2, 3 1 5 0.6 5 s tWHRH1 / tEHRH1 Program Suspend Latency 1,3 5 10 5 10 s tWHRH2 / tEHRH2 Erase Suspend Latency 1,3 5 20 5 20 s tWHQV1 / tEHQV1 Notes: 1. Typical values measured at TA= +25 C and nominal voltages. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 45 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 8.4 AC I/O Test Conditions Figure 12. AC Input/Output Reference Waveform VCCQ Test Points VCCQ/2 Input VCCQ/2 Output 0V Note: Figure 13. Input timing begins, and output timing ends, at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst-case speed conditions are when VCC = VCCMin. Transient Equivalent Testing Load Circuit VCCQ R1 Device Under Test Out CL Note: Table 24. See Table 24 for component values. Test Configuration Component Values for Worst Case Speed Conditions Test Configuration VCCQMin Standard Test Note: 8.5 R2 C L (pF) R1 (k) R2 (k) 50 25 25 CL includes jig capacitance. Device Capacitance TA = 25 C, f = 1 MHz Table 25. Device Capacitance Symbol CIN COUT 18 Aug 2005 46 Parameter Typ Max Unit Condition Input Capacitance 6 8 pF VIN = 0.0 V Output Capacitance 8 12 pF VOUT = 0.0 V Sampled, not 100% tested. Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 9.0 Power and Reset Specifications 9.1 Power-Up/Down Characteristics To prevent any condition that might result in a spurious write or erase operation, power-up VCC and V CCQ together. Conversely, V CC and VCCQ must power-down together. Also power-up VPP with or slightly after VCC. Conversely, VPP must power-down with or slightly before VCC. If VCCQ and/or VPP are not connected to the VCC supply, then VCC must attain V CCMin before applying VCCQ and VPP. Device inputs must not be driven before supply voltage = VCCMin. Power supply transitions must occur only when RP# is low. 9.1.1 RP# Connected to System Reset Use RP# during system reset with automated program/erase devices, because the system expects to read from the flash memory when the system exits reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization does not occur, because the flash memory might be providing status information instead of array data. Connecting RP# to the system CPU RESET# signal to allow proper CPU/flash initialization after a system reset. System designers must guard against spurious writes when VCC voltages are above VLKO. Because both WE# and CE# must be low for a command write, driving either signal to VIH inhibits writes to the flash memory device. The CUI architecture provides additional protection, because memory contents can be altered only after successful completion of the two-step command sequences. The flash memory device is also disabled until RP# is brought to V IH, regardless of the state of its control inputs. By holding the device in reset (RP# connected to system POWERGOOD) during power-up/down, invalid bus conditions during power-up can be masked, providing yet another level of memory protection. 9.1.2 VCC, VPP, and RP# Transitions The CUI latches commands as issued by system software, and is not altered by V PP or CE# transitions or WSM actions. The CUI default state upon power-up, after exit from reset mode or after VCC transitions above V LKO (Lockout voltage), is read-array mode. After any program or Block-Erase operation is complete (even after VPP transitions down to VPPLK), the CUI must be reset to read-array mode, using the Read Array command if access to the flash-memory array is required. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 47 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 9.2 Reset Specifications Table 26. Reset Specifications VCC 2.7 V - 3.6 V Symbol Parameter Min Unit Notes ns 1, 2 Max tPLPH RP# Low to Reset during Read (If RP# is tied to VCC, this specification is not applicable) tPLRH1 RP# Low to Reset during Block Erase 22 s 3 tPLRH2 RP# Low to Reset during Program 12 s 3 100 Notes: 1. If tPLPH is < 100 ns, the device can still reset, but reset is not guaranteed. 2. If RP# is asserted while a Block Erase or Word Program operation is not executing, the reset completes within 100 ns. 3. Sampled, but not 100% tested. Figure 14. Deep Power-Down/Reset Operations Waveforms RP# (P) VIH VIL t PLPH (A) Reset during Read Mode t PHQV t PHWL t PHEL Abort Complete t PLRH RP# (P) VIH t PHQV t PHWL t PHEL V IL t PLPH (B) Reset during Program or Block Erase, t PLPH < t PLRH Abort Deep Complete PowerDown RP# (P) VIH V IL t PLRH t PHQV t PHWL t PHEL t PLPH (C) Reset Program or Block Erase, t PLPH > t PLRH 18 Aug 2005 48 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 9.3 Power Supply Decoupling Flash memory power-switching characteristics require careful device decoupling. System designers must consider the following three supply current issues: 1. Standby current levels (ICCS). 2. Read current levels (ICCR). 3. Transient peaks produced by falling and rising edges of CE#. Transient current magnitudes depend on the device output capacitive and inductive loading. Two-line control and proper decoupling capacitor selection suppresses these transient voltage peaks. Each flash device must have a 0.1 F ceramic capacitor connected between each V CC and GND, and between its VPP and GND. These high-frequency, inherently low-inductance capacitors must be placed as close as possible to the package leads. 9.4 Power Consumption Intel(R) flash memory devices use a tiered approach to power savings that can significantly reduce overall system power consumption. The Automatic Power Savings (APS) feature reduces power consumption when the flash memory device is selected but idle. If CE# is deasserted, the flash memory device enters its standby mode, where current consumption is even lower. The combination of these features can minimize memory power consumption, and therefore minimize overall system power consumption. 9.4.1 Active Power When CE# is at a logic-low level and RP# is at a logic-high level, the flash memory device is in the active mode. Refer to the DC Characteristic tables for ICC current values. Active power is the largest contributor to overall system power consumption. Minimizing the active current can profoundly affect system power consumption, especially for battery-operated devices. 9.4.2 Automatic Power Savings (APS) Automatic Power Savings provides low-power operation during read mode. After data is read from the flash memory array and the address lines are quiescent, APS circuitry places the flash memory device in a mode where typical current is comparable to ICCS. The flash memory stays in this static state with outputs valid until a new location is read. 9.4.3 Standby Power When CE# is at a logic-high level (VIH) and the flash memory device is in read mode, the flash memory is in standby mode. This mode disables much of the device circuitry, and substantially reduces power consumption. Outputs are placed in a high-impedance state independent of the status of the OE# signal. If CE# transitions to a logic-high level during Erase or Program operations, the flash memory device continues to perform the operation and consume corresponding active power until the operation is completed. System engineers must analyze the breakdown of standby time versus active time and quantify the respective power consumption in each mode for their specific application. This approach provides a more accurate measure of application-specific power and energy requirements. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 49 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 9.4.4 Deep Power-Down Mode The deep power-down mode is activated when RP# = VIL (GND 0.2 V). During read modes, RP# going low deselects the flash memory and places the outputs in a high-impedance state. Recovery from deep power-down mode requires a minimum time of tPHQV (see "AC Read Characteristics" on page 37). During program or erase modes, RP# transitioning low aborts the in-progress operation. The memory contents of the address being programmed or the block being erased are no longer valid, because the abort compromises data integrity. During deep power-down, all internal circuits switch to a low-power savings mode (RP# transitioning to V IL or turning off power to the flash memory device clears the Status Register). 10.0 Operations Overview Flash memory combines EEPROM functionality with in-circuit electrical program-and-erase capability. The B3 flash memory device family uses a Command User Interface (CUI) and automated algorithms to simplify Program and Erase operations. The CUI allows for 100% CMOS-level control inputs and fixed power supplies during erasure and programming. When V PP < VPPLK, the flash memory device executes only the following commands successfully: * * * * Read Array Read Status Register Clear Status Register Read Identifier The flash memory device provides standard EEPROM read, standby, and Output-Disable operations. Manufacturer identification and device identification data can be accessed through the CUI. All functions that alter memory contents (program and erase) are accessible through the CUI. The internal Write State Machine (WSM) completely automates Program and Erase operations, while the CUI signals the start of an operation and the Status Register reports status. The CUI handles the WE# interface to the data and address latches, and system status requests during WSM operation. 18 Aug 2005 50 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 10.1 Bus Operations The B3 flash memory device performs read, program, and erase in-system operations through the local CPU or microcontroller. All bus cycles to or from the flash memory conform to standard microcontroller bus cycles. Four control pins dictate the data flow in and out of the flash memory device: * * * * CE# OE# WE# RP# Table 27 summarizes these bus operations. Table 27. Bus Operations(1) Mode Read (Array, Status, or Identifier) Output Disable Standby Note RP# CE# OE# WE# DQ0-7 DQ8-15 2-4 VIH VIL VIL VIH DOUT DOUT 2 VIH VIL VIH VIH High Z High Z 2 VIH VIH X X High Z High Z Reset 2, 7 VIL X X X High Z High Z Write 2, 5-7 VIH VIL VIH VIL DIN DIN Notes: 1. 8-bit devices use only DQ[0:7]. 16-bit devices use DQ[0:15]. 2. X must be VIL, VIH for control pins and addresses. 3. See DC Characteristics for VPPLK, VPP1, VPP2, VPP3, VPP4 voltages. 4. Manufacturer and device codes can also be accessed in read identifier mode (A1-A21 = 0). See Table 29. 5. Refer to Table 30 for valid DIN during a Write operation. 6. To program or erase the lockable blocks, hold WP# at VIH. 7. RP# must be at GND 0.2 V to meet the maximum deep power-down current specified. 10.1.1 Read The B3 flash memory device provides four read modes: * * * * read array read identifier read status read query These modes are accessible independently of the VPP voltage. Issue the appropriate Read Mode command to the CUI to enter the corresponding mode. Upon initial device power-up or after exit from reset, the flash memory device automatically defaults to read-array mode. CE# and OE# must be driven active to obtain data at the outputs. * CE# is the device selection control. When active, CE# enables the flash memory device. * OE# is the data output control, and drives the selected memory data onto the I/O bus. For all read modes, WE# and RP# must be at VIH. Figure 10 on page 40 illustrates a read cycle. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 51 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 10.1.2 Output Disable When OE# is at a logic-high level (VIH), the flash memory device outputs are disabled. Output pins are placed in a high-impedance state. 10.1.3 Standby Deselecting the flash memory device by bringing CE# to a logic-high level (VIH) places the device in standby mode. Standby mode substantially reduces device power consumption, without any latency for subsequent read accesses. In standby mode, outputs are placed in a high-impedance state independent of OE#. If deselected during Program or Erase operation, the flash memory device continues to consume active power until the Program or Erase operation is complete. 10.1.4 Deep Power-Down / Reset From read mode, RP# at V IL for time tPLPH does the following: * * * * * Deselects the flash memory. Places output drivers in a high-impedance state. Turns off all internal circuits. After a return from reset, a time tPHQV is required until the initial read-access outputs are valid. After a return from reset, a delay (tPHWL or tPHEL) is required before a write can be initiated. After this wake-up interval, normal operation is restored. The CUI resets to read-array mode, and the Status Register is set to 80H. Figure 14 "Deep Power-Down/Reset Operations Waveforms" on page 48 (A) illustrates this case. If RP# is taken low for time tPLPH during a Program or Erase operation, the operation aborts. The memory contents at the aborted location (for a program) or block (for an erase) are no longer valid, because the data might be partially erased or written. The abort process uses the following sequence: 1. When RP# goes low, the flash memory device shuts down the operation in progress, a process that takes time tPLRH to complete. 2. After this time tPLRH, the flash memory device either resets to read-array mode (if RP# has gone high during tPLRH, see Figure 14 "Deep Power-Down/Reset Operations Waveforms" on page 48 (B)), or enters reset mode (if RP# is still logic low after tPLRH, see Figure 14 "Deep Power-Down/Reset Operations Waveforms" on page 48 (C)). 3. In both cases, after returning from an aborted operation, the relevant time tPHQV or tPHWL/ tPHEL must elapse before initiating a Read or Write operation, as discussed in the previous paragraph. However, in this case, these delays are referenced to the end of tPLRH rather than when RP# goes high. As with any automated device, RP# must be asserted during system reset. When the system finishes reset, the processor expects to read from the flash memory. Automated flash memories provide status information when read during program or Block-Erase operations. If a CPU reset occurs with no flash memory reset, proper CPU initialization cannot occur, because the flash memory might be providing status information instead of array data. Intel(R) Flash memories allow proper CPU initialization after a system reset, using the RP# input. In this application, RP# is controlled by the same RESET# signal that resets the system CPU. 18 Aug 2005 52 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 10.1.5 Write A write occurs when both CE# and WE# are low and OE# is high. Commands are written to the Command User Interface (CUI) using standard microprocessor write timings to control flash memory operations. The CUI does not occupy an addressable memory location. The address and data buses are latched on the rising edge of the second WE# or CE# pulse, whichever occurs first. Table 30 shows the available commands, and Appendix A provides detailed information about moving between the different modes of operation using CUI commands. Two commands modify array data: * Program (40H). * Erase (20H). Writing either of these commands to the internal Command User Interface (CUI) initiates a sequence of internally timed functions that culminate in the completion of the requested task (unless that operation is aborted by either RP# being driven to V IL for tPLRH or an appropriate Suspend command). 11.0 Operating Modes The flash memory device has four read modes: * * * * read array read identifier read status read query See Figure 1 "B3 Architecture Block Diagram" on page 10). The flash memory device also has two write modes: * program * block erase Three additional modes are available only during suspended operations: * erase suspend to program * erase suspend to read * program suspend to read Table 28 "Command Codes and Descriptions" on page 54 summarizes the commands used to reach these modes. Appendix A, "Write State Machine Current/Next States," is a comprehensive chart showing the state transitions. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 53 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 11.1 Read Array When RP# transitions from VIL (reset) to VIH, the flash memory device defaults to read-array mode and responds to the read-control inputs (CE#, address inputs, and OE#) without any additional CUI commands. When the flash memory device is in read-array mode, four control signals control data output: * * * * WE# must be logic high (VIH) CE# must be logic low (VIL) OE# must be logic low (VIL) RP# must be logic high (VIH) In addition, the address of the preferred location must be applied to the address pins. If the flash memory device is not in read-array mode, such as after a Program or Erase operation, the Read Array command (FFH) must be written to the CUI before array reads can occur. Table 28. Command Codes and Descriptions (Sheet 1 of 2) Code Device Mode Description 00, 01, 60, 2F, C0, 98 Invalid/ Reserved Unassigned commands that must not be used. Intel reserves the right to redefine these codes for future functions. FF Read Array Places the flash memory device in read-array mode, so that array data is output on the data pins. 40 Program Set-Up A two-cycle command. * The first cycle prepares the CUI for a program operation. * The second cycle latches addresses and data information, and initiates the WSM to execute the program algorithm. The flash memory device outputs Status Register data when CE# or OE# is toggled. To read array data, a Read Array command is required after programming. See Section 11.4. 10 Alternate Program Set-Up (See 40H/Program Set-Up) 20 Erase Set-Up Erase Confirm D0 Program / Erase Resume 18 Aug 2005 54 Prepares the CUI for the Erase Confirm command. If the next command is not an Erase Confirm command, then the CUI does the following: 1. Sets both SR.4 and SR.5 of the Status Register to 1. 2. Places the flash memory device into the read-Status Register mode. 3. Waits for another command. See Section 11.5, "Erase Mode" on page 58. If the previous command was an Erase Set-Up command, then the CUI closes the address and data latches, and begins erasing the block indicated on the address pins. During erase, the flash memory device responds only to the Read Status Register and Erase Suspend commands. The device outputs Status Register data when CE# or OE# is toggled. If a Program or Erase operation was previously suspended, this command resumes that operation. Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 28. Code Command Codes and Descriptions (Sheet 2 of 2) Device Mode Description B0 Program / Erase Suspend Issuing this command suspends the currently executing Program/Erase operation. To indicate when the operation has been successfully suspended, the Status Register sets either the program suspend (SR.2) or erase suspend (SR.6), and sets the WSM status bit (SR.7) to 1 (ready). The WSM continues to idle in the SUSPEND state, regardless of the state of all input-control pins except RP#, which immediately shuts down the WSM and the remainder of the device, if it is driven to VIL. See Section 11.4.1, "Suspending and Resuming Programming" on page 58 and Section 11.4.1, "Suspending and Resuming Programming" on page 58. 70 Read Status Register This command places the flash memory device into Read-Status Register mode. Reading the device outputs the contents of the Status Register, regardless of the address presented to the device. The flash memory device automatically enters this mode after a Program or Erase operation is initiated. See Section 11.3, "Read Status Register" on page 56. 50 Clear Status Register The WSM can set the block-lock status (SR.1), VPP status (SR.3), program status (SR.4), and erase status (SR.5) bits in the Status Register to 1. However, the WSM cannot clear these bits to 0. Issuing this command clears these bits to 0. 90 Read Identifier Note: Datasheet Places the flash memory device into the intelligent-identifier-read mode, so that reading the device outputs the manufacturer and device codes (A0 = 0 for manufacturer, A0 = 1 for the device; all other address inputs must be 0). See Section 11.2, "Read Identifier" on page 56. See Chapter 14.0, "Write State Machine Current/Next States," for mode transition information. Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 55 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 11.2 Read Identifier To read the manufacturer and device codes, the flash memory device must be in read-identifier mode, which can be reached by writing the Read Identifier command (90H). As shown in Table 29, once in read-identifier mode: * A0 = 0 outputs the manufacturer identification code. * A0 = 1 outputs the device identifier. Note: A1-A21 = 0. To return to read-array mode, write the Read-Array command (FFH). Table 29. Read Identifier Table Device Identifier Size Mfr. ID 28F004B3 -T (Top Boot) -B (Bottom Boot) D4H D5H 8894H 8895H 0089H 28F400B3 28F008B3 D2H D3H 8892H 8893H 28F016B3 D0H D1H 28F160B3 8890H 8891H 8896H 8897H 8898H 8899H 28F800B3 28F320B3 28F640B3 11.3 0089H 0089H Read Status Register The flash memory device Status Register indicates when a Program or Erase operation is complete, and the success or failure of that operation. * To read the Status Register, issue the Read Status Register (70H) command to the CUI. This command causes all subsequent Read operations to output data from the Status Register until another command is written to the CUI. * To return to reading from the array, issue the Read Array (FFH) command. The Status Register bits are output on DQ0-DQ7. The upper byte, DQ8-DQ15, outputs 00H during a Read Status Register command. The contents of the Status Register are latched on the falling edge of OE# or CE#, which prevents possible Bus errors that might occur if Status Register contents change while being read. CE# or OE# must be toggled with each subsequent status read, or the Status Register does not indicate completion of a Program or Erase operation. When the WSM is active, SR.7 indicates the status of the WSM. The remaining bits in the Status Register indicate whether the WSM was successful in performing the preferred operation (see Table 31 on page 60). 18 Aug 2005 56 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 11.3.1 Clearing the Status Register The WSM sets status bits 1 through 7 to 1, and clears bits 2, 6, and 7 to 0. However, the WSM cannot clear status bits 1 or 3 through 5 to 0. Because bits 1, 3, 4, and 5 indicate various error conditions, these bits can be cleared only through the Clear Status Register (50H) command. By allowing the system software to control the resetting of these bits, several operations can be performed (such as cumulatively programming several addresses or erasing multiple blocks in sequence) before reading the Status Register to determine if an error occurred during that series. Clear the Status Register before beginning another command or sequence. Note: The Read Array command must be issued before data can be read from the flash memory array. 11.4 Program Mode Programming is executed using a two-write sequence. 1. The Program Setup command (40H) is written to the CUI. 2. A second write specifies the address and data to program. The WSM executes a sequence of internally timed events to program preferred bits of the addressed location. The WSM then verifies that the bits are sufficiently programmed. Programming the memory changes specific bits within an address location to 0. If users attempt to program 1 instead of 0, the memory cell contents do not change and no error occurs. The Status Register indicates the programming status: while the program sequence executes, status bit 7 is 0. To poll the Status Register, toggle either CE# or OE#. While programming, the only valid commands are: * Read Status Register * Program Suspend * Program Resume When programming is complete, the program-status bits must be checked. * If the programming operation was unsuccessful, SR.4 is set, indicating a program failure. * If SR.3 is set, then VPP was not within acceptable limits, and the WSM did not execute the program command. * If SR.1 is set, a program operation was attempted on a locked block and the operation aborted. Clear the Status Register before attempting the next operation. Any CUI instruction can follow after programming is completed; however, to prevent inadvertent Status Register reads, be sure to reset the CUI to read-array mode. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 57 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 11.4.1 Suspending and Resuming Programming The Program Suspend command halts the in-progress program operation to read data from another flash memory location. 1. After the programming process starts, writing the Program Suspend command to the CUI requests that the WSM suspend the program sequence (at predetermined points in the program algorithm). 2. The flash memory device continues to output Status Register data after the Program Suspend command is written. 3. Polling SR.7 and SR.2 determines when the program operation has been suspended (both are set to 1). tWHRH1/tEHRH1 specifies the program- suspend latency. 4. A Read Array command can now be written to the CUI to read data from blocks other than the suspended block. The only other valid commands while program is suspended are: -- Read Status Register -- Read Identifier -- Program Resume 5. After the Program Resume command is written to the flash memory, the WSM continues with the program process, and Status Register bits SR.2 and SR.7 are automatically cleared. 6. After the Program Resume command is written, the flash memory device automatically outputs Status Register data when read. See Appendix B, "Program and Erase Flowcharts." Note: VPP must remain at the same V PP level used for program while in program-suspend mode. RP# must also remain at VIH. 11.5 Erase Mode To erase a block: 1. Write the Erase Set-up and Erase Confirm commands to the CUI, along with an address identifying the block to be erased. This address is latched internally when the Erase Confirm command is issued. Block erasure sets all bits within the block to 1. Only one block can be erased at a time. 2. The WSM executes a sequence of internally timed events : a. programs all bits within the block to 0. b. Erases all bits within the block to 1. c. Verifies that all bits within the block are sufficiently erased. While the erase executes, status bit 7 is 0. 18 Aug 2005 58 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 3. When the Status Register indicates that erasure is complete, check the erase-status bit to verify that the Erase operation was successful. -- If the Erase operation was unsuccessful, SR.5 of the Status Register is set to 1, indicating an erase failure. -- If VPP was not within acceptable limits after the Erase Confirm command was issued, the WSM does not execute the erase sequence. Instead, SR.5 is set to indicate an Erase error, and SR.3 is set to 1, indicating that the VPP supply voltage was not within acceptable limits. 4. After an Erase operation, clear the Status Register (50H) before attempting the next operation. Any CUI instruction can follow after erasure is completed. 5. To prevent inadvertent status- register reads, place the flash memory device in read-array mode after the erase is complete. 11.5.1 Suspending and Resuming Erase Because an Erase operation requires on the order of seconds to complete, an Erase Suspend command is provided. Erase Suspend interrupts an erase sequence to read data from--or program data to-- another block in memory. After the erase sequence is started, writing the Erase Suspend command to the CUI requests that the WSM pauses the erase sequence at a predetermined point in the erase algorithm. Note: The Status Register will indicates if/when the Erase operation has been suspended. * A Read Array/Program command can now be written to the CUI, to read data from/ program data to blocks other than the one currently suspended. * The Program command can subsequently be suspended to read yet another array location. The only valid commands while Erase is suspended are: * * * * * Erase Resume Program Read Array Read Status Register Read Identifier During erase-suspend mode, to place the flash memory device in a pseudo-standby mode, set CE# to VIH, which reduces active current consumption. Erase Resume continues the erase sequence when CE# = VIL. As with the end of a standard Erase operation, the Status Register must be read and cleared before the next instruction is issued. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 59 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 30. Command Bus Definitions (1,4) First Bus Cycle Command Notes Second Bus Cycle Oper Addr Data Oper Addr Data Write X FFH Write X 90H Read IA ID Read Status Register Write X 70H Read X SRD Clear Status Register Write X X 40H / 10H 50H Write Write PA PD Block Erase/Confirm Write X 20H Write BA D0H Program/Erase Suspend Write X B0H Program/Erase Resume Write X D0H Read Array Read Identifier 2 Program 3 Notes: PA: Program Address PD: Program Data BA: Block Address IA: Identifier Address ID: Identifier Data SRD: Status Register Data 1. 2. Bus operations are defined in Table 27. Following the Intelligent Identifier command, two Read operations access manufacturer and device codes. - A 0 = 0 for manufacturer code. - A0 = 1 for device code. - A1-A21 = 0. Either the 40H or 10H command is valid. The standard is 40H. When writing commands to the flash memory device, the upper data bus [DQ 8-DQ15] must be either VIL or VIH, to minimize current draw. 3. 4. Table 31. Status Register Bit Definition WSMS ESS ES PS VPPS PSS BLS R 7 6 5 4 3 2 1 0 Bits NOTES: SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy Check Write State Machine bit first to determine word program or block-erase completion, before checking program or erasestatus bits. SR.6 = ERASE-SUSPEND STATUS (ESS) 1 = Erase Suspended 0 = Erase In Progress/Completed When erase suspend is issued, WSM halts execution and sets both WSMS and ESS bits to 1. ESS bit remains set at 1 until an Erase Resume command is issued. SR.5 = ERASE STATUS (ES) 1 = Error In Block Erasure 0 = Successful Block Erase When this bit is set to 1, WSM has applied the maximum number of erase pulses to the block and is still unable to verify successful block erasure. SR.4 = PROGRAM STATUS (PS) 1 = Error in Word Program 0 = Successful Word Program When this bit is set to 1, WSM has attempted but failed to program a word. 18 Aug 2005 60 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Bits NOTES: SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK The VPP status bit does not continuously indicate the VPP level. The WSM interrogates the VPP level only after the Program or Erase command sequences are entered, and informs the system if VPP has not been switched on. The VPP is also checked before the WSM verifies the operation. The VPP status bit is not guaranteed to report accurate feedback between VPPLK max and VPP1 min or between VPP1 max and VPP4 min. SR.2 = PROGRAM SUSPEND STATUS (PSS) 1 = Program Suspended 0 = Program in Progress/Completed When program suspend is issued, WSM halts execution and sets both WSMS and PSS bits to 1. The PSS bit remains set to 1 until a Program Resume command is issued. SR.1 = BLOCK LOCK STATUS 1 = Program/Erase attempted on locked block; Operation aborted 0 = No operation to locked blocks If a Program or Erase operation is attempted to one of the locked blocks, the WSM sets this bit. The operation specified is aborted and the flash memory device returns to read status mode. SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) This bit is reserved for future use and must be masked out when polling the Status Register. Note: A Command Sequence Error is indicated when SR.4, SR.5, and SR.7 are set. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 61 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 12.0 Block Locking The B3 flash memory device architecture features two hardware-lockable parameter blocks. 12.1 WP# = VIL for Block Locking The lockable blocks are locked when WP# = V IL; any program or Erase operation to a locked block results in an error, which is reflected in the Status Register: * For top configuration, the top two parameter blocks are lockable: -- blocks #133 and #134 for 64 Mbit -- blocks #69 and #70 for 32 Mbit -- blocks #37 and #38 for 16 Mbit -- blocks #21 and #22 for 8 Mbit -- blocks #13 and #14 for 4 Mbit * For the bottom configuration, the bottom two parameter blocks are lockable. These are blocks #0 and #1 for 4, 8 , 16, 32, and 64 Mbit. Unlocked blocks can be programmed or erased normally (unless V PP is below VPPLK). 12.2 WP# = VIH for Block Unlocking WP# = VIH unlocks all lockable blocks. These blocks can now be programmed or erased. Note: RP# does not override WP# locking for the B3 flash memory device, as in previous Boot Block devices. * WP# controls all block locking. * VPP provides protection against spurious writes. Table 32 defines the write- protection methods. Table 32. 18 Aug 2005 62 Write-Protection Truth Table for the B3 Device Family VPP WP# RP# Write Protection Provided X X VIL All Blocks Locked VIL X VIH All Blocks Locked VPPLK VIL VIH Lockable Blocks Locked VPPLK VIH VIH All Blocks Unlocked Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 13.0 VPP Program and Erase Voltages TheB3 flash memory device products provide in-system programming and erase at 2.7 V. For customers requiring fast programming in their manufacturing environment, the B3 flash memory device includes an additional low-cost 12-V programming feature. The 12-V VPP mode enhances programming performance during the short period of time typically found in manufacturing processes. However, this mode is not intended for extended use. 12 V can be applied to V PP during program and Erase operations for a maximum of 1000 cycles on the main blocks, and 2500 cycles on the parameter blocks. VPP can be connected to 12 V for a total of 80 hours maximum. Warning: Stressing the flash memory device beyond these limits might cause permanent damage. During Read operations or idle times, V PP can be tied to a 5-V supply. For Program and Erase operations, a 5-V supply is not permitted. The V PP must be supplied with either 2.7 V to 3.6 V or 11.4 V to 12.6 V during Program and Erase operations. 13.1 VPP = VIL for Complete Protection The VPP programming voltage can be held low for complete write protection of all blocks in the flash memory device. When VPP is below VPPLK, any Program or Erase operation results in an error, prompting the corresponding SR.3 to be set. 14.0 Additional Information Order Number Document/Tool 297948 Intel(R) Advanced Boot Block Flash Memory Family Specification Update 292199 AP-641 Achieving Low Power with the 3 Volt Advanced Boot Block Flash Memory 292200 AP-642 Designing for Upgrade to the 3 Volt Advanced Boot Block Flash Memory Note 2 3 Volt Advanced Boot Block Algorithms (`C' and assembly) http://developer.intel.com/design/flash/swtools Contact your Intel Representative 297874 Intel(R) Flash Data Integrator (IFDI) Software Developer's Kit IFDI Interactive: Play with Intel(R) Flash Data Integrator on Your PC Notes: 1. Call the Intel Literature Center at (800) 548-4725 to request Intel documentation. International customers must contact their local Intel or distribution sales office. 2. Visit the Intel home page at http://www.Intel.com or http://developer.intel.com for technical documentation and tools. 3. For the most current information about Intel(R) Advanced Boot Block Flash memory and Intel(R) Advanced+ Boot Block Flash memory, visit http://developer.intel.com/design/flash/ Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 63 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Appendix A Write State Machine Current/Next States Table 33. Write State Machine (Sheet 1 of 2) Command Input (and Next State) Current State SR.7 Data When Read Read Array (FFH) Program Setup (10/40H) Erase Setup (20H) Read Array "1" Array Read Array Program Setup Erase Setup Read Status "1" Status Read Array Program Setup Read Identifier "1" Identifier Read Array Program Setup Prog. Setup "1" Status Program (continue) Program Suspend to Read Status Program Suspend to Read Array "0" "1" "1" Prog/Ers Suspend (B0H) Prog/Ers Resume (D0H) Read Status (70H) Clear Status (50H) Read Identifier. (90H) Read Array Read Status Read Array Read Identifier Erase Setup Read Array Read Status Read Array Read Identifier Erase Setup Read Array Read Status Read Array Read Identifier Program (Command Input = Data to be Programmed) Prog. Sysop. to Rd. Status Program (continue) Status Program (continue) Status Prog. Susp. to Read Array Program Suspend to Read Array Program (continue ) Program Susp. to Read Array Program (continue ) Prog. Susp. to Read Status Prog. Susp. to Read Array Prog. Susp. to Read Identifier Array Prog. Susp. to Read Array Program Suspend to Read Array Program (continue ) Program Susp. to Read Array Program (continue ) Prog. Susp. to Read Status Prog. Sus. to Read Array Prog. Susp. to Read Identifier Program Suspend to Read Array Program (continue ) Program Susp. to Read Array Program (continue ) Prog. Susp. to Read Status Prog. Sus. to Read Array Prog. Susp. to Read Identifier Program Setup Read Status Read Array Read Identifier Prog. Susp. to Read Identifier "1" Identifier Prog. Susp. to Read Array Program (complete) "1" Status Read Array Erase Setup "1" Status Erase Cant. Error "1" Status Erase (continue) "0" Status 18 Aug 2005 64 Erase Confirm (D0H) Erase Setup Erase Command Error Read Array Program Setup Erase Setup Erase (continue) Read Array Erase (continue ) Erase Cant. Error Erase (continue ) Read Array Erase Sus. to Read Status Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Erase Command Error Read Status Read Array Read Identifier Erase (continue) Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 33. Write State Machine (Sheet 2 of 2) Command Input (and Next State) Current State Erase Suspend to Status Erase Susp. to Read Array SR.7 "1" "1" Data When Read Read Array (FFH) Program Setup (10/40H) Erase Setup (20H) Status Erase Susp. to Read Array Program Setup Erase Susp. to Read Array Array Erase Susp. to Read Array Program Setup Erase Susp. to Read Array Program Setup Erase Susp. to Read Array Program Setup Erase Setup Erase Susp. to Read Identifier "1" Identifier Erase Susp. to Read Array Erase (complete) "1" Status Read Array Datasheet Erase Confirm (D0H) Prog/Ers Suspend (B0H) Erase Erase Susp. to Read Array Erase Erase Susp. to Read Array Erase Erase Susp. to Read Array Prog/Ers Resume (D0H) Read Status (70H) Clear Status (50H) Read Identifier. (90H) Erase Erase Susp. to Read Status Erase Susp. to Read Array Ers. Susp. to Read Identifier Erase Erase Susp. to Read Status Erase Susp. to Read Array Ers. Susp. to Read Identifier Erase Erase Susp. to Read Status Erase Susp. to Read Array Ers. Susp. to Read Identifier Read Status Read Array Read Identifier Read Array Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 65 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Appendix B Program and Erase Flowcharts Figure 15. Program Flowchart Start Write 40H Bus Operation Command Write Program Setup Write Program Program Address/Data Data = 40H Data = Data to Program Addr = Location to Program Status Register Data Toggle CE# or OE# to Update Status Register Data Read Check SR.7 1 = WSM Ready 0 = WSM Busy Read Status Register Standby Repeat for subsequent programming operations. No SR.7 = 1? Comments SR Full Status Check can be done after each program or after a sequence of program operations. Yes Write FFH after the last program operation to reset device to read array mode. Full Status Check if Desired Program Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) Bus Operation 1 SR.3 = 0 VPP Range Error Programming Error 0 1 Comments Standby Check SR.3 1 = VPP Low Detect Standby Check SR.4 1 = VPP Program Error Standby Check SR.1 1 = Attempted Program to Locked Block - Program Aborted 1 SR.4 = SR.1 = Command SR.3 MUST be cleared, if set during a program attempt, before further attempts are allowed by the Write State Machine. Attempted Program to Locked Block - Aborted SR.1, SR.3 and SR.4 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are programmed before full status is checked. 0 Program Successful 18 Aug 2005 66 If an error is detected, clear the status register before attempting retry or other error recovery. Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Figure 16. Program Suspend/Resume Flowchart Start Bus Operation Command Write Program Suspend Data = B0H Addr = X Write Read Status Data = 70H Addr = X Comments Write B0H Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Write 70H Read Read Status Register 0 SR.7 = 1 Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.2 1 = Program Suspended 0 = Program Completed Write 0 SR.2 = Read Array Program Completed Read array data from block other than the one being programmed. Read 1 Write FFH Write Data = FFH Addr = X Program Resume Data = D0H Addr = X Read Array Data No Done Reading Yes Datasheet Write D0H Write FFH Program Resumed Read Array Data Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 67 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Figure 17. Block Erase Flowchart Start Bus Operation Write 20H Write D0H and Block Address Command Write Erase Setup Write Erase Confirm Data = D0H Addr = Within Block to Be Erased Status Register Data Toggle CE# or OE# to Update Status Register Data Read Read Status Register Suspend Erase Loop 0 SR.7 = No Suspend Erase Comments Data = 20H Addr = Within Block to Be Erased Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Yes Repeat for subsequent block erasures. Full Status Check can be done after each block erase or after a sequence of block erasures. 1 Full Status Check if Desired Write FFH after the last write operation to reset device to read array mode. Block Erase Complete FULL STATUS CHECK PROCEDURE Read Status Register Data (See Above) Bus Operation 1 SR.3 = 0 Command Standby Check SR.3 1 = V PP Low Detect Standby Check SR.4,5 Both 1 = Command Sequence Error Standby Check SR.5 1 = Block Erase Error Standby Check SR.1 1 = Attempted Erase of Locked Block - Erase Aborted VPP Range Error 1 SR.4,5 = Command Sequence Error 0 1 SR.5 = Block Erase Error Comments SR. 1 and 3 MUST be cleared, if set during an erase attempt, before further attempts are allowed by the Write State Machine. 0 1 SR.1 = 0 Attempted Erase of Locked Block - Aborted SR.1, 3, 4, 5 are only cleared by the Clear Staus Register Command, in cases where multiple bytes are erased before full status is checked. If an error is detected, clear the status register before attempting retry or other error recovery. Block Erase Successful 18 Aug 2005 68 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Figure 18. Erase Suspend/Resume Flowchart Start Bus Operation Command Comments Write Erase Suspend Data = B0H Addr = X Write Read Status Data = 70H Addr = X Write B0H Status Register Data Toggle CE# or OE# to Update Status Register Data Addr = X Write 70H Read Read Status Register 0 SR.7 = 1 Standby Check SR.7 1 = WSM Ready 0 = WSM Busy Standby Check SR.6 1 = Erase Suspended 0 = Erase Completed Write 0 SR.6 = Read Array Erase Completed Read array data from block other than the one being erased. Read 1 Write FFH Write Data = FFH Addr = X Erase Resume Data = D0H Addr = X Read Array Data No Done Reading Yes Datasheet Write D0H Write FFH Erase Resumed Read Array Data Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 69 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Appendix C Ordering Information Figure 19. Ordering Information T E2 8 F 3 2 0 B3 T C7 0 Package TE = 48- Lead TSOP GT = 48- Ball BGA * CSP GE = VF BGA CSP RC = Easy BGA PC = Pb Free Easy BGA PH = Pb Free VFBGA JS = Pb Free TSOP Access Speed (ns ) (70, 80 , 90, 100 , 110 ) Lithography A = 0.25 m C = 0.18 m D = 0.13 m Product line designator (R) for all Intel Flash products T = Top Blocking B = Bottom Blocking Device Density 640 = x16 (64 Mbit ) 320 = x16 (32 Mbit ) 160 = x16 (16 Mbit ) 800 = x16 (8 Mbit ) Table 34. Product Family C3 = 3 Volt Advanced Boot B VCC = 2.7 V-3.6 V VPP = 2 .7 V-3 .6 V or 11 . 4 V-12 .6 V Ordering Information: Valid Combinations (Sheet 1 of 2) 40-Lead TSOP 48-Lead TSOP 48-Ball BGA CSP(1,2) 48-Ball VF BGA Ext. Temp. 64 Mbit TE28F640B3TC80 TE28F640B3BC80 GE28F640B3TC80 GE28F640B3BC80 Ext. Temp. 32 Mbit TE28F320B3TD70 TE28F320B3BD70 TE28F320B3TC70 TE28F320B3BC70 TE28F320B3TC90 TE28F320B3BC90 TE28F320B3TA100 TE28F320B3BA100 TE28F320B3TA110 TE28F320B3BA110 JS28F320B3TD70 JS28F320B3BD70 GE28F320B3TD70 GE28F320B3BD70 GE28F320B3TC70 GE28F320B3BC70 GE28F320B3TC90 GE28F320B3BC90 PH28F320B3BD70 18 Aug 2005 70 Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 Datasheet 28F008/800B3, 28F016/160B3, 28F320B3, 28F640B3 Table 34. Ordering Information: Valid Combinations (Sheet 2 of 2) 40-Lead TSOP Ext. Temp. 16 Mbit Ext. Temp. 8 Mbit TE28F016B3TA90 TE28F016B3BA90 TE28F016B3TA110 TE28F016B3BA110 48-Lead TSOP TE28F160B3TD70 TE28F160B3BD70 TE28F160B3TC70 TE28F160B3BC70 TE28F160B3TC80 TE28F160B3BC80 TE28F160B3TC90 TE28F160B3BC90 TE28F160B3TA90 TE28F160B3BA90 48-Ball BGA CSP(1,2) GT28F160B3TA90(3) GT28F160B3BA90(3) GT28F160B3TA110(3) GT28F160B3BA110(3) 48-Ball VF BGA GE28F160B3TD70 GE28F160B3BD70 GE28F160B3TC70 GE28F160B3BC70 GE28F160B3TC80 GE28F160B3BC80 GE28F160B3TC90 GE28F160B3BC90 TE28F160B3TA110 TE28F160B3BA110 JS28F160B3TA70 JS28F160B3BD70 PH28F160B3TD70 PH28F160B3BD70 TE28F800B3TA90 TE28F800B3BA90 TE28F800B3TA110 TE28F800B3BA110 GE28F800B3TA70 GE28F800B3BA70 GE28F800B3TA90 GE28F800B3BA90 Notes: 1. The 48-ball BGA package top side mark reads F160B3. This mark is identical for both x8 and x16 products. All product shipping boxes or trays provide the correct information regarding bus architecture. However, once the flash memory devices are removed from the shipping media, differentiating based on the top side mark might be difficult. The device identifier (accessible through the Device ID command: see Section 11.2, "Read Identifier" on page 56 for further details) enables x8 and x16 BGA package product differentiation. 2. The second line of the 48-ball BGA package top side mark specifies assembly codes. For samples only, the first character signifies either: - E for engineering samples, or - S for silicon daisy-chain samples. All other assembly codes without an E or an S as the first character are production units. 3. Intel recommends using.18 m Intel(R) Advanced Boot Block Products. Datasheet Intel(R) Advanced Boot Block Flash Memory (B3) Order Number: 290580, Revision: 020 18 Aug 2005 71