74VHCT00AMTCX_NL - Fairchild Semiconductor

July 1997

Revised February 2005

74VHCT00A Quad 2-Input NAND Gate

74VHCT00A

Quad 2-Input NAND Gate

General Descript ion

The VHCT00A is an advanced high-speed CMOS 2-Input

NAND Gate fabricated with silicon gate CMOS technology.

It achieves the high-speed operation similar to equivalent

Bipolar Schottky TTL while maintaining the CMOS low

power dissipation. The internal circuit is composed of 3

stages, including buffer output, which provide high noise

immunity and stable output.

Protection circuits ensure th at 0V to 7V can be applied to

the input pins without regard to the supply voltage and to

the output pins with VCC

0V. These circuits prevent

device destruction due to mismatched supply and input/

output voltages. This de vice can be used to inte rfa c e 3V to

5V systems and two supply systems such as battery

backup.

Features

■High speed: tPD

5.0 ns (typ) at TA

■High noise immunity: VIH

2.0V, VIL

0.8V

■Power down protection is provided on all inputs and

outputs

■Low noise: VOLP

0.8V (max)

■Low power dissipation :

ICC

A (max) at TA

■Pin and function compatible with 74HCT00

Ordering Code:

Surface m ount pack ages are also avai lable on Tape and Reel. Specify by append ing the suffix let t er “X” to the o rdering code.

Pb-Free package per JEDEC J-STD-020B.

Note 1: “_NL” indicat es Pb-Fre e pac k age (per JE D EC J -STD-0 20B). Use th is numbe r to order devic e.

Order Number Package Package Description

Number

74VHCT00AM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHCT00ASJ M14D Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

74VHCT00AMTC MTC14 14-Lead Thi n Shrink Small Outli ne Package (TSSOP), JEDEC MO-153, 4. 4mm Wide

74VHCT00AMTCX_NL

(Note 1) MTC14 Pb-Free 14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm

Wide

74VHCT00AN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

74VHCT00AN_NL

(Note 1) N14A Pb-Free 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

www.fairchildsemi.com 2

74VHCT00A

Logic Symbol Connection Diagram

Pin Descriptions Truth Table

Pin Names Description

An, BnInputs

OnOutputs

ABO

LLH

LHH

HLH

HHL

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74VHCT00A

Absolute Maximum Ratings(Note 2) Recommended Operating

Conditions (Note 6)

Note 2: Absolute Maximum Ratings are values beyond which the device

may be damaged or have its useful life impaired. The databook specifica-

tions should be met, without exception, to ensure that the system design is

reliable over its power supply, temperature, and output/input loading vari-

ables. Fairchild does not recommend operation outside databook specifica-

tions.

Note 3: HIGH or LOW state. IOUT absolute maximum rating must be

observed.

Note 4: VCC

0V.

Note 5: VOUT



GND, VOUT

VCC (Outputs Active)

Note 6: Unused inputs must be held HIGH or LOW. They may not float.

DC Electrical Characteristics

Noise Characteri stics

Note 7: Parameter guaranteed by design.

Supply Voltage (VCC)



0.5V to



7.0V

DC Input Voltage (VIN)



0.5V to



7.0V

DC O utput Voltage (VOUT)

(Note 3)



0.5V to VCC



0.5V

(Note 4)



0.5V to 7.0V

Input Diode Current (IIK)



20 mA

Output Diode Current (IOK)

(Note 5)

20 mA

DC Output Current (IOUT)

25 mA

DC VCC/GND Current (ICC)

50 mA

Storage Temperature (TSTG)



C to



150

Lead Temperature (TL)

(Soldering, 10 seconds) 260

Supply Voltage (VCC) 4.5V to 5.5V

Input Voltage (VIN)0V to



5.5V

Output Voltage (VOUT)

(Note 3) 0V to VCC

(Note 4) 0V to 5.5V

Operating Temperature (TOPR)



C to



Input Rise and Fall Time (tr, tf)

VCC

5.0V

0.5V 0 ns/V

20 ns/V

Symbol Parameter VCC

(V)



C to



CUnits Conditions

Min Typ Max Min Max

VIH HIGH Level Input Voltage 4.5 2.0 2.0 V

5.5 2.0 2.0

VIL LOW Level Input Voltage 4.5 0.8 0.8 V

5.5 0.8 0.8

VOH HIGH Level Output Voltage 4.5 4.40 4.50 4.40 V VIN

VIH IOH



4.5 3.94 3.80 V or VIL IOH



8 mA

VOL LOW Level Output Voltage 4.5 0.0 0.1 0.1 V VIN

VIH IOL

4.5 0.36 0.44 V or VIL IOL

8 mA

IIN Input Leakage Current 0



5.5

0.1

1.0

5.5V or GND

ICC Quiescent Supply Current 5.5 2.0 20.0

VCC or GND

ICCT Maximum ICC/ Input 5.5 1.35 1.50 mA VIN

3.4V

Other Inputs

VCC or GND

IOFF Output Leakage Current 0.0 0.5 5.0

OUT

5.5V

(Power Down State)

Symbol Parameter VCC

(V)

CUnits Conditions

Typ Limit

VOLP

(Note 7) Quiet Output Maximum Dynamic VOL 5.0 0.4 0.8 V CL

50 pF

VOLV

(Note 7) Quiet Output Minimum Dynamic VOL 5.0



0.4



0.8 V CL

50 pF

VIHD

(Note 7) Minimum HIGH Level Dynamic Input Voltage 5.0 2.0 V CL

50 pF

VILD

(Note 7) Maximum LOW Level Dynamic Input Voltage 5.0 0.8 V CL

50 pF

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74VHCT00A

AC Electrical Characteristics

Note 8: CPD is defined as the value of th e internal equi v alent c apacitance, which i s c alculat ed from th e o perating current consumptio n without load. Av erage

operat ing cur rent can be obta ined from th e equatio n: ICC (opr.)

CPD * VCC * fIN



ICC/4 (per gate)

Symbol Parameter VCC

(V)



C to



CUnits Conditions

Min Typ Max Min Max

tPLH Propagation Delay 5.0

0.5 5.0 6.9 1.0 8.0 ns CL

15 pF

tPHL 5.57.91.09.0 C

50 pF

CIN Input Capacitance 4 10 10 pF VCC

Open

CPD Power Dissipation Capacitance 17 pF (Note 8)

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74VHCT00A

Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M14A

www.fairchildsemi.com 6

74VHCT00A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Pb-Free 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M14D

7 www.fairchildsemi.com

74VHCT00A

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lea d Th in S hri nk Sm all Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC14

www.fairchildsemi.com 8

74VHCT00A Quad 2-Input NAND Gate

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N14A

Fairchild does no t assume any responsibility for use of any circui try described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life suppor t de vices o r systems a re devices or syste ms

which, (a) are intended for surgical implant into the

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to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical compon ent in any componen t of a life support

device or system whose failure to perform can be rea-

sonabl y ex pect ed to cause the fa ilu re of the li fe su pp ort

device or system, or to affect its safety or effectiveness.