1
FEATURES
400.0 Mbps low jitter fully differential data path
200MHz clock channel
3.3 V power su pply
10mA LVDS output drivers
Input receiver fail-safe
Cold sparing all pins
Configurable as quad 2:1 mux, 1:2 demu x, repeater or1:2
signal splitter
Fast propagation delay of 3.5ns max
Receiver input threshold < + 100 mV
Radiation-hardened design; total dose irradiation testing to
MIL-STD-883 Method 1019
- Total-dose: 300 krad(Si) and 1 Mrad(Si)
- Latchup immune (LET > 100 MeV-cm2/mg)
Packaging options:
- 64-lead flatpack
Standard Microcircuit Drawing 5962-01537
- QML Q and V compliant part
INTRODUCTION
The UT54LVDM228 is a quad 2x2 crosspoint switch utilizing
Low Voltage Differential Signaling (L VDS) technology for low
power, high speed operation. Data paths are fully differential
from input to output for low noise generation and low pulse
width distortion. The non-blocking design allows connection of
any input to any output or outputs on each switch. LVDS I/O
enable high speed data transmission for point-to point or multi-
drop interconnects. This device can be used as a high speed
differential crosspoint, 2:1 mux, 1:2 demux, repeater or 1:2
signal splitter. The mux and demux functions are useful for
switching between primary and backup circuits in fault tolerant
systems. The 1:2 signal splitter and 2:1 mux functions are useful
for distribution of a bus across several rack-mounted
backplanes.
The individual LVDS outputs can be put into Tri-State by use
of the enable pins.
All pins have Cold Spare buffers. These buffers will be high
impedance when VDD is tied to VSS.
Standard Products
UT54LVDM228 Quad 2x2 400 Mbps Crosspoint Switch
Data Sheet
May 8, 2007
Figure 1a. UT54LVDM228 Crosspoint Switch Block Diagram
(Partial - see Page 2 for complete diagram)
Out1+
En1
In1+ +
-1
0
1
0Out 2+
Sel1
En2
In2+
Sel2
+
-
In1- Out1-
Out 2-
In2-
2
Out1+
En1
In1+ +
-1
0
1
0Out 2+
Sel1
En2
In2+
Sel2
Out3+
En3
In3+
1
0
1
0Out4+
Sel3
En4
In4+
Sel4
Out5+
En5
In5+
1
0
1
0Out6+
Sel5
En6
In6+
Sel6
Out7+
En7
In7+
1
0
1
0Out8+
Sel7
En8
In8+
Sel8
Clk In+ Clk Out+
+
-
+
-
+
-
+
-
+
-
+
-
Figure 1b. UT54LVDM228 Crosspoint Switch Block Diagram
+
-
+
-Skew
Match
In1- Out1-
Out 2-
In2-
Out3-
In3-
In4- Out4-
In5- Out5-
In6- Out6-
In7- Out7-
In8- Out8-
Clk In- Clk Out-
ENCK
3
TRUTH TABLE
PIN DESCRIPTION
Figure 2. UT54LVDS228 Pinout
UT54LVDM228
Crosspoint
Switch
64
63
62
61
60
59
58
57
VDD
1
En1
2
3
4
5
6
7
8
VSS 9
10
11
12
13
14
15
16
VDD
In4+
In4-
CLK In+
17
18
19
20
21
22
23
24
VSS
In5+
In6+
In6-
Sel1
Out2+
56
55
54
53
52
51
50
49
Out4+
CLK Out+
Out3-
Sel4
48
47
46
45
44
43
42
41 Out6-
CLK Out-
Out5-
In1+
En2
In2+
In3+
In3-
En3
En4
ENCK
CLK In-
En5
In5-
En6
Out1+
Out1-
Sel2
Out2-
VSS
Sel3
Out3+
Out4-
VDD
Out5+
VSS
Sel5
Sel6
Out6+
In7+
In7-
VDD
VSS
In8-
En8
En7
In8+
Out7+
VDD
VSS
Sel7
Out8-
Out7-
Sel8
Out8+
In1-
In2-
Out8-
Out5-
25
26
27
28
29
30
31
32
40
39
38
37
36
35
34
33
Sel1 Sel2 Out1 Out2 Mode
0 0 In1 In1 1:2 splitter
0 1 In1 In2 Repeater
10In2In1Switch
1 1 In2 In2 1:2 splitter
Name # of Pins Description
In+ 8 Non-inverting LVDS input
In- 8 Inverting LVDS input
Out+ 8 Non-inverting LVDS output
Out- 8 Inverting LVDS Output
En 8 A logic low on the enable puts
the LVDS output into Tri-State
and reduces the supply current
ENCK 1 A logic low on the enable puts
the LVDS output into Tri-State
and reduces the supply current
Sel 8 2:1 mux input sel ect
VSS 6 Ground
VDD 5 Power supply
CLK In+ 1 Non-Inverting Clock LVDS
Input
CLK In- 1 Inverting clock LVDS Input
CLK Out+ 1 Non-Inverting Clock LVDS
Output
CLK Out- 1 Inverting Clock LVDS Output
4
APPLICATIONS INFORMATION
The UT54LVDM228 provides three modes of operation. In
the 1:2 splitter mode, the two outputs are copies of the same
single input. This is useful for distribution / fan-out
applications. In the repeater mode, the device operates as a
9channel LVDS buffer. Repeating the signal restores the
L VDS amplitude, allowing it to drive another media segment.
This allows for isolation of segments or long distance
applications or buffers standard LVDS to 10mA multi-op
drivers.The switch mode provides a crosspoint function. This
can be used in a system when primary and redundant paths
are supported in a fault tolerant application.
The intended application of these devices and signal ing
technique is for both point-to-point baseband (single
termination) and multipo int (double termination) data
transmissions over controlled impedance media. The
transmission media may be printed-circuit board traces,
backplanes, or cables. (Note: The ultimate rate and distance
of data transfer is dependent upon the attenuation
characteristics of the media, the noise coupling to the
environment, and other application specific characteristics.
Input Fail-Safe:
The UT54LVDM228 also supports OPEN, shorted and
terminated input fail-safe. Receiver output will be HIGH for
all fail-safe conditions.
PCB layout and Power System Bypass:
Circuit board layout and stack-up for the UT54LVDM228
should be designed to provide noise-free power to the device.
Good layout practice also will separate high frequency or high
level inputs and outputs to minimize unwanted stray noise
pickup, feedback and interference. Power system
performance may be greatly improved by using thi n
dielectrics (4 to 10 mils) for power/ground sandwiches. This
increases the intrinsic capacitance of the PCB power system
which improves power supply filtering, especially at hig h
frequencies, and makes the value and placement of external
bypass capacitors less critical. External bypass capacitors
should include both RF ceramic and tantalum electrolytic
types. RF capacitors may use values in the range 0.01μF to
0.1μ F. Tantalum capacitors may be in the range of 2.2μF to
10μF. Voltage rating for tantalum capacitors should be at least
5X the power supply voltage being used. It is recommended
practice to use two vias at each power pin of the
UT54LVDM228, as well as all RF bypass capacitor
terminals. Dual vias reduce the interconnect inductance and
extends the effective frequency range of the bypass
components.
The outer layers of the PCB may be flooded with additional
ground plane. These planes will improve shielding and
isolation, as well as increase the intrinsic capacitance of the
power supply plane system. Naturally, to be effective, thes e
planes must be tied to the ground supply pl ane at frequent
intervals with vias. Frequent via placement also improves
signal integrity in signal transmission lines by providing short
paths for image currents which reduces signal distortion. The
planes should be pulled back from all transmission lines and
component mounting pad s a distan ce equal to the width of
the widest transmission line from the internal power or
ground plane(s) whichever is greater. Doing so minimizes
effects on transmission line impedances and reduces
unwanted parasitic capacitances at component mounting
pads.
Compatibility with LVDS standard:
In backplane multidrop configurations, with closely spaced
loads, the effective differential impedance of the line is
reduced. If the mainline has been designed for 50Ω
differential impedance, the loading effects may reduce this to
the 35Ω range depending upon spacing and capacitance load.
Terminating the lin e with a 35Ω load is a better match than
with 50Ω and reflections are reduced.
5
ABSOLUTE MAXIMUM RATINGS1(Referenced to VSS)
Notes:
1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device
at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability and performance.
2. Maximum junction temperature may be increased to +175 °C during burn-in and life test.
3. Test per MIL-STD-883, Method 1012.
4. For Cold Spare mode (VDD=VSS), VI/O may be -0.3V to the maximum recommended operating VDD + 0.3V.
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER LIMITS
VDD DC supply volta ge -0.3 to 4.0V
VI/O4Voltage on any pin -0.3 to (VDD + 0.3V)
TSTG Storage temperature -65 to +150°C
PDMaximum power dissip at ion 800mW
TJMaximum junction temperature2+150°C
ΘJC Thermal resistance, junction-to-case322°C/W
IIDC input current ±10mA
SYMBOL PARAMETER LIMITS
VDD Positive supply voltage 3.0 to 3.6V
TCCase temperature range -55 to +125°C
VIN DC input voltage, receiver inputs 0 to 2.4V
DC input voltage, logic input s 0 to VDD for EN, SEL
6
DC ELECTRICAL CHARACTERISTICS 1
(VDD = 3.3V + 0.3V; -55°C < TC < +125°C)
SYMBOL PARAMETER CONDITION MIN MAX UNIT
CMOS/TTL DC SPECIFICATIONS (EN, SEL)
VIH High-level input voltage 2.0 VCC V
VIL Low-level input voltage GND 0.8 V
IIH High-level input current VIN=3.6V; VDD = 3.6V -10 +10 μA
IIL Low-level input current VIN=0V; VDD = 3.6V -10 +10 μA
VCL Input clamp voltage ICL=-18mA -1.5 V
ICS Cold Spare Leakage VIN=3.6V, VDD=VSS -20 +20 μΑ
LVDS OUTPUT DC SPECIFICATIONS (OUT+, OUT-)
VOD Differential Output Voltage RL= 35Ω (see Figure 10) 250 450 mV
ΔVOD Change in VOD between
complimentary output states RL= 35Ω35 mV
VOS Offset Voltage 1.055 1.550 V
ΔVOS Change in VOS between complimentary
output states RL=35Ω35 mV
IOZ Output Tri-State Current Tri-State output, VDD = 3.6V
VOUT=VDD or GND
+10 μΑ
ICSOUT Cold Sparing Leakage Current VOUT=3.6V, VDD=VSS -20 +20 μΑ
IOS2,3 Output Short Circuit Current VOUT+ OR VOUT- = 0 V -25 mA
LVDS RECEIVER DC SPECIFICATIONS (IN+, IN-)
VTH3Differential Input High Threshold VCM = +1.2V +100 mV
VTL3Differential Input Low Threshold VCM = +1.2V -100 mV
VCMR Common Mode Voltage Range VID=200mV 0.2 2.00 V
IIN Input Current VIN = +2.4V, VDD = 3.6V -10 +10 μΑ
VIN = 0V, VDD = 3.6V -10 +10 μΑ
ICSIN Cold Sparing Leakage Current VIN=3.6V, VDD=VSS -20 +20 μΑ
Supply Current
ICCD Total Supply Current RL = 35Ω
EN1 - EN8, ENCK = VDD
220 ma
ICCZ Tri-State Supply Current EN1 - EN8, ENCK = VSS 20 ma
RL= 35Ω VOS=(VOH+VOL)
2
(see Figure 10)
7
Notes:
1. Current into device pins is defined as positive. Current out of device pins is defined as negative. All voltages are referenced to ground.
2. Output short circuit current (IOS) is specified as magnitude only, minus sign indicates direction only. Only one output should be shorted at a time, do not exceed
maximum junction temperature specification.
3. Guaranteed by characterization.
8
AC SWITCHING CHARACTERISTICS
(VDD = +3.3V + 0.3V, TA = -55 °C to +125 °C)
Notes:
1. Guaranteed by characterization.
2. TSET and THOLD time specify that data must be in a stable state before and after SEL transition.
3. Guaranteed by design.
4. Max tPZH and tPZL = 4.5ns when EN or ENCL = VDD on another channel.
SYMBOL PARAMETER Conditions MIN MAX UNIT
tSET1, 2 Input to SEL Setup Time (Figure 3 & 4) RL=35Ω, CL=10pf 1.6 ns
tHOLD1,2 Input to SEL Hold Time (Figure 3 & 4) RL=35Ω, CL=10pf 1.5 ns
tSWITCH1SEL to Switched Output (Figure 3 & 4) RL=35Ω, CL=10pf 3.0 ns
tPHZ1Disable Time (Active to Tri-State) High to Z
(Figure 5 & 8) RL=35Ω, CL=10pf 4.5 ns
tPLZ1Disable Time (Active to Tri-S t ate) Low to Z
(Figure 5 & 8) RL=35Ω, CL=10pf 4.5 ns
tPZH1,4 Enable Time (Tri-State to Active) Z to High
(Figure 5 & 8) RL=35Ω, CL=10pf
EN on other channels = GND
11.0 ns
tPZL1,4 Enable Time (Tri-State to Active) Z to Low
(Figure 5 & 8) RL=35Ω, CL=10pf
EN on other channels = GND
11.0 ns
tLHT3Output Low-to-High Transition Time, 20% to 80%
(Figure 5 & 6) RL=35Ω, CL=10pf 600 ps
tHLT3Output High -t o-Low Transition Time, 80% to 20%
(Figure 5 & 6) RL=35Ω, CL=10pf 600 ps
tPLHD Propagation Low to High Delay (Figure 5 & 7) RL=35Ω, CL=10pf 3.5 ns
TPHLD Propagation High to Low Delay (Figure 5 & 7) RL=35Ω, CL=10pf 3.5 ns
TSKEW Pulse Skew TPHLD - TPLHD (Figure 5 & 7) 900 ps
TCCS Output Channel-to-Channel Skew (Figure 5 & 9) 500 ps
9
AC TIMING DIAGRAMS
IN0
IN1
SEL
OUT
EN
TSET THOLD
IN0
TSWITCH
IN1
Figure 3. Input-to-Select Rising Edge Setup and Hold Times and Mux Switch Time
IN0
IN1
SEL
OUT
EN
TSET THOLD
IN1
TSWITCH
IN0
Figure 4. Input-to-Select Falling Edge Setup and Hold Times and Mux Switch Time
10
R
RIN+
Pulse
Generator
50Ω
Figure 5. LVDS Output Load
RIN-
50ΩCL
D
CL
RL
+VOD
tHLT
20%
80%
0V
20%
80%
tLHT
Figure 6. LVDS Output Transition Time
-VOD
Vdiff=(OUT+) - (OUT-)
tPLHD tPHLD
Vdiff = 0V
Vdiff = 0V
IN
OUT
Figure 7. Propagation Delay Low-to-High and High-to-Low
11
EN
tPLZ tPZL
50% 50%
VOL
0V Diff
0V Diff
VOH
VDD
VDD/2VDD/2
50%
tPZH
tPHZ
Figure 8. Output active to TRI-STATE and TRI-STATE to active
50%
OUT
OUT
TCCS
Vdiff = 0V
Vdiff = 0V
OUT 0
OUT 1
Figure 9. Output Channel-to-Channel Skew in 1:2 splitter mode
Figure 10. Driver VOD and VOS Test Circuit or Equivalent Circuit
D
DIN
DOUT-
DOUT+
20pF
Driver Enabled
Generator
50Ω
RL = 35ΩVOD
20pF
12
PACKAGING
Figure 11. 64-pin Flatpack
Notes:
1. All exposed metalized areas are gold plated over electroplated nickel per MIL-PRF-38535.
2. The lid is electrically connected to VSS.
3. Lead finishes are in accordance to MIL-PRF-38535.
4. Package dimensions and symbols are similar to MIL-STD-1835 Requirement 101, Configuration B.
5. Lead position and coplanarity are not measured.
6. ID mark symbol is vendor option.
7. With solder, increase maximum by 0.003.
13
ORDERING INFORMATION
UT54LVDM228 Crosspoint Switch:
UT 54LV DM228 * * * * *
Device Type:
UT54LVDM228 Crosspoint Switch
Access T i me:
Not applicable
Package Type:
(U) = 64-lead Flatpack (dual-in-line)
Screening:
(C) = Military Temperature Range flow
(P) = Prototype flow
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory option (gold or solder)
Notes:
1. Lead finish (A,C, or X) must be specified.
2. If an “X” is specified when ordering, then the part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3. Prototype flow per UTMC Manufactur ing Flows Document . Tested at 25°C only. Lead finish is GOLD ONLY. Radiation neither
tested nor guaranteed.
4. Military T emperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -55°C, room temp, and 125°C.
Radiation neither tested nor guaranteed.
14
UT54LVDM228 Crosspoint Switch: SMD
5962 - ** *
Federal Stock Class Designator: No Options
Total Dose
(R) = 1E5 rad(Si)
(F) = 3E5 rad(Si)
(G) = 5E5 rad(Si)
(H) = 1E6 rad(Si)
Drawing Number: 01537
Device Type
01 = LVDS Crosspoint Switch
Class Designator:
(Q) = QML Class Q
(V) = QML Class V
Case Outline:
(X) = 64-lead Flatpack (dual-in-line)
Lead Finish:
(A) = Hot solder dipped
(C) = Gold
(X) = Factory Option (gold or solder)
**
01537
Notes:
1.Lead finish (A,C, or X) must be specifi ed.
2.If an “X” is specified when ordering, part marking will match the lead finish and will be either “A” (solder) or “C” (gold).
3.Total dose radiation must be specified when ordering. QML Q and QML V not available without radiation hardening.
15
NOTES
