LTC3862-2
1
38622f
Typical applicaTion
FeaTures
applicaTions
DescripTion
Multi-Phase Current Mode
Step-Up DC/DC Controller
The LTC
®
3862-2 is a two-phase constant frequency, current
mode boost and SEPIC controller that drives N-channel
power MOSFETs. Two-phase operation reduces system
filtering capacitance and inductance requirements.
The operating frequency can be set with an external resistor
over a 75kHz to 500kHz range and can be synchronized
to an external clock using the internal PLL. Multiphase
operation is possible using the SYNC input, the CLKOUT
output and the PHASEMODE control pin allowing 2-, 3-,
4-, 6- or 12-phase operation.
Other features include an internal 10V LDO with under-
voltage lockout protection for the gate drivers, a preci-
sion RUN pin threshold with programmable hysteresis,
soft-start and programmable leading edge blanking and
maximum duty cycle.
PART NUMBER INTVCC UV+UV
LTC3862 5V 3.3V 2.9V
LTC3862-1 10V 7.5V 7.0V
LTC3862-2 10V 4.4V 3.9V
n Wide VIN Range: 5.5V to 36V Operation
n 2-Phase Operation Reduces Input and Output
Capacitance
n Fixed Frequency, Peak Current Mode Control
n Internal 10V LDO Regulator
n Lower UVLO Thresholds Allows the Use of
MOSFETs Rated at 6V VGS
n Adjustable Slope Compensation Gain
n Adjustable Max Duty Cycle (Up to 96%)
n Adjustable Leading Edge Blanking
n ±1% Internal Voltage Reference
n Programmable Operating Frequency with One
External Resistor (75kHz to 500kHz)
n Phase-Lockable Fixed Frequency 50kHz to 650kHz
n SYNC Input and CLKOUT for 2-, 3-, 4-, 6- or
12-Phase Operation (PHASEMODE Programmable)
n 24-Lead Narrow SSOP Package
n 5mm × 5mm QFN Package with 0.65mm Lead Pitch
n 24-Lead Thermally Enhanced TSSOP Package
n Automotive, Telecom and Industrial Power Supplies
Efficiency vs Output Current
L, LT, LTC, LTM, Linear Technology, the Linear logo and PolyPhase are registered trademarks
and No RSENSE and ThinSOT are trademarks of Linear Technology Corporation. All other
trademarks are the property of their respective owners. Protected by U.S. Patents, including
6144194, 6498466, 6611131.
VIN
LTC3862-2
SGND
GATE1
SENSE1+
RUN
100k
24.9k
110k
796k 12.4k 12.1k 220pF
0.0033Ω
0.0033Ω
16µH 16µH
22µF
50V
210µF
100V
0.1µF
1nF
10nF
4.7µF
INTVCC
SS
3V8
ITH
FB
VOUT
80V
7A (MAX)
38622 TA01a
VIN
6V TO 32V
BLANK
FREQ
SYNC
PLLFLTR
SENSE1
GATE2
SENSE2+
SENSE2
PGND
CLKOUT
SLOPE
DMAX
PHASEMODE
LOAD CURRENT (mA)
EFFICIENCY (%)
38622 TA01b
97
87
89
91
93
95
77
79
81
83
85
10 1000100 10000
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 24V
VOUT = 80V
LTC3862-2
2
38622f
absoluTe MaxiMuM raTings
Input Supply Voltage (VIN) ......................... 0.3V to 40V
INTVCC Voltage ..........................................0.3V to 11V
INTVCC LDO RMS Output Current .........................50mA
RUN Voltage................................................. 0.3V to 8V
SYNC Voltage ............................................... 0.3V to 6V
SLOPE, PHASEMODE, DMAX,
BLANK Voltage .......................................... 0.3V to 3V8
SENSE1+, SENSE1, SENSE2+,
SENSE2 Voltage ...................................... 0.3V to V3V8
(Notes 1, 2)
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
FE PACKAGE
24-LEAD PLASTIC TSSOP
24
23
22
21
20
19
18
17
16
15
14
13
DMAX
SLOPE
BLANK
PHASEMODE
FREQ
SS
ITH
FB
SGND
CLKOUT
SYNC
PLLFLTR
3V8
SENSE1+
SENSE1
RUN
VIN
INTVCC
GATE1
PGND
GATE2
NC
SENSE2
SENSE2+
25
PGND
TJMAX = 150°C, θJA = 38°C/W
EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
1
2
3
4
5
6
7
8
9
10
11
12
TOP VIEW
GN PACKAGE
24-LEAD NARROW PLASTIC SSOP
24
23
22
21
20
19
18
17
16
15
14
13
DMAX
SLOPE
BLANK
PHASEMODE
FREQ
SS
ITH
FB
SGND
CLKOUT
SYNC
PLLFLTR
3V8
SENSE1+
SENSE1
RUN
VIN
INTVCC
GATE1
PGND
GATE2
NC
SENSE2
SENSE2+
TJMAX = 150°C, θJA = 85°C/W
24 23 22 21 20 19
789
TOP VIEW
25
PGND
UH PACKAGE
24-LEAD (5mm × 5mm) PLASTIC QFN
10 11 12
6
5
4
3
2
1
13
14
15
16
17
18BLANK
PHASEMODE
FREQ
SS
ITH
FB
VIN
INTVCC
GATE1
PGND
GATE2
NC
SLOPE
DMAX
3V8
SENSE1+
SENSE1
RUN
SGND
CLKOUT
SYNC
PLLFLTR
SENSE2+
SENSE2
TJMAX = 150°C, θJA = 44°C/W
EXPOSED PAD (PIN 25) IS PGND, MUST BE SOLDERED TO PCB
pin conFiguraTion
SS, PLLFLTR Voltage ................................ 0.3V to V3V8
ITH Voltage ............................................... 0.3V to 2.7V
FB Voltage .................................................. 0.3V to 3V8
FREQ Voltage ............................................ 0.3V to 1.5V
Operating Junction Temperature Range (Notes 3, 4)
LTC3862-2E .........................................40°C to 85°C
LTC3862-2I ........................................ 40°C to 125°C
LTC3862-2H ....................................... 40°C to 150°C
Storage Temperature Range .................. 65°C to 150°C
Reflow Peak Body Temperature ........................... 260°C
LTC3862-2
3
38622f
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC3862EFE-2#PBF LTC3862EFE-2#TRPBF LTC3862FE-2 24-Lead Plastic TSSOP –40°C to 85°C
LTC3862IFE-2#PBF LTC3862IFE-2#TRPBF LTC3862FE-2 24-Lead Plastic TSSOP –40°C to 125°C
LTC3862HFE-2#PBF LTC3862HFE-2#TRPBF LTC3862FE-2 24-Lead Plastic TSSOP –40°C to 150°C
LTC3862EGN-2#PBF LTC3862EGN-2#TRPBF LTC3862GN-2 24-Lead Plastic SSOP –40°C to 85°C
LTC3862IGN-2#PBF LTC3862IGN-2#TRPBF LTC3862GN-2 24-Lead Plastic SSOP –40°C to 125°C
LTC3862HGN-2#PBF LTC3862HGN-2#TRPBF LTC3862GN-2 24-Lead Plastic SSOP –40°C to 150°C
LTC3862EUH-2#PBF LTC3862EUH-2#TRPBF 38622 24-Lead (5mm × 5mm) Plastic QFN –40°C to 85°C
LTC3862IUH-2#PBF LTC3862IUH-2#TRPBF 38622 24-Lead (5mm × 5mm) Plastic QFN –40°C to 125°C
LTC3862HUH-2#PBF LTC3862HUH-2#TRPBF 38622 24-Lead (5mm × 5mm) Plastic QFN –40°C to 150°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/
orDer inForMaTion
elecTrical characTerisTics
(Notes 2, 3) The l denotes the specifications which apply over the
specified operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, RUN = 2V and SS = open, unless
otherwise noted.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
Supply Input and INTVCC Linear Regulator
VIN VIN Supply Voltage Range l5.5 36 V
IVIN VIN Supply Current
Normal Mode, No Switching
Shutdown
(Note 5)
VRUN = 0V
l
l
1.8
30
3.0
80
mA
µA
INTVCC LDO Regulator Output Voltage 9.5 10.0 10.5 V
dVINTVCC(LINE) Line Regulation 12V < VIN < 36V 0.002 0.02 %/V
dVINTVCC(LOAD) Load Regulation Load = 0mA to 20mA –2 %
VUVLO INTVCC UVLO Voltage Rising INTVCC
Falling INTVCC
4.4
3.9
V
V
3V8 LDO Regulator Output Voltage 3.8 V
Switcher Control Loop
VFB Reference Voltage VITH = 0.8V (Note 6) E-Grade (Note 3)
I-Grade and H-Grade (Note 3)
l
l
1.210
1.199
1.223
1.223
1.235
1.248
V
V
dVFB/dVIN Feedback Voltage VIN Line Regulation VIN = 5.5V to 36V (Note 6) ±0.002 0.01 %/V
dVFB/dVITH Feedback Voltage Load Regulation VITH = 0.5V to 1.2V (Note 6) 0.01 0.1 %
gmTransconductance Amplifier Gain VITH = 0.8V (Note 6), ITH Pin Load = ±5µA 660 µMho
f0dB Error Amplifier Unity-Gain Crossover
Frequency
(Note 7) 1.8 MHz
LTC3862-2
4
38622f
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VITH Error Amplifier Maximum Output Voltage
(Internally Clamped)
VFB = 1V, No Load 2.7 V
Error Amplifier Minimum Output Voltage VFB = 1.5V, No Load 50 mV
IITH Error Amplifier Output Source Current –30 µA
Error Amplifier Output Sink Current 30 µA
IFB Error Amplifier Input Bias Currents (Note 6) –50 –200 nA
VITH(PSKIP) Pulse Skip Mode Operation ITH Pin Voltage Rising ITH Voltage (Note 6)
Hysteresis
0.275
25
V
mV
ISENSE(ON) SENSE Pin Current 0.01 2 µA
VSENSE(MAX) Maximum Current Sense Input Threshold VSLOPE = Float, Low Duty Cycle
(Note 3)
l
68
65
75
75
82
85
mV
mV
VSENSE(MATCH) CH1 to CH2 Maximum Current Sense
Threshold Matching
VSLOPE = Float, Low Duty Cycle (Note 3)
(VSENSE1 – VSENSE2)
l–7 7 mV
RUN/Soft-Start
IRUN RUN Source Current VRUN = 0V
VRUN = 1.5V
–0.5
–5
µA
µA
VRUN High Level RUN Channel Enable Threshold 1.22 V
VRUNHYS RUN Threshold Hysteresis 80 mV
ISS SS Pull-Up Current VSS = 0V –5 µA
RSS SS Pull-Down Resistance VRUN = 0V 10
Oscillator
fOSC Oscillator Frequency RFREQ = 45.6k
RFREQ = 45.6k
l
280
260
300
300
320
340
kHz
kHz
Oscillator Frequency Range l75 500 kHz
VFREQ Nominal FREQ Pin Voltage RFREQ = 45.6k 1.223 V
fSYNC SYNC Minimum Input Frequency VSYNC = External Clock l50 kHz
SYNC Maximum Input Frequency VSYNC = External Clock l650 kHz
VSYNC SYNC Input Threshold Rising Threshold 1.5 V
IPLLFLTR Phase Detector Sourcing Output Current fSYNC > fOSC –15 µA
Phase Detector Sinking Output Current fSYNC < fOSC 15 µA
CH1-CH2 Channel 1 to Channel 2 Phase Relationship VPHASEMODE = 0V
VPHASEMODE = Float
VPHASEMODE = 3V8
180
180
120
Deg
Deg
Deg
CH1-CLKOUT Channel 1 to CLKOUT Phase Relationship VPHASEMODE = 0V
VPHASEMODE = Float
VPHASEMODE = 3V8
90
60
240
Deg
Deg
Deg
DMAX Maximum Duty Cycle VDMAX = 0V (Note 9)
VDMAX = Float
VDMAX = 3V8
96
84
75
%
%
%
elecTrical characTerisTics
(Notes 2, 3) The l denotes the specifications which apply over the
specified operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, RUN = 2V and SS = open, unless
otherwise noted.
LTC3862-2
5
38622f
elecTrical characTerisTics
(Notes 2, 3) The l denotes the specifications which apply over the
specified operating junction temperature range, otherwise specifications are at TA = 25°C. VIN = 12V, RUN = 2V and SS = open, unless
otherwise noted.
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: All currents into device pins are positive; all currents out of device
pins are negative. All voltages are referenced to ground unless otherwise
specified.
Note 3: The LTC3862E-2 is guaranteed to meet performance specifications
from 0°C to 85°C. Specifications over the –40°C to 85°C operating
temperature range are assured by design, characterization and correlation
with statistical process controls. The LTC3862I-2 is guaranteed over the
full –40°C to 125°C operating temperature range and the LTC3862H-2 is
guaranteed over the full –40°C to 150°C operating temperature range.
High junction temperatures degrade operating lifetimes. Operating lifetime
is derated at junction temperatures greater than 125°C.
Note 4: This IC includes overtemperature protection that is intended to
protect the device during momentary overload conditions. Continuous
operation above the specified maximum operating junction temperature
may impair device reliability.
Note 5: Supply current in normal operation is dominated by the current
needed to charge the external MOSFET gates. This current will vary with
supply voltage and the external MOSFETs used.
Note 6: The IC is tested in a feedback loop that adjusts VFB to achieve a
specified error amplifier output voltage.
Note 7: Guaranteed by design, not subject to test.
Note 8: The minimum on-time condition is specified for an inductor peak-
to-peak ripple current = 30% (see Minimum On-Time Considerations in the
Applications Information section).
Note 9: The maximum duty cycle limit is derived from an internal
clock that runs at 12× the programmed switching frequency. See the
Applications Information section for additional information.
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tON(MIN)1 Minimum On-Time VBLANK = 0V (Note 8) 210 ns
tON(MIN)2 Minimum On-Time VBLANK = Float (Note 8) 290 ns
tON(MIN)3 Minimum On-Time VBLANK = 3V8 (Note 8) 375 ns
Gate Driver
RDS(ON) Driver Pull-Up RDS(ON) 3 Ω
Driver Pull-Down RDS(ON) 0.9 Ω
Overvoltage
VFB(OV) VFB, Overvoltage Lockout Threshold VFB(OV) – VFB(NOM) in Percent 8 10 12 %
LTC3862-2
6
38622f
Typical perForMance characTerisTics
Efficiency vs Output Current Load Step Inductor Current at Light Load
Quiescent Current
vs Input Voltage Quiescent Current vs Temperature
Shutdown Quiescent Current
vs Input Voltage
Shutdown Quiescent Current
vs Temperature
LOAD CURRENT (mA)
EFFICIENCY (%)
38622 TA01b
97
87
89
91
93
95
77
79
81
83
85
10 1000100 10000
VIN = 6V
VIN = 9V
VIN = 12V
VIN = 24V
VOUT = 80V
38622 G02
ILOAD
1A/DIV
500mA
TO 1A
ILOAD1
2A/DIV
ILOAD2
2A/DIV
VOUT
1V/DIV
VIN = 24V
VOUT = 72V
400µs/DIV 38622 G03
SW1
50V/DIV
SW2
50V/DIV
IL
1A/DIV
IL
1A/DIV
VIN = 24V
VOUT = 72V
ILOAD = 100mA
1µs/DIV
INPUT VOLTAGE (V)
4
QUIESCENT CURRENT (mA)
2.8
3.2
3.6
4.0
4.4
4.8
5.2
5.6
3632
38622 G04
2.4
2.0
1.6
1.2
0.8
0.4
0
8 12 16 20 2824
TEMPERATURE (°C)
–50
QUIESCENT CURRENT (mA)
1.85
1.90
150
38622 G05
1.80
1.75
1.70
1.65
1.60
1.55
1.50
–25 0 25 50 100 12575
INPUT VOLTAGE (V)
4 8
SHUTDOWN CURRENT (µA)
40
50
36
38622 G06
30
20
10
0
12 16 20 24 3228
TEMPERATURE (°C)
–50
SHUTDOWN CURRENT (µA)
30
40
50
25 75 150
38622 G07
20
10
0
–25 0 50 100 125
VIN = 12V
INTVCC Line Regulation INTVCC Load Regulation
INPUT VOLTAGE (V)
4 8
INTVCC VOLTAGE (V)
6
8
12
10
36
38622 G08
4
2
12 16 20 24 3228
INTVCC LOAD CURRENT (mA)
0
INTVCC VOLTAGE (V)
10.00
10.05
10.10
50
38622 G09
9.95
9.90
10 20 4030
LTC3862-2
7
38622f
Typical perForMance characTerisTics
INTVCC vs Temperature
INTVCC LDO Dropout Voltage
vs Load Current, Temperature
INTVCC UVLO Threshold
vs Temperature
Feedback Voltage vs Temperature
Feedback Voltage Line
Regulation
Current Sense Threshold
vs ITH Voltage
Current Sense Threshold
vs Temperature
Maximum Current Sense
Threshold vs Duty Cycle RUN Threshold vs Temperature
TEMPERATURE (°C)
–50
INTVCC VOLTAGE (V)
10.03
10.04
10.05
25 75 150
38622 G10
10.02
10.01
10.00
9.95
9.96
9.97
9.98
9.99
–25 0 50 100 125
INTVCC LOAD (mA)
0
DROPOUT VOLTAGE (mV)
800
1000
1400
1200
20 50
38622 G11
600
400
200
0
10 30 40
150°C
85°C
25°C
–40°C
125°C
TEMPERATURE (°C)
–50
INTVCC VOLTAGE (V)
4.6
150
38622 G12
4.5
3.6
3.7
3.8
3.9
4.4
4.3
4.2
4.1
4.0
050 100
RISING
FALLING
TEMPERATURE (°C)
–50
1.211
FB VOLTAGE (V)
1.215
1.219
1.223
1.227
1.235
–25 0 25 50
38622 G13
75 100 125 150
1.231
1.213
1.217
1.221
1.225
1.233
1.229
INPUT VOLTAGE (V)
1.220
FB VOLTAGE (V)
1.221
1.222
1.223
1.224
12 20 28 36
38622 G14
1.225
1.226
8 16 24 32
ITH VOLTAGE (V)
CURRENT SENSE THRESHOLD (mV)
50
60
70
38622 G15
30
00 0.4 0.8 1.2 1.6 2.0 2.4
80
40
20
10
TEMPERATURE (°C)
–50
70
CURRENT SENSE THRESHOLD (mV)
71
73
74
75
80
77
050 75
38622 G16
72
78
79
76
–25 25 100 125 150
DUTY CYCLE (%)
0
30
MAXIMUM CURRENT SENSE THRESHOLD (mV)
35
45
50
55
80
65
20 5040 7060
38622 G17
40
70
75
60
10 30 80 90 100
SLOPE = 0.625
SLOPE = 1
SLOPE = 1.66
TEMPERATURE (°C)
–50
1.10
RUN PIN VOLTAGE (V)
1.15
1.20
1.25
1.30
–25 0 25 50
38622 G18
75
ON
OFF
100 125 150
LTC3862-2
8
38622f
Typical perForMance characTerisTics
RUN Threshold vs Input Voltage
RUN (Off) Source Current
vs Temperature
RUN Source Current
vs Input Voltage
RUN (On) Source Current
vs Temperature
Soft-Start Current
vs Soft-Start Voltage
Oscillator Frequency
vs Temperature
Soft-Start Current vs Temperature
Oscillator Frequency
vs Input Voltage RFREQ vs Frequency
INPUT VOLTAGE (V)
0
1.0
RUN PIN VOLTAGE (V)
1.1
1.2
1.3
1.4
1.5
5 10 15 20
38622 G19
25
ON
OFF
30 35 40
TEMPERATURE (°C)
–50
–1.0
RUN PIN CURRENT (µA)
–0.9
–0.7
–0.6
–0.5
0
–0.3
050 75
38622 G20
–0.8
–0.2
–0.1
–0.4
–25 25 100 125 150
TEMPERATURE (°C)
–50
RUN PIN CURRENT (µA)
–4
–2
150
38622 G21
–6
–8 050 100
–25 25 75 125
0
–5
–3
–7
–1
INPUT VOLTAGE (V)
4
RUN PIN CURRENT (µA)
–3
–2
–1
0
16 24 36
38622 G19
–4
–5
–6
8 12 20 28 32
TEMPERATURE (°C)
–50
–5.6
SOFT-START CURRENT (µA)
–5.5
–5.4
–5.3
–5.2
0 50 100 150
38622 G23
–5.1
–5.0
–25 25 75 125
SOFT-START VOLTAGE (V)
0
–6
SOFT-START CURRENT (µA)
–5
–4
–3
–2
1 2 34
38622 G24
–1
0
0.5 1.5 2.5 3.5
TEMPERATURE (°C)
–50
FREQUENCY (kHz)
302
303
304
305
150
38622 G25
301
300
298 050 100
–25 25 75 125
299
307
306
INPUT VOLTAGE (V)
4 8
FREQUENCY (kHz)
300
305
310
315
36
38622 G26
295
290
280 12 20 2816 24 32
285
320
FREQUENCY (kHz)
100
RFREQ (kΩ)
300
1000
38622 G27
10
100
200 1000
900
800700600
500
400
0
LTC3862-2
9
38622f
Typical perForMance characTerisTics
Frequency vs PLLFLTR Voltage
Frequency Pin Voltage
vs Temperature
Minimum On-Time
vs Input Voltage
Minimum On-Time
vs Temperature
Gate Turn-On Waveform Driving
Renesas HAT2267H
Gate Turn-Off Waveform Driving
Renesas HAT2267H
PLLFLTR VOLTAGE (V)
0
1000
1200
1400
2
38622 G28
800
600
0.5 1 1.5 2.5
400
200
0
FREQUENCY (kHz)
TEMPERATURE (°C)
–50
FREQ VOLTAGE (V)
1.223
1.229
1.231
150
38622 G29
1.221
1.219
1.211 050 100
–25 25 75 125
1.215
1.235
1.233
1.227
1.225
1.217
1.213
TEMPERATURE (°C)
–50
130
MINIMUM ON-TIME (ns)
180
230
280
330
0 50 100 150
38622 G30
380
430
–25 25 75 125
BLANK = 3V8
BLANK = FLOAT
BLANK = SGND
INPUT VOLTAGE (V)
4 8
130
MINIMUM ON-TIME (ns)
180
230
280
330
12 20 28 36
38622 G31
380
430
16 24 32
BLANK = 3V8
BLANK = FLOAT
BLANK = SGND
38622 G32
20ns/DIV
VGATE
2V/DIV
VIN = 24V
VOUT = 72V
ILOAD = 0.25A
38622 G33
20ns/DIV
VGATE
2V/DIV
VIN = 24V
VOUT = 72V
ILOAD = 0.25A
LTC3862-2
10
38622f
pin FuncTions
3V8: Output of the Internal 3.8V LDO from INTVCC. Supply
pin for the low voltage analog and digital circuits. A low
ESR 1nF ceramic bypass capacitor should be connected
between 3V8 and SGND, as close as possible to the IC.
BLANK: Blanking Time. Floating this pin provides a nominal
minimum on-time of 290ns. Connecting this pin to 3V8
provides a minimum on-time of 375ns, while connecting
it to SGND provides a minimum on-time of 210ns.
CLKOUT: Digital Output Used for Daisy-Chaining Multiple
LTC3862-2 ICs in Multi-Phase Systems. The PHASEMODE
pin voltage controls the relationship between CH1 and CH2
as well as between CH1 and CLKOUT.
DMAX: Maximum Duty Cycle. This pin programs the
maximum duty cycle. Floating this pin provides 84%
duty cycle. Connecting this pin to 3V8 provides 75% duty
cycle, while connecting it to SGND provides 96% duty
cycle. The maximum duty cycle limit is derived from an
internal clock that runs at 12× the programmed switching
frequency. As a result, the maximum duty cycle limit DMAX
is extremely precise.
FB: Error Amplifier Input. The FB pin should be connected
through a resistive divider network to VOUT to set the
output voltage.
FREQ: A resistor from FREQ to SGND sets the operating
frequency.
GATE1, GATE2: Gate Drive Output. The LTC3862-2 pro-
vides a 10V gate drive referenced to PGND to drive a high
voltage MOSFET.
INTVCC: Output of the Internal 10V Low Dropout Regulator
(LDO). A low ESR 4.7µF (X5R or better) ceramic bypass
capacitor should be connected between INTVCC and PGND,
as close as possible to the IC.
ITH: Error Amplifier Output. The current comparator trip
threshold increases with the ITH control voltage. The ITH
pin is also used for compensating the control loop of the
converter.
PGND: Power Ground. Connect this pin close to the sources
of the power MOSFETs. PGND should also be connected to
the negative terminals of VIN and INTVCC bypass capaci-
tors. PGND is electrically isolated from the SGND pin. The
exposed pad of the QFN and FE packages is connected to
PGND and must be soldered to PCB ground for electrical
contact and rated thermal performance.
PHASEMODE: The PHASEMODE pin voltage programs
the phase relationship between CH1 and CH2 rising gate
signals, as well as the phase relationship between CH1
gate signal and CLKOUT. Floating this pin or connecting
it to either 3V8, or SGND changes the phase relationship
between CH1, CH2 and CLKOUT.
PLLFLTR: PLL Lowpass Filter Input. When synchronizing
to an external clock, this pin serves as the lowpass filter
input for the PLL. A series resistor and capacitor connected
from PLLFLTR to SGND compensate the PLL feedback loop.
RUN: Run Control Input. A voltage above 1.22V on the pin
turns on the IC. Forcing the pin below 1.22V causes the
IC to shut down. There is a 0.5µA pull-up current for this
pin. Once the RUN pin raises above 1.22V, an additional
4.5µA pull-up current is added to the pin for program-
mable hysteresis.
LTC3862-2
11
38622f
pin FuncTions
SENSE1+, SENSE2+: Positive Inputs to the Current
Comparators. The ITH pin voltage programs the current
comparator offset in order to set the peak current trip
threshold. This pin is normally connected to a sense
resistor in the source of the power MOSFET.
SENSE1, SENSE2: Negative Inputs to the Current Com-
parators. This pin is normally connected to the bottom of
the sense resistor.
SGND: Signal Ground. All feedback and soft-start connec-
tions should return to SGND. For optimum load regulation,
the SGND pin should be kelvin connected to the PCB location
between the negative terminals of the output capacitors.
SLOPE: This pin programs the gain of the internal slope
compensation. Floating this pin provides a normalized
slope compensation gain of 1.00. Connecting this pin
to 3V8 increases the normalized slope compensation by
66%, and connecting it to SGND decreases the normal-
ized slope compensation by 37.5%. See the Applications
Information section for more details.
SS: Soft-Start Input. For soft-start operation, connecting
a capacitor from this pin to SGND will clamp the output of
the error amp. An internal 5µA current source will charge
the capacitor and set the rate of increase of the peak switch
current of the converter.
SYNC: PLL Synchronization Input. Applying an external
clock between 50kHz and 650kHz will cause the operating
frequency to synchronize to the clock. SYNC is pulled down
by a 50k internal resistor. The rising edge of the SYNC
input waveform will align with the rising edge of GATE1
in closed-loop operation.
VIN: Main Supply Input. A low ESR ceramic capacitor
should be connected between this pin and SGND.
LTC3862-2
12
38622f
FuncTional DiagraM
+
DMAX
PHASEMODE
FREQ
SLOPE
RFREQ
RC
PLLFLTR
SYNC
CLKOUT
RP
CP
SLOPE
COMPENSATION
SYNC
DETECT
BLANK
SS
3V8
5µA
BLOGIC
BLANK
LOGIC LOGIC
OVER
TEMP BIAS
CSS
CC
CLK1
CLK2
DMAX
OT
OV
OT
UV
SD
1.223V
PSKIP
PSKIP
0.275V
PSKIP
ITRIP
UV
VCO
PWM LATCH
S
R1 Q
OT
UVLO 3.8V
LDO
10V
LDO
UV
SD
BLOGIC
R2
+
+
ICMP RLOOP
V TO I
ITH
RUN
+
OV
OV
1.345V
+
SD
RUN
4.5µA
1.22V
+
EA 0.5µA
SGND
VFB
R1
38622 FD
GATE
3V8
INTVCC
VIN
VIN
PGND
SENSE+
SENSE
DUPLICATE FOR
SECOND CHANNEL
CVCC
CIN
COUT
VOUT
C3V8
M
D
L
R2
RS
LTC3862-2
13
38622f
operaTion
The Control Loop
The LTC3862-2 uses a constant frequency, peak current
mode step-up architecture with its two channels operat-
ing 180 degrees out-of-phase. During normal operation,
each external MOSFET is turned on when the clock for
that channel sets the PWM latch, and is turned off when
the main current comparator, ICMP, resets the latch. The
peak inductor current at which ICMP trips and resets the
latch is controlled by the voltage on the ITH pin, which is
the output of the error amplifier, EA. The error amplifier
compares the output feedback signal at the VFB pin to the
internal 1.223V reference and generates an error signal
at the ITH pin. When the load current increases it causes
a slight decrease in VFB relative to the reference voltage,
which causes the EA to increase the ITH voltage until the
average inductor current matches the new load current.
After the MOSFET is turned off, the inductor current flows
through the boost diode into the output capacitor and load,
until the beginning of the next clock cycle.
Cascaded LDOs Supply Power to the Gate Driver and
Control Circuitry
The LTC3862-2 contains two cascaded PMOS output stage
low dropout voltage regulators (LDOs), one for the gate
drive supply (INTVCC) and one for the low voltage analog
and digital control circuitry (3V8). A block diagram of this
power supply arrangement is shown in Figure 1.
The Gate Driver Supply LDO (INTVCC)
The 10V output (INTVCC) of the first LDO is powered from
VIN and supplies power to the power MOSFET gate driv-
ers. The INTVCC pin should be bypassed to PGND with a
minimum of 4.7μF of ceramic capacitance (X5R or better),
placed as close as possible to the IC pins. If two power
MOSFETs are connected in parallel for each channel in
order to increase the output power level, or if a single
MOSFET with a QG greater than 50nC is used, then it is
recommended that the bypass capacitance be increased
to a minimum of 10μF.
An undervoltage lockout (UVLO) circuit senses the INTVCC
regulator output in order to protect the power MOSFETs from
operating with inadequate gate drive. For the LTC3862-2
the rising UVLO threshold is typically 4.4V and the hys-
teresis is typically 500mV. The LTC3862-2 was optimized
for high voltage power MOSFETs with RDS(ON) ratings at
a VGS of 6V. For applications requiring logic-level power
MOSFETs, please refer to the LTC3862 data sheet.
Figure 1. Cascaded LDOs Provide Gate Drive and Control Circuitry Power
+
SGND
R2 R1
1.223V
LTC3862-2
INTVCC
3V8
GATE
+
SGND
R4 R3
1.223V
P-CH
P-CH
ANALOG
CIRCUITS LOGIC
INTVCC
VIN
CIN
CVCC
C3V8
38622 F01
PGND
3V8
SGND
NOTE: PLACE CVCC AND C3V8 CAPACITORS AS CLOSE AS POSSIBLE TO DEVICE PINS
LTC3862-2
14
38622f
operaTion
In multi-phase applications, all of the FB pins are connected
together and all of the error amplifier output pins (ITH) are
connected together. The INTVCC pins, however, should not
be connected together. The INTVCC regulator is capable of
sourcing current but is not capable of sinking current. As
a result, when two or more INTVCC regulator outputs are
connected together, the highest voltage regulator supplies
all of the gate drive and control circuit current, and the
other regulators are off. This would place a thermal burden
on the highest output voltage LDO and could cause the
maximum die temperature to be exceeded. In multi-phase
LTC3862-2 applications, each INTVCC regulator output
should be independently bypassed to its respective PGND
pin as close as possible to each IC.
The Low Voltage Analog and Digital Supply LDO (3V8)
The second LDO within the LTC3862-2 is powered off
of INTVCC and serves as the supply to the low voltage
analog and digital control circuitry, as shown in Figure 1.
The output voltage of this LDO (which also has a PMOS
output device) is 3.8V. Most of the analog and digital con-
trol circuitry is powered from the internal 3V8 LDO. The
3V8 pin should be bypassed to SGND with a 1nF ceramic
capacitor (X5R or better), placed as close as possible
to the IC pins. This LDO is not intended to be used as a
supply for external circuitry.
Thermal Considerations and Package Options
The LTC3862-2 is offered in three package options. The
5mm × 5mm QFN package (UH24) has a thermal resistance
RTH(JA) of 34°C/W, the 24-pin TSSOP (FE24) package has a
thermal resistance of 38°C/W, and the 24-pin SSOP (GN24)
package has a thermal resistance of 85°C/W. The QFN and
TSSOP package options have a lead pitch of 0.65mm, and
the GN24 option has a lead pitch of 0.025in.
The INTVCC regulator can supply up to 50mA of total
current. As a result, care must be taken to ensure that
the maximum junction temperature of the IC is never
exceeded. The junction temperature can be estimated
using the following equations:
IQ(TOT) = IQ + QG(TOT) • f
PDISS = VIN • (IQ + QG(TOT) • f)
TJ = TA + PDISS • RTH(JA)
The total quiescent current (IQ(TOT)) consists of the static
supply current (IQ) and the current required to charge
the gate capacitance of the power MOSFETs. The value
of QG(TOT) should come from the plot of VGS vs QG in the
Typical Performance Characteristics section of the MOSFET
data sheet. The value listed in the electrical specifications
may be measured at a higher VGS, such as 15V, whereas
the value of interest is at the 10V INTVCC gate drive voltage.
As an example of the required thermal analysis, consider a
2-phase boost converter with a 5.5V to 24V input voltage
range and an output voltage of 72V at 1.5A. The switching
frequency is 150kHz and the maximum ambient tempera-
ture is 70°C. The power MOSFET used for this application
is the Renesas HAT2267H, which has a typical RDS(ON) of
13mΩ at VGS = 10V. From the plot of VGS vs QG, the total
gate charge at VGS = 10V is 30nC (the temperature coef-
ficient of the gate charge is low). One power MOSFET is
used for each phase. For the QFN package option:
IQ(TOT) = 3mA + 2 • 30nC • 150kHz = 12mA
PDISS = 24V • 12mA = 288mW
TJ = 70°C + 288mW • 34°C/W = 79.8°C
In this example, the junction temperature rise is only 9.8°C.
These equations demonstrate how the gate charge current
typically dominates the quiescent current of the IC, and
how the choice of package option and board heat sinking
can have a significant effect on the thermal performance
of the solution.
LTC3862-2
15
38622f
operaTion
To prevent the maximum junction temperature from be-
ing exceeded, the input supply current to the IC should
be checked when operating in continuous mode (heavy
load) at maximum VIN. A trade-off between the operat-
ing frequency and the size of the power MOSFETs may
need to be made in order to maintain a reliable junction
temperature. Finally, it is important to verify the calcula-
tions by performing a thermal analysis of the final PCB
using an infrared camera or thermal probe. As an option,
an external regulator shown in Figure 3 can be used to
reduce the total power dissipation on the IC.
Thermal Shutdown Protection
In the event of an overtemperature condition (external
or internal), an internal thermal monitor will shut down
the gate drivers and reset the soft-start capacitor if the
die temperature exceeds 170°C. This thermal sensor has
a hysteresis of 10°C to prevent erratic behavior at hot
temperatures. The LTC3862-2’s internal thermal sen-
sor is intended to protect the device during momentary
overtemperature conditions. Continuous operation above
the specified maximum operating junction temperature,
however, may result in device degradation.
Operation at Low Supply Voltage
The LTC3862-2 has a minimum input voltage of 5.5V,
making it a good choice for applications that require high
voltage power MOSFETs with 6V RDS(ON) ratings. The gate
driver for the LTC3862-2 consists of PMOS pull-up and
NMOS pull-down devices, allowing the full INTVCC voltage
to be applied to the gates during power MOSFET switch-
ing. Nonetheless, care should be taken to determine the
minimum gate drive supply voltage (INTVCC) in order to
choose the optimum power MOSFETs. Important param-
eters that can affect the minimum gate drive voltage are
the minimum input voltage (VIN(MIN)), the LDO dropout
voltage, the QG of the power MOSFETs, and the operating
frequency.
If the input voltage VIN is low enough for the INTVCC LDO
to be in dropout, then the minimum gate drive supply
voltage is:
VINTVCC = VIN(MIN) – VDROPOUT
The LDO dropout voltage is a function of the total gate
drive current and the quiescent current of the IC (typically
3mA). A curve of dropout voltage vs output current for the
LDO is shown in Figure 2. The temperature coefficient of
the LDO dropout voltage is approximately 6000ppm/°C.
The total Q-current (IQ(TOT)) flowing in the LDO is the sum
of the controller quiescent current (3mA) and the total gate
charge drive current.
IQ(TOT) = IQ + QG(TOT) • f
After the calculations have been completed, it is impor-
tant to measure the gate drive waveforms and the gate
driver supply voltage (INTVCC to PGND) over all operating
conditions (low VIN, nominal VIN and high VIN, as well
as from light load to full load) to ensure adequate power
MOSFET enhancement. Consult the power MOSFET data
sheet to determine the actual RDS(ON) for the measured
VGS, and verify your thermal calculations by measuring
the component temperatures using an infrared camera
or thermal probe.
Figure 2. INTVCC LDO Dropout Voltage vs Current
INTVCC LOAD (mA)
0
DROPOUT VOLTAGE (mV)
800
1000
1400
1200
20 50
38622 F02
600
400
200
0
10 30 40
150°C
85°C
25°C
–40°C
125°C
LTC3862-2
16
38622f
operaTion
Operation at High Supply Voltage
At high input voltages, the LTC3862-2’s internal LDO
can dissipate a significant amount of power, which could
cause the maximum junction temperature to be exceeded.
Conditions such as a high operating frequency, or the use
of more than one power MOSFET per channel, could push
the junction temperature rise to high levels. If the thermal
equations above indicate too high a rise in the junction
temperature, an external bias supply can always be used
to reduce the power dissipation on the IC, as shown in
Figure 3.
For example, a 12V system rail that is available would be
more suitable than the 24V main input power rail to power
the LTC3862-2. Also, the bias power can be generated with
a separate switching or LDO regulator. An example of an
LDO regulator is shown in Figure 3. The output voltage
of the LDO regulator can be set by selecting an appropri-
ate zener diode to be higher than 10V but low enough to
divide the power dissipation between LTC3862-2 and Q1
in Figure 3. The absolute maximum voltage rating of the
INTVCC pin is 11V.
supplies. Independently biasing the INTVCC pin from a
separate power supply can cause one of two possible
failure modes during supply sequencing. If the INTVCC
supply comes up before the VIN supply, high current will
flow from the external INTVCC supply, through the body
diode of the LDO PMOS device, to the input capacitor
and VIN pin. This high current flow could trigger a latchup
condition and cause catastrophic failure of the IC.
If, however, the VIN supply to the IC comes up before the
INTVCC supply, the external INTVCC supply will act as a
load to the internal LDO in the LTC3862-2, and the LDO will
attempt to charge the INTVCC output with its short-circuit
current. This will result in excessive power dissipation and
possible thermal overload of the LTC3862-2.
Programming the Output Voltage
The output voltage is set by a resistor divider according
to the following formula:
VOUT =1.223V 1+R2
R1
The external resistor divider is connected to the output
as shown in Figure 4. Resistor R1 is normally chosen so
that the output voltage error caused by the current flowing
out of the VFB pin during normal operation is negligible
compared to the current in the divider. For an output volt-
age error due to the error amp input bias current of less
than 0.5%, this translates to a maximum value of R1 of
about 30k.
Figure 3. Using the LTC3862-2 with an External Bias Supply
Figure 4. Programming the Output Voltage
with a Resistor Divider
Power Supply Sequencing
As shown in Figure 1, there are body diodes in parallel with
the PMOS output transistors in the two LDO regulators
in the LTC3862-2. As a result, it is not possible to bias
the INTVCC and VIN pins of the chip from separate power
VIN
R1
Q1
D1
CVCC
38622 F03
LTC3862-2
VIN
INTVCC
LTC3862-2
FB
SGND
R2
R1
38622 F04
VOUT
LTC3862-2
17
38622f
operaTion
Operation of the RUN Pin
The control circuitry in the LTC3862-2 is turned on and
off using the RUN pin. Pulling the RUN pin below 1.22V
forces shutdown mode and releasing it allows a 0.5μA
current source to pull this pin up, allowing a “normally
on” converter to be designed. Alternatively, the RUN pin
can be externally pulled up or driven directly by logic.
Care must be taken not to exceed the absolute maximum
rating of 8V for this pin.
The comparator on the RUN pin can also be used to sense
the input voltage, allowing an undervoltage detection
circuit to be designed. This is helpful in boost converter
applications where the input current can reach very high
levels at low input voltage:
IIN =
I
OUT
V
OUT
VIN
The 1.22V input threshold of the RUN comparator is derived
from a precise bandgap reference, in order to maximize
the accuracy of the undervoltage-sensing function. The
RUN comparator has 80mV built-in hysteresis. When the
voltage on the RUN pin exceeds 1.22V, the current sourced
into the RUN pin is switched from 0.5μA to 5μA PTAT
(proportional to absolute temperature) current. The user
can therefore program both the rising threshold and the
amount of hysteresis using the values of the resistors in
the external divider, as shown in the following equations:
VIN(ON) =1.22V 1+RA
RB
0.5µ RA
VIN(OFF) =1.22V 1+RA
RB
5µ RA
Several of the possible RUN pin control techniques are
illustrated in Figure 5.
Frequency Selection and the Phase-Locked Loop
The selection of the switching frequency is a trade-off
between efficiency and component size. Low frequency
operation increases efficiency by reducing MOSFET
switching losses, but requires a larger inductor and output
capacitor to maintain low output ripple.
Figure 5a. Using the RUN Pin for a “Normally On” Converter
Figure 5b. On/Off Control Using External Logic
Figure 5c. Programming the Input Voltage Turn-On and Turn-Off
Thresholds Using the RUN Pin
+
RUN
COMPARATOR
1.22V
38622 F05a
VIN LTC3862-2
RUN
10V
INTERNAL 5V
0.5µA 4.5µA
SGND
BIAS AND
START-UP
CONTROL
+
RUN
COMPARATOR
1.22V
38622 F05b
VIN LTC3862-2
RUN
10V
INTERNAL 5V
EXTERNAL
LOGIC
CONTROL 0.5µA 4.5µA
SGND
BIAS AND
START-UP
CONTROL
+
RUN
COMPARATOR
1.22V
38622 F05c
VIN LTC3862-2
RUN
10V
INTERNAL 5V
0.5µA
RA
4.5µA
SGND
BIAS AND
START-UP
CONTROL
RB
LTC3862-2
18
38622f
operaTion
The LTC3862-2 uses a constant frequency architecture that
can be programmed over a 75kHz to 500kHz range using
a single resistor from the FREQ pin to ground. Figure 6
illustrates the relationship between the FREQ pin resistance
and the operating frequency.
The operating frequency of the LTC3862-2 can be ap-
proximated using the following formula:
RFREQ = 5.5096E9(fOSC)–0.9255
A phase-lock loop is available on the LTC3862-2 to syn-
chronize the internal oscillator to an external clock source
connected to the SYNC pin. Connect a series RC network
from the PLLFLTR pin to SGND to compensate PLLs
feedback loop. Typical compensation components are a
0.01μF capacitor in series with a 10k resistor. The PLLFLTR
pin is both the output of the phase detector and the input
to the voltage controlled oscillator (VCO). The LTC3862-2
phase detector adjusts the voltage on the PLLFLTR pin
to align the rising edge of GATE1 to the leading edge of
the external clock signal, as shown in Figure 7. The ris-
ing edge of GATE2 will depend upon the voltage on the
PHASEMODE pin. The capture range of the LTC3862-2’s
PLL is 50kHz to 650kHz.
Because the operating frequency of the LTC3862-2 can be
programmed using an external resistor, in synchronized
applications, it is recommended that the free-running fre-
quency (as defined by the external resistor) be set to the
same value as the synchronized frequency. This results in
a start-up of the IC at approximately the same frequency
as the external clock, so that when the sync signal comes
alive, no discontinuity at the output will be observed. It also
ensures that the operating frequency remains essentially
constant in the event the sync signal is lost. The SYNC
pin has an internal 50k resistor to ground.
Using the CLKOUT and PHASEMODE Pins
in Multi-Phase Applications
The LTC3862-2 features two pins (CLKOUT and PHASE-
MODE) that allow multiple ICs to be daisy-chained together
for higher current multi-phase applications. For a 3- or
4-phase design, the CLKOUT signal of the master controller
is connected to the SYNC input of the slave controller in
order to synchronize additional power stages for a single
Figure 6. FREQ Pin Resistor Value vs Frequency
Figure 7. Synchronization of the LTC3862-2
to an External Clock Using the PLL
high current output. The PHASEMODE pin is used to adjust
the phase relationship between channel 1 and channel 2,
as well as the phase relationship between channel 1 and
CLKOUT, as summarized in Table 1. The phases are cal-
culated relative to the zero degrees, defined as the rising
edge of the GATE1 output. In a 6-phase application the
CLKOUT pin of the master controller connects to the SYNC
input of the 2nd controller and the CLKOUT pin of the 2nd
controller connects to the SYNC pin of the 3rd controller.
Table 1
PHASEMODE
CH-1 to CH-2
PHASE
CH-1 to CLKOUT
PHASE
APPLICATION
SGND 180° 90° 2-Phase, 4-Phase
Float 180° 60° 6-Phase
3V8 120° 240° 3-Phase
FREQUENCY (kHz)
100
RFREQ (kΩ)
300
1000
38622 F06
10
100
200 1000
900
800700600
500
400
0
SYNC
10V/DIV
GATE1
20V/DIV
GATE2
20V/DIV
CLKOUT
10V/DIV
2µs/DIVVIN = 24V
VOUT = 72V
IOUT = 0.5A
PHASEMODE = SGND
38622 F07
LTC3862-2
19
38622f
operaTion
Using the LTC3862-2 Transconductance (gm) Error
Amplifier in Multi-Phase Applications
The LTC3862-2 error amplifier is a transconductance, or gm
amplifier, meaning that it has high DC gain but high output
impedance (the output of the error amplifier is a current
proportional to the differential input voltage). This style
of error amplifier greatly eases the task of implementing
a multi-phase solution, because the amplifiers from two
or more chips can be connected in parallel. In this case
the FB pins of multiple LTC3862-2s can be connected to-
gether, as well as the ITH pins, as shown in Figure 8. The
gm of the composite error amplifier is simply n times the
transconductance of one amplifier, or gm(TOT) = n 660μS,
where n is the number of amplifiers connected in paral-
lel. The transfer function from the ITH pin to the current
comparator inputs was carefully designed to be accurate,
both from channel-to-channel and chip-to-chip. This way
the peak inductor current matching is kept accurate.
A buffered version of the output of the error amplifier deter-
mines the threshold at the input of the current comparator.
The ITH voltage that represents zero peak current is 0.4V
and the voltage that represents current limit is 1.2V (at
low duty cycle). During an overload condition, the output
of the error amplifier is clamped to 2.6V at low duty cycle,
in order to reduce the latency when the overload condition
terminates. A patented circuit in the LTC3862-2 is used
to recover the slope compensation signal, so that the
maximum peak inductor current is not a strong function
of the duty cycle.
In multi-phase applications that use more than one
LTC3862-2 controller, it is possible for ground currents
on the PCB to disturb the control lines between the ICs,
resulting in erratic behavior. In these applications the FB
pins should be connected to each other through 100Ω
resistors and each slave FB pin should be decoupled locally
with a 100pF capacitor to ground, as shown in Figure 8.
Soft-Start
The start-up of the LTC3862-2 is controlled by the volt-
age on the SS pin. An internal PNP transistor clamps the
current comparator sense threshold during soft-start,
thereby limiting the peak switch current. The base of the
PNP is connected to the SS pin and the emitter to an
Figure 8. LTC3862-2 Error Amplifier Configuration
for Multi-Phase Operation
internal, buffered ITH node (please note that the ITH pin
voltage may not track the soft-start voltage during this time
period). An internal 5μA current source charges the SS
capacitor, and clamps the peak sense threshold until the
voltage on the soft-start capacitor reaches approximately
0.6V. The required amount of soft-start capacitance can
be estimated using the following equation:
CSS =5µA tSS
0.6V
The SS pin has an internal open-drain NMOS pull-down
transistor that turns on when the RUN pin is pulled low,
when the voltage on the INTVCC pin is below its under-
voltage lockout threshold, or during an overtemperature
condition. In multi-phase applications that use more than
FREQ
FB
CLKOUT
SYNC
PLLFLTR
LTC3862-2
MASTER
SGND
ITH
VOUT
INTVCC
SS
PHASEMODE
RUN ON/OFF
CONTROL
ALL RUN PINS
CONNNECTED
TOGETHER
INDIVIDUAL
INTVCC PINS
LOCALLY
DECOUPLED
FREQ
FB
CLKOUT
SYNC
PLLFLTR
LTC3862-2
SLAVE
SGND
ITH
INTVCC
SS
RUN
SLAVE
38622 F08
ALL SS PINS
CONNNECTED
TOGETHER
**
FB
ALL FB PINS
CONNECTED
TOGETHER
ALL ITH PINS
CONNECTED
TOGETHER
CLKOUT
* R = 100Ω
CX = 100pF
SYNC
PLLFLTR
LTC3862-2
SGND
ITH
INTVCC
SS
RUN
**
PHASEMODE
PHASEMODE
LTC3862-2
20
38622f
operaTion
one LTC3862-2 chip, connect all of the SS pins together
and use one external capacitor to program the soft-start
time. In this case, the current into the soft-start capaci-
tor will be ISS = n 5μA, where n is the number of SS
pins connected together. Figure 9 illustrates the start-up
waveforms for a 2-phase LTC3862-2 application.
an excessively large inductor would result in too much
effective slope compensation, and the converter could
become unstable. Likewise, if too small an inductor were
used, the internal ramp compensation could be inadequate
to prevent subharmonic oscillation.
The LTC3862-2 contains a pin that allows the user to
program the slope compensation gain in order to opti-
mize performance for a wider range of inductance. With
the SLOPE pin left floating, the normalized slope gain is
1.00. Connecting the SLOPE pin to ground reduces the
normalized gain to 0.625 and connecting this pin to the
3V8 supply increases the normalized slope gain to 1.66.
With the normalized slope compensation gain set to 1.00,
the design equations assume an inductor ripple current of
20% to 40%, as with previous designs. Depending upon
the application circuit, however, a normalized gain of 1.00
may not be optimum for the inductor chosen. If the ripple
current in the inductor is greater than 40%, the normalized
slope gain can be increased to 1.66 (an increase of 66%)
by connecting the SLOPE pin to the 3V8 supply. If the
inductor ripple current is less than 20%, the normalized
slope gain can be reduced to 0.625 (a decrease of 37.5%)
by connecting the SLOPE pin to SGND.
To check the effectiveness of the slope compensation, apply
a load step to the output and monitor the cycle-by-cycle
behavior of the inductor current during the leading and
trailing edges of the load current. Vary the input voltage
over its full range and check for signs of cycle-by-cycle
SW node instability or subharmonic oscillation. When the
Figure 9. Typical Start-Up Waveforms for a
Boost Converter Using the LTC3862-2
Figure 10. Light Load Switching Waveforms for
the LTC3862-2 at the Onset of Pulse-Skipping
Pulse-Skipping Operation at Light Load
As the load current is decreased, the controller enters
discontinuous mode (DCM). The peak inductor current can
be reduced until the minimum on-time of the controller
is reached. Any further decrease in the load current will
cause pulse-skipping to occur, in order to maintain output
regulation, which is normal. The minimum on-time of the
controller in this mode is approximately 210ns (with the
blanking time set to its minimum value), the majority of
which is leading edge blanking. Figure 10 illustrates the
LTC3862-2 switching waveforms at the onset of pulse-
skipping.
Programmable Slope Compensation
For a current mode boost regulator operating in CCM,
slope compensation must be added for duty cycles above
50%, in order to avoid subharmonic oscillation. For the
LTC3862-2, this ramp compensation is internal and user
adjustable. Having an internally fixed ramp compensation
waveform normally places some constraints on the value
of the inductor and the operating frequency. For example,
with a fixed amount of internal slope compensation, using
RUN
5V/DIV
VOUT
100V/DIV
IL1
2A/DIV
IL2
2A/DIV
1ms/DIVVIN = 24V
VOUT = 72V
RL = 100Ω
38622 F09
SW1
50V/DIV
SW2
50V/DIV
IL1
500mA/DIV
IL2
500mA/DIV
2µs/DIV 38622 F10
VIN = 51V
VOUT = 72V
LIGHT LOAD (10mA)
LTC3862-2
21
38622f
operaTion
Figure 12. Effect of Slope Gain on the Peak SENSE Threshold
slope compensation is too low the converter can suffer
from excessive jitter or, worst case, subharmonic oscil-
lation. When excess slope compensation is applied to
the internal current sense signal, the phase margin of the
control loop suffers. Figure 11 illustrates inductor current
waveforms for a properly compensated loop.
The LTC3862-2 contains a patented circuit whereby most
of the applied slope compensation is recovered, in order
to provide a SENSE+ to SENSE threshold which is not
a strong function of the duty cycle. This sense threshold
is, however, a function of the programmed slope gain, as
shown in Figure 12. The data sheet typical specification of
75mV for SENSE+ minus SENSE is measured at a normal-
ized slope gain of 1.00 at low duty cycle. For applications
where the normalized slope gain is not 1.00, use Figure 12
to determine the correct value of the sense resistor.
Programmable Blanking and the Minimum On-Time
The BLANK pin on the LTC3862-2 allows the user to program
the amount of leading edge blanking at the SENSE pins.
Connecting the BLANK pin to SGND results in a minimum
on-time of 210ns, floating the pin increases this time to
290ns, and connecting the BLANK pin to the 3V8 supply
results in a minimum on-time of 375ns. The majority of the
minimum on-time consists of this leading edge blanking,
due to the inherently low propagation delay of the current
comparator (25ns typ) and logic circuitry (10ns to 15ns).
The purpose of leading edge blanking is to filter out noise on
the SENSE pins at the leading edge of the power MOSFET
turn-on. During the turn-on of the power MOSFET the gate
drive current, the discharge of any parasitic capacitance
on the SW node, the recovery of the boost diode charge,
and parasitic series inductance in the high di/dt path all
contribute to overshoot and high frequency noise that could
cause false-tripping of the current comparator. Due to the
wide range of applications the LTC3862-2 is well-suited
to, fixing one value of the internal leading edge blanking
time would have required the longest delay time to have
been used. Providing a means to program the blank time
allows users to optimize the SENSE pin filtering for each
application. Figure 13 illustrates the effect of the program-
mable leading edge blank time on the minimum on-time
of a boost converter.
Programmable Maximum Duty Cycle
In order to maintain constant frequency and a low output
ripple voltage, a single-ended boost (or flyback or SEPIC)
converter is required to turn off the switch every cycle
for some minimum amount of time. This off-time allows
the transfer of energy from the inductor to the output
capacitor and load, and prevents excessive ripple current
and voltage. For inductor-based topologies like boost and
SEPIC converters, having a maximum duty cycle as close
as possible to 100% may be desirable, especially in low
VIN to high VOUT applications. However, for transformer-
based solutions, having a maximum duty cycle near 100%
is undesirable, due to the need for V sec reset during the
primary switch off-time.
Figure 11. Inductor Current Waveforms for a
Properly Compensated Control Loop
ILOAD
1A/DIV
VOUT
2V/DIV
IL1
1A/DIV
IL2
1A/DIV
20µs/DIV 38622 F11
VIN = 24V
VOUT = 72V
DUTY CYCLE (%)
30
MAXIMUM CURRENT SENSE THRESHOLD (mV)
60
70
80
55
50
45
40
35
65
75
20 40 60 80
38622 F12
100100 30 50 70 90
SLOPE = 0.625
SLOPE = 1
SLOPE = 1.66