1
Microsemi Corporation Confidential and Proprietary
Description
The ZL38067 is part of Microsemi's Timberwolf audio
processor family of products that combines the
company's innovative AcuEdge™ acoustic technology
with Sensory's Truly Handsfree™ Voice Control.
Microsemi ZL38067 improves Automatic Speech
Recognition (ASR) performance at extended distances
with barge-in capability and optimize for detecting
voice commands.
The Microsemi AcuEdge Technology ZL38067 device
is ideal for Connected Home applications. The device
is capable of both voice control and 2-way full duplex
audio with voice enhancements such as Acoustic Echo
Cancellation (AEC), Noise Reduction (NR) to improve
both the intelligibility and subjective quality of voice in
harsh acoustic environments.
Microsemi offers additional tools to speed up the
product development cycle. The MiTuner™ ZLS38508
or ZLS38508LITE GUI software packages allow a user
to interactively configure the ZL38067 device. The
optional ZLE38470BADA Automatic Tuning Kit
provides automatic tuning and easy control for manual
fine tuning adjustments.
Applications
• Integrated smart home gateways
• Connected home devices:
• Thermostats
• Smart Speakers
• Security Systems
• Digital Assistants
• Alarm Clock/Radio Units
Microsemi AcuEdge Technology
ZLS38067 Firmware
There are three Firmware images that may be selected
to provide the desired operating mode. Firmware
images can be swapped during normal operation to
switch modes dynamically. Firmware image size varies
with firmware load.
ZLS38067.1 (Stand-alone ASR)
• Detection of a fixed trigger in ‘spotting’ mode
(ability to detect trigger even in continuous
speech).
• Detection of up to 20 command phrases after the
trigger detection.
• Generation of a wake-on-trigger signal to wake up
another device to enable full-duplex voice
communication.
ZLS38067.2 (ASR with Barge-In)
• All of the features of the ZLS38067.1 for a trigger
and up to 10 command phrases, PLUS:
• Support for Barge-in, or incoming trigger
‘spotting’, even in the presence of DAC audio
output
• Enhanced far field support for distances up to 16
feet from the microphone.
• Command phrase demarcation to assist in
framing audio samples for cloud-ASR streaming.
ZLS38067.0 (Full Duplex Communication)
• Full Narrowband and Wideband Acoustic Echo
cancellation operation
• Supports long tail AEC (up to 256 ms)
• Non-Linear AEC provides higher tolerance for
speaker distortions
• Non-Linear processor
• Howling detection/cancellation
• Prevents oscillation in AEC audio path
Document ID# 155522 Version 3 December 2016
Ordering Information
Device OPN Package Packing
ZL38067LDF1 64-pin QFN (9x9) Tape & Reel
ZL38067LDG1 64-pin QFN (9x9) Tray
ZL38067UGB2 56-ball WLCSP (3.1x3.1) Tape & Reel
These packages meet RoHS 2 Directive 2011/65/EU of the European Council
to minimize the environmental impact of electrical equipment.
Timberwolf Digital Signal Processor family,
powered by AcuEdge™ Technology
Automatic Speech Recognition
ZL38067
Preliminary Data Sheet
2
Microsemi Corporation Confidential and Proprietary
• G.168 Line Echo Canceller
• Advanced noise reduction reduces background
noise from the near-end speech signal using
Psychoacoustic techniques
• Provisions for stereo audio mixing (sample rate of
44.1 or 48 kHz) and stereo music record and
playback (sample rate of 48 kHz) with 8 kHz or
16 kHz voice processing
• Various encoding/decoding options:
• 16-bit linear, G.722, G.711 A/μlaw
• Send and receive path equalizers
• Caller ID Type 1 & 2
• Programmable tone generation
• DTMF detection
• Dual 16-bit digital-to-analog converters (DAC)
• Sampling up to 48 kHz and internal output
drivers
• Headphone amps capable of 4 single-ended or
2 differential outputs
• 32 mW output drive power into 16 ohms
• Impulse pop/click protection
• 1 Digital Microphone input supporting
1 or 2 Microphones
• 2 TDM ports shared between PCM and
Inter-IC Sound (I2S)
• Each port can be a clock master or a slave
• Each port supports delayed and non-delayed
(GCI) timing and I2S normal and left justified
modes
• Each port provides sample rate conversion
and synchronous TDM bus operation
ZL38067 Hardware Features
• DSP with Voice Hardware Accelerators
•SPI or I
2C Slave port for host processor interface
• General purpose UART port for debug
• Master SPI port for serial Flash interface
• Boots from SPI or Flash
• Flash firmware can be updated from SPI Slave
• 14 General Purpose Input/Output (GPIO) pins (11
with the 56 pin WLCSP)
• 2 low power modes controlled by reset
The MiTuner™ Automatic Tuning Kit and
ZLS38508 MiTuner GUI
Microsemi's Automatic Tuning Kit option includes:
• Audio Interface Box hardware
• Microphone and Speaker
• ZLS38508 MiTuner GUI software
• Allows tuning of Microsemi's AcuEdge
Technology Audio Processor
The ZLS38508 software features:
• Auto Tuning and Subjective Tuning support
• Provides visual representations of the audio paths
with drop-down menus to program parameters,
allowing:
• Control of the audio routing configuration
• Programming of key blocks in the transmit (Tx)
and receive (Rx) audio paths
• Setting analog and digital gains
• Configuration parameters allow users to “fine
tune” the overall performance
Tools
• ZLK38000 Evaluation Kit
•MiTuner™ ZLS38508 and ZLS38508LITE GUI
•MiTuner™ ZLE38470BADA Automatic Tuning Kit
Timberwolf Digital Signal Processor family,
powered by AcuEdge™ Technology
Automatic Speech Recognition
ZL38067
Data Sheet
ZL38067 Preliminary Data Sheet
Table of Contents
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Microsemi Corporation Confidential and Proprietary
1.0 ZL38067 Device Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.0 Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1 Full Duplex Communication Mode (ZL38067.0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2 ASR Mode (ZL38067.1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3 Barge-in Mode (ZL38067.2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.0 Audio Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1 Digital Microphone Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.1 ASR Modes (ZLS38067.1 or ZLS38067.2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.1.2 Full Duplex Communication Mode (ZLS38067.0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1.3 Analog Microphone Use. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2 DAC Output - Full Duplex Communication Mode (ZLS38067.0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.1 Output Driver Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3 DAC and Reference Bias Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.0 Digital Interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1 TDM Interface - Full Duplex Communication Mode (ZLS38067.0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
4.1.1 I2S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.1.2 PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.1.3 GCI Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2 Cross Point Switch - Full Duplex Communication Mode (ZLS38067.0) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.3 Host Bus Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.1 SPI Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3.2 I2C Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3.3 UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.3.4 Host Interrupt Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4 Master SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4.1 Flash Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.4.1.1 Flash Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.5 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5.0 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
6.0 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1 Power Supply Sequencing/Power up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.1 Power Supply Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.1.1 External +1.2 V Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.1.1.2 Internal +1.2 V Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
6.1.1.3 Ultra-Low Power Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
7.0 Device Booting and Firmware Swapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.1 Boot Loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.2 Bootstrap Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.3 Loadable Device Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
7.3.1 Boot Speed . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
7.4 Bootup Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
8.0 Device Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.1 64-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8.2 56-Ball WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
9.0 Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.0 Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.1 Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.2 Thermal Resistance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.3 Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.4 Device Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.4.1 Normal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
ZL38067 Preliminary Data Sheet
Table of Contents
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Microsemi Corporation Confidential and Proprietary
10.4.2 Low-Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.4.3 Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.4.4 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.4.5 Ultra-Low Power. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.4.6 Current Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
10.5 DC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.6 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.6.1 Microphone Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
10.6.2 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
10.7 External Clock Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
10.7.1 Crystal Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.7.2 Clock Oscillator Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
10.7.3 PCLKA (Crystal-less) Application. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
10.7.4 AC Specifications - External Clocking Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.0 Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
11.1 TDM Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.1.1 GCI and PCM Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
11.1.2 I2S Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.1.2.1 I2S Slave . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
11.1.2.2 I2S Master . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
11.2 Host Bus Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.2.1 SPI Slave Port Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
11.2.2 I2C Slave Interface Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
11.3 UART Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
11.4 Master SPI Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
12.0 AEC Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
13.0 Package Outline Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
14.0 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
ZL38067 Preliminary Data Sheet
5
Microsemi Corporation Confidential and Proprietary
Figure 1 - Alert Monitoring and Wideband Intercom Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 2 - ZL38067 ASR Audio Processor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 3 - Stand-alone and Barge-in ASR Digital Microphone Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 4 - Single Mono Digital Microphone Interface - Full Duplex Communications Firmware . . . . . . . . . . . . . . 11
Figure 5 - Dual Microphone or Stereo Digital Microphone Interface - Full Duplex Communications Firmware . . . 11
Figure 6 - ECM Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 7 - Audio Output Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 8 - ZL38067 Bias Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9 - I2S Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 10 - Left Justified Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 11 - Dual Codec Configuration - Full Duplex Communications Firmware. . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12 - TDM - PCM Slave Functional Timing Diagram (8-bit, xeDX = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13 - TDM - PCM Slave Functional Timing Diagram (8-bit, xeDX = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14 - TDM - PCM Master Functional Timing Diagram (8-bit, xeDX = 0). . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15 - TDM - PCM Master Functional Timing Diagram (8-bit, xeDX = 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 16 - TDM - GCI Slave Functional Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 17 - TDM - GCI Master Functional Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 18 - SPI Slave Byte Framing Mode - Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19 - SPI Slave Byte Framing Mode - Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 20 - SPI Slave Word Framing Mode - Write, Multiple Data Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 21 - SPI Slave Word Framing Mode - Read, Multiple Data Words . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 22 - SPI Slave Command Framing Mode - Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 23 - SPI Slave Command Framing Mode - Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 24 - Flash Interface Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 25 - External +1.2 V Power Supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 26 - Internal +1.2 V Power Supply Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 27 - Ultra-Low Power Operation Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 28 - ZL38067 64-Pin QFN - Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure 29 - ZL38067 56-Ball WLCSP - Top View. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 30 - THD+N Ratio versus Output Power - Driving Low Impedance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 31 - THD+N Ratio versus VRMS - Driving High Impedance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 32 - Crystal Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 33 - Clock Oscillator Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Figure 34 - Crystal-less Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 35 - Timing Parameter Measurement Digital Voltage Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Figure 36 - GCI Timing, 8-bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 37 - PCM Timing, 8-bit with xeDX = 0 (Transmit on Negative PCLK Edge) . . . . . . . . . . . . . . . . . . . . . . . . 53
Figure 38 - PCM Timing, 8-bit with xeDX = 1 (Transmit on Positive PCLK Edge) . . . . . . . . . . . . . . . . . . . . . . . . . 54
Figure 39 - Slave I2S Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Figure 40 - Master I2S Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 41 - SPI Slave Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 42 - I2C Timing Parameter Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 43 - UART_RX Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 44 - UART_TX Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Figure 45 - Master SPI Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 46 - AIB System Board Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Figure 47 - 64-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Figure 48 - Recommended 64-Pin QFN Land Pattern - Top View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 49 - 56-Ball WLCSP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
Figure 50 - 56-Ball WLCSP Staggered Balls Expanded Bottom View . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
ZL38067 Preliminary Data Sheet
List of Tables
6
Microsemi Corporation Confidential and Proprietary
Table 1 - Allowable TDM Configurations - Full Duplex Communications Firmware. . . . . . . . . . . . . . . . . . . . . . . . 15
Table 2 - HBI Slave Interface Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table 3 - Flash Devices Tested with the ZL38067 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 4 - Supported Flash Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Table 5 - Q1 Component Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 6 - Bootstrap Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 7 - Reset Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 8 - DAC Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 9 - Microphone Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 10 - TDM and I2S Ports Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 11 - HBI - SPI Slave Port Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Table 12 - Master SPI Port Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 13 - Oscillator Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 14 - UART Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 15 - GPIO Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 16 - Supply and Ground Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 17 - No Connect Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 18 - List of Changes to the Preliminary Data Sheet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
ZL38067 Preliminary Data Sheet
7
Microsemi Corporation Confidential and Proprietary
1.0 ZL38067 Device Overview
The ZL38067 integrates the Sensory Truly Hands Free™ Automatic Speech Recognition which provides the
capability to recognize a trigger word and up to 20 command phrases. Recognition is speaker independent and
does not require any end user training. Truly Hands Free™ also allows for trigger-to-command phase detection
without the need of a pause. This provides a user friendly experience. Microsemi's AcuEdge™ ASR assist
enhances the performance by providing barge-in support, noise reduction, and far field processing which extends
the detection range.
The ZL38067 has three primary modes of operation: Automatic Speech Recognition (ASR) with extended
vocabulary, Automatic Speech Recognition with ASR Assist, and Full Duplex Communications mode. The
ZLS38067.0 firmware provides the Full Duplex communications mode, while the other firmware variants
(ZLS38067.1, ZLS38067.2) provide the ASR with extended memory and ASR assist respectively.
Figure 1 - Alert Monitoring and Wideband Intercom Application
Microphone
DAC1
Digital Mic
Flash
Host/IP
Processor
Ethernet
SPI/I2C
TDMA/I2S
Speaker
Optional
Speaker
Driver
TDMB
DAA
Line Circuit
SPIM
ZL38067
ZL38067 Preliminary Data Sheet
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Microsemi Corporation Confidential and Proprietary
For the Full Duplex Communications Firmware, the majority of the signal processing (AEC, Equalization, Noise
Reduction etc.) runs in the Audio Processor Block. Each of the audio inputs (Digital Mics, I2S/TDM) and outputs
(DACs, I2S/TDM) can be routed amongst themselves or to the Audio Processor via a highly configurable Cross
Point Switch.
The main functional blocks of the device are shown in Figure 2, a description of each block follows.
Refer to the Microsemi AcuEdge™ Technology ZLS38067 Firmware Manual for functional blocks of the Automatic Speech
Recognition variants.
Figure 2 - ZL38067 ASR Audio Processor
2.0 Firmware
The three modes of operation in the ZL38067 (Full Duplex Communication, ASR with extended vocabulary, or ASR
with ASR-assist) are selected depending on which Firmware is loaded into the device. The Firmware is initially
loaded at power up, either from external serial Flash or from a host controller (see Section 7.0, “Device Booting and
Firmware Swapping“ on page 31). Real time switching between the Firmware modes can be done during normal
operation. There are timing constraints that should be noted for Firmware swapping (see Section 11.2, “Host Bus
Interface Timing Parameters“ on page 57 for more information).
Please refer to the ZL38067 Firmware Manual for detailed information on the use of the three firmware modes.
The signal processing (which includes Acoustic Echo Cancellation, Equalization, Noise Reduction, Far-Field Mic)
runs in the Audio Processor Block at 16 kHz. Each of the audio inputs (Digital Mics, I2S/TDM) and outputs (DACs,
I2S/TDM) can be routed amongst themselves or to the Audio Processor via a highly configurable Cross Point
Switch.
The ZL38067 device provides the following peripheral interfaces:
• 1 digital microphone interface allowing sampling of 1 or 2 digital microphones
• 2 Time-Division Multiplexing (TDM) buses
• The ports can be configured for Inter-IC Sound (I2S) or Pulse-Code Modulation (PCM) operation
• PCM operation supports PCM and GCI timing, I2S operation supports I2S and left justified timing
• Each port can be a clock master or a slave
• Each port supports up to four bi-directional streams when configured in PCM mode or two bi-directional
streams when configured for I2S mode at data rates from 128 kb/s to 8 Mb/s
ZL38067 Preliminary Data Sheet
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Microsemi Corporation Confidential and Proprietary
• Sample rate conversions are automatically done when data is sent/received at different rates than is
processed internally. Only integer conversions are allowed.
• SPI – The device provides two Serial Peripheral Interface (SPI) ports
• The SPI Slave port is recommended as the main communication port with a host processor. The port
provides the fastest means to Host Boot and configures the device’s firmware and configuration record1.
• The Master SPI port is used to load the device’s firmware and configuration record from external Flash
memory (Auto Boot).
• I2C - The device provides one Inter-Integrated Circuit (I2C) port. (pins are shared with the SPI Slave port)
• The I2C port can be used as the main communication port with a host processor, and can be used to Host
Boot and configure the device’s firmware and configuration record.
• UART – The device provides one Universal Asynchronous Receiver/Transmitter (UART) port.
• The UART port can be used as a debug tool and is used for tuning purposes.
• GPIO – The device provides 14 General Purpose Input/Output (GPIO) ports (full operation with Full Duplex
Communication Firmware, limited operation with ASR Firmware).
• GPIO ports can be used for interrupt and event reporting, fixed function control, bootstrap options, as well
as being used for general purpose I/O for communication and controlling external devices.
• The 56 pin WLCSP package is limited to 11 GPIOs.
2.1 Full Duplex Communication Mode (ZL38067.0)
The ZL38067.0 Firmware offers sophisticated full duplex audio processing for voice communication. This mode
includes Acoustic Echo Cancellation (AEC), Noise Reduction (NR) and a variety of other voice enhancements to
improve both the intelligibility and subjective quality of voice in harsh acoustic environments.
The full duplex communication firmware (ZL38067.0) supports the following additional ports:
• 2 independent headphone drivers
• Dual 16-bit digital-to-analog converters (DACs)
• 16 ohms single-ended or differential drive capability
• 32 mW output drive power into 16 ohms
2.2 ASR Mode (ZL38067.1)
This mode of operation provides reliable ASR for the detection of a fixed trigger and up to 20 command phrases.
This mode of operation supports:
• Detection of a fixed trigger in ‘spotting’ mode (ability to detect trigger even in continuous speech)
• Detection of up to 20 command phrases2 after the trigger detection
• Generation of a wake-on-trigger signal to wake up another device to act on the upcoming command phrase,
or enable full-duplex voice communication
1. The configuration record is a set of register values that are customizable by the application developer to configure and tune the ZL38067 for a
particular design. Refer to the Microsemi AcuEdge™ Technology ZL38067 Firmware Manual for firmware and configuration record informa-
tion.
2. Assuming a variable memory size of around 4K for each command phrase.
ZL38067 Preliminary Data Sheet
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Microsemi Corporation Confidential and Proprietary
2.3 Barge-in Mode (ZL38067.2)
This mode of operation provides reliable ASR in the presence of echo and noise for distances up to 16 feet from the
microphone.
This mode of operation supports all of the ASR features of the ZL38067.1 for trigger and 10 command phrase
detection, along with the addition of ASR assist features that include:
• Support for Barge-in, or incoming trigger ‘spotting’ in the presence of DAC audio output
• Detection of a fixed trigger in ‘spotting’ mode in the presence of echo and/or noise
3.0 Audio Interfaces
3.1 Digital Microphone Interface
3.1.1 ASR Modes (ZLS38067.1 or ZLS38067.2)
This firmware supports one digital microphone using the DMIC_CLK and DMIC_IN interface pins as shown in
Figure 3. The digital microphone clock output (DMIC_CLK) runs at 1.024 MHz.
Of the two possible microphone audio paths only one may be routed to the Audio Processing block for detection
processing at a time. The other path may be routed to the TDM bus for use by the host or an external Codec. The
selection as to which clock edge (rising/falling) is used to clock in the microphone data (left or right) is done via the
Microphone Enable Configuration register (host writable over the HBI) or in the configuration record (loaded from
Flash).
Figure 3 - Stand-alone and Barge-in ASR Digital Microphone Interface
An electret condenser microphone can be used with the digital microphone input by using a Digital Electret
Microphone Pre-Amplifier device as shown in Figure 6.
3.1.2 Full Duplex Communication Mode (ZLS38067.0)
This firmware supports up to two digital microphones using the DMIC_CLK and DMIC_IN interface pins.
The ZL38067 digital microphone clock output (DMIC_CLK) is either 1.024 MHz or 3.072 MHz depending on the
selected TDM-A sample rate. Selecting an 8 kHz or 16 kHz TDM-A sample rate corresponds to a 1.024 MHz digital
microphone clock and selecting a 48 kHz sample rate corresponds to a 3.072 MHz digital microphone clock.
Microphone data is decimated and filtered to operate at the 8 kHz or 16 kHz sampling rate of the Audio Processing
block. When there is no TDM-A bus to set the sample rate, the ZL38067 will operate from the crystal (or clock
oscillator) and will pass digital audio from the microphones operating at a 48 kHz sampling rate.
Of the two possible microphone audio paths only one may be routed to the voice processing algorithms at a time,
the other path may be routed to the TDM bus for use by the host or an external Codec. Alternatively the host
ZL38067
Digital Microphone
DMIC_CLK
DMIC_IN
CLK
DATA
L/R SEL
ZL38067 Preliminary Data Sheet
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Microsemi Corporation Confidential and Proprietary
processor can switch different microphones to the voice processing inputs. AEC is performed only on the
microphone selected to go to the ZL38067 voice processing section.
A stereo digital microphone, or two separate mono digital microphones, send two microphone channels on one pin
by sending the data for one channel on the rising edge and one channel on the falling edge. Various digital
microphone interfaces are presented in Figures 4 - 5.
Figure 4 - Single Mono Digital Microphone Interface Full Duplex Communications Firmware
Figure 5 - Dual Microphone or Stereo Digital Microphone Interface Full Duplex Communications
Firmware
3.1.3 Analog Microphone Use
Electret condenser microphones can be used with the digital microphone interface by using a Digital Electret
Microphone Pre-Amplifier device as shown in Figure 6. External Codecs can also be used to connect to analog
microphones. The external Codecs would interface to the ZL38067 via the TDM buses and the cross point switch
would be used to route the TDM bus into the audio processing block.
To use analog electret condenser microphones (ECM) with the digital microphone interface, a Digital Electret
Microphone Pre-Amplifier device is required. Figure 6 illustrates an analog microphone connection.
The analog microphone is wired to an optional differential amplifier which can provide filtering and gain and
converts the microphone signal to single-ended. The microphone signals are then further amplified and digitized
through the Digital Electret Microphone Pre-Amplifiers and applied to the ZL38067 digital microphone input. A
Microsemi AAP149B ECM Pre-Amplifier is shown. The ZL38067 provides the clock to activate the Digital Electret
Microphone Pre-Amplifier.
ZL38067
Digital Microphone
DMIC_CLK
DMIC_IN
CLK
DATA
L/R SEL
ZL38067
Stereo Digital
Microphone
MIC 1 Left
MIC 2 Right
DMIC_CLK
DMIC_IN
CLK
DATA
CLK
DATA
L/R SEL
L/R SEL
ZL38067 Preliminary Data Sheet
12
Microsemi Corporation Confidential and Proprietary
Figure 6 - ECM Circuit
When using an analog microphone, operation in Low-Power mode is not recommended. For more information, see
Section 10.4, “Device Operating Modes“ on page 43.
3.2 DAC Output Full Duplex Communication Mode (ZLS38067.0)
The Full Duplex Communication Mode supports two 16-bit fully differential delta-sigma digital-to-analog converters.
The two output DACs that can drive 2 outputs either single ended or differentially. There are four analog gain
settings on each DAC output are provided and can be set to: 1x, 0.5x, 0.333x, or 0.25x.
Note: Only the positive DAC outputs are available with the 56-ball WLCSP package. The 56-ball WLCSP package provides
two independent single-ended headphone outputs that can be driven by two independent data streams.
The headphone amplifiers are self-protecting so that a direct short from the output to ground or a direct short across
the terminals does not damage the device.
The ZL38067 provides audible pop suppression which reduces pop noise in the headphone earpiece when the
device is powered on/off or when the device channel configurations are changed. This is especially important when
driving a headphone single-ended through an external capacitor (see 3.2.1, “Output Driver Configurations“,
configuration C).
The DACs and headphone amplifiers can be powered down if they are not required for a given application. To fully
power down the DACs, disable both the positive and negative outputs.
3.2.1 Output Driver Configurations
Figure 7 shows the different possible output driver configurations for the 64-pin QFN package. When using the 56-
ball WLCSP package, only the positive single ended outputs DAC1_P and DAC2_P are provided.
The two output DACs independently drive positive and negative headphone driver amplifiers. The output pins can
be independently configured in the following ways:
A. Direct differential drive of a speaker as low as 32 ohms. For this configuration an analog gain of 1x is
commonly used. (Differentially driving a 16 ohm speaker is possible, but only with the same amount of power
as in the single-ended case. The signal level must be reduced to not exceed ½ scale in this case.)
B. Direct differential drive of a high impedance power amplifier. A Class D amplifier is recommended for this
speaker driver. Use an ON Semiconductor® NCP2820 or equivalent. A 1 F coupling capacitor is generally
used with the Class D amplifier. The analog gain setting depends on the gain of the Class D amplifier,
ZL38067
ECM
DMIC_CLK
DMIC_IN
ECM
preamp
Vbias VDD
CLK
DATA
DGND
IN
VDD
‐
+
L/R
Select
Optional circuitry
Commonly used for handset
microphone with long cord
DGND
AGNDAGND
AAP149B
ZL38067 Preliminary Data Sheet
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Microsemi Corporation Confidential and Proprietary
analog gain settings of 0.25x or 0.5x are commonly used.
C. Driving either a high impedance or a capacitively coupled speaker as low as 16 ohms single-ended. For this
configuration an analog gain of 1x is commonly used. The coupling capacitor value can vary from 10 f to
100 f depending on the type of earpiece used and the frequency response desired.
Figure 7 - Audio Output Configurations
3.3 DAC and Reference Bias Circuits
The common mode bias voltage output signal (CREF) must be decoupled through a 0.1 F (CREF1) and a 1.0 F
(CREF2) ceramic capacitor to VSS.
The positive DAC reference voltage output (CDAC) must be decoupled through a 0.1 F (CDAC) ceramic capacitor
to VSS as shown in Figure 8 if a DAC is ever to be used. If solely using Alarm, Glass Break and Energy Detector
Firmware, this capacitor is not required.
All capacitors can have a 20% tolerance and should have a minimum voltage rating of 6.3 V.
ZL38067
+
-
+
-
En 1P
En 1M
DAC 1
+
-
DAC1_M
DAC1_P
AB
C
+
-
+
-
+
-
+
-
En 2P
En 2M
DAC 1
+
-
DAC2_M
DAC2_P
AB
C
+
-
+
-
ZL38067 Preliminary Data Sheet
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Microsemi Corporation Confidential and Proprietary
Figure 8 - ZL38067 Bias Circuit
ZL38067
CREF
CDAC
C
REF1
C
REF2
C
DAC
0.1 uF
0.1 uF
1.0 uF
ZL38067 Preliminary Data Sheet
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Microsemi Corporation Confidential and Proprietary
4.0 Digital Interfaces
4.1 TDM Interface Full Duplex Communication Mode (ZLS38067.0)
The Full Duplex Communications Mode supports two generic TDM interfaces, TDM-A and TDM-B. Each interface
consists of four signals:
• Data clock (PCLK/I2S_SCK)
• Data rate sync (FS/I2S_WS)
• Serial data input (DR/I2S_SDI)
• Serial data output (DX/I2S_SDO)
The TDM ports can be configured for Inter-IC Sound (I2S) or Pulse-Code Modulation (PCM) operation.
Each TDM block is capable of being a master or a slave. Operation of the TDM interfaces are subject to the
following limitations.
While a TDM bus configuration may carry many encoded audio streams, when using Full Duplex Communication
Firmware, the ZL38067 device can only address a maximum of 4 bi-directional audio streams per TDM bus. These
four audio streams are referred to as channels #1 through #4, and each of these channels can be independently
configured to decode any of the TDM bus’s audio streams.
For a given TDM bus, once it is configured for a data sample rate and encoding, all data rates and encoding on that
bus will be the same. 16-bit linear data will be sent on consecutive 8-bit timeslots (e.g., if timeslot N is programmed
in the timeslot registers, the consecutive timeslot is N+1).
The TDM interface supports bit reversal (LSB first MSB first) and loopbacks within the TDM interface and
from one interface to another (see “Cross Point Switch - Full Duplex Communication Mode (ZLS38067.0)” on
page 20).
The generic TDM interface supports the following mode and timing options.
Table 1 - Allowable TDM Configurations - Full Duplex Communications Firmware
TDM-A
Mode TDM-B Mode
Supported
Sample Rates
(kHz)
Requirements / Limitations
Master Master 16, 48 Both TDM-A and TDM-B must be configured for
the same data clock and data sync.
Master Slave-Synchronous 16, 48
The TDM-B sync rate must be the same as the
TDM_A sync rate or 48 kHz.
Slave Master 16, 48
Slave Slave-Synchronous1
1. This combination requires that both TDM-A clock and TDM-B clock be physically connected to the same source.
16, 48
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4.1.1 I2S Mode
In I2S mode, the 4-wire TDM port conforms to the I2S protocol and the port pins become I2S_SCK, I2S_WS,
I2S_SDI, and I2S_SDO (refer to Table 10 for pin definitions). Both TDM buses have I2S capability.
An I2S bus supports two bi-directional data streams, left and right channel, by using the send and receive data pins
utilizing the common clock and word signals. The send data is transmitted on the I2S_SDO line and the receive
data is received on the I2S_SDI line.
The I2S port can be used to connect external analog-to-digital converters or Codecs. The port can operate in
master mode where the ZL38067 is the source of the port clocks, or slave mode where the word select and serial
clocks are inputs to the ZL38067.
The word select (I2S_WS) defines the I2S data rate and sets the frame period when data is transmitted for the left
and right channels. A frame consists of one left and one right audio channel. When using Full Duplex
Communication Firmware, the I2S ports operate as a slave or a master at sample rates as specified in Table 1. Per
the I2S standard, the word select is output using a 50% duty cycle.
The serial clock (I2S_SCK) rate sets the number of bits per word select frame period and defines the frequency of
I2S_CLK. I2S data is input and output at the serial clock rate. Input data bits are received on I2S_SDI and output
data bits are transmitted on I2S_SDO. Data bits are always MSB first. The number of clock and data bits per frame
can be programmed as 8, 16, 32, 64, 96, 128, 192, 256, 384, 512, or 1024. Any input data bits that are received
after the LSB are ignored.
The I2S port operates in two frame alignment modes (I2S and Left justified) which determine the data start in
relation to the word select.
Figure 9 illustrates the I2S mode, which is left channel first with I2S_WS (Left/Right Clock signal) low, followed by
the right channel with I2S_WS high. The MSB of the data is clocked out starting on the second falling edge of
I2S_SCK following the I2S_WS transition and clocked in starting on the second rising edge of I2S_SCK following
the I2S_WS transition. Figure 9 shows I2S operation with 32 bits per frame.
Figure 9 - I2S Mode
Figure 10 illustrates the left justified mode, which is left channel first associated with I2S_WS (Left/Right Clock
signal) high, followed by the right channel associated with I2S_WS low. The MSB of the data is clocked out starting
on the falling edge of I2S_SCK associated with the I2S_WS transition, and clocked in starting on the first rising
edge of I2S_SCK following the I2S_WS transition.
Left Channel
I2S_WS
I2S_SCK
I2S_SDI
I2S_SDO 0151413 01234 151413 01234
MSB LSB MSB LSB
Left Channel Right Channel
1 Bit Clock Cycle Offset 1 Bit Clock Cycle Offset
Data
Right Channel
Data
01 2 1514131211
10 01 2 151413121110
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Figure 10 - Left Justified Mode
Each I2S interface can support one dual channel Codec (Figure 11) through the Codec’s I2S interface. The four 16-
bit channel processing capacity of the DSP is spread across the two input channels from the ADCs of Codec(0) and
Codec(1), and the two output channels to the DACs of Codec(0) and Codec(1).
Figure 11 - Dual Codec Configuration Full Duplex Communications Firmware
Both I2S bus modes can support full bi-directional stereo communication.
The device supports I2S loopback.
See the Microsemi AcuEdge™ Technology ZLS38067 Firmware Manual for I2S port registers.
4.1.2 PCM Mode
Each of the PCM channels can be assigned an independent timeslot. The timeslots can be any 8-bit timeslot up to
the maximum supported by the PCLK being used.
The PCM ports can be configured for Narrowband G.711 A-law/-Law or Linear PCM or Wideband G.722 encoding.
For a given TDM bus, once it is configured for a data sample rate and encoding, all data rates and encoding on that
01 2 1514131211 012 151413121110
15 14 13 012346 151413 6 4 3 2 10
MSB MSBLSB LSB
I2S_WS
I2S_SCK
I2S_SDI
I2S_SDO
Left Channel Right Channel
Left Channel
Data
Right Channel
Data
10
ZL38067
ADC
ADC
I2S_SDI
I2S_SDO
CODEC(1)
CODEC(0)
DAC
DAC
CODEC(0)
CODEC(1)
Left Codec0 Right Codec 1
Right Codec0 Left Codec1
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bus will be the same. 16-bit linear PCM will be sent on consecutive 8-bit timeslots (e.g., if timeslot N is programmed
in the timeslot registers, the consecutive timeslot is N+1). The PCM interface can transmit/receive 8-bit compressed
or 16-bit linear data with 8 kHz sampling (Narrowband), or 16-bit linear data with 16 kHz sampling (Wideband).
Although the firmware allows it, 44.1 and 48 kHz sampling are not commonly used with PCM.
Wideband audio usually means the TDM bus is operating at a 16 kHz FS, but there are two other operating modes
that support wideband audio using an 8 kHz FS:
• G.722 supports wideband audio with an 8 kHz FS. This uses a single 8-bit timeslot on the TDM bus.
• “Half-FS Mode” supports wideband audio with an 8 kHz FS signal. In this mode, 16-bit linear audio is
received on two timeslot pairs; the first at the specified timeslot (N, N+1) and the second a half-frame later.
In total, four 8-bit timeslots are used per frame, timeslots (N, N+1) and ((N + ((bits_per_frame)/16)), (N + 1 +
((bits_per_frame)/16))). The user programs the first timeslot and the second grouping is generated
automatically 125/2 s from the first timeslot.
The PCM voice/data bytes can occupy any of the available timeslots, except for PCM clock rates that have extra
clocks in the last timeslot. If there is more than one extra clock in the last timeslot, the timeslot data will be
corrupted, do not use the last timeslot for these clock frequencies (e.g., 3.088 MHz etc.).
The PCM block can be configured as a master or a slave and is compatible with the Texas Instruments Inc.
McBSP mode timing format.
Figure 12 and Figure 13 illustrate the PCM format with slave timing, FS and PCLK are provided by the host. Slave
mode accommodates frame sync pulses with various widths (see “GCI and PCM Timing Parameters” on
page 52).
Figure 14 and Figure 15 illustrate the PCM format with master timing, FS and PCLK are provided by the ZL38067.
Master mode outputs a frame sync pulse equal to one PCLK cycle.
Diagrams for PCM transmit on negative edge (xeDX = 0) and PCM transmit on positive edge (xeDX = 1) are
shown for both slave and master timing.
Figure 12 - TDM PCM Slave Functional Timing Diagram (8-bit, xeDX = 0)
5674123010 1230564 7
5674123010 1230564 7
FS
PCLK
DR
DX
Time Slot 0 Time Slot N = 2
n
–1,
where: n = 1 … 8; 0 N 255
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Figure 13 - TDM PCM Slave Functional Timing Diagram (8-bit, xeDX = 1)
Figure 14 - TDM PCM Master Functional Timing Diagram (8-bit, xeDX = 0)
Figure 15 - TDM PCM Master Functional Timing Diagram (8-bit, xeDX = 1)
5674123010 1230564 7
5674123010 1230564 7
FS
PCLK
DR
DX
Time Slot 0 Time Slot N = 2
n
–1,
where: n = 1 … 8; 0 N 255
5674 123010 1230564 7
5674 123010 1230564 7
FS
PCLK
DR
DX
Time Slot 0 Time Slot N = 2
n
–1,
where: n = 1 … 8; 0 N 255
5674 123010 1230564 7
5674 123010 1230564 7
FS
PCLK
DR
DX
Time Slot 0 Time Slot N = 2n–1,
where: n = 1 … 8; 0 N 255
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4.1.3 GCI Mode
The GCI voice/data bytes can occupy any of the available timeslots. The GCI block can be configured as a master
or a slave and supports a clock that has the same frequency as the data rate.
Note: Traditional GCI Monitor, Signalling, and Control channel bytes and double data rate are not supported.
Figure 16 illustrates the GCI format with slave timing, FS and PCLK are provided by the host. Slave mode
accommodates frame sync pulses with various widths (see “GCI and PCM Timing Parameters” on page 52).
Figure 17 illustrates the GCI format with master timing, FS and PCLK are provided by the ZL38067. Master mode
outputs a frame sync pulse equal to one PCLK cycle.
For both, first data bits are aligned with the rising edge of the frame sync pulse.
Figure 16 - TDM GCI Slave Functional Timing Diagram
Figure 17 - TDM GCI Master Functional Timing Diagram
4.2 Cross Point Switch Full Duplex Communication Mode (ZLS38067.0)
The Full Duplex Communications Mode contains a Cross Point Switch that allows any input port to be routed to any
output port as well as routing the input/outputs to/from the audio processor functions. Refer to the Microsemi
AcuEdge™ Technology ZLS38067 Firmware Manual for Cross Point Switch operation and control.
4563 012707 0127453 6
4563 012707 0127453 6
Time Slot 0 Time Slot N = 2
n
–1,
where: n = 1 … 8; 0 N 255
FS
PCLK
DR
DX
FS
PCLK
DR
DX
4563 012707 0127453 6
4563 012707 0127453 6
Time Slot 0 Time Slot N = 2
n
–1,
where: n = 1 … 8; 0 N 255
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4.3 Host Bus Interface
The host bus interface (HBI) is the main communication port from a host processor to the ZL38067. It can be
configured to be either a SPI Slave or an I2C Slave port, either of which can be used to program or query the
device.
The ZL38067 allows for automatic configuration between SPI and I2C operation. For the HBI port, if the HCLK
toggles for two cycles, the HBI will default to the SPI Slave, otherwise it will remain configured as I2C (see Table 2).
The HBI comes up listening in both SPI and I2C modes, but with I2C inputs selected. If HCLK is present, it switches
the data selection before the first byte is complete so that no bits are lost. Once the port is determined to be SPI, a
hardware reset is needed to change back to I2C.
This port can read and write all of the memory and registers on the ZL38067. The port can also be used to boot the
device, refer to “Device Booting and Firmware Swapping” on page 31.
Table 2 - HBI Slave Interface Selection
Note 1: By default, the HBI comes up as an I2C interface. Toggling the HCLK pin will cause the host interface to switch to a SPI interface. If an
I2C interface is desired, HCLK needs to be tied to ground.
4.3.1 SPI Slave
The physical layer is a 4-wire SPI interface. Chip select and clock are both inputs.
The SPI Slave port can support byte, word, or command framing. Write and read diagrams for these framing modes
are shown in Figure 18 Figure 23. The SPI Slave chip select polarity, clock polarity, and sampling phase are fixed.
The ZL38067 command protocol is half duplex, allowing the serial in and serial out to be shorted together for a 3-
wire connection. The chip select is active low. The data is output on the falling edge of the clock and sampled on the
rising edge of the clock.
The SPI Slave supports access rates up to 25 MHz.
The outbound interrupt is always active low.
Figure 18 - SPI Slave Byte Framing Mode Write
Description Condition Operating Mode Notes
HBI Slave interface selection. HCLK toggling Host SPI bus
HDIN tied to VSS Host I2C bus. Slave address 45h (7-bit).
1
HDIN tied to DVDD33 Host I2C bus. Slave address 52h (7-bit).
HCS
HCLK
HDIN
HDOUT
Cmd_wd[15:8] Cmd_wd[7:0] Data_wd[15:8] Data_wd[7:0]
tACC tACC tACC tACC
Cmd_wd
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Figure 19 - SPI Slave Byte Framing Mode Read
Figure 20 - SPI Slave Word Framing Mode Write, Multiple Data Words
Figure 21 - SPI Slave Word Framing Mode Read, Multiple Data Words
HCS
HCLK
HDIN
HDOUT
Cmd_wd[15:8] Cmd_wd[7:0]
Data_wd[15:8] Data_wd[7:0]
t
ACC
t
WR_RDV
t
ACC
t
ACC
Cmd_wd
HCS
HCLK
HDIN
HDOUT
Command word Data word
tACC tACC
Data word
HCS
HCLK
HDIN
HDOUT
Command word
Data word
t
WR_RDV
t
ACC
Data word
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Figure 22 - SPI Slave Command Framing Mode Write
Figure 23 - SPI Slave Command Framing Mode Read
4.3.2 I2C Slave
The I2C bus is similar to the Philips Semiconductor (NXP) 1998 Version 2.0, I2C standard. The ZL38067 I2C bus
supports 7-bit addressing and transfer rates up to 400 kHz. External pull-up resistors are required on the I2C serial
clock input (HCS) and the I2C serial data input/output (HDOUT) when operating in this mode (note, the I2C slave
pins are 3.3 V pins and are not 5 V tolerant).
The selection of the I2C slave address is performed at bootup by the strapping of the HDIN and HCLK pins, see
Tab le 2.
4.3.3 UART
The ZL38067 device incorporates a two-wire UART (Universal Asynchronous Receiver Transmitter) interface with a
fixed 115.2K baud transfer rate, 8 data bits, 1 stop and no parity. TX and RX pins allow bi-directional communication
with a host. The UART pins must be made accessible on the PCB for debug and tuning purposes.
HCS
HCLK
HDIN
HDOUT
Command word Data word
t
ACC
Command word
HCS
HCLK
HDIN
HDOUT
Command word
Data word
t
ACC
Command word
t
WR_RDV
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4.3.4 Host Interrupt Pin
An internal host interrupt controller controls the active low interrupt pin which is part of the host bus interface.
Associated with the interrupt controller is an event queue which reports status information about which event
caused the interrupts.
Upon sensing the interrupt, the host can read the event queue to determine which event caused the interrupt.
Specific events are enabled by the host processor, and are typically not used with a standalone (controllerless)
design.
Refer to Events in the Microsemi AcuEdge™ Technology ZLS38067 Firmware Manual for Event ID Enumerations.
4.4 Master SPI
Like the HBI SPI Slave, the physical layer of the Master SPI is a 4-wire SPI interface supporting half duplex
communication. It supports only one chip select which is multiplexed with GPIO_9.
The Master SPI is only used by the built in boot ROM to load from an external serial Flash. The ZL38067 can
automatically read the Flash data (program code and configuration record) through this interface upon the release
of reset (Auto Boot), depending on the value of the bootstrap options.
Note: An alternative to Auto Boot is to perform a Host Boot through the HBI port. Refer to Section 7.0, “Device Booting and
Firmware Swapping“ on page 31.
4.4.1 Flash Interface
After power-up the ZL38067 will run its resident boot code, which establishes the initial setup of the Master SPI port
and then downloads the firmware from external Flash memory when configured for auto boot mode. This Flash
firmware establishes the resident application and sets the configuration of all the ZL38067 ports.
Figure 24 illustrates the connection of Flash memory to the ZL38067 Master SPI port. Figure 24 and the ZLE38000
demonstration hardware uses the MacronixTM MX25L4006E 4 Mbit CMOS Serial Flash device.
Figure 24 - Flash Interface Circuit
ZL38067
SM_CS
+3.3 V
SM_CLK
100 nF
SM_MISO
SM_MOSI
SCLK
CS
SO/SIO1
SI/SIO0
HOLD
WP
VCC
GND
10K
10K100K 100K
Master SPI
MX25L4006E
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4.4.1.1 Flash Selection
The ZL38067 Boot ROM is designed to work with a wide variety of Flash devices. There are numerous Flash
devices that the ZL38067 Boot ROM can recognize and program without host intervention other than a command to
initialize the Flash. Other unrecognized devices may be utilized if they conform to certain characteristics of known
devices and the host informs the ZL38067 Boot ROM of their type and size.
The ZL38067 identifies Flash devices (with a single binary image) with the ZL38067 boot ROM auto sensing the
Flash type. The ZL38067 complies with JEDEC Manufacturer and Device ID Read Methodology for SPI Compatible
Serial Interface Memory Devices. The ZL38067 is compatible with the Serial Flash Discoverable Parameters
JEDEC standard JESD216B and the Common Flash Interface JESD68.01 JEDEC standard. The ZL38067 can
identify devices by their JEDEC standard JEP106-K Standard Manufacturer’s Identification Code.
Select a Flash size that is adequate to store all the firmware images required of the application. The image sizes
can be obtained from the specific firmware releases.
A list of Flash devices that are identifiable by the ZL38067 Boot ROM are shown in Tab le 3. The size of these
devices are all 2 Mbit or 4 Mbit, the Boot ROM will also recognize the size of 8 Mbit parts that are Type 1 or Type 2
devices (as defined in Table 4).
Table 3 - Flash Devices Tested with the ZL38067
Flash devices whose JEDEC ID or size (usually a size of 16 Mbit or larger) that are not recognized by the ZL38067
Boot ROM can be made to work if they fit the characteristics of one of the 4 Flash types listed in Table 4. By writing
the type (1, 2, 3, or 4) to ZL38067 address 0x118 and the number of sectors to ZL38067 address 0x116 prior to
initializing the Flash device, the Boot ROM will treat it as a known device of known size even though the
manufacturer ID or size field are not recognized.
Table 4 - Supported Flash Types
Manufacturer Part Number Description
Macronix™ MX25V4006EM1I-13G 4 Mbit Flash.
Winbond™ W25X40CLSNIG-ND 4 Mbit Flash.
W25X20CLSNIG-ND 2 Mbit Flash.
Micron®M25P20-VMN6PB 2 Mbit Flash. Large 512 Kbit sectors limit the usefulness
of this device. Holds only 1 application image.
M25P40-VMN6PB 4 Mbit Flash. Large 512 Kbit sectors limit the usefulness
of this device. Holds only 2 or 3 application images.
Microchip™ SST25VF020B-80-4I 2 Mbit Flash.
Atmel®AT25DF041A
AT45DB041D
4 Mbit Flash. Must be used in its 256 byte page variant.
The default configuration is a 264 byte page. It can be
ordered or programmed to use a 256 byte page.
Spansion™ S25FL204K0TMF1010 4 Mbit Flash.
AMIC
Technology
A25L020O-F 2 Mbit Flash.
Characteristic Type 1 Type 2 Type 3 Type 4
Sector Size 512 Kbit (64 KB) 32 Kbit (4 KB) 32 Kbit (4 KB) 16 Kbit (2 KB)
Read Status Reg Cmd 0x05 0x05 0x05 0xD7
Status Reg Busy bit = 0x01 Busy bit = 0x01 Busy bit = 0x01 Done bit = 0x80
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4.5 GPIO
Note: GPIO functionality is limited with ASR related functionality. Refer to the Microsemi AcuEdge™ Technology ZLS38067
Firmware Manual.
The ZL38067 64-pin QFN package has 14 GPIO (General Purpose Input/Output) pins; the ZL38067 56-ball
WLCSP package has 11 GPIO pins.
The GPIO pins can be individually configured as either inputs or outputs, and have associated maskable interrupts
reported to the host processor through the interrupt controller and event queue. The GPIO pins are intended for low
frequency signaling.
When a GPIO pin is defined as an input, the state of that pin is sampled and latched into the GPIO Read Register.
A transition on a GPIO input can cause an interrupt and event to be passed to the host processor.
Certain GPIO pins have special predefined functions associated with the pin. Individual GPIO pins may also be
defined as status outputs with associated enable/disable control. See Fixed Function I/O in the Microsemi
AcuEdge™ Technology ZLS38067 Firmware Manual.
Immediately after any power-on or hardware reset the GPIO pins are defined as inputs and their state is captured in
the GPIO Configuration Register. The state of this register is used to determine which options are selected for the
device. The GPIO pin status is then redefined as specified in the configuration record that is loaded from the Flash
or host.
In addition to the predefined fixed functions and the general functionality of the GPIO pins, the GPIO pins also
support the bootstrap functions listed in Tabl e 6 .
5.0 Reset
The device has a hardware reset pin (RESET) that places the entire device into a known low power state. The
device will perform either a digital or an analog reset depending on the duration of the reset pulse.
Data Read Cmd 0x03 0x03 0x03 0x03
Write Enable Cmd 0x06 0x06 0x06 N/A
Page Write Cmd 0x02 0x02 N/A
Uses AAI to program
word or byte. Uses
Write Disable
command to
terminate AAI.
N/A
Uses write from
buffer command.
4-Byte Bulk Erase Cmd N/A N/A N/A 0xC794809A
Examples Micron®
M25P20-VMN6PB
M25P40-VMN6PB
Winbond™
W25X40CLSNIG-ND
W25X20CLSNIG-ND
Macronix™
MX25V4006EM1I-13G
AMIC Technology
A25L020O-F
Spansion™
S25FL204K0TMF1010
Atmel®
AT25DF041A
Microchip™
SST25VF020B-80-4I
Atmel®
AT45DB021D
AT45DB041D
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•Digital reset When the reset pin is brought low for a duration of between 100 ns and 1 s, a digital reset
occurs and all device states and registers are reset by this pin.
• Analog reset When the reset pin is brought low for a duration greater than 10 s, both a digital and an
analog reset will occur. The analog reset will deactivate the internally generated +1.2 V by shutting off the
external FET and the internal PLL. Raising the reset pin high will immediately turn back on these supplies
(requiring a corresponding PLL startup time, ~3 ms).
For both digital and analog reset cases when reset is released, the device will go though its boot process and the
firmware will be reloaded. If the reset had been an analog reset, then the boot process will take longer waiting for
the system clocks to power back on.
GPIO sensing will occur with either type of reset.
A 10 K pull-up resistor is required on the RESET pin to DVDD33 if this pin is not continuously driven.
6.0 Power Supply
6.1 Power Supply Sequencing/Power up
No special power supply sequencing is required. The +3.3 V or +1.2 V power rails can be applied in either order.
Upon power-up, the ZL38067 begins to boot and senses the external resistors on the GPIO to determine the
bootstrap settings. After 3 ms, the boot process begins and the ZL38067 takes less than 1 second to become fully
operational (for Auto Boot from Flash, including the time it takes to load the firmware).
In order to properly boot, the clocks (and power supplies) to the device must be stable. This requires either the
12.000 MHz crystal or clock oscillator to be active and stable before the ZL38067’s reset is released.
6.1.1 Power Supply Considerations
The ZL38067 requires +1.2 V to power its core DSP power supply (DVDD12). To achieve optimum noise and power
performance, supply DVDD12 from an external source. Use an LDO regulator like the Microsemi LX8213 to
achieve low noise and low overall power consumption. The ZL38067 is designed to minimize power in its active
states when DVDD12 is supplied externally.
To further reduce power, the internal PLL can be shut-down as described in 6.1.1.3, “Ultra-Low Power Mode“.
6.1.1.1 External +1.2 V Power
Figure 25 shows DVDD12 powered from an external supply. A Microsemi LX8213 300 mA Low Noise CMOS LDO
Regulator is shown.
External supply use is selected when the EXT_SEL pin is tied to +3.3 V. The EXT_SEL pin can be pulled high or
simply hard-wired to DVDD33.
VDD12_CTRL is a CMOS output which can be used to control the shutdown of the external supply. VDD12_CTRL
will provide a steady +3.3 V output (with up to 4 mA of source current) for the external supply to be enabled and 0 V
for the supply to be disabled.
For power savings when the ZL38067 does not need to be operational, the external voltage regulator can be
turned off by pulling the RESET pin low for longer than 10 S (Reset mode). This action will force the
VDD12_CTRL pin low, shutting off the external LDO and allowing the +1.2 V supply to collapse to 0 V.
If shutdown of the external +1.2 V supply is not desired, simply leave the VDD12_CTRL output pin floating.
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Figure 25 - External +1.2 V Power Supply Configuration
6.1.1.2 Internal +1.2 V Power
Note: The internal +1.2 V power option is only available with the 64-pin QFN package. The VDD12_CTRL pin is not avail-
able on the 56-ball WLCSP package.
Alternatively, the ZL38067 has a built-in voltage regulator that can be used as the DVDD12 source. The internal
voltage regulator requires an external N-channel FET device and a parallel 470 ohm resistor. Figure 26 shows
DVDD12 powered from the internal supply. Power dissipation is higher with internal regulator use due to the
internal control circuitry and functional blocks being active.
Internal supply use is selected when the EXT_SEL pin is tied to VSS. With the built-in voltage regulator enabled,
VDD12_CTRL will drive Q1 and generate +1.2 V at DVDD12. The parallel 470 ohm resistor is required to ensure
supply start-up. Q1 can be any of the high power FETs shown in Ta bl e 5 , or an equivalent.
For power savings when the ZL38067 does not need to be operational, the internal voltage regulator can be
turned off by pulling the RESET pin low for longer than 10 S (Reset mode). This action will force the
VDD12_CTRL pin low, shutting off the FET and allowing the +1.2 V supply to collapse to 0 V.
VSS
VDD12_CTRL
DVDD12
DVDD33 +3.3 V
ZL38067
LDO
SHDN
+1.2 V
GND
EXT_SEL
+3.3 V
VIN
VOUT
Supply decoupling is not shown
RESET
LX8213
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Figure 26 - Internal +1.2 V Power Supply Configuration
Table 5 - Q1 Component Options
6.1.1.3 Ultra-Low Power Mode
Note: Ultra-low power mode is only available with the 64-pin QFN package. The DVDD33_XTAL pin is not available on the
56-ball WLCSP package.
The ZL38067 can be placed into an Ultra-low power state by turning off the crystal oscillator’s internal voltage
regulator. The circuit required to perform this is shown in Figure 27.
The external circuit that drives the ZL38067 RESET pin can also be used to power the DVDD33_XTAL pin. The
reset drive circuit (gate) needs to provide at least 10 mA of source current when reset is high. The series 100 ohm
resistor provides a time delay to keep crystal power from reacting to short reset pulses. When the reset line goes
low for longer than 10 S, the crystal oscillator’s internal regulator will turn off and the ZL38067 will draw Ultra-low
power as specified in “Device Operating Modes” on page 43.
Manufacturer Part Number
Vishay®Si1422DH
International Rectifier IRLMS2002
Diodes Inc.®ZXMN2B03E6
VSS
VDD12_CTRL
DVDD12
DVDD33 +3.3 V
ZL38067
EXT_SEL
470
Q1
G
D
S
G
Supply decoupling is not shown
RESET
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Microsemi Corporation Confidential and Proprietary
Figure 27 - Ultra-Low Power Operation Circuit
ZL38067
DVDD33_XTAL
Reset
100
Crystal
or OSC
XI
XO
0.1uF
RESET
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7.0 Device Booting and Firmware Swapping
7.1 Boot Loader
The ZL38067 device contains a built-in boot-loader that gets executed after a hardware reset, when power is
initially applied to the part, and during the Firmware Swap process. The Bootloader performs the following actions:
• Reads the GPIO bootstrap information and stores it in the Boot Sense registers
• Determinant on the bootstrap setting, it loads external serial Flash device contents (firmware and
configuration record) into Program RAM (Auto Boot), or waits for the host to load Program RAM (Host Boot
and Firmware Swap)
• If Auto Boot is selected, the Bootloader then programs the ZL38067 configuration registers to their proper
default values, and jumps to Program RAM to execute the firmware
7.2 Bootstrap Modes
Tab le 6 lists the different boot options that can be selected by using external resistor. GPIOs have internal pull-
down resistors, thereby defaulting to a 0 setting. A resistor to DVDD33 is required to select a 1 option. An external
pull-up resistor must have a value of 3.3 K. A GPIO with a bootstrap pull-up can be used for other functionality
following the power-up boot sense process.
Table 6 - Bootstrap Modes
X = Don’t care.
Note 1: GPIO_[2:0] pins can have a pull-up resistor for bootstrap options. If a pull-up resistor is present and GPIO_[2:0] are used for keypad
scanning, it is preferable to use GPIO_[2:0] as column lines to minimize power dissipation.
Note 2: Apply a 3.3 K resistor from GPIO_0 to DVDD33.
Note 3: Apply a 3.3 K resistor from GPIO_1 to DVDD33.
Note 4: Apply a 3.3 K resistor from GPIO_2 to DVDD33. Note, when external flash is selected, GPIO_9 = SM_CS.
7.3 Loadable Device Code
In order for the ZL38067 to operate, it must be loaded with code that resides externally. This code can either be
Auto Booted from an external Flash memory through the Master SPI, or can be loaded into the ZL38067 by the host
processor through the HBI port. An external resistor pull-up or an internal resistor pull-down determines which boot
mode will be used (see Table 6).
The external code consists of two logical segments, the firmware code itself and the configuration record. The
firmware is a binary image which contains all of the executable code allowing the ZL38067 to perform voice
processing and establishes the user command set. The configuration record contains settings for all of the user
registers and defines the power-up operation of the device.
The configuration record is setup so that the registers are initialized to their desired values for normal operation.
GPIO_2 GPIO_1 GPIO_0 Operating Mode Description Notes
X 0 0 Crystal source 12 MHz (default) Clock source selection
X 0 1 TDM FSA source is 8 kHz 1,2
X 1 0 TDM FSA source is 16 kHz 1, 3
X 1 1 Reserved
0 X X Host Boot (default) Boot source selection
1 X X Auto Boot from external flash 1, 4
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A GUI development tool (MiTuner™ ZLS38508) is provided to create and modify a configuration record and create
a bootable Flash image which can then be duplicated for production of the end product. This tool requires access to
the UART and to the I2S port for tuning (refer to Section 12.0, “AEC Tuning“ on page 61).
7.3.1 Boot Speed
When performing an Auto Boot from a Flash device the boot sequence lasts <1 second (for a typical firmware
image and configuration record of size 400kB, and a SPI clock speed of around 3.2MHz or higher).
When performing a Host Boot through the HBI SPI/I2C Slave port, the boot time will vary depending on the host's
communications speed. SPI can run up to a speed of 25 MHz and has less overhead, allowing it to perform a boot
download ~<300 ms; I2C is limited to a speed of 400 kHz, making a boot download last ~>5 seconds. If boot speed
is important, use the HBI SPI Slave port (or Flash) for booting rather than the I2C Slave port.
7.4 Bootup Procedure
Valid clocks (crystal or clock oscillator) must be present before the ZL38067 device can exit its reset state. After the
reset line is released, the ZL38067’s internal voltage regulator will be enabled (if the EXT_SEL pin is strapped low).
Once the +1.2 V supply is established, the PLL will be also be enabled. Based on GPIO_0 and GPIO_1 bootstrap
settings being 0, the ZL38067 will select the system parameters and the PLL will lock to the crystal or clock
oscillator 12.000 MHz operating frequency. An event will be placed in the event-queue and the interrupt pin (HINT)
will be pulled low to signal the host when it’s OK to load boot code.
Next, if the GPIO strapping pins indicate that the ZL38067 will Auto Boot, it will begin reading data from the external
Flash. Refer to the Microsemi AcuEdge™ Technology ZLS38067 Firmware Manual for a listing of the complete
Boot Sequence.
If the GPIO strapping pins indicate that the ZL38067 will Host Boot, the SPI or I2C port that initiates the loading
process becomes the boot master. The ZL38067 allows for automatic configuration between SPI and I2C operation.
For the HBI port, if the HCLK toggles for two cycles, the HBI will default to the SPI Slave, otherwise it will remain
configured as I2C.
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8.0 Device Pinouts
8.1 64-Pin QFN
Figure 28 - ZL38067 64-Pin QFN Top View
64 585960616263 57 56 55 54
11
10
9
8
7
6
5
4
3
2
1
DRB/I2S_SDIB
GPIO_9/SM_CS
PCLKB/I2S_SCKB
FSB/I2S_WSB
DVDD12
DVDD33
HDOUT
UART _TX
VSS
DXB/I2S_SDOB
53 52 51 50 49
16
15
14
13
12
38
39
40
41
42
43
44
45
46
47
48
33
34
35
36
37
3231
3029282726252423
22
2120191817
HCLK
DVDD33
UART _RX
HCS
HINT
DVDD33
GPIO_10
GPIO_8
DVDD12
GPIO_7
GPIO_6
GPIO_12
GPIO_2
GPIO_5
GPIO_4
GPIO_0
GPIO_3
DVDD33
GPIO_13
GPIO_1
FSA/I2S_WSA
DRA/I2S_SDIA
DMIC_IN
NC
DVDD33
NC
XO
DVDD12
DMIC_CLK
NC
EXT_SEL
VSS
DXA/I2S_SDOA
SM_CLK
SM_MISO
SM_MOSI
DVDD33
DAC1_M
DAC1_P
DAC2_P
CDAC
CREF
RESET
DVDD12
GPIO_11
AVDD33
DAC2_M
DVDD12
AVDD33
HDI N
Exposed Ground Pad
VDD12_CTRL
XI
DVDD33_XTAL
PCLKA/I2S_SCKA
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8.2 56-Ball WLCSP
Figure 29 - ZL38067 56-Ball WLCSP Top View
NC XIDMIC_CLK
NCDMIC_IN
VSSDXA/I2S_SDOA
H1 H2 H3 H4 H5 H6 H7
CREF
DVDD12DVDD12
NCDVDD33DRA/I2S_SDIA VSS
G1 G2 G3 G4 G5 G6 G7
XO CDAC
GPIO_2 GPIO_0
GPIO_3FSA/I2S_WSA GPIO_5
F1 F2 F3 F4 F5 F6 F7
GPIO_10GPIO_7 AVDD33
VSSGPIO_1PCLKA/I2S_SCKA GPIO_6
E1 E2 E3 E4 E5 E6 E7
GPIO_8 RESET DAC2_PVSSVSSDVDD12
D1 D2 D3 D4 D5 D6 D7
GPIO_11 DAC1_PPCLKB/I2S_SCKBHINT UART_TX
C1 C2 C3 C4 C5 C6 C7
DVDD33
VSSDVDD12VSS
DVDD33
HCS UART_RX
B1 B2 B3 B4 B5 B6 B7
SM_MOSISM_MISOSM_CLK
GPIO_9/SM_CSHDOUT
HDINHCLK
A1 A2 A3 A4 A5 A6 A7
DRB/I2S_SDIB DXB/I2S_SDOB
FSB/I2S_WSB
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9.0 Pin Descriptions
Table 7 - Reset Pin Description
Table 8 - DAC Pin Descriptions
QFN
Pin #
WLCSP
Ball Name Type Description
15 D6 RESET Input Reset. When low the device is in its reset state and all tristate outputs
will be in a high impedance state. This input must be high for normal
device operation.
A 10 K
pull-up resistor is required on this pin to DVDD33 if this pin is
not continuously driven.
Refer to “Reset” on page 26 for an explanation of the various reset
states and their timing.
QFN
Pin #
WLCSP
Ball Name Type Description
6DAC1_M Output DAC 1 Minus Output. This is the negative output signal of the
differential amplifier of DAC 1. Pin functionality is firmware
dependent.
Not available on the WLCSP package.
7 C7 DAC1_P Output DAC 1 Plus Output. This is the positive output signal of the
differential amplifier of DAC 1. Pin functionality is firmware
dependent.
9DAC2_M Output DAC 2 Minus Output. This is the negative output signal of the
differential amplifier of DAC 2. Pin functionality is firmware
dependent.
Not available on the WLCSP package.
8 D7 DAC2_P Output DAC 2 Plus Output. This is the positive output signal of the
differential amplifier of DAC 2. Pin functionality is firmware
dependent.
12 F7 CDAC Output DAC Reference. This pin may require capacitive decoupling. Refer to
“DAC Output - Full Duplex Communication Mode (ZLS38067.0)” on
page 12.
13 G7 CREF Output Common Mode Reference. This pin requires capacitive decoupling.
Refer to “DAC Output - Full Duplex Communication Mode
(ZLS38067.0)” on page 12.
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Table 9 - Microphone Pin Descriptions
Table 10 - TDM and I2S Ports Pin Descriptions
All of these pins are only functional with Full Duplex Communication Firmware (ZLS38067.0).
The firmware supports two TDM interfaces, TDM-A and TDM-B. Each TDM block is capable of being a master or a
slave. The ports can be configured for Pulse-Code Modulation (PCM) or Inter-IC Sound (I2S) operation. The
ports conform to PCM, GCI, and I2S timing protocols.
QFN
Pin #
WLCSP
Ball Name Type Description
18 H6 DMIC_CLK Output Digital Microphone Clock Output. Clock output for digital
microphones and digital electret microphone pre-amplifier devices.
19 H3 DMIC_IN Input Digital Microphone Input. Stereo or mono digital microphone input.
Accommodates MIC 1 and MIC 2.
Tie to VSS if unused.
QFN
Pin #
WLCSP
Ball Name Type Description
29 E1 PCLKA/
I2S_SCKA
Input/
Output
PCM Port A Clock (Input/Tristate Output). PCLKA is equal to the bit
rate of signals DRA/DXA. In TDM master mode this clock is an output
and in TDM slave mode this clock is an input.
I2S Port A Serial Clock (Input/Tristate Output). This is the I2S port A
bit clock. In I2S master mode this clock is an output and drives the bit
clock input of the external slave device’s peripheral converters. In I2S
slave mode this clock is an input and is driven from a converter
operating in master mode.
After power-up, this signal defaults to be an input in I2S slave mode.
A 100 K
pull-down resistor is required on this pin to VSS. If this pin is
unused, tie the pin to VSS.
When driving PCLKA/I2S_SCKA from a host, one of the following
conditions must be satisfied:
1. Host drives PCLKA low during reset, or
2. Host tri-states PCLKA during reset (the 100 K
resistor will keep
PCLKA low), or
3. Host drives PCLKA at its normal frequency
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30 F1 FSA/
I2S_WSA
Input/
Output
CM Port A Frame Sync (Input/Tristate Output). This is the TDM
frame alignment reference. This signal is an input for applications
where the PCM bus is frame aligned to an external frame signal (slave
mode). In master mode this signal is a frame pulse output.
I2S Port A Word Select (Left/Right) (Input/Tristate Output). This is
the I2S port A left or right word select. In I2S master mode word select
is an output which drives the left/right input of the external slave
device’s peripheral converters. In I2S slave mode this pin is an input
which is driven from a converter operating in master mode.
After power-up, this signal defaults to be an input in I2S slave mode.
Tie this pin to VSS if unused.
31 G1 DRA/
I2S_SDIA
Input PCM Port A Serial Data Stream Input. This serial data stream
operates at PCLK data rates.
I2S Port A Serial Data Input. This is the I2S port serial data input.
Tie this pin to VSS if unused.
32 H1 DXA/
I2S_SDOA
Output PCM Port A Serial Data Stream Output. This serial data stream
operates at PCLK data rates.
I2S Port A Serial Data Output. This is the I2S port serial data output.
60 C4 PCLKB/
I2S_SCKB
Input/
Output
PCM Port B Clock (Input/Tristate Output). PCLKB is equal to the bit
rate of signals DRB/DXB. In TDM master mode this clock is an output
and in TDM slave mode this clock is an input.
I2S Port B Serial Clock (Input/Tristate Output). This is the I2S port B
bit clock. In I2S master mode this clock is an output and drives the bit
clock input of the external slave device’s peripheral converters. In I2S
slave mode this clock is an input and is driven from a converter
operating in master mode.
After power-up, this signal is an input in I2S slave mode.
Tie this pin to VSS if unused.
61 D5 FSB/
I2S_WSB
Input/
Output
PCM Port B Frame Sync (Input/Tristate Output). This is the TDM
frame alignment reference. This signal is an input for applications
where the PCM bus is frame aligned to an external frame signal (slave
mode). In master mode this signal is a frame pulse output.
I2S Port B Word Select (Left/Right) (Input/Tristate Output). This is
the I2S port B left or right word select. In I2S master mode word select
is an output which drives the left/right input of the external slave
device’s peripheral converters. In I2S slave mode this pin is an input
which is driven from a converter operating in master mode.
After power-up, this signal defaults to be an input in I2S slave mode.
Tie this pin to VSS if unused.
QFN
Pin #
WLCSP
Ball Name Type Description
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Table 11 - HBI SPI Slave Port Pin Descriptions
This port functions as a peripheral interface for an external controller, and supports access to the internal registers
and memory of the device.
62 C5 DRB/
I2S_SDIB
Input PCM Port B Serial Data Stream Input. This serial data stream
operates at PCLK data rates.
I2S Port B Serial Data Input. This is the I2S port serial data input.
Tie this pin to VSS if unused.
63 C6 DXB/
I2S_SDOB
Output PCM Port B Serial Data Stream Output. This serial data stream
operates at PCLK data rates.
I2S Port B Serial Data Output. This is the I2S port serial data output.
QFN
Pin #
WLCSP
Ball Name Type Description
52 A1 HCLK Input HBI SPI Slave Port Clock Input.
Clock input for the SPI Slave port. Maximum frequency = 25 MHz.
This input should be tied to VSS in I2C mode, refer to Table 2.
Tie this pin to VSS if unused.
53 B1 HCS Input HBI SPI Slave Chip Select Input. This active low chip select signal
activates the SPI Slave port.
HBI I2C Serial Clock Input. This pin functions as the I2C_SCLK input
in I2C mode. A pull-up resistor is required on this node for I2C
operation.
Tie this pin to VSS if unused.
55 A2 HDIN Input HBI SPI Slave Port Data Input. Data input signal for the SPI Slave
port.
This input selects the slave address in I2C mode, refer to Table 2.
Tie this pin to VSS if unused.
56 A3 HDOUT Input/
Output
HBI SPI Slave Port Data Output (Tristate Output). Data output
signal for the SPI Slave port.
HBI I2C Serial Data (Input/Output). This pin functions as the
I2C_SDA I/O in I2C mode. A pull-up resistor is required on this node
for I2C operation.
57 C1 HINT Output HBI Interrupt Output. This output can be configured as either CMOS
or open drain by the host.
QFN
Pin #
WLCSP
Ball Name Type Description
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Table 12 - Master SPI Port Pin Descriptions
This port functions as the interface to an external Flash device used to optionally Auto Boot and load the device’s
firmware and configuration record from external Flash memory.
Table 13 - Oscillator Pin Descriptions
These pins are connected to a 12.000 MHz crystal or clock oscillator which drives the device’s internal PLL.
Table 14 - UART Pin Descriptions
The ZL38067 device incorporates a two-wire UART (Universal Asynchronous Receiver Transmitter) interface with a
fixed 115.2K baud transfer rate, 8 data bits, 1 stop and no parity. The UART port can be used as a debug tool and is
used for tuning purposes.
QFN
Pin #
WLCSP
Ball Name Type Description
1 A5 SM_CLK Output Master SPI Port Clock (Tristate Output). Clock output for the Master
SPI port. Maximum frequency = 8 MHz.
2 A6 SM_MISO Input Master SPI Port Data Input. Data input signal for the Master SPI port.
3 A7 SM_MOSI Output Master SPI Port Data Output (Tristate Output). Data output signal
for the Master SPI port.
64 A4 GPIO_9/
SM_CS
Input/
Output
Master SPI Port Chip Select (Input Internal Pull-Up/Tristate
Output). Chip select output for the Master SPI port.
Shared with GPIO_9, see Table 15.
QFN
Pin #
WLCSP
Ball Name Type Description
22 H7 XI Input Crystal Oscillator Input. Refer to “External Clock Requirements” on
page 48.
23 F5 XO Output Crystal Oscillator Output. Refer to “External Clock Requirements”
on page 48.
QFN
Pin #
WLCSP
Ball Name Type Description
50 B2 UART_RX Input UART (Input). Receive serial data in. This port functions as a
peripheral interface for an external controller and supports access to
the internal registers and memory of the device.
49 C2 UART_TX Output UART (Tristate Output). Transmit serial data out. This port functions
as a peripheral interface for an external controller and supports
access to the internal registers and memory of the device.
Table 15 - GPIO Pin Descriptions
GPIO ports can be used for interrupt and event reporting, fixed function control, bootstrap options, as well as being
used for general purpose I/O for communication and controlling external devices. Pin functionality is firmware
dependent.
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Table 16 - Supply and Ground Pin Descriptions
QFN
Pin #
WLCSP
Ball Name Type Description
33,34 F4, E4 GPIO_[0:1] Input/
Output
General Purpose I/O (Input Internal Pull-Down/Tristate Output).
These pins can be configured as an input or output and are intended
for low-frequency signalling. They must be pulled low or left floating
when coming out of reset.
36 F3 GPIO_2 Input/
Output
General Purpose I/O (Input Internal Pull-Down/Tristate Output).
These pins can be configured as an input or output and are intended
for low-frequency signalling. Refer to Table 6 for bootstrap
functionality.
37,38
39,40,
41,43
F2, ,
F6, E5,
E2, D3
GPIO_[3:8] Input/
Output
General Purpose I/O (Input Internal Pull-Down/Tristate Output).
These pins can be configured as an input or output and are intended
for low-frequency signalling.
64 A4 GPIO_9/
SM_CS
Input/
Output
General Purpose I/O (Input Internal Pull-Down/Tristate Output).
This pin can be configured as an input or output and is intended for
low-frequency signalling.
Alternate functionality with SM_CS, see Table 12.
44,45,
47,48
E3, C3,
,
GPIO_
[10:13]
Input/
Output
General Purpose I/O (Input Internal Pull-Down/Tristate Output).
These pins can be configured as an input or output and are intended
for low-frequency signalling.
GPIO_12 and GPIO_13 are not available on the WLCSP package.
QFN
Pin #
WLCSP
Ball Name Type Description
17 EXT_SEL Input VDD +1.2 V Select. Select external +1.2 V supply. Tie to DVDD33 if
the +1.2 V supply is to be provided externally. Tie to VSS (0 V) if the
+1.2 V supply is to be generated internally.
Refer to 6.1.1, “Power Supply Considerations“ for more information.
Not available on the WLCSP package.
16 VDD12_CTRL Output VDD +1.2 V Control. Analog control line for the voltage regulator
external FET when EXT_SEL is tied to VSS. When EXT_SEL is tied
to DVDD33, the VDD12_CTRL pin becomes a CMOS output which
can drive the shutdown input of an external LDO.
Refer to 6.1.1, “Power Supply Considerations“ for more information.
Not available on the WLCSP package.
4,14,
24,42,
58
B5, D1,
G5, G6
DVDD12 Power Core Supply. Connect to a +1.2 V ±5% supply.
Place a 100 nF, 20%, 10 V, ceramic capacitor on each pin decoupled
to the VSS plane.
Refer to 6.1.1, “Power Supply Considerations“ for more information.
5,
21,35,
46,51,
59
B3, B7,
G3
DVDD33 Power Digital Supply. Connect to a +3.3 V ±5% supply.
Place a 100 nF, 20%, 10 V, ceramic capacitor on each pin decoupled
to the VSS plane.
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Table 17 - No Connect Pin Description
28 DVDD33_
XTAL
Power Crystal Digital Supply. This pin must be connected to a +3.3 V
supply source capable of delivering 10 mA.
Not available on the WLCSP package.
10,11 E7 AVDD33 Power Analog Supply. Connect to a +3.3 V ±5% supply.
Place a 100 nF, 20%, 10 V, ceramic capacitor on each pin decoupled
to the VSS plane.
20, 54 B4, B6,
D2, D4,
E6, G2,
H2
VSS Ground Ground. Connect to digital ground plane.
Exposed
Ground Pad
Ground Exposed Pad Substrate Connection. Connect to VSS. This pad is
at ground potential and must be soldered to the printed circuit board
and connected via multiple vias to a heatsink area on the bottom of
the board and to the internal ground plane.
Not available on the WLCSP package.
QFN
Pin #
WLCSP
Ball Name Type Description
25, 26,
27
G4, H4,
H5
NC No Connection. These pins are to be left unconnected, do not use
as a tie point.
QFN
Pin #
WLCSP
Ball Name Type Description
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10.0 Electrical Characteristics
10.1 Absolute Maximum Ratings
Stresses above those listed under Absolute Maximum Ratings can cause permanent device failure. Functionality at
or above these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device
reliability.
10.2 Thermal Resistance
Notes:
1. The thermal specifications assume that the device is mounted on an effective thermal conductivity test board (4 layers, 2s2p) per JEDEC
JESD51-7 and JESD51-5.
10.3 Operating Ranges
Microsemi guarantees the performance of this device over the industrial (-40 ºC to 85 ºC) temperature range by
conducting electrical characterization over each range and by conducting a production test with single insertion
coupled to periodic sampling. These characterization and test procedures comply with the Telcordia GR-357-CORE
Generic Requirements for Assuring the Reliability of Components Used in Telecommunications Equipment.
Supply voltage (DVDD33, AVDD33) -0.5 to +4.0 V
Core supply voltage (DVDD12) -0.5 to +1.32 V
Input voltage -0.5 to +4.0 V
Continuous current at digital outputs 15 mA
Reflow temperature, 10 sec., MSL3, per JEDEC J-STD-020 260 C
Storage temperature -55 to +125 C
ESD immunity (Human Body Model) JESD22 Class 1C compliant
Junction to ambient thermal resistance (1), JA 64-pin Q F N
56-ball WLCSP
C/W
C/W
Junction to board thermal resistance (1), JB 64-pin QFN
56-ball WLCSP
C/W
C/W
Junction to exposed pad thermal resistance (1), JC 64-pin QFN C/W
Junction to case thermal resistance (1), JC 56-ball WLCSP C/W
Junction to top characterization parameter, JT 64-pin QFN
56-ball WLCSP
0.1 °C/W
C/W
Parameter Symbol Min. Typ. Max. Units
Ambient temperature TA-40 +85 C
Analog supply voltage VAVDD33 3.135 3.3 3.465 V
Digital supply voltage VDVDD33
Crystal Digital supply voltage VDVDD33_XTAL
Crystal I/O voltage VXI 2.5 2.625 V
Core supply voltage VDVDD12 1.14 1.2 1.26 V
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10.4 Device Operating Modes
When the full duplex communication firmware (ZL38067.0) or the barge-in firmware (ZL38067.2) is running, the
ZL38067 is considered to be in normal operating mode.
Low-power and sleep modes are firmware programmable options. Reset and Ultra-low power modes are hardware
modes that can be utilized to minimize power consumption for all the firmware variants.
Operating modes are highlighted in the following sections. Refer to the Microsemi AcuEdge™ Technology
ZLS38067 Firmware Manual for programming and additional information on the firmware operating modes.
10.4.1 Normal
• Normal firmware mode
• HBI active
• Audio path active, wideband (16KHz) or narrowband (8KHz) operation Note: ASR requires wideband
operation.
• DACs and MICs can be enabled
• Audio Processor always on
Normal mode is recommended for applications that use the internal voltage regulator with analog microphones.
Normal mode keeps the Audio Processor always on, thereby minimizing +1.2 V power supply noise that could be
injected into sensitive analog microphone circuitry via the board layout.
10.4.2 Low-Power
• Low-Power firmware mode
• HBI active
• Audio path active, wideband or narrowband operation
• DACs and MICs can be enabled
• Audio Processor operates in Power Saving Mode
Low-power mode is selected in register 0x206 (System Control Flags) bit 1, or can be selected from the ZLS38508
MiTuner™ GUI in the AEC Control window (Enable Power Saving Mode). Low-Power mode is not recommended
for applications that use the internal voltage regulator with analog microphones.
10.4.3 Sleep
• Sleep firmware mode
• HBI active
• Audio path inactive
• DACs and MICs are powered down
• Audio Processor made inactive, internal clocks are shutdown, requires a wake-up procedure to return to
Normal or Low-Power mode. Note: ASR not enabled in Sleep Mode.
The ZL38067 will respond to no other inputs until it awakens from Sleep mode. To wake from Sleep mode, perform
an HBI Wake From Sleep operation, as described in the ZLS38067 Firmware Manual Appendix D. The firmware
and configuration records loaded into the device RAM are retained, no re-boot is required.
10.4.4 Reset
• Hardware mode, the ZL38067 goes into this mode when the RESET pin is held low for greater than 10 S
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• HBI inactive
• Audio path inactive
• DACs and MICs are powered down
• Audio Processor powered down via removal of +1.2 V supply
See Section 5.0, “Reset“ on page 26 for more information and refer to Section 6.0, “Power Supply“ on page 27 for
information on +1.2 V removal.
10.4.5 Ultra-Low Power
• Hardware mode, the hardware can be configured to enter this mode when the RESET pin is held low for
greater than 10 S
• HBI inactive
• Audio path inactive
• DACs and MICs are powered down
• Audio Processor powered down via removal of +1.2 V supply
• Crystal or clock oscillator supply made inactive
See Section 5.0, “Reset“ on page 26 and Section 6.1.1.3, “Ultra-Low Power Mode“ on page 29 for more
information, refer to Section 6.0, “Power Supply“ on page 27 for information on +1.2 V removal.
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10.4.6 Current Consumption
Device current consumption can vary with the firmware load. Common values are listed here using an external
+1.2 V supply for the core power supply with a 12.000 MHz crystal and a 3.3 K resistor from GPIO_2 to DVDD33
(external Flash selected), unless otherwise noted.
Note 1: Table values include all current entering DVDD33, AVDD33, and DVDD33_XTAL pins.
Add 1.0 mA to Normal, Low-Power, and Sleep modes if the internal voltage regulator is used (EXT_SEL = VSS).
Note 2: Core supply voltage. Table values include all current entering DVDD12 pins.
Note 3: DAC in differential mode, for 2 DACs active in differential mode, add 3.6 mA to +3.3 V current.
Note 4: DMIC_IN active.
Note 5: DVDD12 is removed if the internal regulator is used for +1.2 V generation or if the VDD12_CTRL pin is used to shutdown an
external +1.2 V LDO that provides DVDD12 to the ZL38067.
Note 6: Narrowband (8KHz) mode only available in ZLS38067.0 firmware.
+3.3 V 1+1.2 V 2
Operational Mode
(Firmware Variant) Typ. Max. Typ. Max. Units Notes / Conditions
Normal
Wideband
Narrowband6
10
8
130
83
mA
Firmware active, power-saving off,
1 DAC active3, 1 or 2 MICs active4,
LEC bypassed, HBI is active.
Low-Power
Wideband
Narrowband610
8
90
60
Firmware active, power-saving on,
1 DAC active3, 1 or 2 MICs active4,
LEC bypassed, HBI is active.
Sleep 2 12 Firmware inactive (Firmware and
configuration record are retained),
DACs and MICs are powered down,
HBI is active.
Reset 100 n/a
A
Device in reset (reset > 10 S),
DVDD12 removed5.
Ultra-Low Power 3 n/a Device in reset (reset > 10 S),
DVDD12 not present,
DVDD33_XTAL held low.
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10.5 DC Specifications
Typical values are for TA = 25 ºC and nominal supply voltage. Minimum and maximum values are over the industrial
-40 ºC to 85 ºC temperature range and supply voltage range as shown in “Operating Ranges” on page 42, except
as noted. A 12.000 MHz clock oscillator is active.
10.6 AC Specifications
For all AC specifications, typical values are for TA = 25 ºC and nominal supply voltage. Minimum and maximum
values are over the industrial -40 ºC to 85 ºC temperature range and supply voltage ranges as shown in “Operating
Ranges” on page 42, except as noted. A 12.000 MHz clock oscillator is active with Full Duplex Communication
Firmware in Normal, Wideband operational mode.
10.6.1 Microphone Interface
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
Input high voltage VIH 0.7 *
VDVDD33
VDVDD33 +
0.3
V All digital inputs
Input low voltage VIL VVSS - 0.3 0.3 *
VDVDD33
V All digital inputs
Input hysteresis voltage VHYS 0.4 V
Input leakage (input pins) IIL 5A0 to3.3 V
Input leakage (bi-directional pins) IBL 5A 0 to +3.3 V
Weak pull-up current IPU 38 63 101 A Input at 0 V
Weak pull-down current IPD 19 41 158 A Input at +3.3 V
Input pin capacitance CI5pF
Output high voltage VOH 2.4 V At 12 mA
Output low voltage VOL 0.4 V At 12 mA
Output high impedance leakage IOZ 5A0 to3.3 V
Pin capacitance (output &
input/tristate pins)
CO5pF
Output rise time tRT 1.25 ns 10% to 90%, CLOAD = 20 pF
Output fall time tFT 1.25 ns 90% to 10%, CLOAD = 20 pF
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
Microphone clock output (DMIC_CLK),
8 kHz, 16 kHz sample rate
48 kHz sample rate
1.024
3.072
MHz
MHz
DMIC_CLK, Output high current IOH 20 mA VOH = DVDD33 - 0.4 V
DMIC_CLK, Output low current IOL 30 mA VOL = 0.4 V
DMIC_CLK, Output rise and
fall time
tR, tF5nsC
LOAD = 100 pF
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10.6.2 DAC
Measurements taken using PCM mode. THD+N versus output power for speaker drive applications presented in
Figure 30; THD+N versus output voltage for amplifier drive applications presented in Figure 31.
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
DAC output level:
Full scale: Differential
Single-ended
0 dBm0 : Differential
Single-ended
VDACFS 4.8
2.4
2.8
1.4
VPP
DAC gain = 1, 1 K load.
PCM full scale level (Vppd value) 9 dBm0 DAC gain = 1, 600 load
DAC output power:
Single-ended, 32 ohm load
Single-ended, 16 ohm load
Differential, 32 ohm load
20.6
37.5
86.0
24
47
94
mW
1,
Single-ended loads driven
capacitively to ground
Frequency response:
Sample rate = 48 kS/s fR20 20000 Hz
1,
3 dB cutoff includes external AC
coupling, without AC coupling the
response is low pass.
Dynamic range:
Sample rate = 48 kS/s 92 dBFS
20 Hz - 20 kHz
Total harmonic distortion plus noise THD + N -82 dBFS 2, Input = -3 dBFS.
Signal to Noise Ratio SNR 85 dB 2,1004 Hz, C-message weighted
Allowable capacitive load to ground CL100 pF 1, At each DAC output.
Power supply rejection ratio PSRR 50 70 dB 1, 20 Hz - 100 kHz,
100 mVpp supply noise.
Crosstalk -85 -70 dB 1, Between DAC outputs.
Note 1: Guaranteed by design, not tested in production.
Note 2: Single-ended or differential output.
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Figure 30 - THD+N Ratio versus Output Power Driving Low Impedance
Figure 31 - THD+N Ratio versus VRMS Driving High Impedance
10.7 External Clock Requirements
In all modes of operation the ZL38067 requires an external clock source. The external clock drives the device’s
internal PLL which is the source for the internal timing signals.
The external clock source can either be:
• 12.000 MHz crystal, or
• 12.000 MHz clock oscillator with a 2.5 V output
The following three sections discuss these options.
0.001
0.01
0.1
1
10
0 0.5 1 1.5 2
THD+N(%)
Vrms
100KDifferential
100KSingleEnded
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10.7.1 Crystal Application
The oscillator circuit that is created across pins XI and XO requires an external fundamental mode crystal that has
a specified parallel resonance (fP) at 12.000 MHz.
Figure 32 - Crystal Application Circuit
10.7.2 Clock Oscillator Application
Figure 33 illustrates the circuit that is used when the ZL38067 external clock source is a clock oscillator. The
oscillator pins are 2.5 V compliant and should not be driven from 3.3 V CMOS without a level shifter or voltage
attenuator.
Figure 33 - Clock Oscillator Application Circuit
ZL38067
DVDD33_XTAL
+3.3 V
XI
XO
Crystal
DVDD33
PLL
12.000 MHz
20 pF 20 pF
Supply decoupling is not shown
PCLKA/I2S_SCKA 100K
PCLKA/I2S_SCKA (if used)
GND (VSS)
ZL38067
DVDD33_XTAL
+3.3 V
XI
XO
VDD
DVDD33
PLL
100 nF
12.000
MHz
Oscillator
2.5 V
Output
Supply decoupling is not shown
GND (VSS)
PCLKA/I2S_SCKA 100K
PCLKA/I2S_SCKA (if used)
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11.0 Timing Characteristics
Figure 35 depicts the timing reference points that apply to the timing diagrams shown in this section. For all timing
characteristics, typical values are for TA = 25 ºC and nominal supply voltage. Minimum and maximum values are
over the industrial -40 ºC to 85 ºC temperature range and supply voltage ranges as shown in “Operating Ranges”
on page 42, except as noted.
10.7.3 PCLKA (Crystal-less) Application
Figure 34 illustrates how to configure the ZL38067 for crystal-less operation. PCLKA is used as the PLL clock
source. PLCKA must be set at a frequency of 2.048, 4.096, or 8.192 MHz. Since the crystal circuit is not used,
the DVDD33_XTAL pin can be grounded to VSS to save power. When using crystal-less application, GPIO_0 or
GPIO_1 must be pulled high to set the sample rate and the PCLKA must be active all the time. For more
information, refer to Section 7.2, “Bootstrap Modes“ on page 31.
Figure 34 - Crystal-less Application Circuit
10.7.4 AC Specifications - External Clocking Requirements
These specifications apply to crystal and clock oscillator external clocking.
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
External clocking frequency accuracy AOSC -50 50 ppm
Not tested in production
External clocking duty cycle DCOSC 40 60 %
Holdover accuracy 50 ppm
ZL38067
XI
2.048, 4.096, or
8.192 MHz Clock
XO
DVDD33_XTAL
GND (VSS)
PCLKA/I2S_SCKA
DVDD33 +3.3 V
Supply decoupling is not shown
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Figure 35 - Timing Parameter Measurement Digital Voltage Levels
All Digital
Signals
Timing Reference Points
TiRF/ToRF
VHM
VLM
VT
TiRF/ToRF
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11.1 TDM Interface Timing Parameters
All TDM timing parameters are with Full Duplex Communication Firmware running.
11.1.1 GCI and PCM Timing Parameters
Specifications for GCI and PCM timing modes are presented in the following table. The specifications apply to both
port A and port B in slave operation.
A timing diagram that applies to GCI timing of the TDM interface is illustrated in Figure 36.
Timing diagrams that apply to PCM timing of the TDM interface are illustrated in Figure 37 and Figure 38.
Note 1: PCLK frequency must be within 100 ppm.
Note 2: CLOAD = 40 pF
Note 3: CLOAD = 150 pF
Note 4: Setup times based on 2 ns PCLK rise and fall times; hold times based on 0 ns PCLK rise and fall times.
Note 5: Guaranteed by design, not tested in production.
Parameter Symbol Min Typ Max Unit Notes / Conditions
PCLK period tPCY 122 7812.5
ns
1, 2
PCLK High pulse width tPCH 48 2
PCLK Low pulse width tPCL 48 2
Fall time of clock tPCF 8
Rise time of clock tPCR 8
FS delay (output rising or falling) tFSD
2152
2253
FS setup time (input) tFSS 54
FS hold time (input) tFSH 0.5 125000 -
2tPCY
4
Data output delay tDOD
2152
2253
Data output delay to High-Z tDOZ 0105
Data input setup time tDIS 54
Data input hold time tDIH 04
Allowed PCLK jitter time tPCT 20 Peak-to-peak
Allowed Frame Sync jitter time tFST 20 Peak-to-peak
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Figure 36 - GCI Timing, 8-bit
Figure 37 - PCM Timing, 8-bit with xeDX = 0 (Transmit on Negative PCLK Edge)
V
IH
V
IL
V
IH
First
Bit
V
OL
V
OH
PCLK
FS
DX
DR
t
FSS
t
PCR
t
PCY
t
PCF
t
PCH
t
PCL
t
FSH
t
DOD
t
DIH
t
DIS
t
DOZ
Time Slot Zero, Clock Slot Zero
First
Bit
Second
Bit
V
IL
Time Slot Zero, Clock Slot Zero
First
Bit
PCLK
FS
DX
First
Bit
Second
Bit
V
OL
V
OH
V
IH
V
IL
V
IH
V
IL
DR
tFSS
tPCR
tPCY
tPCF
tPCH
tPCL
tFSH
tDOD
tDIH
tDIS
tDOZ
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Figure 38 - PCM Timing, 8-bit with xeDX = 1 (Transmit on Positive PCLK Edge)
V
IH
V
IL
V
IH
First
Bit
V
OL
V
OH
PCLK
FS
DX
DR
t
FSS
t
PCR
t
PCY
t
PCF
t
PCH
t
PCL
t
FSH
t
DOD
t
DIH
t
DIS
t
DOZ
Time Slot Zero, Clock Slot Zero
First
Bit
Second
Bit
V
IL
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Figure 39 - Slave I2S Timing
11.1.2 I2S Timing Parameters
11.1.2.1 I2S Slave
Specifications for I2S Slave timing are presented in the following table. The specifications apply to both port A and
port B. A timing diagram for the I2S Slave timing parameters is illustrated in Figure 39.
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
I2S_SCK Clock Period
fs = 48 kHz
fs = 8 kHz
tISSCP 651.04
3.91
ns
s
I2S_SCK Pulse Width High
fs = 48 kHz
fs = 8 kHz
tISSCH 292.97
1.76
358.07
2.15
ns
s
I2S_SCK Pulse Width Low
fs = 48 kHz
fs = 8 kHz
tISSCL 292.97
1.76
358.07
2.15
ns
s
I2S_SDI Setup Time tISDS 5ns
I2S_WS Setup Time tISDS 5ns
I2S_SDI Hold Time tISDH 0ns
I2S_WS Hold Time tISDH 0.5 ns
I2S_SCK Falling Edge
to I2S_SDO Valid
tISOD 215nsC
LOAD = 40 pF
tISOD
tISDS
tISDH
tISSCL
tISSCH
tISSCP
I2S_SDI
I2S_SDO
(input)
(output)
I2S_SCK
(input)
I2S_WS
(input)
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Figure 40 - Master I2S Timing
11.1.2.2 I2S Master
Specifications for I2S Slave timing are presented in the following table. The specifications apply to both port A and
port B. A timing diagram for the I2S Master timing parameters is illustrated in Figure 40.
Parameter Symbol Min. Typ. Max. Units Notes/Conditions
I2S_SCK Clock Period
fs = 48 kHz
fs = 8 kHz
tIMSCP 651.04
3.91
ns
s
I2S_SCK Pulse Width High
fs = 48 kHz
fs = 8 kHz
tIMSCH 318.0
1.95
333.0
1.96
ns
s
I2S_SCK Pulse Width Low
fs = 48 kHz
fs = 8 kHz
tIMSCL 318.0
1.95
333.0
1.96
ns
s
I2S_SDI Setup Time tIMDS 5ns
I2S_SDI Hold Time tIMDH 0ns
I2S_SCK Falling Edge to I2S_WS tIMOD 215nsC
LOAD = 40 pF
I2S_SCK Falling Edge
to I2S_SDO Valid
tIMOD 215nsC
LOAD = 40 pF
tIMDS
tIMDH
tIMOD tIMSCP
tIMSCH tIMSCL
I2S_SDI
I2S_SDO
(input)
(output)
I2S_SCK
(output)
I2S_WS
(output)
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Note 1: HCLK may be stopped in the high or low state indefinitely without loss of information. When HCS is at low state, every 16
HCLK cycles, the 16-bit received data will be interpreted by the SPI interface logic.
Note 2: The first data bit is enabled on the falling edge of HCS or on the falling edge of HCLK, whichever occurs last.
Note 3: The SPI Slave requires 61ns HCS off time just to make the transition of HCS synchronized with HCLK clock. In the command
framing mode, there is no HCS off time between each 16-bit command/data, and HCS is held low until the end of command.
Note 4: If HCS is not held low for 8 or 16 HCLK cycles exactly, the SPI Slave will reset. During byte or word framing mode, HCS is
held low for the whole duration of the command. Multiple commands can be transferred with HCS low for the whole duration
of the multiple commands. The rising edge of the HCS indicates the end of the command sequence and resets the SPI Slave.
Note 5: Guaranteed by design, not tested in production.
11.2 Host Bus Interface Timing Parameters
The HBI is the main communication port from the host processor to the ZL38067, this port can read and write all of
the memory and registers on the ZL38067. The port can be configured as SPI Slave or I2C Slave.
For fastest command and control operation, use the SPI Slave configuration. The SPI Slave can be operated with
HCLK speeds up to 25 MHz; the I2C Slave will operate with HCLK speeds up to 400 kHz.
11.2.1 SPI Slave Port Timing Parameters
The following table describes timing specific to the ZL38067 device. A timing diagram for the SPI Slave timing
parameters is illustrated in Figure 41.
For seemless control operation, both the SPI Slave timing and the system timing need to be considered when
operating the SPI Slave at high speeds. System timing includes host set-up and delay times and board delay times.
Parameter Symbol Min. Typ. Max. Units Notes /
Conditions
HCLK Clock Period tSSCP 40
ns
HCLK Pulse Width High tSSCH 16 tSSCP/2 1
HCLK Pulse Width Low tSSCL 16 tSSCP/2 1
HDIN Setup Time tSSDS 5
HDIN Hold Time tSSDH 0
HCS Asserted to HCLK Rising Edge:
Write
Read if host samples on falling edge
Read if host samples on rising edge
tSHCSC 5
5
tSSFD + host
HDOUT setup
time to HCLK
tSSCP/2
tSSCP/2
tSSFD + tSSCP/2
HCLK Driving Edge to HDOUT Valid tSSOD 215C
LOAD = 40 pF
HCS Falling Edge to HDOUT Valid tSSFD 0152, C
LOAD = 40 pF
HCS De-asserted to HDOUT Tristate tSSOZ 0105, C
LOAD = 40 pF
HCS Pulse High tSHCSH 20 tSSCP/2 1, 3
HCS Pulse low tSHCSL 4
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Figure 41 - SPI Slave Timing
11.2.2 I2C Slave Interface Timing Parameters
The I2C interface uses the SPI Slave interface pins.
Specifications for I2C interface timing are presented in the following table. A timing diagram for the I2C timing
parameters is illustrated in Figure 42.
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
SCLK Clock Frequency fSCL 0400
kHz
START Condition Hold Time tSTARTH 0.6 s
SDA data setup time tSDAS 100 ns
SDA Hold Time Input tSDAH 100 ns
SDA Hold Time Output tSDAH 300 ns
High period of SCLK tSCLH 0.6 s
Low period of SCLK tSCLL 1.3 s
STOP Condition Setup Time tSTOPS 0.6 s
Repeated Start Condition
Setup Time
tSTARTS 0.6 s
Pulse Width Spike Suppression,
glitches ignored by input filter
tSP 50 ns
HCS
HCLK
HDOUT
HDIN
tSSDS
tSSCH tSSCL
tSSDH
tSHCSC
tSSCP
tSSOZ
tSHCSH
tSSOD
tSSFD
tSHCSL
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Figure 42 - I2C Timing Parameter Definitions
Figure 43 - UART_RX Timing
Figure 44 - UART_TX Timing
11.3 UART Timing Parameters
Specifications for UART timing are presented in the following table. Timing diagrams for the UART timing
parameters are illustrated in Figure 43 and Figure 44.
Parameter Symbol Min. Typ. Max. Units Notes / Conditions
UART_RX and UART_TX bit width
Baud rate = 115.2 kbps
tUP 8.68 s
Allowed baud rate deviation
8 bits with no parity
4.86 % Guaranteed by design, not
tested in production.
I2C_SCLK
I2C_SDA
(With Start/Stop)
I2C_SDA
(With Start/Repeated Start)
fSCL
tSCLL tSCLH
tSTARTH tSDAS tSDAH tSTOPS
tSTARTS
UART_RX
tUP tUIA
1 Stop bit example
UART_TX
tUP
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Figure 45 - Master SPI Timing
11.4 Master SPI Timing Parameters
Specifications for Master SPI timing are presented in the following table. A timing diagram for the Master SPI
timing parameters is illustrated in Figure 45.
Parameter Symbol Min. Typ. Max. Units Notes/Conditions
SM_CLK Clock Period tMSCP 40 320
ns
Max. 25.0 MHz
SM_CLK Pulse Width High tMSCH (tMSCP/2) - 2 160
SM_CLK Pulse Width Low tMSCL (tMSCP/2) - 2 160
SM_MISO Setup Time tMSDS 3
SM_MISO Hold Time tMSDHD 0
SM_CS Asserted to
SM_CLK Sampling Edge
tMSCC (tMSCP/2) - 4
SM_CLK Driving Edge to SM_MOSI
Valid
tMSOD -1 2 CLOAD = 40 pF
SM_MOSI Setup to
SM_CLK Sampling Edge
tMSOS (tMSCP/2) - 4 CLOAD = 40 pF
SM_MOSI Hold Time to SM_CLK
Sampling Edge
tMSOHD (tMSCP/2) - 4 CLOAD = 40 pF
SM_CS Hold Time after last SM_CLK
Sampling Edge
tMSCSHD (tMSCP/2) - 4
SM_CS Pulse High tMSCSH (tMSCP/2) - 2
SM_CS
SM_CLK
SM_MISO
SM_MOSI
SM_CLK
tMSDS
tMSCH tMSCL
tMSDHD
tMSCC
tMSCP tMSCSHD
tMSOD tMSOHD
tMSCSH
tMSOS
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12.0 AEC Tuning
To optimize the acoustic properties of a given system design, the Audio Processor firmware requires gain and level
tuning. The mechanical design, including the speaker and microphone quality and placement, will all affect the
system’s acoustic performance. Microsemi has developed MiTuner™ GUI Software (ZLS38508) and the Microsemi
Audio Interface Box (AIB) Evaluation Kit (ZLE38470BADA) to automatically optimize the firmware’s tunable
parameters for a given hardware design, facilitating the system design process and eliminating the need for tedious
manual tuning. In order to achieve a high level of acoustic performance for a given enclosure, the MiTuner GUI
Software performs both Auto Tuning and Subjective Tuning.
Access to the UART and TDM port of the ZL38067 need to be provided on the system board in order to perform
Auto Tuning or Subjective Tuning with the ZLS38508 software. Figure 46 shows the nodes that need to be made
available and illustrates an AIB Header that when mounted, will provide a direct connection to the Audio Interface
Box cable (no soldering or jumpers required). TDM port A is shown, but port B can be used instead. The header
only needs to be populated on the system board(s) that are used for tuning evaluation.
Note: Any connections to a host processor need to be isolated from the UART and I2S ports during the tuning process. If a host
processor is connected to these ports, a resistor should be placed between the host and each ZL38067 port signal, so that the
resistor can be removed to isolate the host from the ZL38067 without interfering with the ZL38067’s connection to the AIB.
To interface between the header and the AIB, a 10-wire ribbon cable is used. The cable is terminated on both ends
with a double row, 5 position, 100 mil (2.54 mm) female socket strip. Pin 10 on each socket is keyed to ensure
proper signal connection. On the system board header pin 10 must be removed, or alternatively both pins 9 and 10
can be eliminated to reduce the space needed on the system board. Signal integrity series termination resistors are
provided for the interface in the AIB.
Figure 46 - AIB System Board Connection
Note: A Samtec TSW-105-07-L-D through-hole terminal strip, or a Samtec TSM-105-01-L-DV surface mount terminal strip, or a
suitable equivalent can be used for the AIB Header. The header is a double row, 5 position, 10-pin male 100 mil (2.54 mm)
unshrouded terminal strip with 25 mil (0.64 mm) square vertical posts that are 230 mils (5.84 mm) in length.
1 2
3 4
56
7 8
910
AIB
Header
ZL38067
I2S _SDOA
I2S_SDIA
I2S_WSA
I2S_SCKA
VSS
UART_TX
UART_RX
Key
(Pin removed)
2
1
10
9
X
AIB Header, Top View
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13.0 Package Outline Drawings
Figure 47 - 64-Pin QFN
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Figure 48 - Recommended 64-Pin QFN Land Pattern Top View
64-QFN
9 mm x 9 mm, 0.5 mm pitch
Recommended EPAD configuration uses 0.292"/7.42 mm square pad tied to a ground plane with
a 9 x 9 array of 0.013"/0.33 mm vias. This is necessary for good thermal performance.
* Minimum spacing between pins and epad must be 0.3 mm
EPAD 0. 292 "/7 .42 mm
square pad
0 .013 "/ 0.33 mm drill
tied to ground plane,
9 x 9 array
0.0197 "/0.5 mm
0 .1772 "/4.5 m m
Pad and Past emask
30 mil x 10 mil
Soldermask 35 mil x 15 mil
SOLDER MASK and EPAD
0.3543 "/9 mm
1
0 .0125 "/0.318 mm
0.3 mm min*
EPAD solder mask
0 .287 " sq /7. 29 mm
0.3543 "/9 mm
EPAD 0.292 "/7.42 mm
square pad
EPAD solder mask
0 .287 "/7 .29 m m sq
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Figure 49 - 56-Ball WLCSP
ZL38067 Preliminary Data Sheet
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Figure 50 - 56-Ball WLCSP Staggered Balls Expanded Bottom View
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14.0 Revision History
The following table lists substantive changes that were made to this Preliminary Data Sheet revision.
Changes Pages
Added "Command Framing triggers to ASR-assist feature" 1
Added crystal-less operation and bootstrap configuration. 31, 50
Added typical power consumption values to section 10.4.7 45
Table 18 - List of Changes to the Preliminary Data Sheet
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