Freescale P10XX and P20XX System Clock with Selectable DDR Frequency 6V49205B DATASHEET Description Typical Applications The 6V49205B is a main clock for Freescale P10xx and P20xx-based systems. It has a selectable System CCB clock and 2 DDRCLK speeds - 100M or 66.66M. The 6V49205B also provides LP-HCSL PCIe outputs for low-power and reduced board space. System Clock for Freescale P10xx and P20xx-based designs Features * Replaces 11 crystals, 2 oscillators and 3 clock generators; lowers cost, power and area Output Features * Integrated terminations on LP-HCSL PCIe outputs; * 1 - Sys_CCB 3.3V LVCMOS output at 100M/83.33M/ * * * * * * * 80M/66.66M 1 - DDRCLK 3.3V LVCMOS output at 100M or 66.66M 1 1 - 125M 3.3V LVCMOS output 6 - LP-HCSL PCIe pairs selectable at 100M or 125M 6 - 25MHz 3.3V LVCMOS outputs 2 - 2.048M 3.3V LVCMOS outputs 2 - USB 3.3V LVCMOS outputs at 12M or 24M * * * Key Specifications eliminate 24 resistors, saving 41mm2 of board area Industrial temperature range operation; supports demanding environmental conditions Advanced 3.3V CMOS process; high-performance, low-power Supports independent spread spectrum on Sys_CCB/DDRCLK and PCIe outputs Available in space-saving 7 x 7 mm 48-VFQFPN with 0.5mm pad pitch; reduced board space without the need for fine-pitch assembly techniques * PCIe Gen1-2-3 compliant * < 3p rms phase noise on REF outputs Block Diagram SCLK SDATA ^FS0 ^FS1 ^SEL100#_66 ^SELPCIE125#_100 Control Logic PLL4 (SS) DDRCLK 100MHz PLL3 (nonSS) X1 25MHz Crystal Sys_CCB PLL1 (SS) Crystal Oscillator PLL2 (nonSS) X2 PCIe_L(5:0) USB_CLK(2:1) 2.048M(1:0) 125M REF(5:0) GND Note 1: For DDR Clock: Processor core and I/O supply rails must be ramped with VDD3P3 or earlier. Clock signal will be clamped LOW and output clock will be 100MHz if this is not followed (see diagram below). VDD3P3 R40 10K DDRCLK R39 6V49205B MAY 5, 2017 10K 1 (c)2017 Integrated Device Technology, Inc. 6V49205B DATASHEET Pin Assignments 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 6V49205B X2_25 X1_25 GNDREF REF5 REF4 REF3 VDDREF GNDREF REF2 REF1 ^SELPCIE125#_100/REF0 AVDD12_24 ^FS0/USB_CLK1 ^FS1/USB_CLK2 GND12_24 GND2.048 CK2.048_0 CK2.048_1 VDD2.048 AVDD125 125M GND125M PCIeT_LR0 PCIeC_LR0 VDDREF SDATA SCLK GndDDR ^SEL100#_66/DDRCLK VddDDR AVDDSYS Sys_CCB GNDSYS GNDPCIe PCIeT_LR5 PCIeC_LR5 PCIeT_LR4 PCIeC_LR4 GNDPCIe AVDDPCIe PCIeT_LR3 PCIeC_LR3 PCIeT_LR2 PCIeC_LR2 GNDPCIe VDDPCIe PCIeT_LR1 PCIeC_LR1 PCIeC_LR5 PCIeT_LR5 GNDPCIe GNDSYS Sys_CCB AVDDSYS VddDDR ^SEL100#_66/DDRCLK GndDDR SCLK SDATA VDDREF 48-Pin TSSOP ^ Indicates Internal 100kohm pull up resistor 48 47 46 45 44 43 42 41 40 39 38 37 X2_25 1 36 PCIeT_LR4 X1_25 2 35 PCIeC_LR4 GNDREF 3 34 GNDPCIe REF5 4 33 AVDDPCIe REF4 5 32 PCIeT_LR3 REF3 6 31 PCIeC_LR3 6V49205B VDDREF 7 30 PCIeT_LR2 GNDREF 8 29 PCIeC_LR2 REF2 9 28 GNDPCIe REF1 10 27 VDDPCIe ^SELPCIE125#_100/REF0 11 26 PCIeT_LR1 AVDD12_24 12 25 PCIeC_LR1 PCIeT_LR0 PCIeC_LR0 125M GND125M AVDD125 VDD2.048 CK2.048_1 GND2.048 CK2.048_0 GND12_24 ^FS1/USB_CLK2 ^FS0/USB_CLK1 13 14 15 16 17 18 19 20 21 22 23 24 48-Pin VFQFPN ^ Indicates Internal 100kohm pull up resistor FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY 2 MAY 5, 2017 6V49205B DATASHEET Pin Descriptions PIN # 1 2 3 4 5 6 7 8 9 10 11 PIN NAME X2_25 X1_25 GNDREF REF5 REF4 REF3 VDDREF GNDREF REF2 REF1 ^SELPCIE125#_100/RE F0 PIN TYPE OUT IN PWR OUT OUT OUT PWR PWR OUT OUT I/O 12 AVDD12_24 13 ^FS0/USB_CLK1 PWR I/O 14 ^FS1/USB_CLK2 I/O 15 16 17 18 19 20 21 22 23 GND12_24 GND2.048 CK2.048_0 CK2.048_1 VDD2.048 AVDD125 125M GND125M PCIeT_LR0 PWR PWR OUT OUT PWR PWR OUT PWR OUT 24 PCIeC_LR0 OUT 25 PCIeC_LR1 OUT 26 27 28 PCIeT_LR1 VDDPCIe GNDPCIe OUT PWR PWR 29 PCIeC_LR2 OUT 30 PCIeT_LR2 OUT 31 PCIeC_LR3 OUT 32 33 34 PCIeT_LR3 AVDDPCIe GNDPCIe OUT PWR PWR 35 PCIeC_LR4 OUT 36 PCIeT_LR4 OUT 37 PCIeC_LR5 OUT 38 39 40 41 42 43 PCIeT_LR5 GNDPCIe GNDSYS Sys_CCB AVDDSYS VddDDR OUT PWR PWR OUT PWR PWR 44 ^SEL100#_66/DDRCLK 45 46 47 48 GndDDR SCLK SDATA VDDREF MAY 5, 2017 I/O PWR IN I/O PWR DESCRIPTION Crystal output, Nominally 25.00MHz. Crystal input, Nominally 25.00MHz. Ground pin for the REF outputs. Copy of crystal input Copy of crystal input Copy of crystal input Ref, XTAL power supply, nominal 3.3V Ground pin for the REF outputs. Copy of crystal input Copy of crystal input Latched input to select the PCIe output frequency/REF0 output. 0 = 125M 1 = 100M Power for 12_24MHz PLL core, and outputs. Nominal 3.3V Frequency select latch for Sys_CCB / 12 or 24MHz USB clock output. 3.3V. This pin has an internal pull up resistor. Frequency select latch for Sys_CCB / 12 or 24MHz USB clock output. 3.3V. This pin has an internal pull up resistor. Ground pin for 12_24M outputs. Ground pin for 2.048M outputs. 2.048M output, nominal 3.3V. 2.048M output, nominal 3.3V. Power supply for 2.048M outputs, nominal 3.3V. Power for 125MHz PLL core and output, nominal 3.3V 125M output, nominal 3.3V. Ground pin for 125M outputs. True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor Power supply for PCI Express outputs, nominal 3.3V Ground pin for the PCIe outputs. Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor Analog Power supply for PCI Express clocks, nominal 3.3V Ground pin for the PCIe outputs. Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor Complement clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor True clock of 0.8V differential push-pull PCI_Express pair with integrated 33ohm series resistor Ground pin for the PCIe outputs. Ground pin for the Sys_CCB output System CCB clock output Analog Power supply for Sys_CCB clock and outputs, nominal 3.3V Power supply for DDR Clock output, nominal 3.3V Latched input to select the DDR output frequency/DDRCLK output. See note regarding system power sequencing. 0 = 100M 1 = 66.666M Ground pin for the DDR outputs. Clock pin of SMBus circuitry. Data pin for SMbus circuitry. Ref, XTAL power supply, nominal 3.3V 3 FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY 6V49205B DATASHEET Table 1: PCIEX Spread Table (selectable via SMBUS) SELPCIE125#_100 B0b4 B0b3 Spread % B6b4 0 (125MHz) x x No Spread 1 (100MHz) 0 0 No Spread (default) 1 (100MHz) 0 1 Down -0.5% 1 (100MHz) 1 0 Down -0.75% 1 (100MHz) 1 1 No Spread *Once in spread mode, do not return to non spread without reset Table 2: Sys_CCB and DDR Spread Table (selectable via SMBUS) B0b7 0 0 0 0 1 1 1 1 B0b6 0 0 1 1 0 0 1 1 B0b5 0 1 0 1 0 1 0 1 Spread % No Spread (default) Down -0.5% Down -0.75% Down -0.25% Down -1% Down -1.25% Down -1.5% Down -2% Table 3: Sys_CCB Frequency Select Table (Latched and selectable via SMBUS) FS1 / B4b3 FS0 / B4b2 Sys_CCB (MHz) 0 0 66.66 0 1 100 1 0 80 1 1 83.33 Table 4: PCI Express Amplitude Control B6b7 0 0 1 1 B6b6 0 1 0 1 PCIe Amplitude 700mV 800mV 900mV 1000mV FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY 4 MAY 5, 2017 6V49205B DATASHEET Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the 6V49205B. These ratings, which are standard values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. PARAMETER Maximum Supply Voltage Maximum Input Voltage SYMBOL VDDxxx VIH CONDITIONS Supply Voltage Referenced to GND MIN Minimum Input Voltage VIL Referenced to GND GND - 0.5 Storage Temperature Ts Junction Temperature Tj Input ESD protection ESD prot Human Body Model NOTES on Absolute Max Parameters 1 Operation under these conditions is neither implied, nor guaranteed. TYP -65 MAX 4.6 VDD + 0.5 150 125 2000 UNITS V V Notes 1 1 V 1 C C V 1 1 Electrical Characteristics - Input/Supply/Common Output DC Parameters TAMB = -40 to +85C; VDD = 3.3 V +/-5%, All outputs driving test loads (unless noted otherwise). PARAMETER SYMBOL CONDITIONS Ambient Operating Temp TAMB Supply Voltage VDDxxx Supply Voltage Power supply Ramp Time TPWRRMP Power supply ramp must be monotonic MIN -40 3.135 TYP 25 3.3 MAX 85 3.465 4 UNITS C V ms Latched Input High Voltage VIH_LI Single-ended Latched Inputs 2.1 VDD + 0.3 V Latched Input Low Voltage VIL_LI Single-ended Latched Inputs V SS - 0.3 0.8 V -5 Input Leakage Current IIN VIN = VDD , VIN = GND Operating Supply Current IDDOP3.3 All outputs loaded and running Input Frequency Fi Pin Inductance Lpin CIN Logic Inputs 3 5 pF Input Capacitance COUT Output pin capacitance 5 6 pF CINX X1 & X2 pins From VDD Power-Up or de-assertion of PD to 1st clock 5 6 pF 3.2 5 ms 10 ns 1 10 ns 1 3.3 V 0.4 V Clk Stabilization 23 TSTAB Tfall_SE TFALL Trise_SE TRISE 1.5 5 uA 119 155 mA 25 27 MHz 5 7 nH Notes Fall/rise time of all 3.3V control inputs from 20-80% SMBus Voltage VDD Low-level Output Voltage Current sinking at VOLSMB = 0.4 V VOLSMB @ IPULLUP IPULLUP SMB Data Pin 2.7 4 SCLK/SDATA (Max VIL - 0.15) to TRI2C Clock/Data Rise Time (Min VIH + 0.15) SCLK/SDATA (Min VIH + 0.15) to TFI2C Clock/Data Fall Time (Max VIL - 0.15) SMBus Operating Frequency FSMBUS NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in 1 Signal is required to be monotonic in this region. 2 Input leakage current does not include inputs with pull-up or pull-down resistors. 3 For margining purposes only. Normal operation should have Fin =25MHz. MAY 5, 2017 5 2 3 mA 1000 ns 300 ns 400 kHz production). FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY 6V49205B DATASHEET AC Electrical Characteristics - Low Power HCSL-Compatible PCIe Outputs PARAMETER SYMBOL CONDITIONS Clock Frequency f Spread off ppmSSof f PCIe 100MHz or 125MHz ppmSSon PCIe @ -0.5% spread, 100MHz only Rising/Falling Edge Slew Rate t SLEW Differential Measurement Synthesis error MIN TYP 100.00 125.00 0 MAX UNITS MHz MHz ppm ppm 1,2 5.7 V/ns 1,3,6 +/-100 2.2 4.1 NOTES 2,3 2,3 1,2 Slew Rate Variation tSLVAR Single-ended Measurement 1 20 % 1,6 Maximum Output Voltage VHIGH Includes overshoot 793 1150 mV 6,7 Minimum Output Voltage VLOW Includes undershoot -300 mV 6,7 Differential Voltage Swing VSWING Differential Measurement 300 mV 1,6 300 Crossing Point Voltage VXABS Single-ended Measurement Crossing Point Variation VXABSVAR Single-ended Measurement Duty Cycle DCY C Differential Measurement PCIe Jitter - Cycle to Cycle PCIeJC2C PCIe[5:0] Skew Spread Spectrum Modulation Frequency Notes for PCIe Clocks: -22 419 550 mV 1,4,6 115 140 mV 1,4,5 50.1 55 % 1 Differential Measurement 36 125 ps 1 TSKEwPCIe50 Differential Measurement 1172 1500 ps 1,6,8 fSSMOD Triangular Modulation 31.5 33 kHz 45 30 1 Guaranteed by design and characterization, not 100% tested in production. Clock Frequency specifications are guaranteed assuming that REF is at 25MHz. 3 Slew rate measured through V_swing voltage range centered about differential zero. 4 Vcross is defined at the voltage where Clock = Clock#. 5 Only applies to the differential rising edge (Clock rising, Clock# falling.) 6 At default SMBus settings. 7 The Freescale P-series CPU's have internal terminations on their SerDes Reference Clock inputs. The resulting amplitude at these inputs will be 1/2 of the values listed, which are well within the 800mV Freescale specification for these inputs. 8 This value includes an intentional output-to-output skew of approximately 250ps. 2 Electrical Characteristics - Phase Jitter, PCIe Outputs at 100MHz PARAMETER SYMBOL tjphPCIe1 tjphPCIe2Lo Jitter, Phase t jphPCIe2Hi tjphPCIe3 CONDITIONS PCIe Gen 1 phase jitter PCIe Gen 2 phase jitter Lo-band content PCIe Gen 2 phase jitter Hi-band content TYP MIN PCIe Gen 3 phase jitter 35 MAX 56 1.6 2.4 1.9 2.8 0.5 0.83 INDUSTRY SPEC LIMIT UNITS NOTES 86 ps 1,2,3 ps 3 1,2,3 (RMS) ps 3.1 1,2,3 (RMS) ps 1 1,2,3 (RMS) Notes on Phase Jitter: 1 See http://www.pcisig.com for complete specs. Guaranteed by design and characterization, not tested in production. 2 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12. 3 Applies to PCIe outputs @ default amplitude and 100MHz with spread off or at -0.5%. FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY 6 MAY 5, 2017 6V49205B DATASHEET Electrical Characteristics - DDR Clock PARAMETER DDR Clock Frequency Synthesis error SYMBOL fDDR66.66 CONDITIONS SEL100#_66 = 1, VT = OVDD/2 V fDDR100 SEL100#_66 = 0, VT = OVDD/2 V 100.00 MHz 2,3,6 ppmSSof f Spread off 0 ppm 1,2,5 +/-150 ppm 1,2,5 V 1 V 1 ppmSSon Spread on Output High Voltage VOH VOH at the selected operating frequency Output Low Voltage VOL VOL at the selected operating frequency tSLEW00 '00' = Hi-Z tSLEW01 '01' Slow Slew Rate (Averaging on) Slew Rate VDDO = 3.3V MIN TYP 66.666 MAX 2.4 0.4 Hi-Z 1.1 1.6 UNITS MHz NOTES 2,3,6 V/ns 2.3 V/ns 1,3,8 tSLEW10 '10' Fast Slew Rate (Averaging on) 1.6 2.3 3.2 V/ns 1,3,8 tSLEW11 '11' Fastest Slew Rate (Averaging on) 1.8 2.7 3.7 V/ns 1,3,8 40 1,6 Duty Cycle dt1 VT = OVDD/2 V 51.4 60 % Jitter, Peak period jitter t jpeak VT = OVDD/2 V 96 150 ps 1,6 Phase Noise t phasenoise -56dBc 10 500 kHz 1,7 AC Input Swing Limits @ 3.3V OVDD VAC This is the difference between VOL and VOH at the selected operating frequency. 1.9 3.4 V 1 Spread Spectrum Modulation Frequency fSSMOD Triangular Modulation 30 32.3 60 kHz MIN TYP 66.666 100.00 80.00 83.333 0 MAX UNITS MHz MHz MHz MHz ppm NOTES 2,3,6 2,3,6 2,3,6 2,3,6 1,2,5 ppm 1,2,5 V 1 V 1 Electrical Characteristics - Sys_CCB PARAMETER SYMBOL Clock Frequency fSy s_CCB Synthesis error CONDITIONS FS(1:0) = 00, VT = OVDD/2 V FS(1:0) = 01, VT = OVDD/2 V FS(1:0) = 10, VT = OVDD/2 V FS(1:0) = 11, VT = OVDD/2 V Spread off ppmSSof f ppmSSon Spread on Output High Voltage VOH VOH at the selected operating frequency Output Low Voltage VOL VOL at the selected operating frequency tSLEW00 '00' = Hi-Z +/-150 2.4 0.4 Hi-Z V/ns tSLEW01 '01' Slow Slew Rate (Averaging on) 0.8 1.4 2.1 V/ns 1,3,8 tSLEW10 '10' Fast Slew Rate (Averaging on) 0.9 1.6 2.5 V/ns 1,3,8 tSLEW11 '11' Fastest Slew Rate (Averaging on) 1.1 1.9 3.1 V/ns 1,3,8 Duty Cycle dt1 VT = OVDD/2 V 40 51.4 60 % 1,6 Jitter, Peak period jitter t jpeak VT = OVDD/2 V, SSC < 0.75% 116 150 ps 1 Phase Noise t phasenoise -56dBc 10 500 kHz 1,7 AC Input Swing Limits @ 3.3V OVDD VAC This is the difference between VOL and VOH at the selected operating frequency. 1.9 V 1 Spread Spectrum Modulation Frequency fSSMOD Triangular Modulation 0 31.5 60 kHz TYP 125.00 MAX UNITS ns ppm V NOTES 2,3,6 1,2,5 1 0.5 V 1 0.7 1 ns 1,3 52 53 % 1 150 ps 1 Slew Rate VDDO = 3.3V Electrical Characteristics - 125M PARAMETER Clock frequency Synthesis error Output High Voltage SYMBOL f125M ppm VOH CONDITIONS VT = OVDD/2 V MIN VOH at the selected operating frequency 2.2 Output Low Voltage Rise/Fall time VDDO = 3.3V Duty Cycle VOL VOL at the selected operating frequency tRF125M3.3V Measured between 0.6V and 2.7V dt1 VT = OVDD/2 V Jitter, Peak period jitter t jpeak VT = OVDD/2 V MAY 5, 2017 0 7 47 FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY 6V49205B DATASHEET Electrical Characteristics - REF(5:0) PARAMETER Clock Frequency Crystal Frequency Error Output High Voltage SYMBOL f ppm VOH CONDITIONS VT = OVDD/2 V Including all aging and tuning effects VOH at the selected operating frequency Output Low Voltage Slew Rate VDDO 3 3V Duty Cycle VOL VOL at the selected operating frequency 0.4 V 1 tSLEW '00' = Hi-Z 1.0 1.7 2.7 V/ns 1,3,4 dt1 VT = OVDD/2 V 40 51 60 % 1 Pin to Pin Skew tskew ps 1 Jitter, Peak period jitter t jpeak VT = 1.5 V, odd/even outputs have an intentional 180degree phase shift. VT = OVDD/2 V Jitter, Phase tjphase (12kHz-5MHz), VT = 1.5 V MIN TYP 25.00 -50 2.2 MAX 50 N/A UNITS MHz ppm V NOTES 2,3 1,2 1 78 200 ps 1 1.7 3 ps rms 1 TYP 12.00 MAX UNITS MHz MHz ppm NOTES 2,3 2,3 1,2,5 V 1 V 1 Electrical Characteristics - USB_CLK(2:1) PARAMETER SYMBOL CONDITIONS Clock Frequency fUSB_CLK VT = OVDD/2 V Synthesis error ppm Output High Voltage VOH VOH at the selected operating frequency Output Low Voltage Slew Rate VDDO = 3.3V VOL VOL at the selected operating frequency tSLEW00 '00' = Hi-Z MIN 24.00 0 2.2 0.4 Hi-Z V/ns tSLEW01 '01' Slow Slew Rate (Averaging on) 1.0 1.4 1.8 V/ns tSLEW10 '10' Fast Slew Rate (Averaging on) 1.5 2.0 2.7 V/ns 1,3,4 1,3,4 tSLEW11 '11' Fastest Slew Rate (Averaging on) 1.8 2.3 3.1 V/ns 1,3,4 45 Duty Cycle dt1 VT = OVDD/2 V 50.3 55 % 1 Jitter, RMS tjRMS 12kHz to Nyquist 23 120 ps 1 Jitter, Cycle to cycle tjcy c-cy c VT = OVDD/2 V 142 350 ps 1 TYP 2.048 MAX UNITS MHz NOTES 2,3,6 ppm 1,2,5 Electrical Characteristics - 2.048M(1:0) PARAMETER Clock Frequency SYMBOL fUSB_CLK Synthesis error ppm Output High Voltage VOH VOH at the selected operating frequency Output Low Voltage VOL VOL at the selected operating frequency tSLEW00 '00' = Hi-Z Slew Rate VDDO = 3.3V tSLEW01 '01' Slow Slew Rate (Averaging on) 1.1 tSLEW10 '10' Fast Slew Rate (Averaging on) tSLEW11 dt1 Duty Cycle CONDITIONS VT = OVDD/2 V MIN 0 2.2 V 1 0.4 V 1 1.7 2.5 V/ns 1.6 2.3 3.2 V/ns 1,3,4 '11' Fastest Slew Rate (Averaging on) 1.8 2.6 3.6 V/ns 1,3,4 VT = OVDD/2 V 45 46.7 55 % 1 Hi-Z V/ns 1,3,4 Pin to Pin Skew tskew VT = OVDD/2 V 108 250 ps 1 Jitter, RMS tjRMS 12kHz to Nyquist 47 70 ps 1 Jitter, Peak period jitter t jpeak VT = OVDD/2 V 170 250 ps 1 Notes for single-ended clocks: Guaranteed by design and characterization, not 100% tested in production. 2 Clock Frequency specifications are guaranteed assuming that REF is at 25MHz. 3 At default SMBus settings. 4 Measured between 20% and 80% of OVDD. 5 This is the frequency error with respect to the crystal frequency. 6 Measured at the rising and/or falling edge at OVDD/2 V. 7 Phase noise is calculated as the FFT of the TIE jitter. 8 Slew rate is measured from 0.3VAC at the center of peak to peak voltage at the clock input. 1 FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY 8 MAY 5, 2017 6V49205B DATASHEET General SMBus Serial Interface Information How to Write * * * * * * * * * * How to Read Controller (host) sends a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) sends the byte count = X IDT clock will acknowledge Controller (host) starts sending Byte N through Byte N+X-1 IDT clock will acknowledge each byte one at a time Controller (host) sends a stop bit * * * Index Block Write Operation Controller (Host) T * * * * * * * * * * * Controller (host) will send a start bit Controller (host) sends the write address IDT clock will acknowledge Controller (host) sends the beginning byte location = N IDT clock will acknowledge Controller (host) will send a separate start bit Controller (host) sends the read address IDT clock will acknowledge IDT clock will send the data byte count = X IDT clock sends Byte N+X-1 IDT clock sends Byte 0 through Byte X (if X(H) was written to Byte 8) Controller (host) will need to acknowledge each byte Controller (host) will send a not acknowledge bit Controller (host) will send a stop bit IDT (Slave/Receiver) Index Block Read Operation starT bit Controller (Host) Slave Address D2(H) WR T WRite Slave Address D2(H) ACK WR Beginning Byte = N Beginning Byte = N Data Byte Count = X ACK ACK RT Beginning Byte N X Byte O Repeat starT Slave Address D3(H) ACK O WRite ACK ACK O IDT (Slave/Receiver) starT bit RD ReaD ACK O O Data Byte Count=X O ACK Byte N + X - 1 Beginning Byte N ACK stoP bit Note: I2C compatible. Native mode is SMBus Block mode protocol. To use I2C Byte mode set the 2^7 bit in the command Byte. No Byte count is used. X Byte P ACK O O O O O O Byte N + X - 1 MAY 5, 2017 9 N Not acknowledge P stoP bit FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY 6V49205B DATASHEET Byte 0 Frequency and Spread Select Register Bit 7 6 5 4 3 2 1 0 Name SS4 SS3 SS2 SS1 SS0 REF_5_EN REF_4_EN REF_3_EN Description 0 1 Output enable for REF_5 Output enable for REF_4 Output enable for REF_5 Type RW RW RW RW RW RW RW RW Output Disabled Output Disabled Output Disabled Description Output enable for REF_2 Output enable for REF_1 Output enable for REF_0 Output enable for USB_CLK1 Output enable for USB_CLK2 Output enable for CK2.048_0 Output enable for CK2.048_1 Output enable for DDRCLK Type RW RW RW RW RW RW RW RW Output Output Output Output Output Output Output Output 0 Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Type RW RW RW RW RW RW RW RW Output Output Output Output Output Output Output Output 0 Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Sys_CCB and DDRCLK Spread Selection Table PCIE Spread Selection Table Output Enabled Output Enabled Output Enabled Default 0 0 0 0 0 1 1 1 Output Output Output Output Output Output Output Output 1 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1 Output Output Output Output Output Output Output Output 1 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1 1 Default 0 1 0 1 1 1 0 1 See Table 2: Sys_CCB and DDRCLK Spread Table See Table 1: PCIE Spread Table Byte 1 Output Enable Register Bit 7 6 5 4 3 2 1 0 Name REF_2_EN REF_1_EN REF_0_EN USB_CLK1_EN USB_CLK2_EN CK2.048_0_EN CK2.048_1_EN DDRCLK_EN Byte 2 Output Enable Register Bit 7 6 5 4 3 2 1 0 Name Sys_CCB_EN PCIe5_EN PCIe4_EN PCIe3_EN PCIe2_EN PCIe1_EN PCIe0_EN 125M_EN Description Output enable for Sys_CCB Output enable for PCIe5 Output enable for PCIe4 Output enable for PCIe3 Output enable for PCIe2 Output enable for PCIe1 Output enable for PCIe0 Output enable for 125M Byte 3 Slew Rate Control Register Bit 7 6 5 4 3 2 1 0 Name USB1_SLEW1 USB1_SLEW0 USB2_SLEW1 USB2_SLEW0 CK2.048_SLEW1 CK2.048_SLEW0 Sys_CCB_SLEW1 Sys_CCB_SLEW0 Description USB_CLK1 Slew Rate Control USB_CLK2 Slew Rate Control CK2.048_0 and CK2.048_1 Slew Rate Control Sys_CCB Slew Rate Control Type RW RW RW RW RW RW RW RW 0 See USB Electrical Tables See USB Electrical Tables See CK2.048 Electrical Tables See Sys_CCB Electrical Tables Byte 4 Slew Rate Control Register Bit 7 6 5 4 3 2 1 0 Name DDR_Slew1 DDR_Slew0 Description DDRCLK Slew Rate Control Type RW RW 0 1 See DDR Electrical Tables Reserved Reserved FS1 FS0 USB1_fSel USB2_fSel Sys_CCB Frequency Select Latch USB_CLK1 Clock Frequency Select USB_CLK2 Clock Frequency Select RW RW RW RW See Table 3: Sys_CCB Frequency Selection 12MHz 24MHz 12MHz 24MHz Default 0 1 0 1 Latch Latch 0 1 Byte 5 is Reserved FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY 10 MAY 5, 2017 6V49205B DATASHEET Byte 6 PCI Express Amplitude Control Register Bit 7 6 5 4 3 2 1 0 Name PCIE_AMP1 PCIE_AMP0 SEL100#_66 SELPCIE125#_100 Reserved Reserved Reserved Reserved Description Type RW RW R R RW RW RW RW PCI Express Amplitude Control DDRCLK latch select PCI Express latch select Reserved Reserved Reserved Reserved 0 1 See Table 4: PCIe Amplitude Selection Table 100MHz 66MHz 125MHz 100MHz - Default 0 1 latch latch 0 1 0 1 Byte 7 Revision and Vendor ID Register Bit 7 6 5 4 3 2 1 0 Name REV ID REV ID REV ID REV ID Vendor ID Vendor ID Vendor ID Vendor ID Description Revision ID Vendor ID Type R R R R R R R R 0 - 1 - Default 0 0 0 1 0 0 0 1 Type RW RW RW RW RW RW RW RW 0 1 Default 0 0 0 0 0 1 0 1 Byte 8 Byte Count Register Bit 7 6 5 4 3 2 1 0 Name BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Description Byte Count Programming b(7:0) Writing to this register will configure how many bytes will be read back. Recommended Crystal Characteristics PARAMETER VALUE UNITS NOTES Frequency Resonance Mode Frequency Tolerance @ 25C Frequency Stability, ref @ 25C Over Operating Temperature Range Temperature Range (commercial) Temperature Range (industrial) Equivalent Series Resistance (ESR) Shunt Capacitance (CO) Load Capacitance (CL) Drive Level Aging per year 25 Fundamental 20 MHz PPM Max 1 1 1 20 PPM Max 1 0~70 -40~85 50 7 8 0.1 5 C C Max pF Max pF Max mW Max PPM Max 1 1 1 1 1 1 1 MAY 5, 2017 11 FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY 6V49205B DATASHEET Test Loads Device Low-Power push-pull HCSL Output test load (integrated terminations) Zo L inches Rs=39 Differential Zo 2pF 2pF Test Load CL=4.7pF except DDRCLK outputs where CL=15pf Single-ended Output Differential Test Load, Zo = 100ohm, L = 5 inches Thermal Characteristics (48-TSSOP) PARAMETER SYMBOL CONDITIONS Thermal Resistance JC Jb JA0 JA1 JA3 Junction to Case Junction to Base Junction to Air, still air Junction to Air, 1 m/s air flow Junction to Air, 3 m/s air flow TYP UNITS NOTES VALUE 28 C/W 1 42 C/W 1 C/W 62 1 PAG48 54 C/W 1 51 C/W 1 PKG Thermal Characteristics (48-VFQFPN) PARAMETER SYMBOL CONDITIONS Thermal Resistance JC Jb JA0 JA1 JA3 Junction to Case Junction to Base Junction to Air, still air Junction to Air, 1 m/s air flow Junction to Air, 3 m/s air flow TYP UNITS NOTES VALUE 25 C/W 1 3.1 C/W 1 NLG48 32 C/W 1 25 C/W 1 22 C/W 1 PKG 1 ePad soldered to board Marking Diagrams 25 48 IDT6V4 9205BN LGI YYWW$ IDT 6V49205BPAGI YYWW$ 24 1 48TSSOP 48VFQFPN Notes: 1. "$" is the mark code. 2. "YYWW" is the last two digits of the year, and the week number that the part was assembled. 3. "G" after the two-letter package code denotes Pb free package. 4. "I" denotes industrial temperature range. 5. Bottom marking for TSSOP: country of origin if not USA. FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY 12 MAY 5, 2017 13 6V49205B DATASHEET FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY Package Outline and Dimensions (7 x 7mm 48-VFQFPN) MAY 5, 2017 6V49205B DATASHEET Package Outline and Dimensions (7 x 7mm 48-VFQFPN), cont. FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY 14 MAY 5, 2017 15 6V49205B DATASHEET FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY Package Outline and Dimensions (6.10 mm Body 48-TSSOP) MAY 5, 2017 6V49205B DATASHEET 16 Package Outline and Dimensions (6.10 mm Body 48-TSSOP), cont. FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY MAY 5, 2017 6V49205B DATASHEET Ordering Information Part / Order Number Marking Shipping Packaging Package Temperature 6V49205BPAGI see page 12 Tubes 48-pin TSSOP -40to +85C Tape and Reel 48-pin TSSOP -40to +85C 6V49205BPAGI8 6V49205BNLGI see page 12 6V49205BNLGI8 Tray 48-pin VFQFPN -40to +85C Tape and Reel 48-pin VFQFPN -40to +85C "G" after the two-letter package code denotes Pb-Free configuration, RoHS compliant. Revision History Rev. Issue Date Issuer M 12/9/2013 R. Wade N 6/2/2014 R. Wade P 8/10/2015 R. Wade Q 5/11/2016 RDW R 11/22/2016 RDW S MAY 5, 2017 5/5/2017 RDW Description 1. Extensive overhaul of Electrical tables to more closely align with Freescale published specifications. 2. Updated electrical tables with characterization data. 3. Clarified SMBus registers for Slew Rate Controls 4. Moved electrical tables in front of SMBus for consistency with other data sheets. 5. Updated Thermal Data and added test loads for clarity. 6. Updated front page text 7. Minor updates to pin names (mainly power and ground) for consistency and clarity 8. Move to Final 1. Corrected pin description for pin 44. 1. Updated SMBus operating frequency from 100KHz minimum to 400KHz maximum. 1. Correct PCIeT_LRn and PCIeC_LRn to be PCIeT_Ln and PCIeC_Ln to indicate that the Rs for the PCIe outputs is outside the part and to correct the pin description accordingly. The test loads for the device are correct. 2. Update block diagram PCIe pin names to be consistent. 1. Undo Revision Q 2. PCIe outputs have integrated terminations for 100ohm differential Zo. 3. Update Test Loads 4. Update Features/Benefits 1. Updated bit values in the "Sys_CCB Frequency Select" table. 2. Updated 48-TSSOP and 48-VFQFPN package outline drawings. 3. Updated legal disclaimer. 17 Page # Various 3 5 1-3 1-3, 12 3, 13-16 FREESCALE P10XX AND P20XX SYSTEM CLOCK WITH SELECTABLE DDR FREQUENCY Corporate Headquarters Sales Tech Support 6024 Silver Creek Valley Road San Jose, CA 95138 USA www.IDT.com www.idt.com/go/sales www.idt.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) and its affiliated companies (herein referred to as "IDT") reserve the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed in customer products. The information contained herein is provided without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non-infringement of the intellectual property rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental conditions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary. Integrated Device Technology, Inc.. All rights reserved. 6V49205B MAY 5, 2017 18 (c)2017 Integrated Device Technology, Inc.