Hyundai Micro Electronics GMS81C2020/GMS81C2120 GMS81C2020 / GMS81C2120 CMOS Single-Chip 8-Bit Microcontroller with A/D Converter & VFD Driver 1. OVERVIEW 1.1 Description The GMS81C2020 and GMS81C2120 are an advanced CMOS 8-bit microcontroller with 20K/12K bytes of ROM. These are a powerful microcontroller which provides a highly flexible and cost effective solution to many VFD applications. These provide the following standard features: 20K/12K bytes of ROM, 448 bytes of RAM, 8-bit timer/counter, 8-bit A/D converter, 10-bit High Speed PWM Output, Programmable Buzzer Driving Port, 8-bit Basic Interval Timer, 7-bit Watch dog Timer, 8-bit, Serial Peripheral Interface, on-chip oscillator and clock circuitry. They also come with high voltage I/O pins that can directly drive a VFD(Vacuum Fluorescent Display). In addition, the GMS81C2020 and GMS81C2120 support power saving modes to reduce power consumption. This document is only explained for the base of GMS81C2020(GMS81C2120), the eliminated functions are same as below. Device name ROM Size RAM Size Ports Package GMS81C2020 20Kbytes 448bytes R0,R1,R2,R3,R4,R5,R6,R7 64 SDIP, 64MQFP, 64LQFP, 64TQFP GMS81C2012 12Kbytes 448bytes R0,R2,R3,R5,R6 64SDIP, 64MQFP, 64LQFP, 64TQFP *GMS87C2020 20Kbytes (EPROM) 448bytes R0,R1,R2,R3,R4,R5,R6,R7 64SDIP, 64MQFP, 64LQFP, 64TQFP GMS81C2120 20Kbytes 448bytes R0,R1,R2,R3,R4,R5,R6,R7 42SDIP, 44MQFP, 40PDIP GMS81C2112 12Kbytes 448bytes R0,R2,R3,R5,R6 42SDIP, 44MQFP, 40PDIP *GMS87C2120 20Kbytes (EPROM) 448bytes R0,R1,R2,R3,R4,R5,R6,R7 42SDIP, 44MQFP, 40PDIP [The * Mark Devices are OTP Version] Nov. 1999 Ver 0.0 preliminary 1 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 1.2 Features - 4 By Functional Sources (SPI,ADC,WDT,BIT) * 20K/12K bytes ROM(EPROM) * 12-Channel 8-Bit On-Chip Analog to Digital Con- * 448 Bytes of On-Chip Data RAM (Including STACK Area) verter * Minimum Instruction Execution time : * Oscillatior : - 1uS at 4MHz ( 2cycle NOP Instruction ) - Crystal * One 8-Bit Basic Interval Timer - Ceramic Resonator - External RC Oscillator * One 7-Bit Watch Dog Timer - Internal RCWDT Oscillatior * Two 8-Bit Timer/Counters * Low Power Dissipation Modes * 10-Bit High Speed PWM Output - STOP mode * One 8-bit Serial Peripheral Interface - Wake-up Timer Mode - Standby Mode - Watch Mode * Two external interrupt ports - Subactive Mode * One Programmable 6-Bit Buzzer Driving port * Operating Voltage : 4.0V ~ 5.5V (at 4.5MHz) * 60 I/O Lines - 56 Programmable I/O pins * Operating Frequency : 0.4MHz ~ 4.5MHz : 30 high-voltage pins (40V,max) * Subclock : 32.768KHz Crystal Oscillator - 3 Input Only pins : 1 high-voltage pin - 1 Output Only pin * Enhanced EMS Improvement Power Fail Processor * Eight Interrupt Sources - 2 By External Sources (INT0, INT1) ( Noise Immunity Circuit ) - 2 By Timer/Counter Sources (Timer0, Timer1) Device name Total I/O Normal I/O High Voltage I/O Input Only Output Only GMS81C2020 60 pins 26 pins 30 pins 3 pins 1 pins GMS81C2012 60 pins 26 pins 30 pins 3 pins 1 pins GMS81C2120 38 pins 13 pins 21 pins 3 pins 1 pins GMS81C2112 38 pins 13 pins 21 pins 3 pins 1 pins * w here, T otal I/O is all ports except pow er and ground ports Development Tools The GMS800 family is supported by a full-featured macro assembler, an in-circuit emulators CHOICE-Dr.TM, and add-on board type OTP writer Dr.WriterTM . 2 preliminary In Circuit Emulator CHOICE-Dr. Assembler HME Macro Assembler OTP Writer Dr.Writer Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 2. BLOCK DIAGRAM (GMS81C2020) R07 R06 R05 R04 R03/BUZO R02/EC0 R01/INT1 R00/INT0 AVDD AVSS ADC Power Supply Driver Buzzer PSW ALU R10~R17 R20~R27 R30~R35 R1 R2 R3 R0 Stack Pointer Accumulator Vdisp/RA PC Data Memory (448 bytes) Program Memory Interrupt Controller Data Table 8-b it B a sic In te rva l T im e r S yste m c o n tro lle r S yste m C lo ck C o n tro lle r S u b S yste m C lo ck C o n tro lle r Watchdog Timer 8-bit Timer/ Counter 8-bit serial Interface 8-bit PWM PC 8-bit ADC T im in g g e n e ra to r C lo c k G e n e ra to r Nov. 1999 Ver 0.0 VDD VSS SXI SXO XO XI RESETB R4 Power Supply R40 / T0O R41 R42 R43 R5 R50 R51 R52 R53 / SCLK R54 / SIN R55 / SOUT R56 / PWM1O/T1O R57 preliminary R6 R60 / AN0 R61 / AN1 R62 / AN2 R63 / AN3 R64 / AN4 R65 / AN5 R66 / AN6 R67 / AN7 R7 R70 / AN8 R71 / AN9 R72 / AN10 R73 / AN11 3 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 3. PIN ASSIGNMENT (GMS81C2020) 64SDIP T0O R40 R41 R42 R43 R50 R51 R52 R53 SCLK SIN R54 SOUT R55 PWM1O/T1O R56 R57 RESETB XI XO VSS R74 SXI R75 SXO AVSS R60 AN0 R61 AN1 R62 AN2 R63 AN3 R64 AN4 R65 AN5 R66 AN6 R67 AN7 R70 AN8 R71 AN9 R72 AN10 R73 AN11 AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RA R35 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R06 R05 R04 R03 R02 R01 R00 VDD Vdisp BUZO EC0 INT1 INT0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 R04 R03 R02 R01 R00 VDD AVDD R73 R72 R71 R70 R67 R66 BUZO EC0 INT1 INT0 AN11 AN10 AN9 AN8 AN7 AN6 SCLK SIN SOUT PWM1O/T1O R52 R53 R54 R55 R56 R57 RESETB XI XO VSS SXI R74 SXO R75 AVSS AN0 R60 AN1 R61 AN2 R62 AN3 R63 R64 AN4 AN5 R65 Vdisp T0O R30 R31 R32 R33 R34 R35 RA R40 R41 R42 R43 R50 R51 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 R27 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R06 R05 64MQFP 4 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 64LQFP Vdisp T0O 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 R06 R05 R04 R03 R02 R01 R00 VDD AVDD R73 R72 R71 R70 R67 R66 R65 BUZO EC0 INT1 INT0 AN11 AN10 AN9 AN8 AN7 AN6 AN5 SIN SOUT PWM1O/T1O R54 R55 R56 R57 RESETB XI XO VSS R74 SXI R75 SXO AVSS R60 AN0 R61 AN1 R62 AN2 R63 AN3 R64 AN4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SCLK R27 R30 R31 R32 R33 R34 R35 RA R40 R41 R42 R43 R50 R51 R52 R53 Nov. 1999 Ver 0.0 preliminary 5 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 4. BLOCK DIAGRAM (GMS81C2120) R07 R06 R05 R04 R03/BUZO R02/EC0 R01/INT1 R00/INT0 AVDD AVSS ADC Power Supply Driver Buzzer PSW ALU R0 R20~R27 R30~R34 R2 R3 Stack Pointer Accumulator Vdisp/RA PC Data Memory (448 bytes) Program Memory Interrupt Controller Data Table 8-b it B a sic In te rva l T im e r S yste m c o n tro lle r S yste m C lo ck C o n tro lle r S u b S yste m C lo ck C o n tro lle r Watchdog Timer 8-bit Timer/ Counter 8-bit serial Interface 8-bit PWM PC 8-bit ADC T im in g g e n e ra to r C lo c k G e n e ra to r 6 VDD VSS SXI SXO XO XI RESETB R5 Power Supply R53 / SCLK R54 / SIN R55 / SOUT R56 / PWM1O/T1O R57 preliminary R6 R60 / AN0 R61 / AN1 R62 / AN2 R63 / AN3 R64 / AN4 R65 / AN5 R66 / AN6 R67 / AN7 Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 5. PIN ASSIGNMENT (GMS81C2120) 42PDIP Vdisp SCLK SIN SOUT PWM1O/T1O RA R53 R54 R55 R56 R57 RESETB XI XO VSS AVSS R60 AN0 R61 AN1 R62 AN2 R63 AN3 R64 AN4 R65 AN5 R66 AN6 R67 AN7 AVDD VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R07 R06 R05 R04 R03 R02 R01 R00 BUZO EC0 INT1 INT0 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 33 32 31 30 29 28 27 26 25 24 23 R27 R26 R25 R24 R23 R22 R21 R20 R07 R06 R05 Nov. 1999 Ver 0.0 INT0 INT1 EC0 BUZO AN5 AN6 AN7 R65 R66 R67 AVDD VDD R00 R01 R02 R03 R04 NC R57 RESETB XI XO VSS AVSS R60 AN0 AN1 R61 R62 AN2 R63 AN3 AN4 R64 44 43 42 41 40 39 38 37 36 35 34 NC R56 R55 R54 R53 RA R34 R33 R32 R31 R30 PWM1O/T1O SOUT SIN SCLK 44MQFP 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 preliminary 7 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 40PDIP Vdisp SCLK SIN SOUT PWM1O/T1O RA R53 R54 R55 R56 R57 RESETB XI XO VSS R60 AN0 R61 AN1 R62 AN2 R63 AN3 R64 AN4 R65 AN5 R66 AN6 R67 AN7 VDD R00 INT0 8 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 preliminary 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R07 R06 R05 R04 R03 R02 R01 BUZO EC0 INT1 Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 6. PACKAGE DIMENSION 64SDIP UNIT: INCH 0.750 BSC min. 0.015 0.205 max. 2.280 2.260 0.070 BSC 0.140 0.120 0.050 0.030 0.022 0.016 0.680 0.660 0.012 0.008 0-15 64MQFP 24.15 23.65 20.10 19.90 18.15 17.65 14.10 13.90 UNIT: MM 0-7 3.18 max. 1.95 REF 0.50 0.35 Nov. 1999 Ver 0.0 1.03 0.73 0.23 0.13 0.36 0.10 SEE DETAIL "A" 1.00 BSC preliminary DETAIL "A" 9 GMS81C2020/GMS81C2120 64LQFP Hyundai Micro Electro nics 12.00 BSC 10.00 BSC 1.45 1.35 10.00 BSC 12.00 BSC UNIT: MM 0-7 0.15 0.05 SEE DETAIL "A" 1.60 max. 0.38 0.22 10 0.50 BSC 0.75 0.45 1.00 REF DETAIL "A" preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 7. PIN DESCRIPTIONS (GMS81C2020) VDD: Supply voltage. I/O port. R3 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. VSS: Circuit ground. AVDD: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent power source as well as possible, other than digital power source. R40~R43: R4 is an 8-bit CMOS bidirectional I/O port. R4 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R4 serves the functions of the following special features. AVSS: ADC circuit ground. Port pin RESETB: Reset the MCU. R40 XI: Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XO: Output from the inverting oscillator amplifier. SXI: Input to the internal subsystem clock operating circuit. In addition, SXI serves the R74 pin when selected by the code option. Port pin RA Alternate function Port pin R53 R54 R55 R56 Port pin R00~R07: R0 is an 8-bit high-voltage CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R0 serves the functions of the various following special features. R00 R01 R02 R03 R60 R61 R62 R63 R64 R66 R66 R67 Alternate function INT0 (External interrupt 0) INT1 (External interrupt 1) EC0 (Event counter input) BUZO (Buzzer driver output) SCLK (Serial clock) SIN (Serial data input) SOUT (Serial data output) PWM1O (PWM1 Output) T1O (Timer/Counter 1 output) Alternate function AN0 (Analog Input 0) AN1 (Analog Input 1) AN2 (Analog Input 2) AN3 (Analog Input 3) AN4 (Analog Input 4) AN5 (Analog Input 5) AN6 (Analog Input 6) AN7 (Analog Input 7) R70~R73: R7 is an 8-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R7 is shared with the ADC input. R10~R17: R1 is an 8-bit high-voltage CMOS bidirectional I/O port. R1 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R20~R27: R2 is an 8-bit high-voltage CMOS bidirectional I/O port. R2 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R30~R35: R3 is an 6-bit high-voltage CMOS bidirectional Nov. 1999 Ver 0.0 Alternate function R60~R67: R6 is an 8-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R6 is shared with the ADC input. Vdisp (High-voltage input power supply) Port pin T0O (Timer/Counter 0 output) R50~R57: R5 is an 8-bit CMOS bidirectional I/O port. R5 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R5 serves the functions of the various following special features. SXO: Output from the inverting subsystem oscillator amplifier. In addition, SXO serves the R75 pin when selected by the code option. RA(Vdisp): RA is one-bit high-voltage input only port pin. In addition, RA serves the functions of the Vdisp special features. Vdisp is used as a high-voltage input power supply pin when selected by the mask option.. Alternate function preliminary Port pin R70 R71 R72 R73 Alternate function AN8 (Analog Input 8) AN9 (Analog Input 9) AN10 (Analog Input 10) AN11 (Analog Input 11) 11 GMS81C2020/GMS81C2120 PIN NAME Hyundai Micro Electro nics In/Out Function VDD - Supply voltage VSS - Circuit ground RA (Vdisp) I(I) RESETB I Reset signal input XI I Oscillation input XO O Oscillation output 1-bit high-voltage Input only port High-voltage input power supply pin R00 (INT0) I/O (I) External interrupt 0 input R01 (INT1) I/O (I) External interrupt 1 input R02 (EC0) I/O (I) R03 (BUZO) I/O (O) 8-bit high-voltage I/O ports Buzzer driving output R04~R07 I/O R10~R17 I/O 8-bit high-voltage I/O ports R20~R27 I/O 8-bit high-voltage I/O ports R30~R35 I/O 6-bit high-voltage I/O ports R40 (T0O) I/O (O) R41~R43 I/O R50~R52 I/O R53 (SCLK) I/O (I) R55 (SOUT) I/O (O) R56 (PWM1O/T1O) I/O (O) R57 4-bit general I/O ports I/O (I/O) R54 (SIN) Timer/Counter 0 output Serial clock source 8-bit general I/O ports Serial data input Serial data output PWM 1 pulse output /Timer/Counter 1 output I/O R60~R67 (AN0~AN7) I/O (I) 8-bit general I/O ports R70~R73 (AN8~AN11) I/O (I) 4-bit general I/O ports AVDD - Supply voltage input pin for ADC AVSS - Ground level input pin for ADC 12 Timer/Counter 0 external input preliminary Analog voltage input Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 8. PIN DESCRIPTIONS (GMS81C2120) VDD: Supply voltage. tions of the various following special features. VSS: Circuit ground. Port pin AVDD: Supply voltage to the ladder resistor of ADC circuit. To enhance the resolution of analog to digital converter, use independent power source as well as possible, other than digital power source. R53 R54 R55 R56 AVSS: ADC circuit ground. RESETB: Reset the MCU. XI: Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XO: Output from the inverting oscillator amplifier. RA SCLK (Serial clock) SIN (Serial data input) SOUT (Serial data output) PWM1O (PWM1 Output) T1O (Timer/Counter 1 output) R60~R67: R6 is an 8-bit CMOS bidirectional I/O port. R6 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R6 is shared with the ADC input. RA(Vdisp): RA is one-bit high-voltage input only port pin. In addition, RA serves the functions of the Vdisp special features. Vdisp is used as a high-voltage input power supply pin when selected by the mask option.. Port pin Alternate function Alternate function Vdisp (High-voltage input power supply) Port pin R60 R61 R62 R63 R64 R66 R66 R67 Alternate function AN0 (Analog Input 0) AN1 (Analog Input 1) AN2 (Analog Input 2) AN3 (Analog Input 3) AN4 (Analog Input 4) AN5 (Analog Input 5) AN6 (Analog Input 6) AN7 (Analog Input 7) R00~R07: R0 is an 8-bit high-voltage CMOS bidirectional I/O port. R0 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R0 serves the functions of the various following special features. Port pin R00 R01 R02 R03 Alternate function INT0 (External interrupt 0) INT1 (External interrupt 1) EC0 (Event counter input) BUZO (Buzzer driver output) R20~R27: R2 is an 8-bit high-voltage CMOS bidirectional I/O port. R2 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. R53~R57: R5 is an 5-bit CMOS bidirectional I/O port. R5 pins 1 or 0 written to the Port Direction Register can be used as outputs or inputs. In addition, R5 serves the func- Nov. 1999 Ver 0.0 preliminary 13 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics PIN DESCRIPTIONS (GMS81C2120) PIN NAME In/Out Function VDD - Supply voltage VSS - Circuit ground RA (Vdisp) I(I) RESETB I Reset signal input XI I Oscillation input XO O Oscillation output 1-bit high-voltage Input only port High-voltage input power supply pin R00 (INT0) I/O (I) External interrupt 0 input R01 (INT1) I/O (I) External interrupt 1 input R02 (EC0) I/O (I) R03 (BUZO) I/O (O) 8-bit high-voltage I/O ports Buzzer driving output R04~R07 I/O R20~R27 I/O 8-bit high-voltage I/O ports R30~R34 I/O 5-bit high-voltage I/O ports R53 (SCLK) I/O (I/O) R54 (SIN) I/O (I) R55 (SOUT) I/O (O) R56 (PWM1O/T1O) I/O (O) R57 R60~R67 (AN0~AN7) Serial clock source Serial data input 5-bit general I/O ports Serial data output PWM 1 pulse output /Timer/Counter 1 output I/O I/O (I) 8-bit general I/O ports AVDD - Supply voltage input pin for ADC AVSS - Ground level input pin for ADC 14 Timer/Counter 0 external input preliminary Analog voltage input Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 9. PORT STRUCTURES * RESETB VDD Mask version only Internal RESETB VSS * XI, XO (Crystal Oscillator) VDD Internal System clock XO VSS VDD VDD XI stop or mainclk off VSS * XI, XO (RC Oscillator) VDD Internal System clock XO VSS VDD VDD XI stop or mainclk off VSS Nov. 1999 Ver 0.0 preliminary 15 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics * SXI, SXO (Sub Oscillator) VDD Internal System clock SXO VSS VDD VDD SXI stop or subclk off VSS * R40 / T0O Fu n co ut [T0O] VDD 1 Data Bus Data Register 0 Function Select Direction Register Data Bus V DD VSS Data Bus Metal Option Read * R41~R43, R50~R52, R57 Data Bus Data Bus Data Register Direction Register V DD Data Bus Metal Option Read 16 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 * R53 / SCLK Funcout_sel F un co u t [SCLKOUT] Funcin_sel VDD 1 Data Bus Data Register 0 N-MOS Open Drain sel. Direction Register Data Bus V DD VSS Read Data Bus Metal Option Funcin [SCLKIN] * R54 / SIN VDD Funcin_sel Data Bus Data Register N-MOS Open Drain sel. Direction Register Data Bus VSS V DD Read Data Bus Metal Option Funcin [SIN] * R55 / SOUT Funcout_sel F u n co ut [SOUT] VDD 1 Data Bus Data Register 0 N-MOS Open Drain sel. Data Bus Direction Register Read V DD VSS IOSWB Data Bus Metal Option Funcin [IOSWIN] Nov. 1999 Ver 0.0 preliminary 17 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics * R56 / PWM1O / T1O Funcout_sel F u nco u t [PWM1O/T1O] VDD 1 Data Bus Data Register 0 N-MOS Open Drain sel. Direction Register Data Bus VSS V DD Read Data Bus Metal Option * R60~R67 [AN0 ~ AN7], R70~R74 [AN8 ~ AN11] VDD Data Bus Data Register Data Bus Direction Register V DD Data Bus VSS Metal Option Read To A/D Converter [AN11 ~ AN0] Analog Input Mode [ANSEL11 ~ 0] Analog Ch. Selection [ADCM.5 ~ ADCM.2] * RA / Vdisp VDD Read Data Bus Metal option Vdisp 18 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 * R00 / INT0, R01 / INT1, R02 / EC0 VDD Data Bus Data Register Data Bus Direction Register Pull-down Resistor Funcin_sel Read Vdisp [Metal Option] Data Bus Funcin [INT0, INT1, EC0] * R03 / BUZO Funcout_sel F un co ut [BUZO] VDD 1 Data Register Data Bus Direction Register 0 Pull-down Resistor Data Bus Read Vdisp [Metal Option] Data Bus * R04 ~ R07, R10 ~ R17, R20 ~ R27, R30 ~ R35 Data Bus Data Register Data Bus Direction Register Pull-down Resistor VDD Read Vdisp [Metal Option] Data Bus Nov. 1999 Ver 0.0 preliminary 19 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 10. ELECTRICAL CHARACTERISTICS * Absolute Maximum Ratings Supply Voltage : VDD . . . . . . . . . . . . . . . - 0.3 to + 7.0V Storage Temperature : TSTG . . . . . . . . . . -40 to + 125 C Voltage on any pin with respect to Ground ( VSS ) . . . . . . -0.3 to VDD + 0.3V IOL per I/O Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these of any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition Supply Voltage VDD Operating Frequency fXI Operating Temperature TOPR Specification Unit Min Max fXI = 4.5 MHz 4.0 5.5 V VDD = VDD 0.4 4.5 MHz -40 125 C 10.1 A/D Converter Characteristics (TA=25C, VDD=5V, VSS=0V, AVDD=5.12V, AVSS=0V @fXI =4MHz) Specifications Parameter Symbol Condition Unit Min. Typ. Max. AVDD AVSS - AVDD V VAN AVSS-0.3 AVDD+0.3 V Current Following Between AVDD and AVSS IAVDD - - 200 uA Overall Accuracy CAIN - 1.0 1.5 LSB Non-Linearity Error NNLE - 1.0 1.5 LSB Differential Non-Linearity Error NDNLE - 1.0 1.5 LSB Zero Offset Error NZOE - 0.5 1.5 LSB Full Scale Error NFSE - 0.25 0.5 LSB Gain Error NNLE - 1.0 1.5 LSB - - 20 us Analog Power Supply Input Voltage Range Analog Input Voltage Range Conversion Time 20 TCONV fXI=4MHz preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 DC Characteristics for Standard Pins( 5V ) ( VDD = 5.0V 10%, VSS = 0V, TA = -40 ~ 125C, fXI = 4 MHz, Vdisp=VDD-40V to VDD) Parameter Pin Symbol Test Condition Specification Min Typ Max XI, SXI VIH1 0.9VDD VDD+0.3 RESETB,SIN,R55,SCLK, INT0&1,EC0 VIH2 0.8VDD VDD+0.3 R40~R43,R5,R6,R70~R73 VIH3 0.7VDD VDD+0.3 XI, SXI VIL1 -0.3 0.1VDD RESETB,SIN,R55,SCLK, INT0&1,EC0 VIL2 -0.3 0.2VDD R40~R43,R5,R6,R70~R73 VIL3 -0.3 0.3VDD Output High Voltage R40~R43,R5,R6,R70~R73 BUZO,T0O,PWM1O/T1O, SCLK,SOUT VOH IOH = -0.5mA Output Low Voltage R40~R43,R5,R6,R70~R73 BUZO,T0O,PWM1O/T1O, SCLK,SOUT VOL1 VOL2 IOL = 1.6mA IOL = 10mA R40~R43,R5,R6,R70~R73 IIH1 1 XI IIH2 1 R40~R43,R5,R6,R70~R73 IIL1 -1 XI IIL2 -1 R40~R43,R5,R6,R70~R73 IPU 50 Input High Voltage Input Low Voltage Input High Leakage Current Input Low Leakage Current Input Pull-up Current(*Option) Power Fail Detect Voltage VDD Current dissipation VDD in active mode VDD-0.5 Unit V V V 0.4 2 V uA uA VPFD 100 180 2.7 uA V IDD fXI=4.2MHz 5 mA Current dissipation in standby mode VDD ISTBY fXI=4.2MHz 2 mA Current dissipation in subactive mode VDD ISUB fXI=Off fSXI=32.7KHz 100 uA Current dissipation in watch mode VDD IWTC fXI=Off fSXI=32.7KHz 20 uA Current dissipation in stop mode VDD ISTOP fXI=Off fSXI=32.7KHz 10 uA RESETB,SIN,R55,SCLK, INT0,INT1,EC0 VT+~VT- 0.4 Internal RC WDT Frequency XO TRCWDT 10 RC Oscillation Frequency XO fRCOSC Hysteresis Nov. 1999 Ver 0.0 R= 60K preliminary 1.5 V 2 25 MHz 2.5 MHz 21 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics DC Characteristics for High-Voltage Pins ( VDD = 5.0V 10%, VSS = 0V, TA = -40 ~ 125C, fXI = 4 MHz, Vdisp=VDD-40V to VDD) 22 Test Condition Specification Parameter Pin Symbol Input High Voltage R0,R1,R2,R30~R35,RA VIH 0.7VDD VDD+0.3 V Input Low Voltage R0,R1,R2,R30~R35,RA VIL VDD-40 0.3VDD V Output High Voltage R0,R1,R2,R30~R35 VOH IOH = -15mA IOH = -10mA IOH = - 4mA Output Low Voltage R0,R1,R2,R30~R35 VOL Vdisp=VDD-40 150K atVDD-40 VDD-37 VDD-37 V 20 uA 1000 uA Input High Leakage Current R0,R1,R2,R30~R35,RA IIH VIN=VDD-40V to VDD Input Pull-down Current(*Option) R0,R1,R2,R30~R35 IPD Vdisp=VDD-35V VIN=VDD preliminary Min Typ Max VDD-3.0 VDD-2.0 VDD-1.0 200 Unit V 600 Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 10.2 AC Characteristics (TA=-40~ 125C, VDD=5V10%, VSS=0V) Specifications Parameter Symbol Pins Unit Min. Typ. Max. fCP XI 1 - 8 MHz tCPW XI 80 - - nS tRCP,tFCP XI - - 20 nS Oscillation Stabilizing Time tST XI, XO - - 20 mS External Input Pulse Width tEPW INT0, INT1, EC0 2 - - tSYS tREP,tFEP INT0, INT1, EC0 - - 20 nS tRST RESETB 8 - - tSYS Operating Frequency External Clock Pulse Width External Clock Transition Time External Input Pulse Transiton Time RESET Input Width tCPW 1/fCP tCPW VDD-0.5V XI 0.5V tRCP tSYS tFCP tRST RESETB 0.2VDD tEPW tEPW INT0, INT1 EC0 0.8VDD 0.2VDD tREP tFEP Figure 10-1 Timing Chart Nov. 1999 Ver 0.0 preliminary 23 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 10.3 Typical Characteristics This graphs and tables provided in this section are for design guidance only and are not tested or guranteed. In some graphs or tables the data presented are outside specified operating range (e.g. outside specified VDD range). This is for imformation only and divices are guranteed to operate properly only within the specified range. The data presented in this section is a statistical summary of data collected on units from different lots over a period of time. "Typical" represents the mean of the distribution while "max" or "min" represents (mean + 3) and (mean - 3) respectively where is standard deviation Operating Area Normal Operation IDD-VDD fXI (MHz) IDD (mA) Ta= 25C 10 Ta=25C 8 8 6 6 fXI = 8MHz 4 4MHz 4 2 2 0 0 2 3 4 5 6 2 VDD (V) Wake-up Timer Mode IWKUP-VDD IDD (mA) 3 4 VDD 6 (V) 5 RC-WDT in Stop Mode IRCWDT-VDD IDD (A) Ta=25C 2.0 Ta=25C 20 1.5 15 fXI = 8MHz 1.0 fXI = 8MHz 10 0.5 5 4MHz 4MHz 0 2 3 4 5 0 VDD 6 (V) 2 3 4 5 VDD 6 (V) **** FOR MODIFIED **** 24 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 IOL-VOL, VDD=5V IOH-VOH, VDD=5V IOL (mA) IOH (mA) -25C 25C 40 -25C 25C -20 85C 85C 30 -15 20 -10 10 -5 0 1 VIH1 (V) 2 3 4 VDD-VIH1 XI, RESETB 0 VOL 5 (V) 2 VDD-VIH2 VIH2 (V) fXI=4MHz Ta=25C 3 4 VDD-VIH3 Hysteresis input VIH3 (V) f X I =4M H z Ta=25C 4 4 3 3 3 2 2 2 1 1 1 0 1 VIL1 (V) 2 3 4 5 VDD 6 (V) VDD-VIL1 XI, RESETB 4 0 2 3 VDD-VIL2 VIL2 (V) fXI=4MHz Ta=25C 4 5 VDD 6 (V) VIL3 (V) 3 3 3 2 2 2 1 1 1 2 3 4 5 VDD 6 (V) 4 0 2 3 4 5 VDD 6 (V) 3 VDD-VIL3 4 1 f X I =4M H z Ta=25C 2 4 0 Normal input 0 Hysteresis input f X I =4M H z Ta=25C VOH 6 (V) 5 4 5 VDD 6 (V) Normal input f X I =4M H z Ta=25C 0 2 3 4 5 VDD 6 (V) **** FOR MODIFIED **** Nov. 1999 Ver 0.0 preliminary 25 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 11. MEMORY ORGANIZATION The GMS81C2020 and GMS81C2120 have separate address spaces for Program memory and Data Memory. Program memory can only be read, not written to. It can be up to 20K/12K bytes of Program memory. Data memory can be read and written to up to 448 bytes including the stack area. 11.1 Registers This device has six registers that are the Program Counter (PC), a Accumulator (A), two index registers (X, Y), the Stack Pointer (SP), and the Program Status Word (PSW). The Program Counter consists of 16-bit register. A ACCUMULATOR X X REGISTER Y Y REGISTER SP PCH Generally, SP is automatically updated when a subroutine call is executed or an interrupt is accepted. However, if it is used in excess of the stack area permitted by the data memory allocating configuration, the user-processed data may be lost. The stack can be located at any position within 00H to FFH of the internal data memory. The SP is not initialized by hardware, requiring to write the initial value (the location with which the use of the stack starts) by using the initialization routine. Normally, the initial value of "FFH " is used. STACK POINTER PCL PROGRAM COUNTER PSW PROGRAM STATUS WORD Stack Address ( 0100H ~ 01FFH ) 15 8 01H Figure 11-1 Configuration of Registers The Accumulator can be used as a 16-bit register with Y Register as shown below. Y Note: The Stack Pointer must be initialized by software because its value is undefined after RESET. Example: To initialize the SP LDX #0FFH TXSP ; SP FFH Program Counter: The Program Counter is a 16-bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In reset state, the program counter has reset routine address (PCH:0FFH, PCL:0FEH). A A Two 8-bit Registers can be used as a "YA" 16-bit Register Figure 11-2 Configuration of YA 16-bit Register X, Y Registers: In the addressing mode which uses these index registers, the register contents are added to the specified address, which becomes the actual address. These modes are extremely effective for referencing subroutine tables and memory tables. The index registers also have increment, decrement, comparison and data transfer functions, and they can be used as simple accumulators. Stack Pointer: The Stack Pointer is an 8-bit register used for occurrence interrupts and calling out subroutines. Stack Pointer identifies the location in the stack to be accessed (save or restore). 26 0 SP Hardware fixed Accumulator: The Accumulator is the 8-bit general purpose register, used for data operation such as transfer, temporary saving, and conditional judgement, etc. Y 7 Program Status Word: The Program Status Word (PSW) contains several bits that reflect the current state of the CPU. The PSW is described in Figure 11-3 . It contains the Negative flag, the Overflow flag, the Break flag the Half Carry (for BCD operation), the Interrupt enable flag, the Zero flag, and the Carry flag. [Carry flag C] This flag stores any carry or borrow from the ALU of CPU after an arithmetic operation and is also changed by the Shift Instruction or Rotate Instruction. [Zero flag Z] This flag is set when the result of an arithmetic operation or data transfer is "0" and is cleared by any other result. preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 MSB PSW N LSB V G B H I Z C [RESET VALUE : 00H CARRY FLAG RECEIVES CARRY OUT NEGATIVE FLAG OVERFLOW FLAG ZERO FLAG DIRECT PAGE FLAG INTERRUPT ENABLE FLAG BREAK FLAG HALF CARRY FLAG RECEIVES CARRY OUT FROM BIT 1 OF ADDITION OPERLANDS Figure 11-3 PSW (Program Status Word) Register [Interrupt disable flag I] This flag enables/disables all interrupts except interrupt caused by Reset or software BRK instruction. All interrupts are disabled when cleared to "0". This flag immediately becomes "0" when an interrupt is served. It is set by the EI instruction and cleared by the DI instruction. [Half carry flag H] After operation, this is set when there is a carry from bit 3 of ALU or there is no borrow from bit 4 of ALU. This bit can not be set or cleared except CLRV instruction with Overflow flag (V). [Break flag B] This flag is set by software BRK instruction to distinguish BRK from TCALL instruction with the same vector address [Direct Page flag G] Nov. 1999 Ver 0.0 This flag assign direct page(0-page, 1-page) for direct addressing mode. When G-flag is "0", the direct addressing space is in 0-page(0000h ~ 00FFH). When G-flag is "1", the direct addressing space is in 1-page(0100h ~ 01FFH). It is set and clreared by SETG, CLRG instruction. [Overflow flag V] This flag is set to "1" when an overflow occurs as the result of an arithmetic operation involving signs. An overflow occurs when the result of an addition or subtraction exceeds +127(7FH ) or -128(80H ). The CLRV instruction clears the overflow flag. There is no set instruction. When the BIT instruction is executed, bit 6 of memory is copied to this flag. [Negative flag N] This flag is set to match the sign bit (bit 7) status of the result of a data or arithmetic operation. When the BIT instruction is executed, bit 7 of memory is copied to this flag. preliminary 27 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 11.2 Program Memory A 16-bit program counter is capable of addressing up to 64K bytes, but these devices have 20K/12K bytes program memory space only physically implemented. Accessing a location above FFFFH will cause a wrap-around to 0000H. Example: Usage of TCALL Figure 11-4 , shows a map of Program Memory. After reset, the CPU begins execution from reset vector which is stored in address FFFEH and FFFFH as shown in Figure 11-5 . ; ;TABLE CALL ROUTINE ; FUNC_A: LDA LRG0 RET ; FUNC_B: LDA LRG1 2 RET ; ;TABLE CALL ADD. AREA ; ORG 0FFC0H DW FUNC_A DW FUNC_B As shown in Figure 11-4 , each area is assigned a fixed location in Program Memory. Program Memory area contains the user program. B000H LDA #5 TCALL 0FH : : ;1BYTE INSTRUCTION ;INSTEAD OF 3 BYTES ;NORM AL CALL 1 ;TCALL ADDRESS AREA GMS81C2020 D000H PROGRAM MEMORY GMS81C2012 FEFFH FF00H FFC0H FFDFH FFE0H FFFFH TCALL AREA PCALL AREA The interrupt causes the CPU to jump to specific location, where it commences the execution of the service routine. The External interrupt 0, for example, is assigned to location 0FFFAH. The interrupt service locations spaces 2-byte interval: 0FFF8H and 0FFF9H for External Interrupt 1, 0FFFAH and 0FFFBH for External Interrupt 0, etc. As for the area from 0FF00H to 0FFFFH, if any area of them is not going to be used, its service location is available as general purpose Program Memory. INTERRUPT VECTOR AREA Address Figure 11-4 Program Memory Map 0FFE0H Page Call (PCALL) area contains subroutine program to reduce program byte length by using 2 bytes PCALL instead of 3 bytes CALL instruction. If it is frequently called, it is more useful to save program byte length. Table Call (TCALL) causes the CPU to jump to each TCALL address, where it commences the execution of the service routine. The Table Call service area spaces 2-byte for every TCALL: 0FFC0H for TCALL15, 0FFC2H for TCALL14, etc., as shown in Figure 11-6 . Vector Area Memory - E2 - E4 Serial Peripheral Interface Interrupt Vector Area E6 Basic Interval Interrupt Vector Area E8 Watchdog Timer Interrupt Vector Area EA A/D Converter Interrupt Vector Area EC - EE - F0 - F2 - F4 Timer/Counter 1 Interrupt Vector Area F6 Timer/Counter 0 Interrupt Vector Area F8 External Interrupt 1 Vector Area FA External Interrupt 0 Vector Area FC - FE RESET Vector Area NOTE: "-" means reserved area. Figure 11-5 Interrupt Vector Area 28 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics Address GMS81C2020/GMS81C2120 Address Program Memory 0FFC0H C1 TCALL 15 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF PCALL Area Memory 0FF00H PCALL Area (256 Bytes) 0FFFFH TCALL 14 TCALL 13 TCALL 12 TCALL 11 TCALL 10 TCALL 9 TCALL 8 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF TCALL 7 TCALL 6 TCALL 5 TCALL 4 TCALL 3 TCALL 2 TCALL 1 TCALL 0 / BRK * NOTE: * means that the BRK software interrupt is using same address with TCALL0. Figure 11-6 PCALL and TCALL Memory Area PCALL rel TCALL n 4F35 4A PCALL 35H TCALL 4 4A 4F 35 ~ ~ ~ ~ ~ ~ 0F125H 01001010 ~ ~ NEXT Reverse PC: 11111111 11010110 FH FH D H 6H 0FF00H 0FF35H A 0FF00H NEXT 0FFFFH 0FFD6H 25 0FFD7H F1 A 0FFFFH Nov. 1999 Ver 0.0 preliminary 29 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics Example: The usage software example of Vector address and the initialize part. ORG 0FFE0H DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW DW NOT_USED; (0FFE0) NOT_USED; (0FFE2) SPI_INT; (0FFE4) Serial Peripheral Interface BIT_INT; (0FFE6) Basic Interval Timer WDT_INT; (0FFE8) Watchdog Timer AD_INT; (0FFEA) A/D Converter NOT_USED; (0FFEC) NOT_USED; (0FFEE) NOT_USED; (0FFF0) NOT_USED; (0FFF2) TMR1_INT; (0FFF4) Timer-1 TMR0_INT; (0FFF6) Timer-0 INT1; (0FFF8) Int.1 INT0; (0FFFA) Int.0 NOT_USED; (0FFFC) RESET; (0FFFE) Reset ORG 0F000H ;******************************************** ; MAIN PROGRAM * ;******************************************* ; RESET: DI ;Disable All Interrupts LDX #0 RAM_CLR: LDA #0;RAM Clear(!0000H->!00BFH) STA {X}+ CMPX #0C0H BNE RAM_CLR ; LDX #01FFH;Stack Pointer Initialize TXSP ; CALL INITIAL; ; LDM R0, #0;Normal Port 0 LDM R0IO,#1000_0010B;Normal Port Direction LDM R1, #0;Normal Port 1 LDM R1IO,#1000_0010B;Normal Port Direction : : LDM PFDR,#0;Enable Power Fail Detector : : 30 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 11.3 Data Memory (GMS81C2020) Figure 11-7 shows the internal Data Memory space available. Data Memory is divided into two groups, a user RAM(including Stack) and control registers. 0000H USER MEMORY PAGE0 00BFH 00C0H CONTROL REGISTERS 00FFH 0100H USER MEMORY ( including STACK ) PAGE1 01FFH Address Symbol R/W RESET Value Addressing mode 0C0H 0C1H 0C2H 0C3H 0C4H 0C5H 0C6H 0C7H 0C8H 0C9H 0CAH 0CBH 0CCH 0CDH 0CEH 0CFH R0 R0IO R1 R1IO R2 R2IO R3 R3IO R4 R4IO R5 R5IO R6 R6IO R7 R7IO R/W W R/W W R/W W R/W W R/W W R/W W R/W W R/W W Undefined 0000_0000 Undefined 00000000 Undefined 0000_0000 Undefined --00_0000 Undefined ----_0000 Undefined 0000_0000 Undefined 0000_0000 Undefined ----_0000 byte, bit1 byte2 byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte byte, bit byte 0D0H 0D1H TM0 T0 TDR0 CDR0 TM1 TDR1 T1PPR T1 CDR1 T1PDR PWM1HR BUR R/W R W R R/W W W R R R/W W W --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 1111_1111 byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte byte 0EFH SIOM SIOR IENH IENL IRQH IRQL IEDS ADCM ADCR BITR CKCTLR WDTR WDTR PFDR R/W R/W R/W R/W R/W R/W R/W R/W R R W R W R/W 0000_0001 Undefined 0000_---0000_---0000_---0000_-------_0000 -000_0001 Undefined 0000_0000 -001_0111 0000_0000 0111_1111 ----_-100 byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte, bit 0F4H 0F5H 0F6H 0F7H 0F8H 0F9H 0FAH 0FBH R0FUNC R4FUNC R5FUNC R6FUNC R7FUNC R5NODR SCMR RA W W W W W W R/W R ----_0000 ----_--00 0000_0000 0000_0000 ----_0000 0000_0000 ---0_0000 Undefined byte byte byte byte byte byte byte - 0D1H 0D1H Figure 11-7 Data Memory Map User Memory The GMS81C2020 has 448 x 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converter, basic interval timer, serial peripheral interface, watchdog timer, buzzer driver and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction. 0D2H 0D3H 0D3H 0D4H 0D4H 0D4H 0D5H 0DEH 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0EAH 0EBH 0ECH 0ECH 0EDH 0EDH Table 11-1 Control Registers Example; To write at CKCTLR LDM CKCTLR,#09H ;Divide ratio /16 1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit. Note: Several names are given at same address. Refer to Nov. 1999 Ver 0.0 preliminary 31 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics below table. When read When write Addr. Timer Mode Capture Mode PWM Mode Timer Mode PWM Mode D1H T0 CDR0 - TDR0 - TDR1 T1PPR - T1PDR D3H D4H ECH T1 CDR1 BITR T1PDR CKCTLR Table 11-2 Various Register Name in Same Address 32 Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics Address Name GMS81C2020/GMS81C2120 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T0CK2 T0CK1 T0CK0 T0CN T0ST T1CN T1ST C0H R0 R0 Port Data Register (Bit[7:0]) C1H R0IO R0 Port Direction Register (Bit[7:0]) C2H R1 R1 Port Data Register (Bit[7:0]) C3H R1IO R1 Port Direction Register (Bit[7:0]) C4H R2 R2 Port Data Register (Bit[7:0]) C5H R2IO R2 Port Direction Register (Bit[7:0]) C6H R3 R3 Port Data Register (Bit[5:0]) C7H R3IO R3 Port Direction Register (Bit[5:0]) C8H R4 R4 Port Data Register (Bit[3:0]) C9H R4IO R4 Port Direction Register (Bit[3:0]) CAH R5 R5 Port Data Register (Bit[7:0]) CBH R5IO R5 Port Direction Register (Bit[7:0]) CCH R6 R6 Port Data Register (Bit[7:0]) CDH R6IO R6 Port Direction Register (Bit[7:0]) CEH R7 R7 Port Data Register (Bit[5:0]) CFH R7IO R7 Port Direction Register (Bit[5:0]) D0H TM0 D1H T0/TDR0/ CDR0 D2H TM1 D3H TDR1/ T1PPR Timer1 Data Register / PWM1 Period Register D4H T1/CDR1/ T1PDR Timer1 Register / Capture1 Data Register / PWM1 Duty Register D5H PWM1HR PWM1 High Register(Bit[3:0]) DEH BUR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0 E0H SIOM POL IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF E1H SIOR E2H IENH INT0E INT1E T0E T1E E3H IENL ADE WDTE BITE SPIE - - - - E4H IRQH INT0IF INT1IF T0IF T1IF E5H IRQL ADIF WDTIF BITIF SPIIF - - - - E6H IEDS IED1H IED1L IED0H IED0L EAH ADCM ADS2 ADS1 ADS0 ADST ADSF EBH ADCR ADC Result Data Register ECH BITR1 Basic Interval Timer Data Register ECH CKCTLR1 WDTON BTCL BTS2 BTS1 BTS0 - - CAP0 Timer0 Register / Timer0 Data Register / Capture0 Data Register POL 16BIT PWM1E CAP1 T1CK1 T1CK0 SPI DATA REGISTER - - ADEN WAKEUP ADS3 RCWDT Table 11-3 Control Registers of GMS81C2020 These registers of shaded area can not be accessed by bit manipulation instruction as " SET1, CLR1 ", but should be accessed by register operation instruction as " LDM dp,#imm ". Nov. 1999 Ver 0.0 preliminary 33 GMS81C2020/GMS81C2120 Address Name Bit 7 Hyundai Micro Electro nics Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EDH WDTR WDTCL 7-bit Watchdog Counter Register EFH PFDR2 - - - - - PFDIS PFDM PFDS F4H R0FUNC - - - - BUZO EC0 INT1 INT0 F5H R4FUNC - - - - - - - T0O SOUT SIN SCLK - - - F6H R5FUNC - PWM1O/ T1O F7H R6FUNC AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 F8H R7FUNC - - - - AN11 AN10 AN9 AN8 F9H R5NODR NODR7 NODR6 NODR5 NODR4 NODR3 NODR2 NODR1 NODR0 FAH SCMR - - - CS1 CS0 SUBOFF CLKSEL MAINOFF FBH RA - - - - - - - RA0 Table 11-3 Control Registers of GMS81C2020 These registers of shaded area can not be accessed by bit manipulation instruction as " SET1, CLR1 ", but should be accessed by register operation instruction as " LDM dp,#imm ". 1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. 2.The register PFDR only be implemented on devices, not on In-circuit Emulator. 34 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 11.4 Data Memory (GMS81C2120) Figure 11-8 shows the internal Data Memory space available. Data Memory is divided into two groups, a user RAM(including Stack) and control registers. 0000H USER MEMORY PAGE0 00BFH 00C0H CONTROL REGISTERS 00FFH 0100H USER MEMORY ( including STACK ) PAGE1 Address Symbol R/W RESET Value Addressing mode 0C0H 0C1H R0 R0IO R/W W Undefined 0000_0000 byte, bit1 byte2 0C4H 0C5H 0C6H 0C7H R2 R2IO R3 R3IO R/W W R/W W Undefined 0000_0000 Undefined ---0_0000 byte, bit byte byte, bit byte 0CAH 0CBH 0CCH 0CDH R5 R5IO R6 R6IO R/W W R/W W Undefined 0000_0--Undefined 0000_0000 byte, bit byte byte, bit byte 0D0H 0D1H TM0 T0 TDR0 CDR0 TM1 TDR1 T1PPR T1 CDR1 T1PDR PWM1HR BUR R/W R W R R/W W W R R R/W W W --00_0000 0000_0000 1111_1111 0000_0000 0000_0000 1111_1111 1111_1111 0000_0000 0000_0000 0000_0000 ----_0000 1111_1111 byte, bit byte byte byte byte, bit byte byte byte byte byte, bit byte byte 0EFH SIOM SIOR IENH IENL IRQH IRQL IEDS ADCM ADCR BITR CKCTLR WDTR WDTR PFDR R/W R/W R/W R/W R/W R/W R/W R/W R R W R W R/W 0000_0001 Undefined 0000_---0000_---0000_---0000_-------_0000 -000_0001 Undefined 0000_0000 -001_0111 0000_0000 0111_1111 ----_-100 byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte, bit byte byte byte byte byte byte, bit 0F4H R0FUNC W ----_0000 byte 0F6H 0F7H R5FUNC R6FUNC W W 0000_0--0000_0000 byte byte 0F9H 0FAH 0FBH R5NODR SCMR RA W R/W R 0000_0-----0_0000 Undefined byte byte - 01FFH 0D1H 0D1H Figure 11-8 Data Memory Map User Memory The GMS81C2120 has 448 x 8 bits for the user memory (RAM). Control Registers The control registers are used by the CPU and Peripheral function blocks for controlling the desired operation of the device. Therefore these registers contain control and status bits for the interrupt system, the timer/ counters, analog to digital converter, basic interval timer, serial peripheral interface, watchdog timer, buzzer driver and I/O ports. The control registers are in address range of 0C0H to 0FFH. Note that unoccupied addresses may not be implemented on the chip. Read accesses to these addresses will in general return random data, and write accesses will have an indeterminate effect. More detailed informations of each register are explained in each peripheral section. Note: Write only registers can not be accessed by bit manipulation instruction. Do not use read-modify-write instruction. Use byte manipulation instruction. 0D2H 0D3H 0D3H 0D4H 0D4H 0D4H 0D5H 0DEH 0E0H 0E1H 0E2H 0E3H 0E4H 0E5H 0E6H 0EAH 0EBH 0ECH 0ECH 0EDH 0EDH Table 11-4 Control Registers Example; To write at CKCTLR LDM CKCTLR,#09H ;Divide ratio /16 1. "byte, bit" means that register can be addressed by not only bit but byte manipulation instruction. 2. "byte" means that register can be addressed by only byte manipulation instruction. On the other hand, do not use any read-modify-write instruction such as bit manipulation for clearing bit. Note: Several names are given at same address. Refer to Nov. 1999 Ver 0.0 preliminary 35 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics below table. When read When write Addr. Timer Mode Capture Mode PWM Mode Timer Mode PWM Mode D1H T0 CDR0 - TDR0 - TDR1 T1PPR - T1PDR D3H D4H ECH T1 CDR1 BITR T1PDR CKCTLR Table 11-5 Various Register Name in Same Address 36 Stack Area The stack provides the area where the return address is saved before a jump is performed during the processing routine at the execution of a subroutine call instruction or the acceptance of an interrupt. When returning from the processing routine, executing the subroutine return instruction [RET] restores the contents of the program counter from the stack; executing the interrupt return instruction [RETI] restores the contents of the program counter and flags. The save/restore locations in the stack are determined by the stack pointed (SP). The SP is automatically decreased after the saving, and increased before the restoring. This means the value of the SP indicates the stack location number for the next save. preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics Address Name GMS81C2020/GMS81C2120 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 T0CK2 T0CK1 T0CK0 T0CN T0ST T1CN T1ST C0H R0 R0 Port Data Register (Bit[7:0]) C1H R0IO R0 Port Direction Register (Bit[7:0]) C4H R2 R2 Port Data Register (Bit[7:0]) C5H R2IO R2 Port Direction Register (Bit[7:0]) C6H R3 R3 Port Data Register (Bit[4:0]) C7H R3IO R3 Port Direction Register (Bit[4:0]) CAH R5 R5 Port Data Register (Bit[7:3]) CBH R5IO R5 Port Direction Register (Bit[7:3]) CCH R6 R6 Port Data Register (Bit[7:0]) CDH R6IO R6 Port Direction Register (Bit[7:0]) D0H TM0 D1H T0/TDR0/ CDR0 D2H TM1 D3H TDR1/ T1PPR Timer1 Data Register / PWM1 Period Register D4H T1/CDR1/ T1PDR Timer1 Register / Capture1 Data Register / PWM1 Duty Register D5H PWM1HR PWM1 High Register(Bit[3:0]) DEH BUR BUCK1 BUCK0 BUR5 BUR4 BUR3 BUR2 BUR1 BUR0 E0H SIOM POL IOSW SM1 SM0 SCK1 SCK0 SIOST SIOSF E1H SIOR E2H IENH INT0E INT1E T0E T1E E3H IENL ADE WDTE BITE SPIE - - - - E4H IRQH INT0IF INT1IF T0IF T1IF E5H IRQL ADIF WDTIF BITIF SPIIF - - - - E6H IEDS IED1H IED1L IED0H IED0L EAH ADCM ADS2 ADS1 ADS0 ADST ADSF EBH ADCR ADC Result Data Register ECH BITR1 Basic Interval Timer Data Register ECH CKCTLR1 WDTON BTCL BTS2 BTS1 BTS0 EDH WDTR WDTCL EFH PFDR2 - - - - - PFDIS PFDM PFDS F4H R0FUNC - - - - BUZO EC0 INT1 INT0 F5H R4FUNC - - - - - - - T0O - PWM1O/ T1O SOUT SIN SCLK - - - F6H R5FUNC - - CAP0 Timer0 Register / Timer0 Data Register / Capture0 Data Register POL 16BIT PWM1E CAP1 T1CK1 T1CK0 SPI DATA REGISTER - - ADEN WAKEUP ADS3 RCWDT 7-bit Watchdog Counter Register Table 11-6 Control Registers of GMS81C2120 These registers of shaded area can not be accessed by bit manipulation instruction as " SET1, CLR1 ", but should be accessed by register operation instruction as " LDM dp,#imm ". Nov. 1999 Ver 0.0 preliminary 37 GMS81C2020/GMS81C2120 Address Hyundai Micro Electro nics Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F7H R6FUNC AN7 AN6 AN5 AN4 AN3 AN2 AN1 AN0 F8H R7FUNC - - - - AN11 AN10 AN9 AN8 F9H R5NODR NODR7 NODR6 NODR5 NODR4 NODR3 NODR2 NODR1 NODR0 FAH SCMR - - - CS1 CS0 SUBOFF CLKSEL MAINOFF FBH RA - - - - - - - RA0 Table 11-6 Control Registers of GMS81C2120 These registers of shaded area can not be accessed by bit manipulation instruction as " SET1, CLR1 ", but should be accessed by register operation instruction as " LDM dp,#imm ". 1.The register BITR and CKCTLR are located at same address. Address ECH is read as BITR, written to CKCTLR. 2.The register PFDR only be implemented on devices, not on In-circuit Emulator. 38 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 11.5 Addressing Mode The GMS87C1404 and GMS87C1408 uses six addressing modes; (3) Direct Page Addressing dp * Register addressing Example; * Immediate addressing C535 In this mode, a address is specified within direct page. LDA ;A RAM[35H] 35H * Direct page addressing * Absolute addressing 0035H data A * Indexed addressing ~ ~ * Register-indirect addressing ~ ~ 0F550H C5 0F551H 35 data A (1) Register Addressing Register addressing accesses the A, X, Y, C and PSW. (2) Immediate Addressing #imm (4) Absolute Addressing !abs In this mode, second byte (operand) is accessed as a data immediately. Example: 0435 ADC #35H Absolute addressing sets corresponding memory data to Data , i.e. second byte(Operand I) of command becomes lower level address and third byte (Operand II) becomes upper level address. With 3 bytes command, it is possible to access to whole memory area. MEMORY ADC, AND, CMP, CMPX, CMPY, EOR, LDA, LDX, LDY, OR, SBC, STA, STX, STY 04 A+35H+C A 35 Example; 0735F0 E45535 LDM ADC data 0F035H 35H,#55H ~ ~ 0F100H ~ ~ A ~ ~ A+data+C A 07 0F101H 35 0F102H F0 address: 0F035 ~ ~ 0F100H data 55H data 0035H ;A ROM[0F035H] !0F035H A E4 0F101H 55 0F102H 35 Nov. 1999 Ver 0.0 preliminary 39 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics The operation within data memory (RAM) ASL, BIT, DEC, INC, LSR, ROL, ROR Example; Addressing accesses the address 0135H . 983500 INC ;A RAM[035H] !0035H X indexed direct page, auto increment {X}+ In this mode, a address is specified within direct page by the X register and the content of X is increased by 1. LDA, STA Example; X=35H DB data 0035H ~ ~ LDA {X}+ A A ~ ~ data+1 data 0F100H 98 0F101H 35 address: 0035 0F102H 00 35H A data ~ ~ data A ~ ~ 36H X DB (5) Indexed Addressing X indexed direct page (no offset) {X} In this mode, a address is specified by the X register. ADC, AND, CMP, EOR, LDA, OR, SBC, STA, XMA Example; X=15H D4 LDA {X} ;ACCRAM[X]. X indexed direct page (8 bit offset) dp+X This address value is the second byte (Operand) of command plus the data of -register. And it assigns the memory in Direct page. ADC, AND, CMP, EOR, LDA, LDY, OR, SBC, STA STY, XMA, ASL, DEC, INC, LSR, ROL, ROR Example; X=015H 15H C645 data ~ ~ LDA 45H+X A data A ~ ~ 0E550H 5AH D4 data A ~ ~ 40 preliminary A ~ ~ 0E550H C6 0E551H 45 data A 45H+15H=5AH Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 Y indexed direct page (8 bit offset) dp+Y 3F35 JMP [35H] This address value is the second byte (Operand) of command plus the data of Y-register, which assigns Memory in Direct page. This is same with above (2). Use Y register instead of X. 35H 0A 36H E3 Y indexed absolute !abs+Y ~ ~ Sets the value of 16-bit absolute address plus Y-register data as Memory. This addressing mode can specify memory in whole area. 0E30AH LDA 0FA00H D5 0F101H 00 0F102H FA ~ ~ 0FA55H ~ ~ 3F 35 !0FA00H+Y 0F100H A jump to address 0E30AH NEXT ~ ~ Example; Y=55H D500FA ~ ~ X indexed indirect [dp+X] 0FA00H+55H=0FA55H ~ ~ Processes memory data as Data, assigned by 16-bit pair memory which is determined by pair data [dp+X+1][dp+X] Operand plusX-register data in Direct page. A data A data A ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; X=10H 1625 ADC [25H+X] (6) Indirect Addressing Direct page indirect [dp] Assigns data address to use for accomplishing command which sets memory data(or pair memory) by Operand. Also index can be used with Index register X,Y. 35H 05 36H E0 0E005H JMP, CALL 0E005H ~ ~ A ~ ~ ~ ~ Example; 0FA00H preliminary 25 + X(10) = 35H ~ ~ 16 25 Nov. 1999 Ver 0.0 data A A + data + C A 41 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics Y indexed indirect [dp]+Y Absolute indirect [!abs] Processes momory data as Data, assigned by the data [dp+1][dp] of 16-bit pair memory paired by Operand in Direct pageplus Y-register data. The program jumps to address specified by 16-bit absolute address. ADC, AND, CMP, EOR, LDA, OR, SBC, STA Example; Example; Y=10H 1725 ADC JMP 1F25E0 JMP [!0C025H] [25H]+Y PROGRAM MEMORY 25H 05 0E025H 25 26H E0 0E026H E7 ~ ~ 0E015H ~ ~ 0FA00H ~ ~ 0E725H ~ ~ 0FA00H 17 A jump to address 0E30AH NEXT ~ ~ ~ ~ 25 42 0E005H + Y(10) = 0E015H data ~ ~ A ~ ~ 1F 25 A A + data + C A preliminary E0 Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 12. I/O PORTS The GMS81C2020 has eight ports, R0, R1, R2, R3, R4, R5, R6 and R7. The GMS81C2120 has five ports, R0, R2, R3, R5 and R6. These ports pins may be multiplexed with an alternate function for the peripheral features on the device. In general, when a initial reset state, all ports are used as a general purpose input port. port can directly drive a vacuum fluorescent display. R03 port is multiplexed with Buzzer Output Port(BUZO), R02 port is multiplexed with Event Counter Input Port (EC0), and R01~R00 are multiplexed with External Interrupt Input Port(INT1, INT0). ADDRESS : C0H RESET VALUE : Undefined R0 Data Register All pins have data direction registers which can set these ports as output or input. A "1" in the port direction register defines the corresponding port pin as output. Conversely, write "0" to the corresponding bit to specify as an input pin. For example, to use the even numbered bit of R0 as output ports and the odd numbered bits as input ports, write "55 H" to address C1H (R0 direction register) during initial setting as shown in Figure 12-1 . R07 R0 R06 R05 C1H R0 DIRECTION C2H R1 DATA C3H R1 DIRECTION - BIT O I O I O I O RA is one-bit high-voltage input only port pin. In addition, RA serves the functions of the Vdisp special features. Vdisp is used as a high-voltage input power supply pin when selected by the mask option.. ADDRESS : FBH RESET VALUE : Undefined RA Data Register - - - - - RA0 INPUT DATA Port pin RA - EC0 BUZO INT1 0 : R02 1 : EC0 INT0 0 : R00 1 : INT0 0 : R01 1 : INT1 Figure 12-2 Registers of Port R0 12.1 RA(Vdisp) register - - 7 6 5 4 3 2 1 0 PORT Figure 12-1 Example of port I/O assignment - - ADDRESS : F4H RESET VALUE : ----0000 0 : R03 1 : BUZO I R00 DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT I : INPUT PORT O : OUTPUT PORT RA R01 R0IO R0 Function Selection Register 0 1 0 1 0 1 0 1 7 6 5 4 3 2 1 0 R0 DATA R02 ADDRESS : C1H RESET VALUE : 00000000 R0 Direction Register R0FUNC C0H R03 INPUT / OUTPUT DATA Reading data register reads the status of the pins whereas writing to it will write to the port latch.. WRITE "55H" TO PORT RA DIRECTION REGISTER R04 Alternate function The control register R0FUNC (address F4H) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as Buzzer Output, External Event Counter Input and External Interrupt Input, write "1" to the corresponding bit of R0FUNC. Regardless of the direction register R0IO, R0FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features (BUZO, EC0, INT1, INT0) PORT R0FUNC [3:0] R03/ BUZO 0 R00 (Normal I/O Port) 1 BUZO (Buzzer Output Port) R02/ EC0 0 R01 (Normal I/O Port) 1 EC0 (Event Counter Input Port) 0 R01 (Normal I/O Port) 1 INT1 (External interrupt 1 Input Port) Vdisp (High-voltage input power supply) R01/ INT1 12.2 R0 and R0IO registers Description R0 is an 8-bit high-voltage CMOS bidirectional I/O port (address C0H). Each port can be set individually as input and output through the R0IO register (address C1 H). Each Nov. 1999 Ver 0.0 preliminary 43 GMS81C2020/GMS81C2120 R00/ INT0 Hyundai Micro Electro nics 0 R00 (Normal I/O Port) 1 INT0 (External interrupt 0 Input Port) (address C6H). Each port can be set individually as input and output through the R3IO register (address C7H). Each port can directly drive a vacuum fluorescent display.. 12.3 R1 and R1IO registers R3 Data Register R1 is an 8-bit high-voltage CMOS bidirectional I/O port (address C2H). Each port can be set individually as input and output through the R1IO register (address C3 H). Each port can directly drive a vacuum fluorescent display.. R3 - ADDRESS : C6H RESET VALUE : Undefined - R35 R34 R33 ADDRESS : C2H RESET VALUE : Undefined R1 R17 R16 R15 R14 R13 R12 R11 R30 ADDRESS : C7H RESET VALUE : --000000 R3IO R10 DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT INPUT / OUTPUT DATA A D D R E SS : C 3H R E SE T V A LU E : 00000 000 R1 Direction Register R31 INPUT / OUTPUT DATA R3 Direction Register R1 Data Register R32 R1IO Figure 12-5 Registers of Port R3 12.6 R4 and R4IO registers R4 is an 4-bit bidirectional I/O port (address C8H). Each port can be set individually as input and output through the R4IO register (address C9H). DIREC TION SELEC T 0 : IN P U T P O R T 1 : O U T P U T PO R T R40 port is multiplexed with Timer 0 Output Port(T0O), r Figure 12-3 Registers of Port R1 ADDRESS : C8H RESET VALUE : Undefined R4 Data Register 12.4 R2 and R2IO registers - R4 - - - R43 R2 is an 8-bit high-voltage CMOS bidirectional I/O port (address C4H). Each port can be set individually as input and output through the R2IO register (address C5 H). Each port can directly drive a vacuum fluorescent display.. ADDRESS : C4H RESET VALUE : Undefined R2 R27 R26 R25 R24 R23 R22 R21 R40 ADDRESS : C9H RESET VALUE : ----0000 R4IO R20 DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT INPUT / OUTPUT DATA R4 Function Selection Register R2 Direction Register R41 INPUT / OUTPUT DATA R4 Direction Register R2 Data Register R42 ADDRESS : C5H RESET VALUE : 00000000 ADDRESS : F5H RESET VALUE : -------0 R4FUNC - - - - - - - T0O R2IO 0 : R40 1 : T0O DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT Figure 12-6 Figure 12-4 Registers of Port R2 12.5 R3 and R3IO registers R1 is an 6-bit high-voltage CMOS bidirectional I/O port 44 Registers of Port R4 The control register R4FUNC (address F5H) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as Timer 0 Output, write "1" to the corresponding bit of R4FUNC. Regardless of the direction register R4IO, R4FUNC is selected to use as alternate functions, port pin preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 can be used as a corresponding alternate features (T0O) PORT R40/ T0O R4FUNC [0] Description 0 R40 (Normal I/O Port) 1 T0O (Timer 0 Compare Output Port) Nov. 1999 Ver 0.0 preliminary 45 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 12.7 R5 and R5IO registers 12.8 R6 and R6IO registers R5 is an 8-bit bidirectional I/O port (address CAH). Each pin can be set individually as input and output through the R5IO register (address CBH).In addition, Port R5 is multiplexed with Serial Peripheral Interface (SPI). The control register R5FUNC (address F6H) controls to select Serial Peripheral Interface function.After reset, the R5IO register value is "0", port may be used as general I/O ports. To select Serial Peripheral Interface function, write "1" to the corresponding bit of R5FUNC. R6 is an 8-bit bidirectional I/O port (address CCH). Each port can be set individually as input and output through the R6IO register (address CDH). ADDRESS : CCH RESET VALUE : Undefined R6 Data Register R6 R67 R66 R65 R64 R57 R56 R55 R54 R53 R52 R51 R6 Direction Register R50 R63 R62 R61 R60 INPUT / OUTPUT DATA ADDRESS : CAH RESET VALUE : Undefined R5 Data Register R5 R67~R60 ports are multiplexed with Analog Input Port ( AN7~AN0 ).. ADDRESS : CDH RESET VALUE : 00000000 R6IO INPUT / OUTPUT DATA DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT ADDRESS : CBH RESET VALUE : 00000000 R5 Direction Register R5IO R6 Function Selection Register R6FUNC DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT R5 Function Selection Register R5FUNC - PWM1O SOUT SIN ANSEL7 ANSEL6 ANSEL5 ANSEL4 ANSEL3 ANSEL2 ANSEL1 ANSEL0 0 : R64 1 : AN4 0 : R65 1 : AN5 0 : R66 1 : AN6 0 : R67 1 : AN7 ADDRESS : F6H RESET VALUE : -0000--SCLK - - - 0 : R53 1 : SCLK 0 [R5IO.3] : SCLKO 1 [R5IO.3] : SCLKI 0 : R54 1 : SIN 0 : R56 1 : PWM1O/T1O 0 : R55 1 : SOUT PORT R5FUNC [6:3] R56/ PWM1O/ T1O 0 R56 (Normal I/O Port) 1 PWM1 Data Output / Timer 1 Data Output 0 R55 (Normal I/O Port) 1 SPI Serial Data Output 0 R54 (Normal I/O Port) 1 SPI Serial Data Input 0 R53 (Normal I/O Port) R54/SIN R53/SCLK 0 : R60 1 : AN0 0 : R61 1 : AN1 0 : R62 1 : AN2 0 : R63 1 : AN3 Figure 12-8 Registers of Port R6 Figure 12-7 Registers of Port R5 R55/SOUT ADDRESS : F7H RESET VALUE : 00000000 Description 0 [R5IO.3] SCLKO SPI Synchronous Clock Output 1 [R5IO.3] SCLKI SPI Synchronous Clock Input Table 12-1 Registers of Port R5FUNC 46 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 The control register R6FUNC (address F7H) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as Analog Input, write "1" to the corresponding bit of R6FUNC. Regardless of the direction register R6IO, R6FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features (AN7~AN0) PORT R67/AN7 R66/AN6 R65/AN5 R64/AN4 R63/AN3 R62/AN2 R61/AN1 R60/AN0 AN11~AN8 ).. ADDRESS : CEH RESET VALUE : Undefined R7 Data Register - R7 - - - R72 R71 R70 INPUT / OUTPUT DATA ADDRESS : CFH RESET VALUE : ----0000 R7 Direction Register R6FUNC [7:0] R73 Description R7IO 0 R67 ( Normal I/O Port ) 1 AN7 ( ADS3~0=0111 ) 0 R66 ( Normal I/O Port ) 1 AN6 ( ADS3~0=0110 ) R7 Function Selection Register 0 R65 ( Normal I/O Port ) R7FUNC 1 AN5 ( ADS3~0=0101 ) 0 R64 ( Normal I/O Port ) 1 AN4 ( ADS3~0=0100 ) 0 R63 ( Normal I/O Port ) 1 AN3 ( ADS3~0=0011 ) 0 R62 ( Normal I/O Port ) 1 AN2 ( ADS3~0=0010 ) 0 R61 ( Normal I/O Port ) Figure 12-9 Registers of Port R6 1 AN1 ( ADS3~0=0001 ) 0 R60 ( Normal I/O Port ) 1 AN0 ( ADS3~0=0000 ) The control register R7FUNC (address F8H) controls to select alternate function. After reset, this value is "0", port may be used as general I/O ports. To select alternate function such as Analog Input, write "1" to the corresponding bit of R7FUNC. Regardless of the direction register R7IO, R7FUNC is selected to use as alternate functions, port pin can be used as a corresponding alternate features. DIRECTION SELECT 0 : INPUT PORT 1 : OUTPUT PORT - - - ANSEL11 ANSEL10 ANSEL9 ANSEL8 0 : R70 1 : AN8 0 : R71 1 : AN9 0 : R72 1 : AN10 0 : R73 1 : AN11 12.9 R7 and R7IO registers R7 is an 4-bit bidirectional I/O port (address CEH). Each port can be set individually as input and output through the R7IO register (address CFH). PORT R73~R70 ports are multiplexed with Analog Input Port R73/AN11 R72/AN10 R71/AN9 R70/AN8 Nov. 1999 Ver 0.0 - ADDRESS : F8H RESET VALUE : ----0000 preliminary R7FUNC [7:0] Description 0 R73 ( Normal I/O Port ) 1 AN11 ( ADS3~0=1011 ) 0 R72 ( Normal I/O Port ) 1 AN10 ( ADS3~0=1010 ) 0 R71 ( Normal I/O Port ) 1 AN9 ( ADS3~0=1001 ) 0 R70 ( Normal I/O Port ) 1 AN8 ( ADS3~0=1000 ) 47 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 13. CLOCK GENERATOR The clock generator produces the basic clock pulses which provide the system clock to be supplied to the CPU and peripheral hardware. The main system clock oscillator oscillates with a crystal resonator or a ceramic resonator CLKSEL OSCILLATION CIRCUIT fXI CS[1:0] 0 1 SUB OSCILLATION CIRCUIT connected to the XI and XO pins. External clocks can be input to the main system clock oscillator. In this case, input a clock signal to the XI pin and open the XO pin. fSXI fXI/ 4 fXI/ 8 fXI/32 CLOCK PULSE GENERATOR MUX Internal system clock PRESCALER STOP WAKEUP /1 /2 /4 /8 /16 /32 /64 /128 /256 /512 /1024 /2048 /4096 Peripheral clock System Clock Mode Register - SCMR CS[1:0] - - CS1 CS0 SUBOFF CLKSEL MAINOFF Clock selection enable bits 00 : fXI / 210 : fXI /16 CLKSEL Clock selection bit 0 : Main clock selection 1 : Sub clock selection Sub clock control bit 0: On sub clock 1: Off sub clock MAINOFF Main clock control bit 0: On main clock 1: Off main clock 01 : fXI / 811 : fXI / 64 SUBOFF ADDRESS : FAH RESET VALUE : ---00000 Figure 13-1 Block Diagram of Clock Pulse Generator 13.1 Oscillation Circuit XI and XO are the input and output, respectively, a inverting amplifier which can be set for use as an on-chip oscillator, as shown in Figure 13-2 . C1 Figure 13-2 Oscillator Connections SXI and SXO are the input and output, respectively, a inverting amplifier which can be set for use as an on-chip os- XO C2 XI Vss Recommended: C1, C2 = 30pF10pF for Crystals 48 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 cillator, as shown in Figure 13-2 . Oscillation circuit is designed to be used either with a external RC oscillator. Since External RC oscillator has their own characteristic, the user should figure out the appropriate value of external resister. (Please refer the DC Spec) SXO C1 C2 SXI XO REXT Vss XI Recommended: C1, C2 = 20pF4pF for Crystals Vss Figure 13-3 Sub Oscillator Connections To drive the device from an external clock source, XO should be left unconnected while XI is driven as shown in Figure 13-4 . There are no requirements on the duty cycle of the external clock signal, since the input to the internal clocking circuitry is through a divide-by-two flip-flop, but minimum and maximum high and low times specified on the data sheet must be observed. Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components. OPEN External Clock Source XO Figure 13-4 External R Connection Note: When using a system clock oscillator, carry out wiring in the broken line area in Figure 13-2 to prevent any effects from wiring capacities. - Minimize the wiring length. - Do not allow wiring to intersect with other signal conductors. - Do not allow wiring to come near changing high current. - Set the potential of the grounding position of the oscillator capacitor to that of VSS. Do not ground to any ground pattern where high current is present. - Do not fetch signals from the oscillator. XI Vss Nov. 1999 Ver 0.0 preliminary 49 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 14. Basic Interval Timer cillator, prescaler ( only fXI/2048 ) and Timer0. The GMS81C2020 and GMS81C2120 has one 8-bit Basic Interval Timer that is free-run, can not stop. Block diagram is shown in Figure 14-1 .The 8-bit Basic interval timer register (BITR) is increased every internal count pulse which is divided by prescaler. Since prescaler has divided ratio by 8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator frequency. As the count overflows from FFH to 00H, this overflow causes to generate the Basic interval timer interrupt. The BITIF is interrupt request flag of Basic interval timer. If the STOP instruction executed after writing "1" to bit RCWDT of CKCTLR, it goes into the internal RC oscillated watchdog timer mode. In this mode, all of the block is halted except the internal RC oscillator, Basic Interval Timer and Watchdog Timer. More detail informations are explained in Power Saving Function. The bit WDTON decides Watchdog Timer or the normal 7-bit timer Note: All control bits of Basic interval timer are in CKCTLR register which is located at same address of BITR (address ECH). Address ECH is read as BITR, written to CKCTLR. Therefore, the CKCTLR can not be accessed by bit manipulation instruction. When write "1" to bit BTCL of CKCTLR, BITR register is cleared to "0" and restart to count-up. The bit BTCL becomes "0" after one machine cycle by hardware. If the STOP instruction executed after writing "1" to bit WAKEUP of CKCTLR, it goes into the wake-up timer mode. In this mode, all of the block is halted except the os- . WAKEUP STOP RCWDT BTS[2:0] fXI /8 / 16 / 32 / 64 / 128 / 256 / 512 /1024 BTCL To Watchdog Timer Clear 0 MUX BITIF BITR ( 8-BIT ) Basic Interval Timer Interrupt 1 Internal RC OSC Figure 14-1 Block Diagram of Basic Interval Timer Clock Control Register CKCTLR - WAKEUP RCWDT WDTON BTCL BTS2 BTS1 BTS0 ADDRESS : ECH RESET VALUE : -0010111 Bit Manipulation Not Available Basic Interval Timer Clock Selection Symbol WAKEUP 000 : fXI / 8 Function Description 001 : fXI / 16 1: Enables Wake-up Timer 0: Disables Wake-up Timer 010 : fXI / 32 RCWDT 1: Enables Internal RC Watchdog Timer 0: Disables Internal RC Watchdog Timer WDTON 1: Enables Watchdog Timer 0: Operates as a 7-bit Timer BTCL 011 : fXI / 64 100 : fXI / 128 101 : fXI / 256 110 : fXI / 512 1: BITR is cleared and BTCL becomes "0" automatically after one machine cycle, and BITR continue to count-up 111 : fXI / 1024 Figure 14-2 CKCTLR : Clock Control Register 50 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 15. TIMER / COUNTER The GMS81C2020 and GMS81C2120 has two Timer/ Counter registers. Each module can generate an interrupt to indicate that an event has occurred (i.e. timer match). Timer 0 and Timer 1 can be used either the two 8-bit Timer/Counter or one 16-bit Timer/Counter by combining them. In the "timer" function, the register is increased every internal clock input. Thus, one can think of it as counting internal clock input. Since a least clock consists of 2 and most clock consists of 2048 oscillator periods, the count rate is 1/2 to 1/2048 of the oscillator frequency in Timer0. And Timer1 can use the same clock source too. In addition, Timer1 has more fast clock source ( 1/1 to 1/8 ). sponse to a 0-to-1 (rising & falling edge) transition at its corresponding external input pin, EC0(Timer 0). In addition the "capture" function, the register is increased in response external interrupt same with timer function. When external interrupt edge input, the count register is captured into capture data register CDRx. Timer1 is shared with "PWM" function and "Compare output" function It has seven operating modes: "8-bit timer/counter", "16bit timer/counter", "8-bit capture", "16-bit capture", "8-bit compare output", "16-bit compare output" and "10-bit PWM" which are selected by bit in Timer mode register TMx as shown in Figure 15-1 and Table 12-1 . In the "counter" function, the register is increased in re- Timer 0 Mode Register - TM0 - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST ADDRESS : D0H RESET VALUE : --000000 CAP0 Capture mode selection bit. 0 : Disables Capture 1 : Enables Capture T0CN Continue control bit 0 : Stop counting 1 : Start counting continuously T0CK[2:0] Input clock selection 000 : fXI / 2100 : fXI / 128 T0ST Start control bit 0 : Stop counting 1 : Counter register is cleared and start again 001 : fXI / 4101 : fXI / 512 010 : fXI / 8110 : fXI / 2048 011 : fXI / 32111 : External Event (EC0) Timer 1 Mode Register TM1 POL POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST ADDRESS : D2H RESET VALUE : 00000000 PWM Output Polarity 0 :Duty active low 1 : Duty active high T1CK[2:0]] 16BIT 16-bit mode selection 0 : 8-bit mode 1 : 16-bit mode T1CN Continue control bit 0 : Stop counting 1 : Start counting continuously PWM1E PWM enable bit 0 : Disables PWM 1 : Enables PWM T1ST Start control bit 0 : Stop counting 1 : Counter register is cleared and start again CAP1 Capture mode selection bit. 0 : Disables Capture 1 : Enables Capture Input clock selection 00 : fXI 10 : fXI / 8 01 : fXI / 211 : using the Timer 0 clock Figure 15-1 Timer Mode Register ( TMx , x = 0~1 ) Nov. 1999 Ver 0.0 preliminary 51 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 16BIT CAP0 CAP1 PWM1E T0CK[2:0] T1CK[1:0] PWMO TIMER 0 TIMER1 0 0 0 0 XXX XX 0 8-bit Timer 8-bit Timer 0 0 1 0 111 XX 0 8-bit Event Counter 8-bit Capture 0 1 0 0 XXX XX 1 8-bit Capture 8-bit Compare output 0 X1 0 1 XXX XX 1 8-bit Timer/Counter 10-bit PWM 1 0 0 0 XXX 11 0 16-bit Timer 1 0 0 0 111 11 0 16-bit Event Counter 1 1 X 0 XXX 11 0 16-bit Capture 1 0 0 0 XXX 11 1 16-bit Compare output Table 15-1 Operating Modes of Timer 0 and Timer 1 1. X : The value "0" or "1" corresponding your operation. 15.1 8-bit Timer/Counter Mode The GMS81C2020 and GMS81C2120 has four 8-bit Timer/Counters, Timer 0, Timer 1 as shown in Figure 15-2 . The "timer" or "counter" function is selected by mode registers TMx as shown in Figure 15-1 and Table 15-1 . To TM0 TM1 use as an 8-bit timer/counter mode, bit CAP0 of TM0 is cleared to "0" and bits 16BIT of TM1 should be cleared to "0"(Table 15-1 ). - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST - - 0 X X X X X POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST X 0 0 0 X X X X T0ST Edge Detector 0 : Stop 1 : Clear and Start fXI /2 /4 /8 / 32 / 128 / 512 / 2048 /1 /2 /8 ADDRESS : D2H RESET VALUE : 00000000 X : The value "0" or "1" corresponding your operation. T0CK[2:0] EC0 ADDRESS : D0H RESET VALUE : --000000 T0CK MUX 1 T0 ( 8-bit ) F/F CLEAR R40/T0O R4FUNC.0 TIMER 0 INTERRUPT T0IF COMPARATOR T0CN TDR0 ( 8-bit ) T1CK[1:0] T1ST 0 : Stop 1 : Clear and Start 1 MUX T1 ( 8-bit ) F/F CLEAR R56/PWM1O/T1O R5FUNC.6 T1IF COMPARATOR T1CN TIMER 1 INTERRUPT TDR1 ( 8-bit ) Figure 15-2 8-bit Timer / Counter Mode 52 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 These timers have each 8-bit count register and data register. The count register is increased by every internal or external clock input. The internal clock has a prescaler divide ratio option of 2, 4, 8, 32,128, 512, 2048 (selected by control bits T0CK2, T0CK1 and T0CK0 of register TM0) and 1, 2, 8 (selected by control bits T1CK1 and T1CK0 of register TM1). In the Timer 0, timer register T0 increases from 00H until it matches TDR0 and then reset to 00H. The match output of Timer 0 generates Timer 0 interrupt (latched in T0IF bit). As TDRx and Tx register are in same address, when reading it as a Tx, written to TDRx. In counter function, the counter is increased every 0-to1(1-to-0) (rising & falling edge) transition of EC0 pin. In order to use counter function, the bit EC0 of the R0 Function Selection Register (R0FUNC.2) is set to "1". The Timer 0 can be used as a counter by pin EC0 input, but Timer 1 can not. TDR1 n n-1 ~~ up -c ou nt ~~ PCP ~~ 9 8 7 6 5 4 3 2 1 0 Timer 1 (T1IF) Interrupt TIME Interrupt period = PCP x (n+1) Occur interrupt Occur interrupt Occur interrupt Figure 15-3 Counting Example of Timer Data Registers TDR1 disable t ~~ clear & start enable up -c ou n stop ~~ TIME Timer 1 (T1IF) Interrupt Occur interrupt T1ST Start & Stop T1ST = 0 Occur interrupt T1ST = 1 T1CN Control count T1CN = 0 T1CN = 1 Figure 15-4 Timer Count Operation Nov. 1999 Ver 0.0 preliminary 53 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 15.2 16-bit Timer/Counter Mode The Timer register is being run with 16 bits. A 16-bit timer/ counter register T0, T1 are increased from 0000H until it matches TDR0, TDR1 and then resets to 0000 H . The match output generates Timer 0 interrupt not Timer 1 interrupt. In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1 should be set to "1" respectively. - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST - - 0 X X X X X POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST X 1 0 0 1 1 X X TM0 TM1 The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0CK0. ADDRESS : D0H RESET VALUE : --000000 ADDRESS : D2H RESET VALUE : 00000000 X : The value "0" or "1" corresponding your operation. T1CK[1:0] T0CK[2:0] T0ST T0CN Edge Detector 0 : Stop 1 : Clear and Start 1 11 EC0 fXI /2 /4 /8 / 32 / 128 / 512 / 2048 T1 ( 8-bit ) MUX T0 ( 8-bit ) CLEAR F/F XX R40/T0O R4FUNC.0 fXI /1 /2 /8 T0IF COMPARATOR TDR1 ( 8-bit ) TIMER 0 INTERRUPT TDR0 ( 8-bit ) Figure 15-5 16-bit Timer / Counter Mode 15.3 8-bit Compare Output ( 16-bit ) The GMS81C2020 and GMS81C2120 has a function of Timer Compare Output. To pulse out, the timer match can goes to port pin(T0O, T1O) as shown in Figure 15-2 and Figure 15-5 . Thus, pulse out is generated by the timer match. These operation is implemented to pin, T0O, PWM1O/T1O. This pin output the signal having a 50 : 50 duty square wave, and output frequency is same as below equation. = ------------------------------------------------------------------------------------------ x x ( + ) In this mode, the bit PWM1O/T1O of R5 function register (R5FUNC.6) should be set to "1", and the bit PWM1E of timer1 mode register ( TM1 ) should be set to "0". In addition, 16-bit Compare output mode is available, also. 15.4 8-bit Capture Mode The Timer 0 capture mode is set by bit CAP0 of timer mode register TM0 (bit CAP1 of timer mode register TM1 for Timer 1) as shown in Figure 15-6 . As mentioned above, not only Timer 0 but Timer 1 can also 54 be used as a capture mode. The Timer/Counter register is increased in response internal or external input. This counting function is same with normal timer mode, and Timer interrupt is generated when preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 timer register T0 (T1) increases and matches TDR0 (TDR1). This timer interrupt in capture mode is very useful when the pulse width of captured signal is more wider than the maximum period of Timer. For example, in Figure 15-8 , the pulse width of captured signal is wider than the timer data value (FF H ) over 2 times. When external interrupt is occured, the captured value (13H) is more little than wanted value. It can be obtained correct value by counting the number of timer overflow occurence. tured into registers CDRx (CDR0, CDR1), respectively. After captured, Timer x register is cleared and restarts by hardware. It has three transition modes: "falling edge", "rising edge", "both edge" which are selected by interrupt edge selection register IEDS (Refer to External interrupt section). In addition, the transition at INTx pin generate an interrupt. Note: The CDRx, TDRx and Tx are in same address. In the capture mode, reading operation is read the CDRx, not Tx because path is opened to the CDRx, and TDRx is only for writing operation. Timer/Counter still does the above, but with the added feature that a edge transition at external input INTx pin causes the current value in the Timer x register (T0,T1), to be cap- - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST - - 1 X X X X X POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST X 0 0 1 X X X X TM0 TM1 T0CK[2:0] 0 : Stop 1 : Clear and Start T0CK fXI /2 /4 /8 / 32 / 128 / 512 / 2048 ADDRESS : D2H RESET VALUE : 00000000 T0ST Edge Detector EC0 ADDRESS : D0H RESET VALUE : --000000 1 T0 ( 8-bit ) MUX CLEAR T0IF CAPTURE T0CN COMPARATOR CDR0 ( 8-bit ) TDR0 ( 8-bit ) INT 0 INTERRUPT INT0IF INT0 TIMER 0 INTERRUPT T0ST 0 : Stop 1 : Clear and Start IEDS[1:0] /1 /2 /8 1 MUX CLEAR T1 ( 8-bit ) CAPTURE T1IF COMPARATOR T1CN T1CK[1:0] IEDS[3:2] CDR1 ( 8-bit ) TIMER 1 INTERRUPT TDR1 ( 8-bit ) INT1IF INT 1 INTERRUPT INT1 Figure 15-6 8-bit Capture Mode Nov. 1999 Ver 0.0 preliminary 55 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics This value is loaded to CDR0 n T0 n-1 up -c ou nt ~~ ~~ 9 8 7 6 5 4 ~~ 3 2 1 0 TIME Ext. INT0 Pin Interrupt Request ( INT0F ) Interrupt Interval Period Ext. INT0 Pin Interrupt Request ( INT0F ) Delay Capture ( Timer Stop ) Clear & Start Figure 15-7 Input Capture Operation Ext. INT0 Pin Interrupt Request ( INT0F ) Interrupt Interval Period = FFH + 01H + FFH +01H + 13H = 213H Interrupt Request ( T0F ) FFH FFH T0 13H 00H 00H Figure 15-8 Excess Timer Overflow in Capture Mode 56 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 15.5 16-bit Capture Mode 16-bit capture mode is the same as 8-bit capture, except that the Timer register is being run will 16 bits. In 16-bit mode, the bits T1CK1,T1CK0 and 16BIT of TM1 should be set to "1" respectively. The clock source of the Timer 0 is selected either internal or external clock by bit T0CK2, T0CK1 and T0CK0. - - CAP0 T0CK2 T0CK1 T0CK0 T0CN T0ST - - 1 X X X X X POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST X 1 0 X 1 1 X X TM0 TM1 ADDRESS : D0H RESET VALUE : --000000 ADDRESS : D2H RESET VALUE : 00000000 X : The value "0" or "1" corresponding your operation. T1CK[1:0] T0CK[2:0] T0ST T0CN Edge Detector 0 : Stop 1 : Clear and Start 1 11 EC0 fXI /2 /4 /8 / 32 / 128 / 512 / 2048 CLEAR T0 + T1 ( 16-bit ) MUX XX fXI /1 /2 /8 T0IF COMPARATOR CAPTURE TIMER 0 INTERRUPT CDR1 CDR0 TDR1 TDR0 ( 8-bit ) ( 8-bit ) ( 8-bit ) ( 8-bit ) INT0IF INT 0 INTERRUPT INT0 IEDS[1:0] Figure 15-9 16-bit Capture Mode 15.6 PWM Mode The GMS81C2020 and GMS81C2120 has a high speed PWM (Pulse Width Modulation) functions which shared with Timer1. In PWM mode, pin R56/PWM1O/T1O outputs up to a 10bit resolution PWM output. This pin should be configured as a PWM output by setting "1" bit PWM1O in R5FUNC.6 register. The period of the PWM output is determined by the T1PPR (PWM1 Period Register) and PWM1HR[3:2] (bit3,2 of PWM1 High Register) and the duty of the PWM output is determined by the T1PDR (PWM1 Duty Register) and PWM1HR[1:0] (bit1,0 of PWM1 High Register). And writes duty value to the T1PDR and the PWM1HR[1:0] same way. The T1PDR is configured as a double buffering for glitchless PWM output. In Figure 15-10 , the duty data is transfered from the master to the slave when the period data matched to the counted value. ( i.e. at the beginning of next duty cycle ) PWM Period = [ PWM1HR[3:2]T1PPR ] X Source Clock PWM Duty = [ PWM1HR[1:0]T1PDR ] X Source Clock The relation of frequency and resolution is in inverse proportion. Table 15-2 shows the relation of PWM frequency vs. resolution. The user writes the lower 8-bit period value to the T1PPR and the higher 2-bit period value to the PWM1HR[3:2]. Nov. 1999 Ver 0.0 preliminary 57 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics If it needed more higher frequency of PWM, it should be reduced resolution. The bit POL of TM1 decides the polarity of duty cycle. If the duty value is set same to the period value, the PWM output is determined by the bit POL ( 1: High, 0: Low ). And if the duty value is set to "00H", the PWM output is determined by the bit POL ( 1: Low, 0: High ). Frequency Resolution T1CK[1:0] = 00(250nS) T1CK[1:0] = 01(500nS) T1CK[1:0] = 10(2uS) 10-bit 3.9KHz 0.98KHZ 0.49KHZ 9-bit 7.8KHz 1.95KHz 0.97KHz 8-bit 15.6KHz 3.90KHz 1.95KHz 7-bit 31.2KHz 7.81KHz 3.90KHz It can be changed duty value when the PWM output. Howerver the changed duty value is output after the current period is over. And it can be maintained the duty value at present output when changed only period value shown as Figure 15-12 . As it were, the absolute duty time is not changed in varying frequency. But the changed period value must greater than the duty value. Table 15-2 PWM Frequency vs. Resolution at 4MHz TM1 PWM1HR POL 16BIT PWM1E CAP1 T1CK1 T1CK0 T1CN T1ST X 0 1 0 X X X X - - - - - - - - PWM1HR3PWM1HR2PWM1HR1PWM1HR0 X X X Period High T1ST ADDRESS : D5H RESET VALUE : ----0000 Bit Manipulation Not Available X Duty High X : The value "0" or "1" corresponding your operation. PWM1HR[3:2] T0 clock source [T0CK] ADDRESS : D2H RESET VALUE : 00000000 T1PPR(8-bit) 0 : Stop 1 : Clear and Start R56/ PWM1O/T1O COMPARATOR S Q CLEAR 1 fXI /1 /2 /8 MUX (2-bit) COMPARATOR T1CK[1:0] R T1 ( 8-bit ) PWM1O [R5FUNC.6] POL T1CN Slave T1PDR(8-bit) PWM1HR[1:0] Master T1PDR(8-bit) Figure 15-10 PWM Mode 58 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 ~ ~ ~ ~ fXI 02 03 04 05 80 81 3FF 00 01 02 03 ~ ~ ~ ~ PWM POL=1 7F ~ ~ ~ ~ 00 01 ~ ~ ~ ~ ~ ~ T1 ~ ~ PWM POL=0 Duty Cycle [ 80H x 250nS = 32uS ] Period Cycle [ 3FFH x 250nS = 255.75uS, 3.9KHz ] T1CK[1:0] = 00 ( fXI ) PWM1HR = 0CH T1PPR (8-bit) Period PWM1HR3PWM1HR2 1 1 FFH T1PPR = FFH T1PDR = 80H Duty T1PDR (8-bit) PWM1HR1PWM1HR0 0 0 80H Figure 15-11 Example of PWM at 4MHz T 1C K [1:0] = 10 ( 1uS ) P W M 1H R = 00H T 1P P R = 0E H T 1P D R = 05H Write T1PPR to 0AH Period changed Source clock T1 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 01 02 03 04 05 06 07 08 09 0A 01 02 03 04 05 PWM POL=1 Duty Cycle [ 05H x 2uS = 10uS ] Duty Cycle [ 05H x 2uS = 10uS ] Period Cycle [ 0EH x 2uS = 28uS, 35.5KHz ] Duty Cycle [ 05H x 2uS = 10uS ] Period Cycle [ 0AH x 2uS = 20uS, 50KHz ] Figure 15-12 Example of Changing the Period in Absolute Duty Cycle (@4MHz) Nov. 1999 Ver 0.0 preliminary 59 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 16. Serial Peripheral Interface The Serial Peripheral Interface (SPI) module is a serial interface useful for communicating with other peripheral of microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D converters, etc. SPI Mode Control Register POL SIOM IOSW SM1 SM0 SCK1 SCK0 SIOST ADDRESS : E0H RESET VALUE : 00000000 SIOSF Serial Clock Polarity Selection bit. 0 : Data Transmission at falling edge ( Received data latch at rising edge ) 1 : Data Transmission at rising edge ( Received data latch at falling edge ) SCK[1:0] IOSW Serial Input Pin Selection bit 0 : SIN(R54) Pin Selection 1 : SOUT(R55) Pin Selection SIOST Serial Transmit Start bit 0 : Disable 1 : Start ( After one SCLK, becomes "0" ) SM[1:0] Serial Operation Mode Selection bits 00 : Normal Port ( R55, R54, R53 ) 01 : Transmit Mode ( SOUT,R54, SCLK ) 10 : Receive Mode ( R55, SIN, SCLK ) 11 : Transmit & Receive Mode ( SOUT, SIN, SCLK ) SIOSF Serial Transmit Status bit 0 : During Transmission 1 : Finished POL Serial Clock Selection bits 00 : fXI / 4 01 : fXI / 16 10 : TMR0OV ( Overflow of Timer 0 ) 11 : External Clock SPI Data Register ADDRESS : E1H RESET VALUE : Undefined SIOR T0CK[2:0] POL [SIOM.7] / 4 /16 fXI R53/SCLK 0 : Disable 1 : Clear and Start SIOSF 0 : Process 1 : Completed SPI Control Circuit Octal Counter ( 3-Bit ) MUX TMR0OV (Timer 0 overflow) 1 0 SIOST SPIIF SPI INTERRUPT SCLKI LSB MSB SCLKO SIOR ( 8-Bit ) R55/SOUT R54/SIN SCLK [R5FUNC.3] IOSW IOSW Figure 16-1 SPI Registers and Block Diagram The SPI allows 8-bits of data to be synchronously transmitted and received. To accomplish communication, typically three pins are used: - Serial Data In - Serial Data Out - Serial Clock 60 R54/SIN R55/SOUT R53/SCLK The serial data transfer operation mode is decided by setting the SM1 and SM0 of SPI Mode Control Register, and the transfer clock rate is decided by setting the SCK1 and SCK0 of SPI Mode Control Register as shown in Figure 16-1 . And the polarity of transfer clock is selected by set- preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 ting the POL.. SIOST SCLK (POL=1) SCLK (POL=0) D0 SOUT SIN D0 D1 D1 D2 D2 D3 D3 D4 D4 D5 D5 D6 D6 D7 D7 SPIIF (SPI Int. Req) 7 6 5 4 3 2 1 0 C "0" C SIOR (Data Output :SOUT) 7 6 5 4 3 2 1 0 SIOR (Data Input :SIN) Figure 16-2 SPI Timing Diagram Nov. 1999 Ver 0.0 preliminary 61 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 17. Buzzer Output function The buzzer driver consists of 6-bit binary counter, the buzzer register BUR and the clock selector. It generates square-wave which is very wide range frequency (480 Hz~250 KHz at fxin = 4 MHz) by user programmable counter. Also, it is cleared by counter overflow and count up to output the square wave pulse of duty 50%. The bit 0 to 5 of BUR determines output frequency for buzzer driving. Frequency calculation is following as shown below. Pin R03 is assigned for output port of Buzzer driver by setting the bit BUZO of R0FUNC to "1". The 6-bit buzzer counter is cleared and start the counting by writing signal to the register BUR. It is increased from 00H until it matches 6-bit register BUR. BUR BUCK1 BUCK0 Input clock selection 00 : fXI / 8 BUR5 BUR4 BUR3 Oscillator Frequency ( ) = ------------------------------------------------------------------------------------ x Prescaler Ratio x ( + ) The bits BUCK1, BUCK0 of BUR selects the source clock from prescaler output. BUR2 BUR1 BUR0 ADDRESS : DEH RESET VALUE : 11111111 Bit Manipulation Not Available Buzzer Period Data 01 : fXI / 16 10 : fXI / 32 11 : fXI / 64 fXI /8 / 16 / 32 / 64 MUX Counter ( 6-bit ) Overflow Detector F/F R03/BUZO Writing to BUR[5:0] BUZO [R0FUNC.3] RESET BUCK[1:0] BUR ( 6-bit ) Figure 17-1 Buzzer Driver 62 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 18. ANALOG TO DIGITAL CONVERTER The analog-to-digital converter (A/D) allows conversion of an analog input signal to a corresponding 8-bit digital value. The A/D module has twelve analog inputs, which are multiplexed into one sample and hold. The output of the sample and hold is the input into the converter, which generates the result via successive approximation. The A/D module has two registers which are the control register ADCM and A/D result register ADCR. The ADCM register, shown in Figure 18-2 , controls the operation of the A/D converter module. The port pins can be configured as analog inputs or digital I/O. To use analog inputs, each port is assigned analog input port by setting the bit ANSEL[7:0] in R6FUNC register. Also it is assigned analog input port by setting the bit AN- SEL[11:8] in R7FUNC register. And selected the corresponding channel to be converted by setting ADS[3:0]. The processing of conversion is start when the start bit ADST is set to "1". After one cycle, it is cleared by hardware. The register ADCR contains the results of the A/D conversion. When the conversion is completed, the result is loaded into the ADCR, the A/D conversion status bit ADSF is set to "1", and the A/D interrupt flag ADIF is set. The block diagram of the A/D module is shown in Figure 18-1 . The A/D status bit ADSF is set automatically when A/D conversion is completed, cleared when A/D conversion is in process. The conversion time takes maximum 20 uS (at fXI=4 MHz). ADS[3:0] R6FUNC[7:0] R67/AN7 R7FUNC[3:0] 0111 1011 0110 1010 0101 1001 0100 1000 R73/AN11 ANSEL11 ANSEL7 R66/AN6 R72/AN10 ANSEL10 ANSEL6 R65/AN5 R71/AN9 ANSEL9 ANSEL5 R64/AN4 R70/AN8 ANSEL4 ANSEL8 0011 R63/AN3 ANSEL3 0010 R62/AN2 A/D Result Register ADCR(8-bit) ANSEL2 ADDRESS : EBH RESET VALUE : Undefined 0001 R61/AN1 Sample & Hold ANSEL1 COMPARATOR 0000 R60/AN0 Successive Approximation Circuit S/H ANSEL0 A D IF A/D Interrupt Resistor Ladder Circuit AVDD ADEN [ADCM.6] Figure 18-1 A/D Converter Block Diagram Nov. 1999 Ver 0.0 preliminary 63 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics A/D Control Register ADCM - ADEN ADS3 ADS2 ADS1 ADS0 ADST ADSF Reserved A/D Status bit 0 : A/D Conversion is in process 1 : A/D Conversion is completed Analog Channel Select 0000 : Channel 0 ( R60/AN0 ) 0001 : Channel 1 ( R61/AN1 ) 0010 : Channel 2 ( R62/AN2 ) 0011 : Channel 3 ( R63/AN3) 0100 : Channel 4 ( R64/AN4 ) 0101 : Channel 5 ( R65/AN5 ) 0110 : Channel 6 ( R66/AN6 ) 0111 : Channel 7 ( R67/AN7 ) 1000 : Channel 8 ( R64/AN8 ) 1001 : Channel 9 ( R65/AN9 ) 1010 : Channel 10 ( R66/AN10 ) 1011 : Channel 11 ( R67/AN11 ) A/D Enable bit 1 : A/D Conversion is enable 0 : A/D Converter module shut off and consumes no operation current ADDRESS : EAH RESET VALUE : -0000001 A/D Start bit 1 : A/D Conversion is started After 1 cycle, cleared to "0" 0 : Bit force to zero A/D Result Data Register ADCR ADCR7 ADCR6 ADCR5 ADCR4 ADCR3 ADCR2 ADCR1 ADCR0 ADDRESS : EBH RESET VALUE : Undefined Figure 18-2 A/D Converter Registers A/D Converter Cautions (1) Input range of AN11 to AN0 ENABLE A/D CONVERTER The input voltages of AN11 to AN0 should be within the specification range. In particular, if a voltage above AVDD or below AVSS is input (even if within the absolute maximum rating range), the conversion value for that channel can not be indeterminate. The conversion values of the other channels may also be affected. A/D INPUT CHANNEL SELECT ANALOG REFERENCE SELECT (2) Noise countermeasures In order to maintain 8-bit resolution, attention must be paid to noise on pins AVDD and AN11 to AN0. Since the effect in- A/D START ( ADST = 1 ) creases in proportion to the output impedance of the analog input source, it is recommended that a capacitor be connected externally as shown in Figure 18-4 in order to reduce noise. NOP Analog Input ADSF = 1 NO AN11~AN0 100~1000pF YES READ ADCR Figure 18-4 Analog Input Pin Connecting Capacitor Figure 18-3 A/D Converter Operation Flow 64 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 (3) Pins AN11/R73 to AN8/R70 and AN7/R67 to AN0/ R60 noise. Therefore, avoid applying pulses to pins adjacent to the pin undergoing A/D conversion. The analog input pins AN11 to AN0 also function as input/ output port (PORT R7 and R6) pins. When A/D conversion is performed with any of pins AN11 to AN0 selected, be sure not to execute a PORT input instruction while conversion is in progress, as this may reduce the conversion resolution. (4) AVDD pin input impedance Also, if digital pulses are applied to a pin adjacent to the pin in the process of A/D conversion, the expected A/D conversion value may not be obtainable due to coupling Nov. 1999 Ver 0.0 A series resistor string of approximately 10K is connected between the AVDD pin and the AVSS pin. Therefore, if the output impedance of the reference voltage source is high, this will result in parallel connection to the series resistor string between the AVDD pin and the AVSS pin, and there will be a large reference voltage error. preliminary 65 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 19. INTERRUPTS The GMS81C2020 and GMS81C2120 interrupt circuits consist of Interrupt enable register (IENH, IENL), Interrupt request flags of IRQH, IRQL, Interrupt Edge Selection Register (IEDS), priority circuit and Master enable flag("I" flag of PSW). The configuration of interrupt circuit is shown in Figure and Interrupt priority is shown in Table 19-1 . The External Interrupts INT0 and INT1 can each be transition-activated (1-to-0, 0-to-1 and both transiton). The flags that actually generate these interrupts are bit INT0IF and INT1IF in Register IRQH. When an external interrupt is generated, the flag that generated it is cleared by the hardware when the service routine is vectored to only if the interrupt was transition-activated. The Timer 0 and Timer 1 Interrupts are generated by T0IF and T1IF, which are set by a match in their respective timer/counter register. The AD converter Interrupt is generated by ADIF which is set by finishing the analog to digital conversion. The Watch dog timer Interrupt is generated by WDTIF which set by a match in Watch dog timer register (when the bit WDTON is set to "0"). The Basic Interval Timer Interrupt is generated by BITIF which is set by a overflowing of the Basic Interval Timer Register(BITR). The Serial Peripheral Interface (SPI) is generated by SPIIF which is set by communicating with other peripheral of microcontroller devices (by finishing the data transmission). Internal bus line IEDS[3:0] IENH[7:4] IRQH External Int. 0 INT0IF External Int. 1 INT1IF Timer 0 T0IF Timer 1 T1IF Interrupt Enable Register (Higher byte) 7 Release STOP 6 5 To CPU 4 I Flag IRQH[7:4] Priority Control IRQL[7:4] ADIF A/D Converter WDT WDTIF BIT BITIF SPI SPIIF IRQL I-flag is in PSW, it is cleared by "DI", set by "EI" instruction.When it goes interrupt service, I-flag is cleared by hardware, thus any other interrupt are inhibited. When interrupt service is completed by "RETI" instruction, I-flag is set to "1" by hardware. Interrupt Master Enable Flag[PSW.2] 7 6 Interrupt Vector Address Generator 5 4 IENL[7:4] Interrupt Enable Register (Lower byte) Internal bus line Figure 19-1 Block Diagram of Interrupt Function 66 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 The interrupts are controlled by the interrupt master enable flag I-flag (bit 2 of PSW), the interrupt enable register (IENH, IENL) and the interrupt request flags (in IRQH, IRQL) except Power-on reset and software BRK interrupt. Interrupt enable registers are shown in Figure 19-2 . These registers are composed of interrupt enable flags of each interrupt source, these flags determines whether an interrupt will be accepted or not. When enable flag is "0", a corresponding interrupt source is prohibited. Note that PSW contains also a master enable bit, I-flag, which disables all interrupts at once. Reset/Interrupt Symbol Priority Vector Addr. Hardware Reset External Interrupt 0 External Interrupt 1 Timer 0 Timer 1 A/D Converter Watch Dog Timer Basic Interval Timer Serial Interface RESET INT0 INT1 Timer 0 Timer 1 A/D C WDT BIT SPI 1 2 3 4 5 6 7 8 FFFEH FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H Table 19-1 Interrupt Priority Interrupt Enable Register High IENH INT0E INT1E T0E T1E - - - - ADDRESS : E2H RESET VALUE : 0000---- SPIE - - - - ADDRESS : E3H RESET VALUE : 0000---- Interrupt Enable Register Low IENL ADE WDTE BITE Enables or disables the interrupt individually If flag is cleared, the interrupt is disabled. 0 : Disable 1 : Enable Interrupt Request Register High IRQH INT0IF INT1IF T0IF T1IF - - - - ADDRESS : E4H RESET VALUE : 0000---- SPIIF - - - - ADDRESS : E5H RESET VALUE : 0000---- Interrupt Request Register Low IRQL ADIF WDTIF BITIF Shows the interrupt occurrence 0 : Not occurred 1 : Interrupt request is occurred Figure 19-2 Interrupt Enable Registers and Interrupt Request Registers When an interrupt is occured, the I-flag is cleared and disable any further interrupt, the return address and PSW are pushed into the stack and the PC is vectored to. Once in the interrupt service routine the source(s) of the interrupt can be determined by polling the interrupt request flag bits. Nov. 1999 Ver 0.0 The interrupt request flag bit(s) must be cleared by software before re-enabling interrupts to avoid recursive interrupts. The Interrupt Request flags are able to be read and written. preliminary 67 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 19.1 Interrupt Sequence An interrupt request is held until the interrupt is accepted or the interrupt latch is cleared to "0" by a reset or an instruction. Interrupt acceptance sequence requires 8 f OSC (2 s at fXI=4MHz) after the completion of the current instruction execution. The interrupt service task is terminated upon execution of an interrupt return instruction [RETI]. Interrupt acceptance 1. The interrupt master enable flag (I-flag) is cleared to "0" to temporarily disable the acceptance of any following maskable interrupts. When a non-maskable interrupt is accepted, the acceptance of any following interrupts is temporarily disabled. 2. Interrupt request flag for the interrupt source accepted is cleared to "0". 3. The contents of the program counter (return address) and the program status word are saved (pushed) onto the stack area. The stack pointer decreases 3 times. 4. The entry address of the interrupt service program is read from the vector table address and the entry address is loaded to the program counter. 5. The instruction stored at the entry address of the interrupt service program is executed. System clock Instruction Fetch SP Address Bus PC Data Bus Not used SP-1 PCH PCL SP-2 PSW V.L. V.L. ADL V.H. ADH New PC OP code Internal Read Internal Write Interrupt Processing Step Interrupt Service Task V.L. and V.H. are vector addresses. ADL and ADH are start addresses of interrupt service routine as vector contents. Figure 19-3 Timing chart of Interrupt Acceptance and Interrupt Return Instruction Basic Interval Timer Vector Table Address 0FFE6H 0FFE7H 012H 0E3H When nested interrupt service is required, the I-flag should be set to "1" by "EI" instruction in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. Entry Address 0E312H 0E313H 0EH 2EH Saving/Restoring General-purpose Register Correspondence between vector table address for BIT interrupt and the entry address of the interrupt service program. A interrupt request is not accepted until the I-flag is set to "1" even if a requested interrupt has higher priority than that of the current interrupt being serviced. 68 During interrupt acceptance processing, the program counter and the program status word are automatically saved on the stack, but accumulator and other registers are not saved itself. These registers are saved by the software if necessary. Also, when multiple interrupt services are nested, it is necessary to avoid using the same data memory area for saving registers. preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 The following method is used to save/restore the generalpurpose registers. General-purpose register save/restore using push and pop instructions; Example: Register save using push and pop instructions INTxx: PUSH PUSH PUSH A X Y main task ;SAVE ACC. ;SAVE X REG. ;SAVE Y REG. acceptance of interrupt interrupt service task saving registers interrupt processing POP POP POP RETI Y X A ;RESTORE Y REG. ;RESTORE X REG. ;RESTORE ACC. ;RETURN restoring registers interrupt return 19.2 BRK Interrupt Software interrupt can be invoked by BRK instruction, which has the lowest priority order. Interrupt vector address of BRK is shared with the vector of TCALL 0 (Refer to Program Memory Section). When BRK interrupt is generated, B-flag of PSW is set to distinguish BRK from TCALL 0. Each processing step is determined by B-flag as shown in Figure 19-4 . B-FLAG BRK or TCALL0 =0 =1 BRK INTERRUPT ROUTINE TCALL0 ROUTINE RETI RET Figure 19-4 Execution of BRK/TCALL0 19.3 Multi Interrupt If two requests of different priority levels are received simultaneously, the request of higher priority level is serviced. If requests of the interrupt are received at the same time simultaneously, an internal polling sequence determines by hardware which request is serviced. Nov. 1999 Ver 0.0 However, multiple processing through software for special features is possible. Generally when an interrupt is accepted, the I-flag is cleared to disable any further interrupt. But as user sets I-flag in interrupt routine, some further interrupt can be serviced even if certain interrupt is in progress. preliminary 69 GMS81C2020/GMS81C2120 Main Program service Hyundai Micro Electro nics Example: Even though Timer1 interrupt is in progress, INT0 interrupt serviced without any suspend. TIMER 1 service enable INT0 disable other INT0 service EI Occur TIMER1 interrupt Occur INT0 TIMER1: PUSH PUSH PUSH LDM LDM EI : : : : : : LDM LDM POP POP POP RETI enable INT0 enable other A X Y IENH,#80H IENL,#0 ;Enable INT0 only ;Disable other ;Enable Interrupt IENH,#0FFH ;Enable all interrupts IENL,#0F0H Y X A In this example, the INT0 interrupt can be serviced without any pending, even TIMER1 is in progress. Because of re-setting the interrupt enable registers IENH,IENL and master enable "EI" in the TIMER1 routine. Figure 19-5 Execution of Multi Interrupt 70 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 19.4 External Interrupt The external interrupt on INT0 and INT1 pins are edge triggered depending on the edge selection register IEDS (address 0E6H) as shown in Figure 19-6 . The edge detection of external interrupt has three transition activated mode: rising edge, falling edge, and both edge. INT0 pin INT0 INTERRUPT INT1IF edge selection INT1 pin INT0IF INT1 INTERRUPT Example: To use as an INT0, INT1 : : ;**** Set port as an input port R00,R01 LDM R0IO,#1111_1100B ; ;**** Set port as an interrupt port LDM R0FUNC,#03H ; ;**** Set Falling-edge Detection LDM IEDS,#0000_0101B : : : Response Time The INT0 and INT1 edge are latched into INT0IF and INT3IF at every machine cycle. The values are not actually polled by the circuitry until the next machine cycle. If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the requested service routine will be the next instruction to be executed. The DIV itself takes twelve cycles. Thus, a minimum of twelve complete machine cycles elapse between activation of an external interrupt request and the beginning of execution of the first instruction of the service routine. IEDS [0E6H] Figure 19-6 External Interrupt Block Diagram ADDRESS : 0E6H RESET VALUE : ----0000 Ext. Interrupt Edge Selection Register W W W W shows interrupt response timings. IEDS INT1 edge select 00: Int. disable 01: falling 10: rising 11: both INT0 edge select 00: Int. disable 01: falling 10: rising 11: both max. 12 fOSC Interrupt Interrupt goes latched active 8 fOSC Interrupt processing Interrupt routine Figure 19-7 Interrupt Response Timing Diagram Nov. 1999 Ver 0.0 preliminary 71 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 20. WATCHDOG TIMER The purpose of the watchdog timer is to detect the malfunction (runaway) of program due to external noise or other causes and return the operation to the normal condition. The watchdog timer has two types of clock source. The first type is an on-chip RC oscillator which does not require any external components. This RC oscillator is separate from the external oscillator of the Xin pin. It means that the watchdog timer will run, even if the clock on the Xin pin of the device has been stopped, for example, by entering the STOP mode. The other type is a prescaled system clock. The watchdog timer consists of 7-bit binary counter and the watchdog timer data register. When the value of 7-bit binary counter is equal to the lower 7 bits of WDTR, the interrupt request flag is generated. This can be used as WDT interrupt or reset the CPU in accordance with the bit WDTON . Note: Because the watchdog timer counter is enabled after clearing Basic Interval Timer, after the bit WDTON set to "1", maximum error of timer is depend on prescaler ratio of Basic Interval Timer. The 7-bit binary counter is cleared by setting WDTCL(bit7 of WDTR) and the WDTCL is cleared automatically after 1 maching cycle. The RC oscillated watchdog timer is activated by setting the bit RCWDT as shown below. : LDM LDM STOP NOP NOP : CKCTLR,#3FH; enable the RC-osc WDT WDTR,#0FFH; set the WDT period ; enter the STOP mode ; RC-osc WDT running The RCWDT oscillation period is vary with temperature, VDD and process variations from part to part (approximately, 40~120uS ). The following equation shows the RCWDT oscillated watchdog timer time-out. T R C W D T = C L K R C W D T x28x[W D T R .6~ 0]+ (C L K R C W D T x28)/2 w here, C L K R C W D T = 40~ 120uS In addition, this watchdog timer can be used as a simple 7bit timer by interrupt WDTIF. The interval of watchdog timer interrupt is decided by Basic Interval Timer. Interval equation is as below. TWDT = [WDTR.6~0] x Interval of BIT Clock Control Register - CKCTLR WAKEUP RCWDT Watchdog Timer Register WDTR 0 WDTCL WAKEUP STOP fXI X /8 / 16 / 32 / 64 / 128 / 256 / 512 /1024 WDTON BTCL BTS2 BTS1 BTS0 1 X X X X ADDRESS : ECH RESET VALUE : -0010111 Bit Manipulation Not Available ADDRESS : EDH RESET VALUE : 01111111 Bit Manipulation Not Available 7-bit Watchdog Counter Register RCWDT WDTCL WDTR (7-bit) BTCL WDTCL MUX WDTON RESET Clear 1 0 BITR (8-BIT) 7-bit Counter To RESET OFD 0 1 Overflow Detection BTS[2:0] BITIF Internal RC OSC Basic Interval Timer Interrupt Watchdog Timer Interrupt Request Figure 20-1 Block Diagram of Watchdog Timer 72 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 21. Power Saving Mode For applications where power consumption is a critical factor, device provides four kinds of power saving functions, STOP mode, Subactive mode and Wake-up Timer Peripheral STOP Mode mode(Standby mode, Watch mode). Table 21-1 shows the status of each Power Saving Mode. Wake-up Timer Mode Subactive Mode Standby Mode Watch Mode RAM Retain Retain Retain Retain Control Registers Retain Retain Retain Retain I/O Ports Retain Retain Retain Retain CPU Stop Operation Stop Stop Timer0 Stop Operation Operation Operation Oscillation Stop Stop Oscillation Stop Sub Oscillation Stop Oscillation Stop Oscillation Prescaler Stop Operation / 2048 only / 2048 only Entering Condition [WAKEUP] 0 0 1 1 Table 21-1 Power Saving Mode The power saving function is activated by execution of STOP instruction and by execution of STOP instruction after setting the corresponding status (WAKEUP) of CKCTLR. Release Source STOP Mode we shows the release sources from each Power Saving Mode Wake-up Timer Mode Subactive Mode Standby Mode Watch Mode RESET O O O O RCWDT O O O O O O O O X X O O EXT.INT EXT.INT1 Timer0 Table 21-2 Release Sources from Power Saving Mode Nov. 1999 Ver 0.0 preliminary 73 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 21.1 Operating Mode SUB-ACTIVE Mode fXI fSXI fSYS fSUB cpu tmr peri SCMR.1 = 1 SCMR.0 = 0/1 : main clock frequency : sub clock frequency : fXI/2,fXI/8,fXI/16,fXI/64 : fSXI/2,fSXI/8,fSXI/16,fSXI/64 : system clock : timer0 clock : peripheral clock fXI : stop fSXI : oscillation cpu : fSUB tmr : fSUB peri : fSUB CKCTLR[10] + STOP CKCTLR = CKCTLR[6:5] SCMR.0 = 0 + SCMR.1 = 0 STANDBY Mode CKCTLR[10] + STOP SCMR.1 = 0 fXI : oscillation fSXI : oscillation cpu : stop tmr : ps11(fXI) peri : stop TIMER0 EXT_INT RESET RC_WDT TIMER0 EXT_INT RESET RC_WDT SCMR.1 = 1 ACTIVE Mode WATCH Mode SCMR.1 = 0 fXI : oscillation fSXI : oscillation cpu : fSYS tmr : fSYS peri : fSYS SCMR.1 = 1 fXI : stop fSXI : oscillation cpu : stop tmr : ps11(fSXI) peri : stop CKCTLR[00] + STOP EXT_INT RESET RC_WDT STOP Mode SCMR.2 = 1 (SUB_CLK OFF) CKCTLR[00] + STOP EXT_INT RESET RC_WDT fXI : stop fSXI : stop cpu : stop tmr : stop peri : stop System Clock Mode Register SCMR CS[1:0] - - - CS1 CS0 SUBOFF CLKSEL MAINOFF Clock selection enable bits 00 : fXI / 210 : fXI /16 CLKSEL Clock selection bit 0 : Main clock selection 1 : Sub clock selection Sub clock control bit 0: On sub clock 1: Off sub clock MAINOFF Main clock control bit 0: On main clock 1: Off main clock 01 : fXI / 811 : fXI / 64 SUBOFF 74 ADDRESS : FAH RESET VALUE : ---00000 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 21.2 Stop Mode In the Stop mode, the on-chip oscillator is stopped. With the clock frozen, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. Oscillator stops and the systems internal operations are all held up. Release the STOP mode The exit from STOP mode is hardware reset or external interrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. * The states of the RAM, registers, and latches valid immediately before the system is put in the STOP state are all held. If I-flag = 1, the normal interrupt response takes place. If Iflag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine. ( refer to Figure 21-1 ) * The program counter stop the address of the instruction to be executed after the instruction "STOP" which starts the STOP operating mode. The Stop mode is activated by execution of STOP instruction after clearing the bit WAKEUP of CKCTLR to "0". ( This register should be written by byte opereation. If this register is set by bit manipulation instrunction, for example "set1" or "clr1" instruction, it may be undesired operation ) In the Stop mode of operation, VDD can be reduced to minimize power consumption. Care must be taken, however, to ensure that VDD is not reduced before the Stop mode is invoked, and that VDD is restored to its normal operating level, before the Stop mode is terminated. When exit from Stop mode by external interrupt, enough oscillation stabilization time is required to normal operation. Figure 21-4 shows the timing diagram. When release the Stop mode, the Basic interval timer is activated on wake-up. It is increased from 00H until FFH . The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from Stop mode is shown in Figure 21-5 . STOP INSTRUCTION The reset should not be activated before VDD is restored to its normal operating level, and must be held active long enough to allow the oscillator to restart and stabilize. STOP Mode Interrupt Request Note: After STOP instruction, at least two or more NOP instruction should be written Ex) LDM CKCTLR,#0000_1110B STOP NOP NOP In the STOP operation, the dissipation of the power associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level gets higher than the power voltage level (by approximately 0.3 to 0.5V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring to fix the level by pull-up or other means. Nov. 1999 Ver 0.0 preliminary Corresponding Interrupt Enable Bit (IENH, IENL) IEXX =0 =1 STOP Mode Release Master Interrupt Enable Bit PSW[2] I-FLAG =0 =1 Interrupt Service Routine Next INSTRUCTION Figure 21-1 STOP Releasing Flow by Interrupts 75 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics by pull-up or other means. Minimizing Current Consumption The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. Note: In the STOP operation, the power dissipation associated with the oscillator and the internal hardware is lowered; however, the power dissipation associated with the pin interface (depending on the external circuitry and program) is not directly determined by the hardware operation of the STOP feature. This point should be little current flows when the input level is stable at the power voltage level (VDD/VSS); however, when the input level becomes higher than the power voltage level (by approximately 0.3V), a current begins to flow. Therefore, if cutting off the output transistor at an I/O port puts the pin signal into the high-impedance state, a current flow across the ports input transistor, requiring it to fix the level It should be set properly that current flow through port doesn't exist. First conseider the setting to input mode. Be sure that there is no current flow after considering its relationship with external circuit. In input mode, the pin impedance viewing from external MCU is very high that the current doesn't flow. But input voltage level should be VSS or VDD. Be careful that if unspecified voltage, i.e. if unfirmed voltage level (not VSSor VDD) is applied to input pin, there can be little current (max. 1mA at around 2V) flow. If it is not appropriate to set as an input mode, then set to output mode considering there is no current flow. Setting to High or Low is decided considering its relationship with external circuit. For example, if there is external pull-up resistor then it is set to output mode, i.e. to High, and if there is external pull-down register, it is set to low. VDD INPUT PIN INPUT PIN VDD VDD internal pull-up VDD i=0 O OPEN O i i GND X Weak pull-up current flows Very weak current flows VDD X GND O OPEN O i=0 When port is configured as an input, input level should be closed to 0V or 5V to avoid power consumption. * Pull-up is Metal Option Figure 21-2 Application Example of Unused Input Port 76 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 OUTPUT PIN OUTPUT PIN VDD ON OPEN OFF ON OFF O OFF OFF GND ON OFF i=0 ON i VDD X L ON i GND VDD L GND X O In the left case, Tr. base current flows from port to GND. To avoid power consumption, there should be low output to the port . O In the left case, much current flows from port to GND. Figure 21-3 Application Example of Unused Input Port Minimizing Current Consumption in Stop Mode VSS or at VDD (or as close to rail as possible). The Stop mode is designed to reduce power consumption. To minimize current drawn during Stop mode, the user should turn-off output drivers that are sourcing or sinking current, if it is practical. Weak pull-ups on port pins should be turned off, if possible. All inputs should be either as An intermediate voltage on an input pin causes the input buffer to draw a significant amount of current. ~ ~ ~ ~ ~ ~ ~ ~ Oscillator (XI pin) ~ ~ Internal Clock ~ ~ External Interrupt ~ ~ STOP Instruction Execution ~ ~ N-2 N-1 N N+1 N+2 00 01 FE FF 00 00 ~ ~ BIT Counter Clear Basic Interval Timer Normal Operation STOP Mode Stabilization Time tST > 20mS Normal Operation Figure 21-4 Timing of STOP Mode Release by External Interrupt Nov. 1999 Ver 0.0 preliminary 77 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics STOP Mode ~ ~ ~~ ~ ~ ~ ~ Oscillator (XI pin) ~ ~ ~ ~ ~ ~ Internal Clock RESETB ~ ~ Internal RESETB ~ ~ STOP Instruction Execution Time can not be control by software Stabilization Time tST = 64mS @4MHz Figure 21-5 Timing of STOP Mode Release by RESET 21.3 Wake-up Timer Mode In the Wake-up Timer mode, the on-chip oscillator is not stopped. Except the Prescaler( only 2048 devided ratio ) and Timer0, all functions are stopped, but the on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. The Wake-up Timer mode is activated by execution of STOP instruction after setting the bit WAKEUP of CKCTLR to "1". ( This register should be written by byte opereation. If this register is set by bit manipulation instrunction, for example "set1" or "clr1" instruction, it may be undesired operation ) Note: After STOP instruction, at least two or more NOP instruction should be written Ex) LDM TDR0,#0FFH LDM TM0,#0001_1011B LDM CKCTLR,#0100_1110B STOP NOP NOP If I-flag = 1, the normal interrupt response takes place. If Iflag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.( refer to Figure 21-1 ) When exit from Wake-up Timer mode by external interrupt or timer0 overflow, the oscillation stabilization time is not required to normal operation. Because this mode do not stop the on-chip oscillator shown as Figure 21-6 . ~ ~ ~ ~ CPU Clock STOP Instruction Execution ~ ~ Normal Operation 78 Release the Wake-up Timer mode The exit from Wake-up Timer mode is hardware reset, Timer0 overflow or external interrupt. Reset re-defines all the Control registers but does not change the on-chip RAM. External interrupts and Timer0 overflow allow both on-chip RAM and Control registers to retain their values. ~ ~ Oscillator (XI pin) Interrupt Request In addition, the clock source of timer0 should be selected to 2048 devided ratio. Otherwise, the wake-up function can not work. And the timer0 can be operated as 16-bit timer with timer1. ( refer to timer function )The period of wake-up function is varied by setting the timer data register 0, TDR0. Wake-up Timer Mode ( stop the CPU clock ) preliminary Normal Operation Do not need Stabilization Time Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 Figure 21-6 Wake-up Timer Mode Releasing by External Interrupt or Timer0 Interrupt 21.4 Internal RC-Oscillated Watchdog Timer Mode In the Internal RC-Oscillated Watchdog Timer mode, the on-chip oscillator is stopped. But internal RC oscillation circuit is oscillated in this mode. The on-chip RAM and Control registers are held. The port pins out the values held by their respective port data register, port direction registers. The Internal RC-Oscillated Watchdog Timer mode is activated by execution of STOP instruction after setting the bit WAKEUP and RCWDT of CKCTLR to " 01 ". ( This register should be written by byte opereation. If this register is set by bit manipulation instruction, for example "set1" or "clr1" instruction, it may be undesired operation ) Note: Caution : After STOP instruction, at least two or more NOP instruction should be written Ex) LDM WDTR,#1111_1111B LDM CKCTLR,#0010_1110B STOP NOP NOP The exit from Internal RC-Oscillated Watchdog Timer mode is hardware reset or external interrupt. Reset re-defines all the Control registers but does not change the onchip RAM. External interrupts allow both on-chip RAM and Control registers to retain their values. If I-flag = 1, the normal interrupt response takes place. In this case, if the bit WDTON of CKCTLR is set to "0" and the bit WDTE of IENH is set to "1", the device will execute the watchdog timer interrupt service routine.(Figure 21-7 ) However, if the bit WDTON of CKCTLR is set to "1", the device will generate the internal RESET signal and execute the reset processing. (Figure 21-8 ) If I-flag = 0, the chip will resume execution starting with the instruction following the STOP instruction. It will not vector to interrupt service routine.( refer to Figure 21-1 ) When exit from Internal RC-Oscillated Watchdog Timer mode by external interrupt, the oscillation stabilization time is required to normal operation. Figure 21-7 shows the timing diagram. When release the Internal RC-Oscillated Watchdog Timer mode, the basic interval timer is activated on wake-up. It is increased from 00H until FFH . The count overflow is set to start normal operation. Therefore, before STOP instruction, user must be set its relevant prescaler divide ratio to have long enough time (more than 20msec). This guarantees that oscillator has started and stabilized. By reset, exit from internal RC-Oscillated Watchdog Timer mode is shown in Figure 21-8 . ~ ~ ~ ~ ~ ~ Oscillator (XI pin) Internal RC Clock ~ ~ ~ ~ Internal Clock ~ ~ External Interrupt ( or WDT Interrupt ) ~ ~ STOP Instruction Execution ~ ~ N-2 N-1 N N+1 N+2 00 01 FE FF 00 00 ~ ~ BIT Counter Clear Basic Interval Timer Normal Operation RCWDT Mode Stabilization Time tST > 20mS Normal Operation Figure 21-7 Internal RCWDT Mode Releasing by External Interrupt or WDT Interrupt Nov. 1999 Ver 0.0 preliminary 79 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics RCWDT Mode ~ ~ ~ ~ ~ ~ Oscillator (XI pin) Internal RC Clock ~ ~ ~ ~ ~ ~ RESET ~ ~ Internal Clock RESET by WDT ~ ~ STOP Instruction Execution Time can not be control by software ~ ~ Internal RESET Stabilization Time tST = 64mS @4MHz Figure 21-8 Internal RCWDT Mode Releasing by RESET 80 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 22. RESET The reset input is the RESET pin, which is the input to a Schmitt Trigger. A reset in accomplished by holding the RESET pin low for at least 8 oscillator periods, while the oscillator running. After reset, 64ms (at 4 MHz) add with 7 oscillator periods are required to start execution as shown in Figure 26-2 . Internal RAM is not affected by reset. When VDD is turned on, the RAM content is indeterminate. Therefore, this RAM should be initialized before reading or testing it. Initial state of each register is shown as Table 11-3 . 1 ? ? 4 5 6 7 ~ ~ ? ? FFFE FFFF Start ~ ~ ~ ~ ? ? ? ? FE ADL ADH OP ~ ~ DATA BUS 3 ~ ~ RESET ADDRESS BUS 2 ~ ~ Oscillator (XI pin) MAIN PROGRAM Stabilization Time tST = 64mS at 4MHz RESET Process Step Figure 22-1 Timing Diagram after RESET Nov. 1999 Ver 0.0 preliminary 81 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 23. POWER FAIL PROCESSOR The GMS81C2020 and GMS81C2120 has an on-chip power fail detection circuitry to immunize against power noise. A configuration register, PFDR, can enable (if clear/ programmed) or disable (if set) the Power-fail Detect circuitry. If VDD falls below 2.4~3.0V range for longer than 50 nS, the Power fail situation may reset MCU according to PFDM bit of PFDR. cuit emulator, user can not experiment with it. Therefore, after final development of user program, this function may be experimented. Note: Power fail processor function is not available on 3V operation, because this function will detect power fail all the time. As below PFDR register is not implemented on the in-cir- Power Fail Detector Register PFDR - - - - PFDIS PFDM ADDRESS : EFH RESET VALUE : -----100 PFS Reserved Power Fail Status 0 : Normal Operate 1 : This bit force to "1" when Power fail was detected Operation Mode 0 : Normal operation regardless of power fail 1 : MCU will be reset during power fail Disable Flag 0 : Power fail detection enable 1 : Power fail detection disable Figure 23-1 Power Fail Detector Register RESET VECTOR PFS =1 YES NO RAM CLEAR INITIALIZE RAM DATA Skip the initial routine INITIALIZE ALL PORTS INITIALIZE REGISTERS FUNTION EXECUTION Figure 23-2 Example S/W of RESET by Power fail 82 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 VDD PFVDDMAX PFVDDMIN 64mS Internal RESET VDD When PFDM = 1 Internal RESET 64mS PFVDDMAX PFVDDMIN t < 64mS VDD PFVDDMAX PFVDDMIN 64mS Internal RESET Figure 23-3 Power Fail Processor Situations Nov. 1999 Ver 0.0 preliminary 83 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 24. OTP PROGRAMMING 24.1 DEVICE CONFIGURATION AREA The Device Configuration Area can be programmed or left unprogrammed to select device configuration such as security bit. sixteen memory locations ( 7030H ~ 703FH ) are designat- ed as Customer ID recording locations where the user can store check-sum or other customer identification numbers. This area is not accessible during normal execution but is readable and writable during program / verify. 7030H ID 7030H ID 7031H ID 7032H ID 7033H ID 7034H ID 7035H ID 7036H ID 7037H ID 7038H ID 7039H ID 703AH ID 703BH ID 703CH ID 703DH ID 703EH CONFIG 703FH DEVICE CONFIGURATION AREA 703FH Configuration Register CONFIG - SXB / R7 PFD1 PFD0 - CODE PROTECT - ADDRESS :703FH EXTERNAL RCOSC 0 : Crystal Oscillator 1 : External RC Oscillator PFD LEVEL SELECTION 0 0 : PFD1 = 2.7V 0 1 : PFD1 = 2.7V 1 0 : PFD2 = 3.0V 1 1 : PFD3 = 2.4V SXB / R7 0 : SUB CLOCK 1 : R74, R75 EXTERNAL RCOSC CODE PROTECT 0 : ALLOW CODE READ OUT 1 : LOCK CODE READ OUT Figure 24-1 Device Configuration Area 84 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics 64SDIP CTL3 CTL2 CTL1 CTL0 VPP EPROM Enable VSS A_D0 A_D1 A_D2 A_D3 A_D4 A_D5 A_D6 A_D7 GMS81C2020/GMS81C2120 R40 R41 R42 R43 R50 R51 R52 R53 R54 R55 R56 R57 RESETB XI XO VSS SXI SXO AVSS R60 R61 R62 R63 R64 R65 R66 R67 R70 R71 R72 R73 AVDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RA/Vdisp R35 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R17 R16 R15 R14 R13 R12 R11 R10 R07 R06 R05 R04 R03 R02 R01 R00 VDD VDD Figure 24-2 Pin Assignmen (64SDIP)t User Mode EPROM MODE Pin No. Pin Name Pin Name Description 8 R53 CTL3 Read/Write Control P_Vb 9 R54 CTL2 Address/Data Control D_Ab 10 R55 CTL1 Write 8Bytes Control PGM8 11 R56 CTL0 Write 4Bytes Control PGM4 13 RESETB VPP Programming Power (0V, 12.75V) 14 XI EPROM Enable High Active, Latch Address in falling edge 15 XO NC No connection 16 VSS VSS Connect to VSS (0V) 20 R60 A_D0 21 R61 A_D1 22 R62 A_D2 23 R63 A_D3 A11 A3 D3 24 R64 A_D4 A12 A4 D4 25 R65 A_D5 A13 A5 D5 26 R66 A_D6 A14 A6 D6 27 R67 A_D7 A15 A7 D7 33 VDD VDD Address Input Data Input/Output Address Input Data Input/Output A8 A0 D0 A9 A1 D1 A10 A2 D2 Connect to VDD (6.0V) Table 24-1 Pin Description in EPROM Mode (GMS81C2020) Nov. 1999 Ver 0.0 preliminary 85 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics 42PDIP RA R53 R54 R55 R56 R57 RESETB XI XO VSS AVSS R60 R61 R62 R63 R64 R65 R66 R67 AVDD VDD CTL3 CTL2 CTL1 CTL0 VPP EPROM Enable VSS A_D0 A_D1 A_D2 A_D3 A_D4 A_D5 A_D6 A_D7 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 R34 R33 R32 R31 R30 R27 R26 R25 R24 R23 R22 R21 R20 R07 R06 R05 R04 R03 R02 R01 R00 Figure 24-3 Pin Assignmen (42SDIP)t User Mode EPROM MODE Pin No. Pin Name Pin Name Description 2 R53 CTL3 Read/Write Control P_Vb 3 R54 CTL2 Address/Data Control D_Ab 4 R55 CTL1 Write 8Bytes Control PGM8 5 R56 CTL0 Write 4Bytes Control PGM4 7 RESETB VPP Programming Power (0V, 12.75V) 8 XI EPROM Enable High Active, Latch Address in falling edge 9 XO NC No connection Connect to VSS (0V) 10 VSS VSS 12 R60 A_D0 13 R61 A_D1 14 R62 A_D2 15 R63 A_D3 A11 A3 D3 16 R64 A_D4 A12 A4 D4 17 R65 A_D5 A13 A5 D5 18 R66 A_D6 A14 A6 D6 19 R67 A_D7 A15 A7 D7 21 VDD VDD Address Input Data Input/Output Address Input Data Input/Output A8 A0 D0 A9 A1 D1 A10 A2 D2 Connect to VDD (6.0V) Table 24-2 Pin Description in EPROM Mode (GMS81C2120) 86 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics TSET1 GMS81C2020/GMS81C2120 THLD1 TDLY1 THLD2 TDLY2 ~ ~ VIHP ~ ~ TVPPS ~ ~ ~ ~ EPROM Enable VPP TVDDS CTL3 0V VDD1H TCD1 TCD1 HA LA DATA IN LA DATA IN ~ ~ ~~ DATA OUT ~ ~ ~ ~ A_D7~ A_D0 TCD1 ~ ~ 0V VDD1H TCD1 ~ ~ CTL2 ~ ~ ~ ~ 0V ~ ~ ~ ~ CTL0/1 TVPPR DATA OUT VDD1H VDD High 8bit Address Input Low 8bit Address Input Write Mode Verify Low 8bit Address Input Write Mode Verify Figure 24-4 Timing Diagram in Program (Write & Verify) Mode Nov. 1999 Ver 0.0 preliminary 87 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics After input a high address, output data following low address input TSET1 THLD1 TDLY1 THLD2 Anothe high address step TDLY2 EPROM Enable TVPPS VIHP VPP TVDDS CTL0/1 0V TVPPR VDD2H CTL2 0V CTL3 0V TCD2 VDD2H TCD1 A_D7~ A_D0 TCD2 TCD1 HA LA DATA LA DATA HA LA DATA High 8bit Address Input Low 8bit Address Input DATA Output Low 8bit Address Input DATA Output High 8bit Address Input Low 8bit Address Input DATA Output VDD2H VDD Figure 24-5 Timing Diagram in READ Mode Parameter Symbol MIN TYP MAX Unit Programming Supply Current IVPP - - 50 mA Supply Current in EPROM Mode IVDDP - - 20 mA VPP Level during Programming VIHP 11.5 12.0 12.5 V VDD Level in Program Mode VDD1H 5 6 6.5 V VDD Level in Read Mode VDD2H - 2.7 - V CTL3~0 High Level in EPROM Mode VIHC 0.8VDD - - V CTL3~0 Low Level in EPROM Mode VILC - - 0.2VDD V A_D7~A_D0 High Level in EPROM Mode VIHAD 0.9VDD - - V A_D7~A_D0 Low Level in EPROM Mode VILAD - - 0.1VDD V VDD Saturation Time TVDDS 1 - - mS VPP Setup Time TVPPR - - 1 mS VPP Saturation Time TVPPS 1 - - mS EPROM Enable Setup Time after Data Input TSET1 200 nS EPROM Enable Hold Time after TSET1 THLD1 500 nS Table 24-3 AC/DC Requirements for Program/Read Mode 88 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 EPROM Enable Delay Time after THLD1 TDLY1 200 nS EPROM Enable Hold Time in Write Mode THLD2 100 nS EPROM Enable Delay Time after THLD2 TDLY2 200 nS CTL2,1 Setup Time after Low Address input and Data input TCD1 100 nS CTL1 Setup Time before Data output in Read and Verify Mode TCD2 100 nS Table 24-3 AC/DC Requirements for Program/Read Mode START Set VDD=VDD1H Report Programming failure Set VPP=VIHP Verify OK NO Verify blank Report Verify failure Verify fof all address NO YES YES Report Programming OK First Address Location Next address location VDD=VPP=0v Report Programming failure N=1 NO END YES EPROM Write 100uS program time Verify pass NO Verify pass YES Apply 3N program cycle NO Last address YES Figure 24-6 Programming Flow Chart Nov. 1999 Ver 0.0 preliminary 89 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics START Set VDD=VDD2H Verify fof all address Set VPP=VIHP First Address Location Next address location NO Last address YES Report Read OK VDD=0V VPP=0V END 90 preliminary Nov. 1999 Ver 0.0 Hyundai Micro Electronics GMS81C2020/GMS81C2120 GMS81C2 Series [GMS81C2020/12] Option List Package 64SDIP 64LQFP 64MQFP 64TQFP Date of Order 1999 / 2000. . . Customer Department RA / Vdisp Name ROM Code Name RA Without pull-down resistance Check sum Vdisp 20KBytes ROM Size 12KBytes *Note : In the I/O options list, you must select Vdisp even if only one pin is selected with pull-down resistance. ROM Code Option List : 703FH Bit7 Bit6 Bit5 Bit4 Bit3 - SXB / R7 PFD1 PFD0 - 0 0 1 0 1 0 1 1 0 1 Bit2 Bit1 Bit0 - LOW VOLTAGE RCOSC 0 1 0 1 0 1 * Refer to Device Configuration Area I/O Option [VFD Driving Port] Bit Bit I/O I/O Option On I/O I/O Option On Off Bit I/O I/O Option On Off Bit I/O I/O Option On Off Off R00/INT0 I/O R10 I/O R20 I/O R30 I/O R01/INT1 I/O R11 I/O R21 I/O R31 I/O R02/EC0 I/O R12 I/O R22 I/O R32 I/O R03/BUZO I/O R13 I/O R23 I/O R33 I/O I/O R24 I/O R34 I/O R35 I/O Bit I/O I/O Option R04 I/O R14 R05 I/O R15 I/O R25 I/O R06 I/O R16 I/O R26 I/O R07 I/O R17 I/O R27 I/O Bit I/O I/O Option Bit I/O I/O Option * On : with pull-down resistance * Off : without pull-down resistance I/O Option [Normal Port] Bit I/O I/O Option On R40/T0O I/O R41 I/O R42 I/O R43 I/O Off On Off On On Off R70/AN8 I/O R50 I/O R60/AN0 I/O R51 I/O R61/AN1 I/O R71/AN9 I/O I/O R62/AN2 I/O R72/AN10 I/O R53/SCLK I/O R63/AN3 I/O R73/AN11 I/O R52 R64/AN4 I/O R74 I/O R55/SOUT I/O R65/AN5 I/O R75 I/O R56/PWM1OI/O R66/AN6 I/O R54/SIN R57 I/O I/O Off R67/AN7 I/O * On : with pull-up * Off : without pull-up Nov. 1999 Ver 0.0 preliminary 91 GMS81C2020/GMS81C2120 Hyundai Micro Electro nics GMS81C2 Series [GMS81C2120/12] Option List Package 42SDIP Date of Order 44MQFP 1999 / 2000. . . Customer 40PDIP Department RA / Vdisp Name ROM Code Name RA Without pull-down resistance Check sum Vdisp 20KBytes ROM Size 12KBytes *Note : In the I/O options list, you must select Vdisp even if only one pin is selected with pull-down resistance. ROM Code Option List : 703FH Bit7 Bit6 Bit5 Bit4 Bit3 - - PFD1 PFD0 - 0 1 0 0 1 1 0 1 0 Bit2 0 1 Bit1 Bit0 LOW VOLTAGE RCOSC 0 1 1 0 1 * Refer to Device Configuration Area I/O Option [VFD Driving Port] Bit I/O I/O Option On Bit I/O I/O Option On Off Bit I/O I/O Option On Off R00/INT0 I/O R20 I/O R30 I/O R01/INT1 I/O R21 I/O R31 I/O R02/EC0 I/O R22 I/O R32 I/O R03/BUZO I/O R23 I/O R33 I/O R34 I/O R04 I/O R24 I/O R05 I/O R25 I/O R06 I/O R26 I/O R07 I/O R27 I/O Bit I/O I/O Option Off * On : with pull-down resistance * Off : without pull-down resistance I/O Option [Normal Port] Bit I/O I/O Option On R53/SCLK I/O R54/SIN Off On I/O R61/AN1 I/O R55/SOUT I/O R62/AN2 I/O R56/PWM1OI/O R63/AN3 I/O R57 I/O Off R60/AN0 I/O R64/AN4 I/O R65/AN5 I/O * On : with pull-up * Off : without pull-up 92 R66/AN6 I/O R67/AN7 I/O preliminary Nov. 1999 Ver 0.0