SP802LCN-L/TR - Sipex Corporation

SP690A/692A/802L/

802M/805L/805M

Low Power Microprocessor Supervisory

with Battery Switch-Over

The SP690A/692A/802L/802M/805L/805M are a family of microprocessor (µP) supervisory

circuits that integrate a myriad of components involved in discrete solutions to monitor power-

supply and battery-control functions in µP and digital systems. The series will significantly

improve system reliability and operational efficiency when compared to discrete solutions.

The features of the SP690A/692A/802L/802M/805L/805M include a watchdog timer, a µP

reset and backup-battery switchover, and power-failure warning, a complete µP monitoring

and watchdog solution. The series is ideal for applications in automotive systems, computers,

controllers, and intelligent instruments. All designs where it is critical to monitor the power

supply to the µP and it’s related digital components will find the series to be an ideal solution.

FEATURES

■ Precision Voltage Monitor:

SP690A/SP802L/SP805L at 4.65V

SP692A/SP802M/SP805M at 4.40V

■ Reset Time Delay - 200ms

■ Watchdog Timer - 1.6 sec timeout

■ Minimum component count

■ 60µA Maximum Operating Supply Current

■ 0.6µA Maximum Battery Backup Current

■ 0.1µA Maximum Battery Standby Current

■ Power Switching

250mA Output in VCC Mode (0.6Ω)

25mA Output in Battery Mode (5Ω)

■ Voltage Monitor for Power Fail or

Low Battery Warning

■ Available in 8 pin SO and DIP packages

■ RESET asserted down to VCC = 1V

DESCRIPTION

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8 PIN NSOIC

VOUT

VCC

GND

PFI

VBATT

RESET (RESET)*

WDI

PFO

*SP805 only

Now Available in Lead Free Packaging

■ Pin Compatible Upgrades to

MAX690A/692A/802L/802M/805L

APPLICATIONS

■ Critical µP Power Monitoring

■ Intellegent Instruments

■ Computers

■ Controllers

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation

of the device at these ratings or any other above those

indicated in the operation sections of the specifica-

tions below is not implied. Exposure to absolute maxi-

mum rating conditions for extended periods of time

may affect reliability and cause permanent damage to

the device.

VCC........................................................-0.3V to 6.0V

VBATT.....................................................-0.3V to 6.0V

All Other Inputs (NOTE 1)..................-0.3V to (VCC to 0.3V)

Input Current:

VCC.........................................................250mA

VBATT........................................................50mA

GND........................................................20mA

Output Current:

VOUT.....Short-Circuit Protected for up to 10sec

All Other Inputs.................................20mA

Rate of Rise, VCC,VBATT..................100V/µs

Continuous Power Dissipation.......500mW

Storage Temperature.......-65°C to +160°C

Lead Temperature(soldering,10sec).................+300°C

ESD Rating.............................................................4KV

ELECTRICAL CHARACTERISTICS

Vcc=4.75v to 5.50V for SP690A/SP802L/SP805L, VCC=4.50V to 5.50V for SP692A/SP802M/SP805M, VBATT=2.80V, TA=TMIN to TMAX, typical specified at 25OC,

unless otherwise noted.

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NOTE 1: The input voltage limits on PFI (pin 4) and WDI (pin 6) may be exceeded if the current into

these pins is limited to less than 10 mA.

NOTE 2: Either VCC or VBATT can go to 0V if the other is greater than 2.0V.

NOTE 3: "-" equals the battery-charging current, "+" equals the battery-discharging current.

NOTE 4: WDI is guaranteed to be in an intermediate, non-logic level state if WDI is floating and VCC

is in the operating voltage range. WDI is internally biased to 35% of VCC with an input impedance of

50KΩ.

NOTE 5: SP690A, SP692A, SP802L, and SP802M only.

NOTE 6: SP805L and SP805M only.

NOTE 7: WDI Minimum Rise/Fall time is 2µs.

ELECTRICAL CHARACTERISTICS

Vcc=4.75v to 5.50V for SP690A/SP802L/SP805L, VCC=4.50V to 5.50V for SP692A/SP802M/SP805M, VBATT=2.80V, TA=TMIN to TMAX, typical specified at 25OC,

unless otherwise noted.

NOTE 7

PIN ASSIGNMENTS

Pin 1 —VOUT — Output Supply Voltage. VOUT

connects to VCC when VCC is greater than

VBATT and VCC is above the reset thresh-

old. When VCC falls below VBATT and

VCC is below the reset threshold, VOUT

connects to VBATT. Connect a 0.1µF

capacitor from VOUT to GND.

Pin 2 — VCC — +5V Supply Input

Pin3 — GND — Ground reference for all signals

Pin 4 — PFI — Power-Fail Input. This is the

noninverting input to the power-fail com-

parator. When PFI is less than 1.25V,

PFO goes low. Connect PFI to GND or

VOUT when not used.

Pin 5 — PFO — Power-Fail Output.

Pin 6 — WDI — Watchdog Input. WDI is a

three level input. If WDI remains high or

low for 1.6sec, the internal watchdog timer

triggers a reset. If WDI is left floating or

connected to a high-impedance tri-state

buffer, the watchdog feature is disabled.

The internal watchdog timer clears when-

ever reset is asserted.

Pin 7 for SP690A/692A/802 only — RESET

(Active Low)– Reset Output. RESET Out-

put goes low whenever VCC falls below

the reset threshold or whenever WDI

remains high or low longer than 1.6

seconds. RESET remains low for 200ms

after VCC crosses the reset threshold

voltage on power-up or after being trig-

gered by WDI.

Pin 7 for SP805 only — RESET (Active High)–

Reset Output is the inverse of RESET;

when RESET is asserted, the RESET

output voltage = VCC or VBATT ,

whichever is higher.

Pin 8 — VBATT — Backup-Battery Input. When

VCC falls below the reset threshold, VBATT

will be switched to VOUT if VBATT is

20mV greater than VCC. When VCC rises

20mV above VBATT, VOUT will be

reconnected to VCC. The 40mV

hysteresis prevents repeated switching if

VCC falls slowly.

Figure 10. Pinout

Figure 11. Internal Block Diagram

OUT

GND

PFI

BATT

RESET (RESET)*

WDI

PFO

*( ) SP805 only

1.25V

0.8V

3.5V

1.25V

BATTERY-SWITCHOVER

CIRCUITRY

PFI

WDI

VCC

VBATT

RESET

GENERATOR

VOUT

RESET

(RESET)*

PFO

WATCHDOG

TIMER

*( ) SP805 only

VCC Supply Current vs.

Temperature (Normal Mode) Battery Supply Current vs.

Temperature (Backup Mode)

-60 -30 0 30 60 90 120 150

Current (µA)

Temperature Deg. C

2.9

2.4

1.9

1.4

0.9

0.4

-0.1

BATT

Current (µA)

-60 Temperature Deg. C

-40 -20 0 20 40 60 80 100120140

VCC=5V

VBATT=2.8V VCC=0V

VBATT=2.8V

TYPICAL PERFORMANCE CHARACTERISTICS

-60 -30 0 30 6 0 90 120 150

Temperature Deg. C

PFI Threshold

vs. Temperature

1.256

1.254

1.252

1.250

1.248

1.246

PFI Threshold (V)

VCC=5V

VBATT=0

NO LOAD ON PFO

VBATT to VOUT ON

Resistance vs. Temperature VCC to VOUT On

Resistance vs. Temperature

Resistance (ohms)

-60 -30 0 30 60 90 120 150

Temperature Deg. C

0.9

0.8

0.7

0.6

0.5

0.4

0.3

Resistance (ohms)

Temperature Deg. C

VBATT=2.8V

VBATT=4.5V

VCC=0V VBATT=2V

Reset Threshold

vs. Temperature

4.70

4.69

4.68

4.67

4.66

4.65

4.64

4.63

4.62

4.61

4.60

Reset Threshold (V)

Temperature Deg. C

VBATT=0V

Power Down

VCC=5V

VBATT=0V

Reset Output Resistance

vs. Temperature Reset Delay

vs. Temperature

600

500

400

300

200

100

Resistance (ohms)

-60 -30 0 30 60 90 120 150

Temperature Deg. C

212

210

208

206

204

202

200

Reset Delay (mS)

-60 -30 0 30 60 90 120 150

Temperature Deg. C

VCC=5V,VBATT=2.8V

Soucing Current VCC=0V to 5V Step,

VBATT=2.8V

VCC=0V,VBATT=2.8V

Sink Current

IE+2

IE+1

IE+0

IE-1

IE-2

IE-3

IE-4

IE-5

IE-6

IE-7

IE-8

BATT

Current(µA) Log Scale

.0000 5.000

VCC (0.5V/div)

Battery Current vs. VCC Voltage

VBATT=2.8V

SP690A

-60 -30 0 30 60 90 120 150 -60 -30 0 30 60 90 120 150

(25oC, unless otherwise noted)

Figure 1. VCC to VOUT Vs. Output Current

Figure 3A. SP690A RESET Output Voltage vs.

Supply Voltage

Figure 2. VBATT to VOUT Vs. Output Current

Figure 3B. Circuit for the SP690A/802L RESET

Output Voltage vs. Supply Voltage

GND

RESET

330pF

2KΩ

RESET

BATT

= 0V

= +25 C

Voltage Drop(mV)

1 10 100 1000

IOUT (mA)

VCC=4.5V

VBATT=0V

Slope=0.6Ω

Voltage Drop(mV)

1 10 100

IOUT (mA)

VBATT=4.5V

VCC=0V

Slope=5Ω

Figure 4A. SP805L RESET Output Voltage vs.

Supply Voltage Figure 4B. Circuit for the SP805 RESET Output

Voltage vs. Supply Voltage

GND

RESET

330pF

10KΩ

BATT

1000

100

1000

100

RESET

BATT

= 0V

= 25 C

div

RESET

div

1sec/div

Figure 5A. SP690A RESET Response Time Figure 5B. Circuit for the SP690A/802L RESET

Response Time

GND

RESET

VCC

30pF

VCC

10KΩ

TA = +25 C

Figure 6A. SP805L RESET Response Time Figure 6B. Circuit for the SP805 RESET

Response Time

GND

RESET

330pF

10KΩ

BATT

Figure 7B. Circuit for the Power-Fail Comparator

Response Time (FALL)

Figure 7A. Power-Fail Comparator Response Time (FALL)

30pF

1KΩ

PFO

+1.25V

+5V

PFI

= +5V

= +25 C

RESET

+4V

+5V

RESET

+5V

+4V

+1.3V

+1.2V

PFI

= 5V

BATT

= 0V

PFO

2µs/div

500ns/div

Figure 8A. Power-Fail Comparator Response Time (RISE) Figure 8B. Circuit for the Power-Fail Comparator

Response Time (RISE)

30pF 1KΩ

PFO

+1.25V

+5V

PFI

= +5V

= +25 C

Figure 9. Timing Diagram

RESET*

PFO

OUT

+5V

3.0V

+5V

+5V t

3.0V

+5V

RESET**

BATT

= PFI = 3.0V *SP690A/692A/802L/802M

**SP805L/805M

+1.3V

+1.2V

PFI

= 5V

BATT

= 0V

PFO

2µs/div

THEORY OF OPERATION

The SP690A/692A/802L/802M/805L/805M

microprocessor (µP) supervisory circuits

monitor the power supplied to digital circuits

such as microprocessors, microcontrollers, or

memory. The series is an ideal solution for

portable, battery-powered equipment that

requires power supply monitoring. Implementing

this series will reduce the number of

components and overall complexity. The

watchdog functions of this product family will

continuously oversee the operational status of a

system. The operational features and benefits of

the SP690A/692A/802L/802M/805L/805M are

described in more detail below.

Reset Output

The microprocessor's (µP's) reset input starts

the µP in a known state. When the µP is in an

unknown state, it should be held in reset. The

SP690A/SP692A/SP802 assert reset during

power-up and prevent code execution errors

during power-down or brownout conditions.

On power-up, once VCC reaches 1V, RESET is

guaranteed to be a logic low. As VCC rises,

RESET remains low. When VCC exceeds the

reset threshold, RESET will remain low for

200ms, Figure 9. If a brownout condition

occurs and VCC dips below the reset threshold,

RESET is triggered. Each time RESET is

triggered, it stays low for the reset pulse width

interval. If a brownout condition interrupts a

previously initiated reset pulse, the reset pulse

continues for another 200ms. On power-down,

once VCC goes below the threshold, RESET is

guaranteed to be logic low until VCC drops

below 1V.

RESET is also triggered by a watchdog timeout.

If WDI remains either high or low for a period

that exceeds the watchdog timeout period (1.6

sec), RESET pulses low for 200mS. As long as

RESET is asserted, the watchdog timer remains

clear. When RESET comes high, the watchdog

resumes timing and must be serviced within

1.6sec. If WDI is tied high or low, a RESET

pulse is triggered every 1.8sec (tWD plus tRS).

FEATURES

The SP690A/692A/802L/802M/805L/805M

provide four key functions:

1. A battery backup switching for CMOS RAM,

CMOS microprocessors, or other logic.

2. A reset output during power-up, power-down

and brownout conditions.

3. A reset pulse if the optional watchdog timer

has not been toggled within a specified time.

4. A 1.25V threshold detector for power-fail

warning, low battery detection, or to monitor a

power supply other than +5V.

The parts differ in their reset-voltage threshold

levels and reset outputs. The SP690A/802L/

805L generate a reset when the supply voltage

drops below 4.65V. The SP692A/802M/805M

generate a reset below 4.40V.

The SP690A/692A/802L/802M/805L/805M

are ideally suited for applications in automotive

systems, intelligent instruments, and battery-

powered computers and controllers. All designs

into an environment where it is critical to

monitor the power supply to the µP and it’s

related digital components will find the

SSP690A/692A/802L/802M/805L/805M ideal.

Figure 12. Typical Operating Circuit

GND

RESET

NMI

I/O LINE

VCC

RESET

PFO

WDI

VOUT

BUS

VCC

GND

VBATT

Unregulated

Regulated +5V

VCC

0.1µF

PFI

Lithium

Battery

3.6V

µP

CMOS

RAM

The SP805L/M active-high RESET output is

the inverse of the SP690A/SP692A/SP802 RE-

SET output, and is valid with VCC down to 1V.

Some µP's, such as Intel's 80C51, require an

active-high reset pulse.

Watchdog Input

The watchdog circuit monitors the µP's activity.

If the µP does not toggle the watchdog input

(WDI) within 1.6sec, a reset pulse is triggered.

The internal 1.6sec timer is cleared by either a

reset pulse or by floating the WDI input. As long

as RESET is asserted or the WDI input is

floating, the timer remains cleared and does not

count. As soon as RESET is released and WDI

is driven high or low, the timer starts counting.

It can detect pulses as short as 50ns.

Power-Fail Comparator

The Power-Fail Comparator can be used as an

under-voltage detector to signal the failing of a

power supply (it is completely separate from the

rest of the circuitry and does not need to be

dedicated to this function). The PFI input is

compared to an internal 1.25V reference. If PFI

is less than 1.25V, PFO goes low. The external

voltage divider drives PFI to sense the

unregulated DC input to the +5V regulator. The

voltage-divider ratio can be chosen such that the

voltage at PFI falls below 1.25V just before the

+5V regulator drops out. PFO then triggers an

interrupt which signals the µP to prepare for

power-down.

When VBATT connects to VOUT, the power-fail

comparator is turned off and PFO is forced low

to conserve backup-battery power.

Backup-Battery Switchover

In the event of a brownout or power failure, it

may be necessary to preserve the contents of

RAM. With a backup battery installed at VBATT,

the RAM is assured to have power if VCC fails.

As long as VCC exceeds the reset threshold,

VOUT connects to VCC through a 0.6Ω PMOS

power switch. Once VCC falls below the reset

threshold, VCC or VBATT, whichever is higher,

switches to VOUT. VBATT connects to VOUT

through a 5Ω switch only when VCC is below the

reset threshold and VBATT is greater than VCC.

When VCC exceeds the reset threshold, it is

connected to VOUT, regardless of the voltage

applied to VBATT Figure 13. During this time,

the diode (D1) between VBATT and VOUT will

conduct current from VBATT to VOUT if VBATT is

more than .6V above VOUT.

When VBATT connects to VOUT, backup mode is

activated and the internal circuitry will be pow-

ered from the battery Figure 14. When VCC is

just below VBATT, in the backup mode the

current drawn from VBATT will be typically

30µA. When VCC drops to more than 1V below

VBATT, the internal switchover comparator shuts

off and the supply current falls to less than 0.6µA.

Reset Threshold = 4.65V in SP690A/802L/805L

Reset Threshold = 4.40V in SP692A/802M/805M

Figure 13. BACKUP-BATTERY Switchover Block Diagram

SW1 D1 D2

SW2

BATT

GND

OUT

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Using a High Capacity Capacitor

as a Backup Power Source

VBATT has the same operating v oltage range as

VCC, and the battery-switchover threshold volt-

ages are typically +20mV centered at VBATT,

allowing use of a capacitor and a simple char ging

circuit as a backup source (see Figure 16) .

If VCC is above the reset threshold and VBATT

is 0.5V abov e V CC, current flows to V OUT and

VCC from VBATT until the voltage at VBATT is

less than 0.5V above V CC.

Leakage current through the capacitor charging

diode and the SP690A/SP802L/SP805L internal

power diode eventually discharges the capacitor

to VCC. Also, if VCC and VBATT start from 0.5V

above the reset threshold and power is lost at

VCC, the capacitor on VBATT discharges through

VCC until VBATT reaches the reset threshold; the

SP690A/SP802L/SP805L then switches to

battery-backup mode.

Figure 15. Allowable BACKUP-BATTERY Voltages

Figure 14. Input and Output Status in Battery-Backup Mode.

To enter the Battery-Backup mode, VCC must be less than the

Reset threshold and less than VBATT.

Figure 16. Backup Power Source Using High Capacity

Capacitor with SP690A/802L/805L and a +5V ±5% Supply

Figure 17. Backup Power Source Using High Capacity

Capacitor with SP692A/802M/805M and a +5V ±10% Supply

+5V

GND

BATT

OUT

RESET

CONNECT T O

STATIC RAM

TO µP

0.1F CONNECT

(RESET)*

*( ) SP805L only

VCC

+5V

GND

VBATT VOUT

RESET

CONNECT T O

STATIC RAM

TO µP

100KΩ

0.1F CONNECT

(RESET)*

*( ) SP805M only

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Allowable Backup Power-Source

Batteries

Lithium batteries work very well as backup

batteries due to very low self-discharge rate and

high energy density. Single lithium batteries

with open-circuit voltages of 3.0V to 3.6V are

ideal. Any battery with an open-circuit voltage

less than the minimum reset threshold plus 0.3V

can be connected directly to the VBATT input of

this series with no additional circuitry; see

FIGURE 12. However, batteries with open-

circuit voltages that are greater than this value

cannot be used for backup, as current is sourced

into VOUT through the diode (D1 in Figure 13)

when VCC is close to the reset threshold.

Operation Without a Backup Power

Source

If a backup power source is not used, ground

VBATT and connect VOUT to VCC. Since there is

no need to switch over to any backup power

source, VOUT does not need to be switched. A

direct connection to VCC eliminates any voltage

drops across the switch which may push VOUT

below VCC.

Replacing the Backup Battery

The backup battery can be removed while VCC

remains valid, without danger of triggering

RESET/RESET. As long as VCC stays above the

reset threshold, battery-backup mode cannot be

entered.

Adding Hysteresis to the Power-Fail

Comparator

Hysteresis adds a noise margin to the power-fail

comparator and prevents repeated triggering of

PFO when VIN is close to its trip point. Figure 18

shows how to add hysteresis to the power-fail

comparator. Select the ratio of R1 and R2 such

that PFI sees 1.25V when VIN falls to its trip

point (VTRIP). R3 adds the hysteresis. It will

typically be an order of magnitude greater (about

10 times) than R1 or R2. The current through R1

and R2 should be at least 1µA to ensure that the

25nA (max) PFI input current does not shift the

trip point. R3 should be larger than 10KΩ so it

does not load down the PFO pin. Capacitor C1

adds additional noise rejection.

Monitoring a Negative Voltage

The power-fail comparator can be used to monitor

a negative supply rail using the circuit of Figure

19. When the negative rail is valid, PFO is low.

When the negative supply voltage drops, PFO

goes high. This circuit's accuracy is

affected by the PFI threshold tolerance, the VCC

voltage, and the resistors, R1 and R2.

Figure 18. Adding Hysteresis to the POWER-FAIL

Comparator

PFI

PFO

connect to µP

+5V

GND

PFO

+5V

TRIP

0V0V

*optional

TRIP

= R

+ R

= R

|| R

+ R

|| R

1.25

- 1.25

5.0 - 1.25

1.25

Interfacing to Microprocessors with

Bidirectional Reset Pins

Microprocessors with bidirectional reset pins,

such as the Motorola 68HC11 series, can con-

tend with this series' RESET output. If, for

example, the RESET output is driven high and

the µP wants to pull it low, indeterminate logic

levels may result. To correct this, connect a

4.7KΩ resistor between the RESET output and

the µP reset I/O, as in Figure 20. Buffer the

RESET output to other system components.

Figure 19. Monitoring a Negative Voltage

Figure 20. Interfacing to Microprocessors with

Bidirectional RESET I/O

PFI

PFO

+5V

GND

PFO

V-

+5V

TRIP

5.0 - 1.25

1.25 - V

TRIP

V-

TRIP

is a negative voltage

+5V

GND

+5V

GND

RESET RESET

4.7KΩ

µP

Buffered RESET connects to System Components

INDEX

AREA

123

N/2

SYMBOL MIN NOM MAX

A--0.21

A1 0.15 - -

A2 0.115 0.13 0.195

b0.014 0.018 0.022

b2 0.045 0.06 0.07

b3 0.3 0.039 0.045

c0.008 0.01 0.014

D0.355 0.365 0.4

D1 0.005 - -

E0.3 0.31 0.325

E1 0.24 0.25 0.28

eB - - 0.43

L0.115 0.13 0.15

Note: Dimensions in (mm)

.100 BSC

.300 BSC

8 PIN PDIP JEDEC MS-001 (BA) Variation

PACKAGE: 8 PIN PDIP

AA1

A2 SIDE VIEW

Seating Plane

SECTION B-B

WITH PLATING

SYMBOL MIN NOM MAX

A1.35-1.75

A1 0.1 - 0.25

A2 1.25 - 1.65

b0.31-0.51

c0.17-0.24

L0.4-1.27

ø0º-8º

ø1 5º - 15º

Note: Dimensions in (mm)

8 Pin NSOIC JEDEC MO-012 (AA) Variation

4.90 BSC

6.00 BSC

3.90 BSC

1.27 BSC

1.04 REF

0.25 BSC

Gauge Plane

Ø1

Seating Plane L2

VIEW C

TOP VIEW

SEE VIEW C

E/2

INDEX AREA

(D/2 X E1/2)

E1/2

BASE METAL

PACKAGE: 8 PIN NSOIC

ORDERING INFORMATION

Model Temperature Range Package Types

SP690ACN........................................................0°C to +70°C.....................................................8-Pin NSOIC

SP690ACN/TR...................................................0°C to +70°C.....................................................8-Pin NSOIC

SP690ACP........................................................0°C to +70°C.........................................................8-Pin PDIP

SP690AEN......................................................-40°C to +85°C.....................................................8-Pin NSOIC

SP690AEN/TR.................................................-40°C to +85°C.....................................................8-Pin NSOIC

SP690AEP.......................................................-40°C to +85°C.......................................................8-Pin PDIP

SP692ACN........................................................0°C to +70°C......................................................8-Pin NSOIC

SP692ACN/TR..................................................0°C to +70°C......................................................8-Pin NSOIC

SP692ACP........................................................0°C to +70°C.........................................................8-Pin PDIP

SP692AEN......................................................-40°C to +85°C.....................................................8-Pin NSOIC

SP692AEN/TR................................................-40°C to +85°C.....................................................8-Pin NSOIC

SP692AEP.......................................................-40°C to +85°C.......................................................8-Pin PDIP

SP802LCN........................................................0°C to +70°C......................................................8-Pin NSOIC

SP802LCN/TR..................................................0°C to +70°C......................................................8-Pin NSOIC

SP802LCP........................................................0°C to +70°C.........................................................8-Pin PDIP

SP802LEN.......................................................-40°C to +85°C....................................................8-Pin NSOIC

SP802LEN/TR.................................................-40°C to +85°C....................................................8-Pin NSOIC

SP802LEP.......................................................-40°C to +85°C.......................................................8-Pin PDIP

SP802MCN.......................................................0°C to +70°C......................................................8-Pin NSOIC

SP802MCN/TR.................................................0°C to +70°C......................................................8-Pin NSOIC

SP802MCP.......................................................0°C to +70°C.........................................................8-Pin PDIP

SP802MEN......................................................-40°C to +85°C....................................................8-Pin NSOIC

SP802MEN/TR................................................-40°C to +85°C....................................................8-Pin NSOIC

SP802MEP......................................................-40°C to +85°C.......................................................8-Pin PDIP

SP805LCN........................................................0°C to +70°C......................................................8-Pin NSOIC

SP805LCN/TR..................................................0°C to +70°C......................................................8-Pin NSOIC

SP805LCP........................................................0°C to +70°C.........................................................8-Pin PDIP

SP805LEN.......................................................-40°C to +85°C....................................................8-Pin NSOIC

SP805LEN/TR.................................................-40°C to +85°C....................................................8-Pin NSOIC

SP805LEP.......................................................-40°C to +85°C.......................................................8-Pin PDIP

SP805MCN.......................................................0°C to +70°C......................................................8-Pin NSOIC

SP805MCN/TR..................................................0°C to +70°C......................................................8-Pin NSOIC

SP805MCP.......................................................0°C to +70°C.........................................................8-Pin PDIP

SP805MEN......................................................-40°C to +85°C....................................................8-Pin NSOIC

SP805MEN/TR................................................-40°C to +85°C....................................................8-Pin NSOIC

SP805MEP......................................................-40°C to +85°C.......................................................8-Pin PDIP

Corporation

ANALOG EXCELLENCE

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described hereing; neither does it convey any license under its patent rights nor the rights of others.

Sipex Corporation

Headquarters and

Sales Office

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

/TR = Tape and Reel

Pack quantity 2,500 for NSOIC.

Available in lead free packaging. To order add “-L” suffix to part number.

Example: SP802LCN/TR = standard; SP802LCN-L/TR = lead free

CLICK HERE TO ORDER SAMPLES