Philips Semiconductors Preliminary Specification eee errr ee eee ee eee eee ee eS Octal D-type transparent latch with 5-volt tolerant 74LVC2573A inputs/outputs; damping resistor; 3-state 74LVCH2573A FEATURES * -volt tolerant inputs/outputs, for interfacing with 5-volt logic. Wide supply voltage range of 2.7 V to 3.6 V. In accordance with JEDEC standard no. 8-1A. Inputs accept voltages upto 5.5V CMOS low power consumption Direct interface with TTL levels Flow-through pin-out architecture Bushold on all data inputs (LVCH2573A only). integrated 30Q damping resistor. * oee . . e DESCRIPTION The 74LVC(H)2573A is a high-performance, low-power, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows'the use of these devices as translators in a mixed 3.3 V/5 V environment. The 74LVC(H)2573A is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. A latch enable (LE) input and an output enable (OE) input are common to all internal latches. The 2573 consists of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the D, inputs enters the latches. In this condition the latches are transparent, i.e. a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information. that was present at the D-inputs a set-up time preceding the HIGH-to-LOW transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to.the high impedance OFF-state. Operation of the OE input does not affect the state of the latches. 1996 Feb QUICK REFERENCE DATA GND = 0 V; Tip = 25 C: = t, $2.5 ns SYMBOL PARAMETER CONDITIONS | TYPICAL | UNIT propagation delay C, = 50 pF trite. | D, to Q,; Veo = 3.3 V 4.4 LE to Q, 5.0 ns C, input capacitance 5.0 pF Cop power dissipation notes 1 and 2 20 pe capacitance per latch Notes to the quick reference data 1. Cp, is used to determine the dynamic power dissipation (P, in uW): Py = Cop X Voge? Xf, + E (C, x Ve? x F,) where: f, = input frequency in MHz; C, = output load capacity in pF; f, = output frequency in MHz; V,, = supply voltage in V; E(C, x Voc" x f,) = sum of outputs. 2. The condition is V, = GND to Veo. ORDERING INFORMATION ACKAGES TYPE NUMBER PACKAGE PINS |PACKAGE| MATERIAL CODE 74LVC(H)2573AD | 20 so plastic SOT163-1 74LVC(H)2573ADB | 20 SSOP plastic SOT339-1 7ALVC(H)2573APW] 20 | TSSOP plastic SOT360-1 PINNING PIN SYMBOL NAME AND FUNCTION 1 OE output enable input (active LOW) 2,3,4,5, . 6.7.8.9 D, to D, data inputs 19, 18, 17, 16, 15,14, 13,12 Q, to Q, 3-state latch outputs 10 GND ground (0 V) 11 LE latch enable input (active HIGH) 20 Voc positive supply voltage The '2573 is functionally identical to the 2373, but the '2373' has a different pin arrangement. 3-213Pailips Semiconductors Preliminary Specification Octal D-type transparent latch with 5-volt tolerant 74LVC2573A inputs/outputs; damping resistor; 3-state 74LVCH2573A oe [1 U [20] Vee | Do LZ] 19] Qo d po, [34 18} ay 2} Do Oe Qo - 19 De [4] 117] Qo 3o, a, 18 D3 [5 | 573 116] Og 4| De Qo > 17 D4 [6 | 15] Oy 5 D3 Q3 f 16 os [7] 144] Qs 6]D, Q4 15 Deg [8] 113] Qg 7-[ Ds Qs p14 o7 [8] 12] @7 ~) Pe 6 %8 @np [70] rit] Le 9~ D7 le Q7 Pp 12 1 Fig.1 Pin configuration. Fig.2 Logic symbol. 3-STATE OUTPUTS | Q4 Fig3. [EC logic symbol. Fig.4 Functional diagram. 0 Di Dg x) D4 Os Dg $ Ye a Lp ary 8 Ye Q dD Qk 40 a D ak HD oF LATCH LATCH LATCH carol | LATCH LATCH) LATCH LATCH ] 1 2 3 4 & 6 7 8 _ _ i= __ i TE Le (TE 1E| LE Le CE LE CE LE} LE LE] LE LE LE Le] Ti TT L I {J | te pol p-_t i Q Qy Qg Q3 Q4 Qs Og Qy Fig. Logic diagram. 1996 Feb 3-214Philips Semiconductors Preliminary Specification Octal D-type transparent latch with 5-volt tolerant T4LVC2573A inputs/outputs; damping resistor; 3-state 7T4LVCH2573A FUNCTION TABLE INPUTS OUTPUTS INTERNAL OPERATING MODES OE LE D, LATCHES | 4, to @, enable and read register L H L L L (transparent mode) L H H H H latch and read register L L | L L L L h H H jatch register and disable H L \ L Zz outputs H L h H Zz H = HIGH voltage levei h_ = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level { = LOW voltage level one set-up.time prior to the HIGH-to-LOW LE transition X = don't care Z = high impedance OFF-state DC. CHARACTERISTICS FOR 74LVC(H)2573A For the DC characteristics see chapter LVC(H)-A family characteristics", section "Family specifications". AC CHARACTERISTICS FOR 74LVC(H)2573A GND = 0 V; t, =< 2.5 ns; C, = 50 pF Tom (0) TEST CONDITIONS SYMBOL [PARAMETER =40 to +85 uNiT |~ Vv... WAVEFORMS MIN. | TYP. | MAX: (Vv) ropagation dela ~ 21 ~ 12 trwttew |B wo y 15 | 47 | 95 | ns 27 |Figs 6, 10 nO Mn 15 | 43" | 385 3.0 to 3.6 opagation dela ~ 23 ~ 12 tou/teun fee y 15 | 53 ] 1 ns 27 |Figs 7, 10 i 15 | 46 |] 95 3.0 to 3.6 3-state output enable - 17 - 1.2 terwtpz, {time 15 | 44 1 ns 2.7 |Figs 8, 10 OE to Q, 15 | 38 | 9.0 3.0 to 3.6 3-state output disable ~ 8.0 - 1.2 : teuz'terz _ time 15 | 40 | 65 | ns 2.7 |Figs 8, 10 OE to Q, 15 |] 35* 1 60 3.0 to 3.6 = 3.0 = 27 tw LE pulse width HIGH . 30 _ "S |30t036 Fig.7 set-up time 1.0 0.2 ~ 27 . tw LD, to LE to | o2 | -~ | |30t0a6|Pio? hold time 1.0 0 ~ 2.7 . h D, to LE to | o | - "S 130 to36|99 Notes: Ail typicai values are measured at T,,,, = 25 C. * Typical values are measured at Vo, = 3.3 V. 1996 Feb 3215Philips Semiconductors Preliminary Specification Octal D-type transparent latch with 5-volt tolerant inputs/outputs; damping resistor; 3-state AC WAVEFORMS 74LVC2573A 74LVCH2573A My Fig.6 Waveforms showing the input (D,) to output (Q,) propagation delays. Vysceereees LE INPUT GND Vou Qy OUTPUT Fig.7 Waveforms showing the latch enabie input (LE) pulse width, the latch enable input to output (Q,) propagation delays. O INPUT cnn / Voc + Gy OUTPUT LOW-t0-OFF fo | OFF-to-LOW yy (3) Vo?! " | rtp HZ ete Vou!) ______4 Gy OUTPUT HIGH-10-OFF CFF-to-HIGH GND creer outputs 3 outputs enabled. | disabled enabled Fig.8 Waveforms showing the 3-state enable and disable times Fig.9 Waveforms showing the data set-up and hold times for the D, input to the LE input. Note to Fig.9: The shaded areas indicate when the input is permitted to change for predictable output performance. 2 Voc Nv, oOpen co } GND ( 500 42 PULSE re pF Joe a Test 84 tpLHipHL | Open tprztez, | 2 * Voc tpHztpzH | GND Voc Vi <27V Yoo 27-36V| 27V Fig.10 Load circuitry for switching times. 1996 Feb Notes: (1) Vy=15VatVoo 22.7 V Vy = 0.5 - Veg at Veg < 2.7 V (2) Voy, and Vg, are the typical output voltage drop that occur with the output load (38) Vy= Vo. +03 VatVog 22.7 V Vy = Vo. + 0.1 + Veg at Veg < 2.7 V (4) Vy = Voy - 0.8 V at Veg 22.7 V Vy = Von 0.1 + Veg at Veg < 2.7 V 3-216 cc ratermepm aman oem a mrapmeninicriaenaminare ath