VME01 16-Bit TTL Compatible Data Transceiver with Incident Wave Switching General Description Features The VME01 contains sixteen non-inverting bidirectional buffers with 3-STATE outputs designed with incident wave switching, live insertion support and enhanced noise margin for TTL backplane applications. A VCC bias pin provides for the precharging of the A side outputs during live insertion. When set at 5.0V, this pin will establish a voltage of 1.5V on the A port before VCC is connected. This precharge will minimize the capacitive discharge, and associated discontinuity, onto the active backplane during board insertion. The B port includes a bus hold circuit to latch the output to the value last forced on that pin. The B port of this device includes 25 series output resistors, which minimize undershoot and ringing. n Supports the VME64 ETL specification n Functionally and pin compatible with TI SN74ABTE16245 n Improved TTL-compatible input threshold range n High drive TTL-compatible outputs (IOH = -60 mA, IOL = 90 mA) n Supports 25 incident wave switching on the A port n VCC Bias pin minimizes signal distortion during live insertion n BiCMOS design significantly reduces power dissipation. n Distributed VCC and GND pin configuration minimizes high-speed switching noise n 25 series-dampening resistor on B-port n Available in 48-pin SSOP and ceramic flatpak n Guaranteed output skew n Guaranteed simultaneous switching noise level and dynamic threshold performance n Guaranteed latchup protection Ordering Code: Order Number See Section 0 Package Number Package Description MS48A 48-Lead SSop (0.300"Wide) (SS) WA48A 48-Pin Ceramic Flatpak (FPFP) Device also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code. Logic Symbol DS011624-1 Pin Description Pin Names VME01 October 1997 VME01 16-Bit TTL Compatible Data Transceiver with Incident Wave Switching PRELIMINARY DSXXX Description 1DIR-2DIR Transmit/Receive Inputs OE Output Enable Input (Active LOW) 1An, 2An Backplane Bus Inputs or 3-STATE Outputs, with Live Insertion 1Bn, 2Bn Local Bus Input Pins or 3-STATE Outputs, with Bus Hold VCC Bias (c) 1997 Fairchild Semiconductor Corporation Live Insertion Power Supply www.fairchildsemi.com DS011624 PrintDate=1997/10/16 PrintTime=11:57:42 21131 ds011624 Rev. No. 4 cmserv Proof 1 1 Connection Diagram Functional Description The device uses byte-wide Direction (DIR) control and a singular Output Enable (OE ) control. The DIR inputs determine the direction of data flow through the device. The OE input disables both the A and the B ports, effectively isolating both buses. The part contains active circuitry which keeps all outputs disabled when VCC is less than 2.2V to aid in live insertion applications. Pin Assignment for SSOP and Flatpak Truth Tables (Each 8-bit Section) Inputs Operation DIR OE L L A Data to B Bus L H B Data to A Bus H X Isolation DS011624-2 Logic Diagram (Positive Logic) DS011624-3 www.fairchildsemi.com 2 PrintDate=1997/10/16 PrintTime=11:57:44 21131 ds011624 Rev. No. 4 cmserv Proof 2 ETL's Improved Noise Immunity TTL input thresholds are typically determined by temperature-dependent junction voltages which result in worst case input thresholds between 0.8V and 2.0V. By contrast, ETL provides greater noise immunity because its input thresholds are determined by current mode input circuits similar to those used for ECL or BTL. ETL's worst case input thresholds, between 1.4V and 1.6V, are compensated for temperature, voltage and process variations. Improved Input Threshold Characteristics of ETL DS011624-8 DS011624-5 ETL Worst Case VOUT-VIN TTL Worst Case VOUT-VIN Incident Wave Switching When TTL logic is used to drive fully loaded backplanes, the combination of low backplane bus characteristic impedance, wide TTL input threshold range and limited TTL drive generally require multiple waveform reflections before a valid signal can be received across the backplane. The VME International Trade Association (VITA) defined ETL to provide incident wave switching which increases the data transfer rate of a VME backplane and extends the life of VME applications. TTL compatibility with existing VME backplanes and modules was maintained. To demonstrate the incident wave switching capability, consider a VME application. A VME bus must be terminated to +2.94V with 190 at each end of its 21 card backplane. The surge impedance presented by a fully loaded VME backplane is approximately 25. If the output voltage/current of an ABTC driver is plotted with this load, the intersection at 1.2V for a falling edge and at 1.6V for a rising edge does not reach the worst case input threshold of a second ABTC circuit. This is shown in the two figures below. However, an ETL driver located at one end of the backplane is able to provide incident wave switching because it has a higher drive and a tighter input threshold. Estimated ETL/ABTC Initial Falling Edge Step DS011624-9 3 PrintDate=1997/10/16 PrintTime=11:57:45 21131 ds011624 Rev. No. 4 www.fairchildsemi.com cmserv Proof 3 Incident Wave Switching (Continued) Estimated ETL/ABTC Initial Rising Edge Step DS011624-11 Because ETL has a much more precise input threshold region, an ETL receiver will interpret its predicted falling input of 0.85V as a logic ZERO and the initial rising edge of 1.9V as a logic ONE. This comparison is for the case of a 25 surge impedance backplane driven from one end. The resulting ABTC and ETL waveform predictions and their input thresholds are compared below. This shows how ETL can achieve backplane speeds not always possible with conventional TTL compatible logic families. Comparing the Incident Wave Switching of ETL with ABTC DS011624-12 Live Insertion Module Replacement nector pins. The differential length connector pins allow power sequencing to the module so that the signal pins can be controlled to a biased high impedance before they make contact with the backplane. VITA's ETL modules will use an early VCC power input,called VCC Bias, to control the ETL transceivers to a high impedance to minimize insertion disturbance. In addition, VCC Bias is used to precharge the backplane driver output capaci- To allow a system module to be replaced without disturbing signals passing between other operating modules requires careful design of operating systems, applications software and hardware. ETL supports live insertion module replacement with features that minimize backplane signal disturbance while a module is inserted. As specified by VITA, live insertion requires several backward-compatible system enhancements including: an improved backplane connector with an embedded ground plane and differential length conwww.fairchildsemi.com 4 PrintDate=1997/10/16 PrintTime=11:57:45 21131 ds011624 Rev. No. 4 cmserv Proof 4 Live Insertion Module Replacement (Continued) When applying power to a printed circuit board containing ETL transceivers, the system VCC can be connected to VCC. Bias without damage to the device. If the advantages of Live Insertion are to be included in the system, then VCC Bias should be allowed to reach normal operating levels before VCC becomes higher than 2.2 volts. In addition, when removing a module, or turning off system power, VCC should be reduced below 2.2 volts before VCC. Bias is allowed to drop below normal operating limits. This sequencing is shown below. The figure VCC Power-up Critical Voltages shows the relationship between VCC and OE while power is being applied and removed. This relationship holds if VCC Bias is within normal operating conditions or if VCC Bias is equal to VCC. tance including the module connector pin and module etch. The precharge voltage is to 1.5V using a switched 40 k resistor. This precharge will minimize the capacitive discharge onto an active backplane as the signal connection is made. To allow designers to maintain this condition until after a module is fully powered and initialized, the OE pin can be used to maintain outputs in the high impedance, precharged state. Contact bounce during live insertion will charge each output pin to a logic ONE or ZERO. If the contact bounces open, the 40 k resistor will reestablish the 1.5V level in a few microseconds. DS011624-13 Power Sequencing to Achieve Live Insertion Precharging DS011624-14 VCC and OE Power-Up Relationship 5 PrintDate=1997/10/16 PrintTime=11:57:46 21131 ds011624 Rev. No. 4 www.fairchildsemi.com cmserv Proof 5 Absolute Maximum Ratings Storage Temperature Ambient Temperature under Bias Junction Temperature under Bias Ceramic Plastic VCC Pin Potential to Ground Pin Input Voltage (Note 2) Input Current (Note 2) Voltage Applied to Any Output in the Disabled or Power-off State in the HIGH State Current Applied to Output in LOW State (Max) DC Latchup Source Current Over Voltage Latchup (I/O) (Note 1) -65C to +150C -55C to +125C -500 mA 10V Recommended Operating Conditions -55C to +175C -55C to +150C Free Air Ambient Temperature Commercial Supply Voltage Commercial Minimum Input Edge Rate Data Input Enable Input -0.5V to +7.0V -0.5V to +7.0V -50 mA to +5.0 mA -0.5V to 5.5V -0.5V to VCC -40C to +85C +4.5V to +5.5V (t/V) 20 ns/V 50 ns/V Note 1: Absolute maximum ratings are values beyond which the device may be damaged or have its useful life impaired. Functional operation under these conditions is not implied. Note 2: Either voltage limit or current limit is sufficient to protectinputs. 128 mA DC Electrical Characteristics Symbol Parameter VIH Input HIGH Voltage VIL Input LOW Voltage VCD Input Clamp Diode Voltage VOH Output HIGH Voltage Min OE 2.0 Other Inputs 1.6 Typ Max OE 0.8 Other Inputs 1.4 B Port VOL Output LOW Voltage Bus Hold Current V Recognized LOW Signal V V Min IIN = -18 mA (OEn, DIR) IOH = -100 A V 2.0 V IOH = -12 mA V IOH = -1 mA 2.4 V 2.0 V 0.4 V 0.8 V 0.55 V 0.9 V 100 A Min IOH = -1 mA 2.4 B Port B Port Conditions Recognized HIGH Signal -1.2 A Port IHOLD VCC V VCC - 1 VCC - 1 A Port Units Min IOH = -32 mA IOH = -60 mA Min IOL = 1 mA IOL = 12 mA Min IOL = 64 mA IOL = 90 mA Min OE = HIGH, VO = 0.8V OE = HIGH, -100 VO = 2.0V ICC VCC = VCC Bias VCC Bias Supply Current 10 mA 100 A VCC Bias = 0 to 5.5V IO = 0 IOFF Output Current, Power Down 0.0 VCC Bias = 0V VI or VO 4.5V II IIH + Military 10 A 5.5 VIN = 0 or VCC Commercial 5 A 5.5 VIN = 0 or VCC Output Leakage Current A Port 50 A 5.5 VOUT = 2.7V, OE = 2.0V Output Leakage Current A Port -50 A 5.5 VOUT = 0.5V, OE = 2.0V 40 mA Max Input Current Control Pins IOZH IIL + IOZL ICCH Power Supply Current All Outputs HIGH, OE = LOW, DIR = HIGH or LOW ICCL Power Supply Current 80 mA Max All Outputs LOW, OE = LOW, DIR = HIGH or LOW www.fairchildsemi.com 6 PrintDate=1997/10/16 PrintTime=11:57:49 21131 ds011624 Rev. No. 4 cmserv Proof 6 DC Electrical Characteristics Symbol ICCZ (Continued) Parameter Min Typ Power Supply Current Max Units VCC Conditions OE = HIGH 40 mA Max All Others at VCC or GND DIR = HIGH or LOW ICCD Dynamic ICC 0.15 mA/ MHz No Load Max (Note 3) VLI = GND, DIR = HIGH n One Bit Toggling, 50% Duty Cycle Output Live A Port 1.3 1.7 V 5.0 IOUT = 0 mA, OE = HIGH VCC Bias = 5.0V Insertion Voltage IPRE Outputs Open OE Precharge Current -20 -100 A 5.0 OE = HIGH, VO = 0V, VCC Bias = 5.0V A-Port 20 100 A 5.0 VO = 3V, VCC Bias = 5.0V, OE = High VOLP Quiet Output Maximum 1.0 V 5.0 VOLV Quiet Output Minimum -1.4 V 5.0 Minimum High Level Dynamic 2.7 V 5.0 Minimum High Level Dynamic 2.0 1.5 Input Voltage (Note 3) VILD TA = 25C (Note 6) CL = 50 pF; RL = 500 Output Voltage (Note 3) VIHD TA = 25C (Note 4) CL = 50 pF; RL = 500 Dynamic VOL VOHV TA = 25C (Note 4) CL = 50 pF; RL = 500 Dynamic VOL Maximum Low Level Dynamic 1.2 0.8 Input Voltage (Note 3) V 5.0 V 5.0 TA = 25C (Note 5) CL = 50 pF; RL = 500 TA = 25C (Note 5) CL = 50 pF; RL = 500 Note 3: Guaranteed, but not tested. Note 4: Max. number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested. Note 5: Max. number of data inputs (n) switching. n - 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (VILD), 0V to threshold (VIHD). Guaranteed, but not tested. Note 6: Max. number of outputs defined as (n). n - 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested. AC Electrical Characteristics Symbol Parameter Commercial Military Commercial TA = +25C TA = -55C to +125C TA = -40C to +85C VCC = +5V Min Typ VCC = 4.5V-5.5V Units Fig. No. ns Figures 1, 2, 3, 4, 6 ns Figures 1, 2, 3, 4, 6 VCC = 4.5V-5.5V Max Min Max Min Max tPLH Propagation 1.5 7.0 1.5 7.0 1.5 7.0 tPHL Delay A-Port to B-Port 1.5 7.0 1.5 7.0 1.5 7.0 tPLH Propagation 1.5 7.0 1.5 7.0 1.5 7.0 tPHL Delay B-Port to A-Port 1.5 7.0 1.5 7.0 1.5 7.0 tPZH Output Enable 1.0 7.0 1.0 7.0 1.0 7.0 tPZL Time 1.0 7.0 1.0 7.0 1.0 7.0 tPHZ Output Disable 1.0 7.0 1.0 7.0 1.0 7.0 tPLZ Time 1.0 7.0 1.0 7.0 1.0 7.0 tr Rise Time 1V 2V, 1.2 3.0 0.8 4.0 1.2 1.2 3.0 0.8 4.0 1.2 ns ns Figures 1, 2, 3, 4, 5 3.0 ns Figures 1, 2, 3, 4, 6 3.0 ns Figures 1, 2, 3, 4, 6 A-Port Outputs tf Fall Time 2V 1V, A-Port Outputs 7 PrintDate=1997/10/16 PrintTime=11:57:53 21131 ds011624 Rev. No. 4 Figures 1, 2, 3, 4, 5 www.fairchildsemi.com cmserv Proof 7 Skew Symbol Parameter tOHS Pin-to-Pin Skew (Notes 7, 8) LH/HL A-Port to B-Port tOHS Pin-to-Pin Skew (Notes 7, 8) LH/HL B-Port to A-Port tPS Duty Cycle Skew (Notes 7, 8) B-Port to A-Port tPS Duty Cycle Skew (Notes 7, 8) A-Port to B-Port Commercial Military TA = -40C to +85C TA = -55C to +125C Units VCC = 4.5V-5.5V VCC = 4.5V-5.5V 16 Outputs Switching 16 Outputs Switching Max Max 1.3 1.3 ns 1.3 1.3 ns 2.0 2.0 ns 2.0 2.0 ns Conditions Figures 1, 2, 3, 4, 6 Figures 1, 2, 3, 4, 6 Figures 1, 2, 3, 4, 6 Figures 1, 2, 3, 4, 6 VME Extended Skew Symbol Parameter tPV Device-to-Device Skew LH/HL (Notes 7, 8) Transitions B-Port to A-Port tPV Device-to-Device Skew LH/HL (Notes 7, 8) Transitions A-Port to B-Port tCP Change in Propagation Delay (Notes 7, 9) with Load B-Port to A-Port tCPV Device-to-Device, Change (Notes 7, 8, 9) in Propagation Delay with Commercial Military TA = -40C to +85C TA = -55C to +125C Units Conditions VCC = 4.5V-5.5V VCC = 4.5V-5.5V 16 Outputs Switching 16 Outputs Switching Max Max 4.0 4.5 ns Figures 1, 2, 3, 4, 6 2.5 3.0 ns Figures 1, 2, 3, 4, 6 4.0 4.5 ns Figures 1, 2, 3, 4, 6 6.0 7.0 ns Figures 1, 2, 3, 4, 6 Load B-Port to A-Port Note 7: Skew is defined as the absolute difference in delay between two outputs. The specification applies to any outputs switching HIGH to LOW, LOW to HIGH, or any combination switching HIGH-to-LOW or LOW-to-HIGH. This specification is guaranteed but not tested. Note 8: This is measured with both devices at the same value of VCC 1% and with package temperature differences of 20C from each other. Note 9: This is measured with Rx in Figure 1 at 13 for one unit and at 56 for the other unit. Capacitance Symbol Parameter Conditions, TA = 25C Typ Max Units CIN Input Capacitance 5 8 pF VCC = 0.0V (OEn, DIR) CI/O (Note 10) Output Capacitance 9 12 pF VCC = 5.0V (An) Note 10: CI/O is measured at frequency f = 1 MHz, per MIL-STD-883B, Method 3012. www.fairchildsemi.com 8 PrintDate=1997/10/16 PrintTime=11:57:55 21131 ds011624 Rev. No. 4 cmserv Proof 8 AC Loading Amplitude Rep. Rate tw tr tf 3.0V 1 MHz 500 ns 2.5 ns 2.5 ns FIGURE 3. Test Input Signal Requirements Test Port SW1 SW2 tPHZ, A, B Open Open Rx A, B +7 Open A Open Closed B Open Open tr, tf A Open Closed 26 tPV A Open Closed 26 tPV B Open Open tCP A Open Closed 13 then 56 tCPV A Open Closed 13 and 56 tPZH tPLZ, tPZL DS011624-4 tPLH, *Includes jig and probe capacitance 26 tPHL FIGURE 1. Standard AC Test Load tPLH, tPHL Note 11: Defined to emulate the range of VME bus transmission line loading as a function of board population and driver location. Rx = 13, 26 or 56 depending on test. FIGURE 4. DS011624-6 FIGURE 2. Input Pulse Requirements DS011624-7 FIGURE 5. 3-STATE Output HIGH and LOW Enable and Disable Times DS011624-10 FIGURE 6. Rise, Fall Time and Propagation Delay Waveforms Book Extract End 9 PrintDate=1997/10/16 PrintTime=11:57:59 21131 ds011624 Rev. No. 4 www.fairchildsemi.com cmserv Proof 9 THIS PAGE IS IGNORED IN THE DATABOOK 10 PrintDate=1997/10/16 PrintTime=11:58:00 21131 ds011624 Rev. No. 4 cmserv Proof 10 Ordering Information The device number is used to form part of a simplified purchasing code where the package type and temperature range are defined as follows: DS011624-15 Physical Dimensions inches (millimeters) unless otherwise noted 48-Lead SSOP (0.300" Wide) (SS) Package Number MS48A 48-Pin Ceramic Flatpak (FPFP)Package Number WA48A 11 PrintDate=1997/10/16 PrintTime=11:58:00 21131 ds011624 Rev. No. 4 www.fairchildsemi.com cmserv Proof 11 11 VME01 16-Bit TTL Compatible Data Transceiver with Incident Wave Switching LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 2. A critical component in any component of a life support 1. Life support devices or systems are devices or sysdevice or system whose failure to perform can be reatems which, (a) are intended for surgical implant into sonably expected to cause the failure of the life support the body, or (b) support or sustain life, and (c) whose device or system, or to affect its safety or effectiveness. failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. Fairchild Semiconductor Corporation Americas Customer Response Center Tel: 1-888-522-5372 Fairchild Semiconductor Europe Fax: +49 (0) 1 80-530 85 86 Email: europe.support@nsc.com Deutsch Tel: +49 (0) 8 141-35-0 English Tel: +44 (0) 1 793-85-68-56 Italy Tel: +39 (0) 2 57 5631 Fairchild Semiconductor Hong Kong Ltd. 13th Floor, Straight Block, Ocean Centre, 5 Canton Rd. Tsimshatsui, Kowloon Hong Kong Tel: +852 2737-7200 Fax: +852 2314-0061 www.fairchildsemi.com National Semiconductor Japan Ltd. Tel: 81-3-5620-6175 Fax: 81-3-5620-6179 Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. PrintDate=1997/10/16 PrintTime=11:58:01 21131 ds011624 Rev. No. 4 cmserv Proof 12