User Defined Fault Protection and Detection,
0.8 pC Q
INJ
, 8:1/Dual 4:1 Multiplexers
Data Sheet
ADG5248F/ADG5249F
Rev. A Document Feedback
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FEATURES
User defined secondary supplies set overvoltage level
Overvoltage protection up to −55 V and +55 V
Power-off protection up to −55 V and +55 V
Overvoltage detection on source pins
Minimum secondary supply level: 4.5 V single-supply
Interrupt flags indicate fault status
Low charge injection (QINJ): 0.8 pC
Low drain/source on capacitance
ADG5248F: 19 pF
ADG5249F: 14 pF
Latch-up immune under any circumstance
Known state without digital inputs present
VSS to VDD analog signal range
±5 V to ±22 V dual-supply operation
8 V to 44 V single-supply operation
Fully specified at ±15 V, ±20 V, +12 V, and +36 V
APPLICATIONS
Analog input/output modules
Process control/distributed control systems
Data acquisition
Instrumentation
Avionics
Automatic test equipment
Communication systems
Relay replacement
FUNCTIONAL BLOCK DIAGRAMS
ADG5248F
S1
S8
D
A0 A1 A2 EN
FF
SF
POSFV NEGFV
FAULT DETECTION
AND
SWITCH DRIVER
13072-001
Figure 1. ADG5248F Functional Block Diagram
ADG5249F
S1A
S4A
DA
S1B
S4B
DB
A0 A1 EN POSFV NEGFV
FF
SF
FAULT DETECTION
AND
SWITCH DRIVER
13072-002
Figure 2. ADG5249F Functional Block Diagram
GENERAL DESCRIPTION
The ADG5248F and ADG5249F are 8:1 and dual 4:1 analog
multiplexers. The ADG5248F switches one of eight inputs to a
common output, and the ADG5249F switches one of four differen-
tial inputs to a common differential output. Each channel conducts
equally well in both directions when on, and each channel has an
input signal range that extends to the supplies. The primary supply
voltages define the on-resistance profile, whereas the secondary
supply voltages define the voltage level at which the overvoltage
protection engages.
When no power supplies are present, the channel remains in the off
condition, and the switch inputs are high impedance. Under normal
operating conditions, if the analog input signal levels on any Sx pin
exceed positive fault voltage (POSFV) or negative fault voltage
(NEGFV) by a threshold voltage (VT), the channel turns off and
that Sx pin becomes high impedance. If the switch on, the drain pin
is pulled to the secondary supply voltage that was exceeded. Input
signal levels up to +55 V or −55 V relative to ground are blocked, in
both the powered and unpowered conditions.
The low capacitance and charge injection of these switches make
them ideal solutions for data acquisition and sample-and-hold
applications, where low glitch switching and fast settling times
are required.
Note that, throughout this data sheet, multifunction pins, such as
A0/F0, are referred to either by the entire pin name or by a single
function of the pin, for example, A0, when only that function is
relevant.
PRODUCT HIGHLIGHTS
1. Source pins are protected against voltages greater than the
secondary supply rails, up to −55 V and +55 V.
2. Source pins are protected against voltages between −55 V
and +55 V in an unpowered state.
3. Overvoltage detection with digital output indicates
operating state of switches.
4. Trench isolation guards against latch-up.
5. Optimized for low charge injection and on capacitance.
6. The ADG5248F/ADG5249F can be operated from a dual
supply of ±5 V to ±22 V or a single power supply of 8 V to 44 V.
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 2 of 34
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagrams ............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
±15 V Dual Supply ....................................................................... 3
±20 V Dual Supply ....................................................................... 5
12 V Single Supply ........................................................................ 7
36 V Single Supply ........................................................................ 9
Continuous Current per Channel, Sx, D, or Dx ..................... 12
Absolute Maximum Ratings .......................................................... 13
ESD Caution ................................................................................ 13
Pin Configurations and Function Descriptions ......................... 14
Typical Performance Characteristics ........................................... 18
Test Circuits ..................................................................................... 23
Terminology .................................................................................... 28
Theory of Operation ...................................................................... 30
Switch Architecture .................................................................... 30
User Defined Fault Protection .................................................. 31
Applications Information .............................................................. 32
Power Supply Rails ..................................................................... 32
Power Supply Sequencing Protection ...................................... 32
Signal Range ................................................................................ 32
Power Supply Recommendations ............................................. 32
High Voltage Surge Suppression .............................................. 32
Intelligent Fault Detection ........................................................ 33
Large Voltage, High Frequency Signals ................................... 33
Outline Dimensions ....................................................................... 34
Ordering Guide .......................................................................... 34
REVISION HISTORY
7/2016—Rev. 0 to Rev. A
Added 20-Lead LFCSP ....................................................... Universal
Changes to Table 5 .......................................................................... 12
Changes to Table 6 .......................................................................... 13
Added Figure 4; Renumbered Sequentially ................................ 14
Changes to Table 7 .......................................................................... 14
Added Figure 6 ................................................................................ 16
Changes to Table 10 ........................................................................ 16
Updated Outline Dimensions ....................................................... 34
Changes to Ordering Guide .......................................................... 34
4/2015—Revision 0: Initial Version
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 3 of 34
SPECIFICATIONS
±15 V DUAL SUPPLY
VDD = 15 V ± 10%, VSS = −15 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 1.
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH VDD = +13.5 V, VSS = −13.5 V, see Figure 38
Analog Signal Range
V
DD
to V
SS
V
On Resistance, RON 250 Ω typ VS = ±10 V, IS = −1 mA
270 335 395 Ω max
250 Ω typ VS = ±9 V, IS = −1 mA
270 335 395 Ω max
On-Resistance Match Between
Channels, ∆RON
2.5 Ω typ VS = ±10 V, IS = −1 mA
6 12 13 Ω max
2.5 Ω typ VS = ±9 V, IS = −1 mA
6 12 13 Ω max
On-Resistance Flatness, RFLAT(ON) 6.5 Ω typ VS = ±10 V, IS = −1 mA
8
9
Ω max
1.5 Ω typ VS = ±9 V, IS = −1 mA
3.5 4 4 Ω max
Threshold Voltage, VT 0.7 V typ See Figure 30
LEAKAGE CURRENTS VDD = +16.5 V, VSS = −16.5 V
Source Off Leakage, IS (Off ) ±0.1 nA typ VS = ±10 V, VD =
∓
10 V, see Figure 36
±1 ±2 ±5 nA max
Drain Off Leakage, ID (Off ) ±0.1 nA typ VS = ±10 V, VD =
∓
10 V, see Figure 36
±1 ±5 ±10 nA max
Channel On Leakage, ID (On), IS (On) ±0.3 nA typ VS = VD = ±10 V, see Figure 37
±1.5 ±20 ±25 nA max
FAULT
Source Leakage Current, IS
With Overvoltage ±66 ±78 µA typ VDD = +16.5 V, VSS = −16.5 V, GND = 0 V, VS = ±55 V,
see Figure 35
Power Supplies Grounded or
Floating
±25 ±40 µA typ VDD = 0 V or floating, VSS = 0 V or floating, GND = 0 V,
Ax = 0 V or floating, VS = ±55 V, see Figure 34
Drain Leakage Current, ID
With Overvoltage ±10 nA typ VDD = +16.5 V, VSS = −16.5 V, GND = 0 V, VS = ±55 V,
see Figure 35
±50
±90
nA max
Power Supplies Grounded ±500 nA typ VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, Ax =
0 V, see Figure 34
±700 ±700 ±700 nA max
Power Supplies Floating ±50 ±50 ±50 µA typ VDD = floating, VSS = floating, GND = 0 V, VS = ±55 V,
Ax = 0 V, see Figure 34
DIGITAL INPUTS
Input Voltage
High, VINH 2.0 V min
Low, VINL 0.8 V max
Input Current, IINL or IINH ±0.7 µA typ VIN = GND or VDD
±1.1 ±1.2 µA max
Digital Input Capacitance, CIN 5.0 pF typ
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 4 of 34
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
Output Voltage
High, VOH 2.0 V min
Low, VOL 0.8 V max
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 210 ns typ RL = 1 kΩ, CL = 35 pF
290 305 310 ns max VS = 10 V, see Figure 50
tON (EN) 200 ns typ RL = 1 kΩ, CL = 35 pF
280 295 315 ns max VS = 10 V, see Figure 49
tOFF (EN) 105 ns typ RL = 1 kΩ, CL = 35 pF
120 160 160 ns max VS = 10 V, see Figure 49
Break-Before-Make Time Delay, tD 155 ns typ RL = 1 kΩ, CL = 35 pF
90
ns min
V
S
= 10 V, see Figure 48
Overvoltage Response Time, tRESPONSE 90 ns typ RL = 1 kΩ, CL = 5 pF, see Figure 43
115 130 130 ns max
Overvoltage Recovery Time, tRECOVERY 745 ns typ RL = 1 kΩ, CL = 5 pF, see Figure 44
945 965 970 ns max
Interrupt Flag Response Time, tDIGRESP 90 ns typ CL = 12 pF, see Figure 45
Interrupt Flag Recovery Time, tDIGREC 65 µs typ CL = 12 pF, see Figure 46
900 ns typ CL = 12 pF, RPULLUP = 1 kΩ, see Figure 47
Charge Injection, QINJ −0.8 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 51
Off Isolation −75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 41, worst
case channel
Channel-to-Channel Crosstalk
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 40
Adjacent Channels −75 dB typ
Nonadjacent Channels −88 dB typ
Total Harmonic Distortion Plus Noise,
THD + N
0.005 % typ RL = 10 kΩ, VS = 15 V p-p, f = 20 Hz to 20 kHz, see
Figure 39
−3 dB Bandwidth RL = 50 Ω, CL = 5 pF, see Figure 42
ADG5248F
190
MHz typ
ADG5249F 320 MHz typ
Insertion Loss 10.5 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 42
CS (Off) 4 pF typ VS = 0 V, f = 1 MHz
CD (Off) VS = 0 V, f = 1 MHz
ADG5248F
13
pF typ
ADG5249F 8 pF typ
CD (On), CS (On) VS = 0 V, f = 1 MHz
ADG5248F 19 pF typ
ADG5249F 14 pF typ
POWER REQUIREMENTS VDD = POSFV = +16.5 V; VSS = NEGFV = −16.5 V;
GND = 0 V; digital inputs = 0 V, 5 V, or VDD
Normal Mode
IDD 1.15 mA typ
IPOSFV 0.15 mA typ
IDD + IPOSFV 2 2 mA max
IGND 0.75 mA typ
1.25 1.25 mA max
ISS 0.45 mA typ
I
NEGFV
0.2
mA typ
ISS + INEGFV 0.8 0.85 mA max
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 5 of 34
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
Fault Mode VS = ±55 V
IDD 1.4 mA typ
IPOSFV 0.2 mA typ
IDD + IPOSFV 2.2 2.3 mA max
IGND 0.9 mA typ
1.6 1.7 mA max
ISS 0.45 mA typ
INEGFV 0.2 mA typ
I
SS
+ I
NEGFV
1.0
1.1
mA max
VDD/VSS ±5 V min GND = 0 V
±22 V max GND = 0 V
1 Guaranteed by design; not subject to production test.
±20 V DUAL SUPPLY
VDD = 20 V ± 10%, VSS = −20 V ± 10%, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 2.
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH VDD = +18 V, VSS = −18 V, see Figure 38
Analog Signal Range VDD to VSS V
On Resistance, R
ON
260
V
S
= ±15 V, I
S
= −1 mA
280 345 405 Ω max
250 Ω typ VS = ±13.5 V, IS = −1 mA
270 335 395 Ω max
On-Resistance Match Between
Channels, ∆RON
2.5 Ω typ VS = ±15 V, IS = −1 mA
6
12
13
2.5 Ω typ VS = ±13.5 V, IS = −1 mA
6 12 13 Ω max
On-Resistance Flatness, RFLAT(ON) 12.5 Ω typ VS = ±15 V, IS = −1 mA
14 15 15 Ω max
1.5
V
S
= ±13.5 V, I
S
= −1 mA
3.5 4 4 Ω max
Threshold Voltage, VT 0.7 V typ See Figure 30
LEAKAGE CURRENTS
V
DD
= +22 V, V
SS
= −22 V
Source Off Leakage, IS (Off ) ±0.1 nA typ VS = ±15 V, VD =
∓
15 V, see Figure 36
±1 ±2 ±5 nA max
Drain Off Leakage, ID (Off ) ±0.1 nA typ VS = ±15 V, VD =
∓
15 V, see Figure 36
±1 ±5 ±10 nA max
Channel On Leakage, ID (On), IS (On) ±0.3 nA typ VS = VD = ±15 V, see Figure 37
±1.5
±20
±25
FAULT
Source Leakage Current, IS
With Overvoltage ±66 µA typ VDD = 22 V, VSS = −22 V, GND = 0 V, VS = ±55 V,
see Figure 35
Power Supplies Grounded or Floating ±25 µA typ VDD = 0 V or floating, VSS = 0 V or floating, GND =
0 V, Ax = 0 V or floating, VS = ±55 V, see Figure 34
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 6 of 34
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
Drain Leakage Current, ID
With Overvoltage ±10 nA typ VDD = +22 V, VSS = −22 V, GND = 0 V, VS = ±55 V,
see Figure 35
±2 ±2 ±2 µA max
Power Supplies Grounded ±500 nA typ VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, Ax =
0 V, see Figure 34
±700 ±700 ±700 nA max
Power Supplies Floating ±50 ±50 ±50 µA typ VDD = floating, VSS = floating, GND = 0 V, VS =
±55 V, Ax = 0 V, see Figure 34
DIGITAL INPUTS
Input Voltage
High, V
INH
2.0
Low, VINL 0.8 V max
Input Current, IINL or IINH ±0.7 µA typ VIN = GND or VDD
±1.1 ±1.2 µA max
Digital Input Capacitance, CIN 5.0 pF typ
Output Voltage
High, VOH 2.0 V min
Low, VOL 0.8 V max
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 230 ns typ RL = 1 kΩ, CL = 35 pF
335 340 340 ns max VS = 10 V, see Figure 50
tON (EN) 225 ns typ RL = 1 kΩ, CL = 35 pF
325 340 340 ns max VS = 10 V, see Figure 49
tOFF (EN) 100 ns typ RL = 1 kΩ, CL = 35 pF
135
155
155
V
S
= 10 V, see Figure 49
Break-Before-Make Time Delay, tD 175 ns typ RL = 1 kΩ, CL = 35 pF
95 ns min VS = 10 V, see Figure 48
Overvoltage Response Time, tRESPONSE 75 ns typ RL = 1 kΩ, CL = 5 pF, see Figure 43
105 105 105 ns max
Overvoltage Recovery Time, tRECOVERY 820 ns typ RL = 1 kΩ, CL = 5 pF, see Figure 44
1100 1250 1400 ns max
Interrupt Flag Response Time, tDIGRESP 75 ns typ CL = 12 pF, see Figure 45
Interrupt Flag Recovery Time, tDIGREC 65 µs typ CL = 12 pF, see Figure 46
1000 ns typ CL = 12 pF, RPULLUP = 1 kΩ, see Figure 47
Charge Injection, QINJ −1.2 pC typ VS = 0 V, RS = 0 Ω, CL = 1 nF, see Figure 51
Off Isolation
−75
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 41,
worst case channel
Channel-to-Channel Crosstalk RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
Adjacent Channels −75 dB typ
Nonadjacent Channels −88 dB typ
Total Harmonic Distortion Plus Noise,
THD + N
0.005 % typ RL = 10 kΩ, VS = 20 V p-p, f = 20 Hz to 20 kHz,
see Figure 39
−3 dB Bandwidth RL = 50 Ω, CL = 5 pF, see Figure 42
ADG5248F 190 MHz typ
ADG5249F 320 MHz typ
Insertion Loss 10.5 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 42
C
S
(Off)
4
V
S
= 0 V, f = 1 MHz
CD (Off) VS = 0 V, f = 1 MHz
ADG5248F 13 pF typ
ADG5249F 8 pF typ
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 7 of 34
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
CD (On), CS (On) VS = 0 V, f = 1 MHz
ADG5248F 19 pF typ
ADG5249F 14 pF typ
POWER REQUIREMENTS VDD = POSFV = +22 V; VSS = NEGFV = −22 V;
digital inputs = 0 V, 5 V, or VDD
Normal Mode
IDD 1.15 mA typ
IPOSFV 0.15 mA typ
IDD + IPOSFV 2 2 mA max
IGND 0.75 mA typ
1.25 1.25 mA max
I
SS
0.45
INEGFV 0.2 mA typ
ISS + INEGFV 0.8 0.85 mA max
Fault Mode VS = ±55 V
IDD 1.4 mA typ
IPOSFV 0.2 mA typ
IDD + IPOSFV 2.2 2.3 mA max
IGND 0.9 mA typ
1.6 1.7 mA max
ISS 0.45 mA typ
INEGFV 0.2 mA typ
I
SS
+ I
NEGFV
1.0
1.1
VDD/VSS ±5 V min GND = 0 V
±22 V max GND = 0 V
1 Guaranteed by design; not subject to production test.
12 V SINGLE SUPPLY
VDD = 12 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 3.
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH VDD = 10.8 V, VSS = 0 V, see Figure 38
Analog Signal Range 0 V to VDD V
On Resistance, R
ON
630
Ω typ
V
S
= 0 V to 10 V, I
S
= −1 mA
690 710 730 Ω max
270 Ω typ VS = 3.5 V to 8.5 V, IS = −1 mA
290 355 410 Ω max
On-Resistance Match Between
Channels, ∆RON
6 Ω typ VS = 0 V to 10 V, IS = −1 mA
17 19 19 Ω max
3 Ω typ VS = 3.5 V to 8.5 V, IS = −1 mA
6.5 11 12 Ω max
On-Resistance Flatness, RFLAT(ON) 380 Ω typ VS = 0 V to 10 V, IS = −1 mA
440 460 460 Ω max
25
Ω typ
V
S
= 3.5 V to 8.5 V, I
S
= −1 mA
27 28 28 Ω max
Threshold Voltage, VT 0.7 V typ See Figure 30
LEAKAGE CURRENTS
V
DD
= 13.2 V, V
SS
= 0 V
Source Off Leakage, IS (Off ) ±0.1 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 36
±1 ±2 ±5 nA max
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 8 of 34
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
Drain Off Leakage, ID (Off ) ±0.1 nA typ VS = 1 V/10 V, VD = 10 V/1 V, see Figure 36
±1 ±5 ±10 nA max
Channel On Leakage, ID (On), IS (On) ±0.3 nA typ VS = VD = 1 V/10 V, see Figure 37
±1.5 ±20 ±25 nA max
FAULT
Source Leakage Current, IS
With Overvoltage ±63 µA typ VDD = 13.2 V, VSS = 0 V, GND = 0 V, VS = ±55 V,
see Figure 35
Power Supplies Grounded or Floating ±25 µA typ VDD = 0 V or floating, VSS = 0 V or floating, GND =
0 V, Ax = 0 V or floating, VS = ±55 V, see Figure 34
Drain Leakage Current, ID
With Overvoltage
±10
nA typ
V
DD
= 13.2 V, V
SS
= 0 V, GND = 0 V, V
S
= ±55 V,
see Figure 35
±50 ±70 ±90 nA max
Power Supplies Grounded ±500 nA typ VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, Ax =
0 V, see Figure 34
±700 ±700 ±700 nA max
Power Supplies Floating ±50 ±50 ±50 µA typ VDD = floating, VSS = floating, GND = 0 V, VS =
±55 V, Ax = 0 V, see Figure 34
DIGITAL INPUTS
Input Voltage
High, VINH 2.0 V min
Low, VINL 0.8 V max
Input Current, IINL or IINH ±0.7 µA typ VIN = GND or VDD
±1.1 ±1.2 µA max
Digital Input Capacitance, C
IN
5.0
pF typ
Output Voltage
High, VOH 2.0 V min
Low, VOL 0.8 V max
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 165 ns typ RL = 1 kΩ, CL = 35 pF
205 215 230 ns max VS = 8 V, see Figure 50
tON (EN) 160 ns typ RL = 1 kΩ, CL = 35 pF
200
215
230
ns max
V
S
= 8 V, see Figure 49
tOFF (EN) 125 ns typ RL = 1 kΩ, CL = 35 pF
150 155 155 ns max VS = 8 V, see Figure 49
Break-Before-Make Time Delay, tD 100 ns typ RL = 1 kΩ, CL = 35 pF
60 ns min VS = 8 V, see Figure 48
Overvoltage Response Time, tRESPONSE 110 ns typ RL = 1 kΩ, CL = 5 pF, see Figure 43
145
145
145
ns max
Overvoltage Recovery Time, tRECOVERY 500 ns typ RL = 1 kΩ, CL = 5 pF, see Figure 44
655 720 765 ns max
Interrupt Flag Response Time, tDIGRESP 95 ns typ CL = 12 pF, see Figure 45
Interrupt Flag Recovery Time, tDIGREC 65 µs typ CL = 12 pF, see Figure 46
900 ns typ CL = 12 pF, RPULLUP = 1 kΩ, see Figure 47
Charge Injection, QINJ 0.2 pC typ VS = 6 V, RS = 0 Ω, CL = 1 nF, see Figure 51
Off Isolation −75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 41,
worst case channel
Channel-to-Channel Crosstalk RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
Adjacent Channels −75 dB typ
Nonadjacent Channels
−88
dB typ
Total Harmonic Distortion Plus Noise,
THD + N
0.044 % typ RL = 10 kΩ, VS = 6 V p-p, f = 20 Hz to 20 kHz,
see Figure 39
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 9 of 34
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
−3 dB Bandwidth RL = 50 Ω, CL = 5 pF, see Figure 42
ADG5248F 175 MHz typ
ADG5249F 290 MHz typ
Insertion Loss 10.5 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 42
CS (Off) 4 pF typ VS = 6 V, f = 1 MHz
CD (Off) VS = 6 V, f = 1 MHz
ADG5248F 14 pF typ
ADG5249F 8 pF typ
C
D
(On), C
S
(On)
V
S
= 6 V, f = 1 MHz
ADG5248F 20 pF typ
ADG5249F 14 pF typ
POWER REQUIREMENTS
VDD = 13.2 V; VSS = 0 V; digital inputs = 0 V, 5 V,
or VDD
Normal Mode
IDD 1.15 mA typ
IPOSFV 0.15 mA typ
IDD + IPOSFV 2 2 mA max
IGND 0.75 mA typ
1.4 1.4 mA max
ISS 0.3 mA typ
INEGFV 0.2 mA typ
ISS + INEGFV 0.65 0.7 mA max
Fault Mode
V
S
= ±55 V
IDD 1.4 mA typ
IPOSFV 0.2 mA typ
IDD + IPOSFV 2.2 2.3 mA max
IGND 0.9 mA typ
1.6 1.7 mA max
I
SS
0.45
mA typ
Digital inputs = 5 V
INEGFV 0.2 mA typ
ISS + INEGFV 1.0 1.1 mA max VS = ±55 V, VD = 0 V
VDD 8 V min GND = 0 V
44 V max GND = 0 V
1 Guaranteed by design; not subject to production test.
36 V SINGLE SUPPLY
VDD = 36 V ± 10%, VSS = 0 V, GND = 0 V, CDECOUPLING = 0.1 µF, unless otherwise noted.
Table 4.
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
ANALOG SWITCH VDD = 32.4 V, VSS = 0 V, see Figure 38
Analog Signal Range 0 V to VDD V
On Resistance, RON 310 Ω typ VS = 0 V to 30 V, IS = −1 mA
335 415 480 Ω max
250 Ω typ VS = 4.5 V to 28 V, IS = −1 mA
270
335
395
Ω max
On-Resistance Match Between
Channels, ∆RON
3 Ω typ VS = 0 V to 30 V, IS = −1 mA
7 16 18 Ω max
3 Ω typ VS = 4.5 V to 28 V, IS = −1 mA
6.5 11 12 Ω max
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 10 of 34
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
On-Resistance Flatness, RFLAT(ON) 62 Ω typ VS = 0 V to 30 V, IS = −1 mA
70 85 100 Ω max
1.5 Ω typ VS = 4.5 V to 28 V, IS = −1 mA
3.5 4 4 Ω max
Threshold Voltage, VT 0.7 V typ See Figure 30
LEAKAGE CURRENTS VDD = 39.6 V, VSS = 0 V
Source Off Leakage, IS (Off ) ±0.1 nA typ VS = 1 V/30 V, VD = 30 V/1 V, see Figure 36
±1 ±2 ±5 nA max
Drain Off Leakage, ID (Off ) ±0.1 nA typ VS = 1 V/30 V, VD = 30 V/1 V, see Figure 36
±1 ±5 ±10 nA max
Channel On Leakage, ID (On), IS (On) ±0.3 nA typ VS = VD = 1 V/30 V, see Figure 37
±1.5
±20
±25
nA max
FAULT
Source Leakage Current, IS
With Overvoltage
±58
µA typ
VDD = 39.6 V, VSS = 0 V, GND = 0 V, VS = +55 V,
−40 V, see Figure 35
Power Supplies Grounded or
Floating
±25 µA typ VDD = 0 V or floating, VSS = 0 V or floating, GND =
0 V, Ax = 0 V or floating, VS = ±55 V, see Figure 34
Drain Leakage Current, ID
With Overvoltage
±10
nA typ
V
DD
= 39.6 V, V
SS
= 0 V, GND = 0 V, V
S
= +55 V,
−40 V, see Figure 35
±50 ±70 ±90 nA max
Power Supplies Grounded ±500 nA typ VDD = 0 V, VSS = 0 V, GND = 0 V, VS = ±55 V, Ax =
0 V, see Figure 34
±700 ±700 ±700 nA max
Power Supplies Floating
±50
±50
±50
µA typ
VDD = floating, VSS = floating, GND = 0 V, VS = ±55 V,
Ax = 0 V, see Figure 34
DIGITAL INPUTS
Input Voltage
High, VINH 2.0 V min
Low, VINL 0.8 V max
Input Current, IINL or IINH ±0.7 µA typ VIN = VGND or VDD
±1.1 ±1.2 µA max
Digital Input Capacitance, C
IN
5.0
pF typ
Output Voltage
High, VOH 2.0 V min
Low, VOL 0.8 V max
DYNAMIC CHARACTERISTICS1
Transition Time, tTRANSITION 195 ns typ RL = 1 kΩ, CL = 35 pF
255 275 285 ns max VS = 18 V, see Figure 50
tON (EN) 190 ns typ RL = 1 kΩ, CL = 35 pF
245 270 280 ns max VS = 18 V, see Figure 49
tOFF (EN) 105 ns typ RL = 1 kΩ, CL = 35 pF
135 145 145 ns max VS = 18 V, see Figure 49
Break-Before-Make Time Delay, tD 110 ns typ RL = 1 kΩ, CL = 35 pF
60 ns min VS = 18 V, see Figure 48
Overvoltage Response Time, tRESPONSE 60 ns typ RL = 1 kΩ, CL = 5 pF, see Figure 43
80
85
85
ns max
Overvoltage Recovery Time, tRECOVERY 1400 ns typ RL = 1 kΩ, CL = 5 pF, see Figure 44
1900 2100 2200 ns max
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 11 of 34
Parameter +25°C
−40°C to
+85°C
−40°C to
+125°C Unit Test Conditions/Comments
Interrupt Flag Response Time, tDIGRESP 85 ns typ CL = 12 pF, see Figure 45
Interrupt Flag Recovery Time, tDIGREC 65 µs typ CL = 12 pF, see Figure 46
1600 ns typ CL = 12 pF, RPULLUP = 1 kΩ, see Figure 47
Charge Injection, QINJ −1.2 pC typ VS = 18 V, RS = 0 Ω, CL = 1 nF, see Figure 51
Off Isolation −75 dB typ RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 41,
worst case channel
Channel-to-Channel Crosstalk RL = 50 Ω, CL = 5 pF, f = 1 MHz, see Figure 40
Adjacent Channels −75 dB typ
Nonadjacent Channels
−88
dB typ
Total Harmonic Distortion Plus Noise,
THD + N
0.007 % typ RL = 10 kΩ, VS = 18 V p-p, f = 20 Hz to 20 kHz,
see Figure 39
−3 dB Bandwidth RL = 50 Ω, CL = 5 pF, see Figure 42
ADG5248F 200 MHz typ
ADG5249F 320 MHz typ
Insertion Loss
10.5
dB typ
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz, see Figure 42
CS (Off) 4 pF typ VS = 18 V, f = 1 MHz
CD (Off) VS = 18 V, f = 1 MHz
ADG5248F 13 pF typ
ADG5249F 7 pF typ
C
D
(On), C
S
(On)
V
S
= 18 V, f = 1 MHz
ADG5248F 18 pF typ
ADG5249F 12 pF typ
POWER REQUIREMENTS
V
DD
= 39.6 V; V
SS
= 0 V; digital inputs = 0 V, 5 V, or V
DD
Normal Mode
IDD 1.15 mA typ
IPOSFV 0.15 mA typ
IDD + IPOSFV 2 2 mA max
IGND 0.75 mA typ
1.4
1.4
mA max
ISS 0.3 mA typ
INEGFV 0.2 mA typ
ISS + INEGFV 0.65 0.7 mA max
Fault Mode VS = +55 V, −40 V
I
DD
1.4
mA typ
IPOSFV 0.2 mA typ
IDD + IPOSFV 2.2 2.3 mA max
IGND 0.9 mA typ
1.6 1.7 mA max
ISS 0.45 mA typ
I
NEGFV
0.2
mA typ
ISS + INEGFV 1.0 1.1 mA max
VDD 8 V min GND = 0 V
44 V max GND = 0 V
1 Guaranteed by design; not subject to production test.
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 12 of 34
CONTINUOUS CURRENT PER CHANNEL, Sx,1 D, OR Dx
Table 5.
Parameter 25°C 85°C 125°C Unit Test Conditions/Comments
ADG5248F
20-Lead TSSOP, θJA = 112.6°C/W 27 16 8 mA max VS = VSS to VDD − 4.5 V
16 11 7 mA max VS = VSS to VDD
20-Lead LFCSP, θJA = 30.4°C/W 48 25 11 mA max VS = VSS to VDD − 4.5 V
27 17 9 mA max VS = VSS to VDD
ADG5249F
20-Lead TSSOP, θJA = 112.6°C/W 20 13 8 mA max VS = VSS to VDD − 4.5 V
12 8 6 mA max VS = VSS to VDD
20-Lead LFCSP, θJA = 30.4°C/W 36 20 10 mA max VS = VSS to VDD − 4.5 V
21 13 8 mA max VS = VSS to VDD
1 Sx is the S1 to S8 pins on the ADG5248F, and the S1A to S4A and S1B to S4B pins on the ADG5249F.
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 13 of 34
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 6.
Parameter Rating
VDD to VSS 48 V
VDD to GND −0.3 V to +48 V
VSS to GND −48 V to +0.3 V
POSFV to GND −0.3 V to VDD + 0.3 V
NEGFV to GND VSS − 0.3 V to + 0.3 V
Sx Pins −55 V to +55 V
Sx to VDD or VSS 80 V
VS to VD 80 V
D or Dx Pins1 NEGFV − 0.7 V to POSFV +
0.7 V or 30 mA, whichever
occurs first
Digital Inputs GND − 0.7 V to 48 V or
30 mA, whichever occurs first
Peak Current, Sx, D, or Dx Pins 72.5 mA (pulsed at 1 ms,
10% duty cycle maximum)
Continuous Current, Sx, D, or Dx
Pins
Data2 + 15%
Digital Outputs
GND − 0.7 V to 6 V or 30 mA,
whichever occurs first
D or Dx Pins, Overvoltage State,
Load Current
1 mA
Operating Temperature Range −40°C to +125°C
Storage Temperature Range −65°C to +150°C
Junction Temperature
150°C
Thermal Impedance, θJA (4-Layer
Board)
20-Lead TSSOP 112.6°C/W
20-Lead LFCSP 30.4°C/W
Reflow Soldering Peak
Temperature, Pb-Free
As per JEDEC J-STD-020
1 Overvoltages at the D or Dx pins are clamped by internal diodes. Limit the
current to the maximum ratings given.
2 See Table 5.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Only one absolute maximum rating can be applied at any
one time.
ESD CAUTION
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 14 of 34
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
A0/F0
1
EN/F2
2
V
SS 3
S1
4
A1/F1
20
A2
19
GND
18
V
DD
17
S2
5
S5
16
S3
6
S6
15
S4
7
D
7
NEGFV
9
SF
10
S7
14
S8
13
POSFV
12
FF
11
8
ADG5248F
TOP VIEW
(No t t o Scal e)
13072-003
Figure 3. ADG5248F Pin Configuration (TSSOP)
14
13
12
1
3
4
S5
15
V
DD
S6
S7
11 S8
V
SS
S2 2
S1
S3 5
S4
7
NEGFV 6
D
8
SF 9
FF10
POSFV
19 A0/F0
20 EN/F2
18 A1/F1
17 A2
16 GND
NOTES
1. THE EX P OSE D P AD IS CO NNE CTED I NTERNAL LY. FO R
INCREAS E D RE LI ABILITY OF THE S O LDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, I T I S RECOMMENDED
THAT THE P AD BE S OLDE RE D TO THE SUBS TRAT E , V
SS
.
ADG5248F
TOP VIEW
(No t t o Scal e)
13072-004
Figure 4. ADG5248F Pin Configuration (LFCSP)
Table 7. ADG5248F Pin Function Descriptions
Pin No.
TSSOP
LFCSP
Mnemonic
Description
1 19 A0/F0 Logic Control Input (A0). See Table 8.
Decoder Pin (F0). This pin is used together with the specific fault pin (SF) to indicate which input is
in a fault condition. See Table 9.
2 20 EN/F2 Active High Digital Input (EN). When this pin is low, the device is disabled and all switches are off.
When this pin is high, the Ax logic inputs determine the on switches.
Decoder Pin (F2). This pin is used together with the specific fault pin (SF) to indicate which input is
in a fault condition. See Table 9.
3
1
VSS
Most Negative Power Supply Potential.
4
2
S1
Overvoltage Protected Source Terminal 1. This pin can be an input or an output.
5
3
S2
Overvoltage Protected Source Terminal 2. This pin can be an input or an output.
6
4
S3
Overvoltage Protected Source Terminal 3. This pin can be an input or an output.
7
5
S4
Overvoltage Protected Source Terminal 4. This pin can be an input or an output.
8
6
D
Drain Terminal. This pin can be an input or an output.
9 7 NEGFV Negative Fault Voltage. This pin is the negative supply voltage that determines the overvoltage
protection level. If a secondary supply is not used, connect this pin to VSS.
10 8 SF Specific Fault Digital Output. This pin has a high output (weak internal pull-up resistor, nominally 3
V output) when the device is in normal operation, or a low output when a fault condition is
detected on a specific pin, depending on the state of F0, F1, and F2 as shown in Table 9.
11 9 FF Fault Flag Digital Output. This pin has a high output when the device is in normal operation, or a
low output when a fault condition occurs on any of the Sx inputs. The FF pin has a weak internal
pull-up resistor that allows multiple signals to be combined into a single interrupt for larger
modules that contain multiple devices.
12 10 POSFV Positive Fault Voltage. This pin is the positive supply voltage that determines the overvoltage
protection level. If a secondary supply is not used, connect this pin to V
DD
.
13
11
S8
Overvoltage Protected Source Terminal 8. This pin can be an input or an output.
14
12
S7
Overvoltage Protected Source Terminal 7. This pin can be an input or an output.
15
13
S6
Overvoltage Protected Source Terminal 6. This pin can be an input or an output.
16
14
S5
Overvoltage Protected Source Terminal 5. This pin can be an input or an output.
17
15
V
DD
Most Positive Power Supply Potential.
18
16
GND
Ground (0 V) Reference.
19
17
A2
Logic Control Input.
20 18 A1/F1 Logic Control Input (A1). See Table 8.
Decoder Pin (F1). This pin is used together with the specific fault pin (SF) to indicate which input is
in a fault condition. See Table 9.
Not
Applicable
Exposed
Pad
EP Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints
and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 15 of 34
Table 8. ADG5248F Switch Selection Truth Table
A2 A1 A0 EN On Switch
X1 X1 X1 0 None
0 0 0 1 S1
0 0 1 1 S2
0 1 0 1 S3
0 1 1 1 S4
1 0 0 1 S5
1 0 1 1 S6
1 1 0 1 S7
1 1 1 1 S8
1 X is don’t care.
Table 9. ADG5248F Fault Diagnostic Output Truth Table
State of Specific Flag (SF) with Control Inputs (F2, F1, F0)
Switch in Fault1 0, 0, 0 0, 0, 1 0, 1, 0 0, 1, 1 1, 0, 0 1, 0, 1 1, 1, 0 1, 1, 1 State of the Fault Flag (FF)
None 1 1 1 1 1 1 1 1 1
S1 0 1 1 1 1 1 1 1 0
S2 1 0 1 1 1 1 1 1 0
S3 1 1 0 1 1 1 1 1 0
S4 1 1 1 0 1 1 1 1 0
S5 1 1 1 1 0 1 1 1 0
S6 1 1 1 1 1 0 1 1 0
S7
1
1
1
1
1
1
0
1
0
S8 1 1 1 1 1 1 1 0 0
1 More than one switch can be in fault. See the Applications Information section for more information.
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 16 of 34
A0/F0
1
EN/F2
2
V
SS 3
S1A
4
A1/F1
20
GND
19
V
DD
18
S1B
17
S2A
5
S2B
16
S3A
6
S3B
15
S4A
7
DA
7
NEGFV
9
SF
10
S4B
14
DB
13
POSFV
12
FF
11
8
ADG5249F
TOP VIEW
(No t t o Scal e)
13072-005
Figure 5. ADG5249F Pin Configuration (TSSOP)
14
13
12
1
3
4
S2B
15
S1B
S3B
S4B
11 DB
V
SS
S2A 2
S1A
S3A 5
S4A
7
NEGFV 6
DA
8
SF 9
FF10
POSFV
19 A0/F0
20 EN/F2
18 A1/F1
17 GND
16 V
DD
NOTES
1. THE EX P OSE D P AD IS CO NNE CTED I NTERNAL LY. FO R
INCREAS E D RE LI ABILITY OF THE S O LDER JOINTS AND
MAXIMUM THERMAL CAPABILITY, I T I S RECOMMENDED
THAT THE P AD BE S OLDE RE D TO THE SUBS TRAT E , V
SS
.
ADG5249F
TOP VIEW
(No t t o Scal e)
13072-006
Figure 6. ADG5249F Pin Configuration (LFCSP)
Table 10. ADG5249F Pin Function Descriptions
Pin No.
TSSOP LFCSP Mnemonic Description
1 19 A0/F0 Logic Control Input (A0). See Table 11.
Decoder Pin (F0). This pin is used together with the specific fault pin (SF) to indicate which input is
in a fault condition. See Table 12.
2 20 EN/F2 Active High Digital Input (EN). When this pin is low, the device is disabled and all switches are off.
When this pin is high, the Ax logic inputs determine the on switches.
Decoder Pin (F2). This pin is used together with the specific fault pin (SF) to indicate which input is
in a fault condition. See Table 12.
3 1 VSS Most Negative Power Supply Potential.
4 2 S1A Overvoltage Protected Source Terminal 1A. This pin can be an input or an output.
5 3 S2A Overvoltage Protected Source Terminal 2A. This pin can be an input or an output.
6 4 S3A Overvoltage Protected Source Terminal 3A. This pin can be an input or an output.
7 5 S4A Overvoltage Protected Source Terminal 4A. This pin can be an input or an output.
8 6 DA Drain Terminal A. This pin can be an input or an output.
9 7 NEGFV Negative Fault Voltage. This pin is the negative supply voltage that determines the overvoltage
protection level. If a secondary supply is not used, connect this pin to VSS.
10 8 SF Specific Fault Digital Output. This pin has a high output (weak internal pull-up resistor, nominally
3 V output) when the device is in normal operation, or a low output when a fault condition is
detected on a specific pin, depending on the state of F0, F1, and, F2 as shown in Table 12.
11 9 FF Fault Flag Digital Output. This pin has a high output when the device is in normal operation, or a
low output when a fault condition occurs on any of the Sx inputs. The FF pin has a weak internal
pull-up resistor that allows multiple signals to be combined into a single interrupt for larger
modules that contain multiple devices.
12
10
POSFV
Positive Fault Voltage. This pin is the positive supply voltage that determines the overvoltage
protection level. If a secondary supply is not used, connect this pin to VDD.
13 11 DB Drain Terminal B. This pin can be an input or an output.
14 12 S4B Overvoltage Protected Source Terminal 4B. This pin can be an input or an output.
15 13 S3B Overvoltage Protected Source Terminal 3B. This pin can be an input or an output.
16 14 S2B Overvoltage Protected Source Terminal 2B. This pin can be an input or an output.
17 15 S1B Overvoltage Protected Source Terminal 1B. This pin can be an input or an output.
18 16 VDD Most Positive Power Supply Potential.
19 17 GND Ground (0 V) Reference.
20 18 A1/F1 Logic Control Input (A1). See Table 11.
Decoder Pin (F1). This pin is used together with the specific fault pin (SF) to indicate which input is
in a fault condition. See Table 12.
Not
Applicable
Exposed
Pad
EP Exposed Pad. The exposed pad is connected internally. For increased reliability of the solder joints
and maximum thermal capability, it is recommended that the pad be soldered to the substrate, VSS.
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 17 of 34
Table 11. ADG5249F Switch Selection Truth Table
A1 A0 EN On Switch Pair
X1 X1 0 None
0 0 1 S1x
0 1 1 S2x
1 0 1 S3x
1 1 1 S4x
1 X is don’t care.
Table 12. ADG5249F Fault Diagnostic Output Truth Table
State of Specific Flag (SF) with Control Inputs (F2, F1, F0)
Switch in Fault1 0, 0, 0 0, 0, 1 0, 1, 0 0, 1, 1 1, 0, 0 1, 0, 1 1, 1, 0 1, 1, 1 State of the Fault Flag (FF)
None
1
1
1
1
1
1
1
1
1
S1A 0 1 1 1 1 1 1 1 0
S2A 1 0 1 1 1 1 1 1 0
S3A 1 1 0 1 1 1 1 1 0
S4A 1 1 1 0 1 1 1 1 0
S1B 1 1 1 1 0 1 1 1 0
S2B 1 1 1 1 1 0 1 1 0
S3B 1 1 1 1 1 1 0 1 0
S4B 1 1 1 1 1 1 1 0 0
1 More than one switch can be in fault. See the Applications Information section for more information.
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 18 of 34
TYPICAL PERFORMANCE CHARACTERISTICS
1200
1000
800
600
400
200
0
–25 –20 –15 –10 –5 0 5 10 15 20 25
ON RESISTANCE (Ω)
VS, VD (V)
±22V
±20V
±18V
±16.5V
±15.0V
±13.5V
TA = 25° C
13072-105
Figure 7. RON as a Function of VS, VD, Dual Supply
1200
1000
800
600
400
200
00141210864
2
ON RESISTANCE (Ω)
VS, VD (V)
13.2V
12.0V
10.8V
TA = 25° C
13072-106
Figure 8. RON as a Function of VS, VD, 12 V Single Supply
1200
1000
800
600
400
200
00403530252015105
ON RESISTANCE (Ω)
VS, VD (V)
39.6V
36.0V
32.4V
TA = 25° C
13072-107
Figure 9. RON as a Function of VS, VD, 36 V Single Supply
1400
1200
1000
800
600
400
200
0
–15 –12 –9 –6 –3 036912 15
ON RESISTANCE (Ω)
V
S
, V
D
(V)
V
DD
= +15V
V
SS
= –15V
+125°C
+85°C
+25°C
–40°C
13072-108
Figure 10. RON as a Function of VS, VD for Different Temperatures,
±15 V Dual Supply
1400
1200
1000
800
600
400
200
0
–20 –15 –10 –5 0 5 10 15 20
ON RESISTANCE (Ω)
V
S
, V
D
(V)
V
DD
= +20V
V
SS
= –20V
+125°C
+85°C
+25°C
–40°C
13072-109
Figure 11. RON as a Function of VS, VD for Different Temperatures,
±20 V Dual Supply
1400
1200
1000
800
600
400
200
0012108
642
ON RESISTANCE (Ω)
VS, VD (V)
VDD = 12V
VSS = 0V
+125°C
+85°C
+25°C
–40°C
13072-110
Figure 12. RON as a Function of VS, VD for Different Temperatures,
12 V Single Supply
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 19 of 34
1400
1200
1000
800
600
400
200
003632282420161284
ON RESISTANCE (Ω)
V
S
, V
D
(V)
V
DD
= 36V
V
SS
= 0V
+125°C
+85°C
+25°C
–40°C
13072-111
Figure 13. RON as a Function of VS, VD for Different Temperatures,
36 V Single Supply
2.5
–2.0
–1.5
–1.0
–0.5
0
0.5
1.0
1.5
2.0
012010080604020
LE AKAG E CURRE NT (nA)
TEMPERATURE (°C)
VDD = + 15V
VSS = –15V
VBIAS = ±10V
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
13072-112
Figure 14. Leakage Current vs. Temperature, ±15 V Dual Supply
3
–3
–2
–1
0
1
2
012010080604020
LE AKAG E CURRE NT (nA)
TEMPERATURE (°C)
VDD = + 20V
VSS = –20V
VBIAS = ±15V
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
13072-113
Figure 15. Leakage Current vs. Temperature, ±20 V Dual Supply
1.5
–1.0
–0.5
0
0.5
1.0
012010080604020
LE AKAG E CURRE NT (nA)
TEMPERATURE (°C)
V
DD
= 12V
V
SS
= 0V
V
BIAS
= 1V, 10V
I
S
(OFF) + –
I
S
(OFF) – +
I
S
, I
D
(ON) + +
I
D
(OFF) + –
I
D
(OFF) – +
I
S
, I
D
(O N) – –
13072-114
Figure 16. Leakage Current vs. Temperature, 12 V Single Supply
3
–4
–3
–2
–1
0
1
2
012010080604020
LE AKAG E CURRE NT (nA)
TEMPERATURE (°C)
VDD = 36V
VSS = 0V
VBIAS = 1V , 30V
IS (OFF) + –
IS (OFF) – +
IS, ID (ON) + +
ID (OFF) + –
ID (OFF) – +
IS, ID (ON) – –
13072-115
Figure 17. Leakage Current vs. Temperature, 36 V Single Supply
6
0
1
2
3
4
5
012010080604020
LE AKAG E CURRE NT (nA)
TEMPERATURE (°C)
VDD = + 15V
VSS = –15V
VS = –30V
VS = +30V
VS = –55V
VS = +55V
13072-116
Figure 18. Overvoltage Leakage Current vs. Temperature, ±15 V Dual Supply
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 20 of 34
6
0
1
2
3
4
5
012010080604020
LE AKAG E CURRE NT (nA)
TEMPERATURE (°C)
VDD = + 20V
VSS = –20V
VS = –30V
VS = +30V
VS = –55V
VS = +55V
13072-117
Figure 19. Overvoltage Leakage Current vs. Temperature, ±20 V Dual Supply
6
0
1
2
3
4
5
0120100
80604020
LE AKAG E CURRE NT (nA)
TEMPERATURE (°C)
VDD = 12V
VSS = 0V
VS = –30V
VS = +30V
VS = –55V
VS = +55V
13072-118
Figure 20. Overvoltage Leakage Current vs. Temperature, 12 V Single Supply
6
0
1
2
3
4
5
012010080604020
LE AKAG E CURRE NT (nA)
TEMPERATURE (°C)
VDD = 36V
VSS = 0V
VS = –30V
VS = +40V
VS = –40V
VS = +55V
13072-119
Figure 21. Overvoltage Leakage Current vs. Temperature, 36 V Single Supply
OFF ISOLATION (dB)
FRE Q UE NCY ( Hz )
0
–140
–120
–100
–80
–60
–40
–20
1k 1G100M10M1M100k10k
V
DD
= +15V
V
SS
= –15V
T
A
= 25° C
13072-120
Figure 22. Off Isolation vs. Frequency, ±15 V Dual Supply
0
–140
–120
–100
–80
–60
–40
–20
10k 1G100M
10M
1M100k
CROSS TAL K ( dB)
FRE QUENCY ( Hz )
VDD = + 15V
VSS = –15V
TA = 25° C
ADJACENT CHANNE LS
NONADJACE NT CHANNEL S , COM M ON DRAIN
NONADJACE NT CHANNEL S , SEP ARATE DRAI N
13072-121
Figure 23. Crosstalk vs. Frequency, ±15 V Dual Supply
6
4
2
0
–2
–10
–8
–6
–4
0403530252015105
CHARGE INJECTION (p C)
V
S
(V)
T
A
= 25° C
V
DD
= 12V, V
SS
= 0V
V
DD
= 36V, V
SS
= 0V
13072-122
Figure 24. Charge Injection vs. Source Voltage (VS), Single Supply
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 21 of 34
8
6
4
2
0
–2
–10
–8
–6
–4
–20 201510
5
0–5
–10–15
CHARGE INJECTION (p C)
V
S
(V)
T
A
= 25° C
V
DD
= +15V, V
SS
= –15V
V
DD
= +20V, V
SS
= –20V
13072-123
Figure 25. Charge Injection vs. Source Voltage (VS), Dual Supply
0
–120
–100
–80
–60
–40
–20
10k 1G100M10M1M100k
ACPSRR (dB)
FREQUENCY ( Hz )
V
DD
= +15V
V
SS
= –15V
T
A
= 25° C
13072-124
Figure 26. ACPSRR vs. Frequency, ±15 V Dual Supply
0.06
0.05
0.04
0.03
0.02
0.01
002015105
THD + N ( %)
FRE Q UE NCY ( kHz )
LOAD = 10kΩ
T
A
= 25° C
V
DD
= +12V, V
SS
= 0V, V
S
= +6V p-p
V
DD
= +36V, V
SS
= 0V, V
S
= +18V p-p
V
DD
= +15V, V
SS
= –15V, V
S
= +15V p-p
V
DD
= +20V, V
SS
= –20V, V
S
= +20V p-p
13072-125
Figure 27. THD + N vs. Frequency
–9
–20
–19
–15
–16
–17
–18
–14
–13
–12
–11
–10
10k 1G100M
10M1M
100k
BANDWIDTH ( dB)
FRE Q UE NCY ( Hz )
V
DD
= +15V
V
SS
= –15V
T
A
= 25° C
ADG5248F
ADG5249F
13072-126
Figure 28. Bandwidth vs. Frequency
tTRANSITION
(n s)
TEMPERATURE (°C)
140
160
180
190
280
260
240
220
–40 –20 020 40 60 80 100 120
V
DD
= +12V, V
SS
= 0V
V
DD
= +36V, V
SS
= 0V
V
DD
= +15V, V
SS
= –15V
V
DD
= +20V, V
SS
= –20V
13072-127
Figure 29. tTRANSITION vs. Temperature
THRESHOLD VOLTAGE, V
T
(V)
TEMPERATURE (°C)
0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
–40 –20 020 40 60 80 100 120
13072-128
Figure 30. Threshold Voltage (VT) vs. Temperature
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 22 of 34
CH1 10V CH2 10V
CH3 10V CH4 10V 1µs A CH1 15.2V
2
T –10.0ns 2.5GS/s
100k POINT S
T
POSFV
NEGFV
V
S
DRAIN
13072-129
Figure 31. Drain Output Response to Positive Overvoltage
CH1 10V CH2 10V
CH3 10V CH4 10V 1µs A CH1 –15.6V
2
T –10.0ns
2.5GS/s
100k POINT S
T
POSF
NEGFV
V
S
DRAIN
13072-130
Figure 32. Drain Output Response to Negative Overvoltage
SIGNAL VOLTAGE (V p-p)
FREQUENCY (MHz)
0
20
16
12
8
4
110 100
DISTORTIONLESS
OPERATING REGION
TA = 25° C
VDD = + 10V
VSS = –10V
13072-131
Figure 33. Large Signal Voltage Tracking vs. Frequency
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 23 of 34
TEST CIRCUITS
V
S
Sx
V
DD
= V
SS
= GND = 0V
D/Dx
A A
I
S
I
D
R
L
10kΩ
13072-040
Figure 34. Switch Unpowered Leakage
|V
S
| > |V
DD
| OR |V
SS
|
Sx D/Dx
A A
I
S
I
D
R
L
10kΩ
13072-039
Figure 35. Switch Overvoltage Leakage
VD
S1 D
A A
IS (OFF) ID (OFF)
VS
S8
A
ADG5248F*
*SIM IL AR CONNECT ION FOR ADG5249F.
13072-035
Figure 36. Off Leakage
V
D
S1 DA
NC
I
D
(ON)
V
S
S8
A
S2
NC = NO CONNECT
ADG5248F*
*SIM IL AR CONNECT ION FOR ADG5249F.
13072-036
Figure 37. On Leakage
IDS
Sx D/Dx
VS
V
RON = V/IDS
13072-034
Figure 38. On Resistance
V
OUT
R
S
AUDIO
PRECISION
R
L
10kΩ
Ax
V
IN
Sx
D/Dx
V
S
V p-p
V
DD
V
SS
0.1µFV
DD
0.1µF
V
SS
GND
13072-042
Figure 39. THD + N
CHANNEL-TO-CHANNEL CROS S TALK = 20 log V
OUT
GND
S1/S1x
D/Dx S2/S2x
NETWORK
ANALYZER
R
L
50Ω
R
L
50Ω
V
S
V
DD
V
SS
0.1µFV
DD
0.1µF
V
SS
V
S
V
OUT
13072-038
Figure 40. Channel-to-Channel Crosstalk
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 24 of 34
VOUT
50Ω
NETWORK
ANALYZER
RL
50Ω
Ax
VIN
Sx
D/Dx
OFF ISOLATION = 20 log VOUT
VS
VS
VDD VSS
0.1µFVDD 0.1µF
VSS
GND
50Ω
13072-037
Figure 41. Off Isolation
V
OUT
50Ω
NETWORK
ANALYZER
R
L
50Ω
Ax
V
IN
Sx
D/Dx
INSERTION LOSS = 20 log V
OUT
WITH SWITCH
V
OUT
WITHOUT SWITCH
V
S
V
DD
V
SS
0.1µFV
DD
0.1µF
V
SS
GND
13072-041
Figure 42. Bandwidth
V
D
ADG5248F/
ADG5249F
GND
Sx
OTHER SOURCE/
DRAIN PINS
D/Dx C
L
5pF
0.1µF0.1µF
V
S
V
DD
V
SS
V
DD
V
SS
POSFV + 0.5V
0V
tRESPONSE
SOURCE
VOLTAGE
(V
S
)
R
L
1kΩ
POSFV
0.1µF
POSFV
NEGFV
0.1µF
NEGFV
POSFV
0V
OUTPUT
(V
D
)
OUTPUT × 0.5
NOTES
1. THE OUTPUT PULLS TO V
DD
WITHOUT A 1kΩ RESISTOR (INTERNAL
40kΩ PULL-UP RESISTOR TO THE SUPPLY RAIL DURING A FAULT).
13072-043
Figure 43. Overvoltage Response Time, tRESPONSE
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 25 of 34
V
D
ADG5248F/
ADG5249F
GND
Sx
OTHER SOURCE/
DRAIN PINS
D/Dx C
L
5pF
V
S
R
L
1kΩ
POSFV + 0.5V
0V
tRECOVERY
SOURCE
VOLTAGE
(V
S
)
0V
POSFV × 0.5
OUTPUT
(V
D
)
0.1µF0.1µF V
DD
V
SS
V
DD
V
SS
POSFV
0.1µF
POSFV
NEGFV
0.1µF
NEGFV
NOTES
1. THE OUTPUT STARTS FROM THE POSFV CLAMP LEVEL WITHOUT A 1kΩ RESISTOR
(INTERNAL 40kΩ PULL-UP RESISTOR TO THE POSFV SUPPLY RAIL DURING A FAULT).
13072-044
Figure 44. Overvoltage Recovery Time, tRECOVERY
ADG5248F/
ADG5249F
GND
Sx
xF
D/Dx
V
S
OTHER SOURCE/
DRAIN PINS
*INCLUDES TRACK CAPACI TANCE
C
L
*
12pF
POSFV + 0.5V
0V
0V
OUTPUT
(V
xF
)
t
DIGRESP
0.1V
OUT
SOURCE
VOLTAGE
(V
S
)
13072-058
0.1µF
0.1µF V
DD
V
SS
V
DD
V
SS
POSFV
0.1µF
POSFV
NEGFV
0.1µF
NEGFV
Figure 45. Interrupt Flag Response Time, tDIGRESP
ADG5248F/
ADG5249F
GND
Sx
xF
D/Dx
VSOTHER
SOURCE P INS
*INCLUDES TRACK CAPACI TANCE
CL*
12pF
POSFV + 0.5V
0V
0V
OUTPUT
(VxF)
tDIGREC
0.9VOUT
SOURCE
VOLTAGE
(VS)
13072-056
0.1µF0.1µF VDD VSS
VDD VSS
POSFV
0.1µF
POSFV
NEGFV
0.1µF
NEGFV
Figure 46. Interrupt Flag Recovery Time, tDIGREC
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 26 of 34
ADG5248F/
ADG5249F
GND
Sx
xF
D/Dx
V
S
OTHER SOURCE/
DRAIN PINS
*INCLUDES TRACK CAPACI TANCE
C
L
*
12pF
POSFV + 0.5V
0V
5V
0V
OUTPUT
(V
xF
)
t
DIGREC
3V
SOURCE
VOLTAGE
(V
S
)
R
PULLUP
1kΩ
5V
OUTPUT
13072-057
0.1µF0.1µF V
DD
V
SS
V
DD
V
SS
POSFV
0.1µF
POSFV
NEGFV
0.1µF
NEGFV
Figure 47. Interrupt Flag Recovery Time, tDIGREC, with a 1 kΩ Pull-Up Resistor
OUTPUT
ADG5248F*
A0
A1
A2
1kΩ
GND
S1
S2 TO S7
S8
D
35pF
V
IN
2.0V EN
V
DD
V
SS
V
S
*
SIMILAR CONNE CTION FOR ADG 5249F.
3V
0V
OUTPUT 80% 80%
ADDRESS
DRIVE (V
IN
)
tD
0.1µF0.1µF V
DD
V
SS
13072-045
Figure 48. Break-Before-Make Time Delay, tD
OUTPUT
ADG5248F*
A0
A1
A2
1kΩ
GND
S1
S2 TO S8
D
35pF
VIN
EN
VDD VSS
VS
*SIMILAR CONNE CTION FOR ADG 5249F.
3V
0V
OUTPUT
50% 50%
t
OFF (EN)
t
ON (EN)
0.9VOUT
0.1VOUT
ENABLE
DRIVE (VIN)
0.1µF0.1µF VDD VSS
13072-046
Figure 49. Enable Delay, tON (EN), tOFF (EN)
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 27 of 34
3V
0V
OUTPUT
t
r
< 20ns
t
f
< 20ns
ADDRESS
DRIVE (V
IN
)
t
TRANSITION
t
TRANSITION
50% 50%
90%
90%
OUTPUT
ADG5248F*
A0
A1
A2
1kΩ
GND
S1
S2 TO S7
S8
D
35pF
V
IN
2.0V EN
V
DD
V
SS
V
S1
V
S8
*
SIMILAR CONNE CTION FOR ADG 5249F.
0.1µF0.1µF V
DD
V
SS
13072-047
Figure 50. Address to Output Switching Time, tTRANSITION
3V
V
IN
V
OUT
Q
INJ
= C
L
× ΔV
OUT
ΔV
OUT
DS1
EN GND C
L
1nF
V
OUT
V
IN
R
S
V
S
V
DD
V
SS
A0
A1
A2
ADG5248F*
*SIM IL AR CONNECT ION FOR ADG5249F .
0.1µF0.1µF V
DD
V
SS
13072-048
Figure 51. Charge Injection, QINJ
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 28 of 34
TERMINOLOGY
IDD
IDD represents the positive supply current.
ISS
ISS represents the negative supply current.
IPOSFV
IPOSFV represents the positive secondary supply current.
INEGFV
INEGFV represents the negative secondary supply current.
VD, VS
VD and VS represent the analog voltage on the D or Dx pins and
the Sx pins, respectively.
RON
RON represents the ohmic resistance between the D or Dx pins
and the Sx pins.
∆RON
∆RON represents the difference between the RON of any two
channels.
RFLAT(ON)
RFLAT(ON) is the flatness that is defined as the difference between
the maximum and minimum value of on resistance measured
over the specified analog signal range.
IS (Off)
IS (off) is the source leakage current with the switch off.
ID (Off)
ID (off) is the drain leakage current with the switch off.
ID (On), IS (On)
ID (on) and IS (on) represent the channel leakage currents with
the switch on.
VINL
VINL is the maximum input voltage for Logic 0.
VINH
VINH is the minimum input voltage for Logic 1.
IINL, IINH
IINL and IINH represent the low and high input currents of the
digital inputs.
CD (Off)
CD (off) represents the off switch drain capacitance, which is
measured with reference to ground.
CS (Off)
CS (off) represents the off switch source capacitance, which is
measured with reference to ground.
CD (On), CS (On)
CD (on) and CS (on) represent the on switch capacitances, which
are measured with reference to ground.
CIN
CIN is the digital input capacitance.
tON (EN)
tON (EN) represents the delay between applying the digital
control input and the output switching on (see Figure 49).
tOFF (EN)
tOFF (EN) represents the delay between applying the digital
control input and the output switching off (see Figure 49).
tTRANSITION
tTRANSITION represents the delay time between the 50% and 90%
points of the digital inputs and the switch on condition when
switching from one address state to another.
tD
tD represents the off time measured between the 90% points of
both switches when switching from one address state to
another.
tDIGRESP
tDIGRESP is the time required for the FF pin to go low (0.3 V),
measured with respect to the voltage on the source pin
exceeding the supply voltage by 0.5 V.
tDIGREC
tDIGREC is the time required for the FF pin to return high,
measured with respect to voltage on the Sx pin falling below the
supply voltage plus 0.5 V.
tRESPONSE
tRESPONSE represents the delay between the source voltage
exceeding the supply voltage by 0.5 V and the drain voltage
falling to 50% of its peak voltage.
tRESPONSE (EN)
tRESPONSE (EN) represents the delay between the enable pin being
asserted and the drain reaching 90% of POSFV or NEGFV for a
switch that is in fault.
tRECOVERY
tRECOVERY represents the delay between an overvoltage on the Sx
pin falling below the supply voltage plus 0.5 V and the drain
voltage rising from 0 V to 50% of its voltage.
Off Isolation
Off isolation is a measure of unwanted signal coupling through
an off switch.
Charge Injection
Charge injection is a measure of the glitch impulse transferred
from the digital input to the analog output during switching.
Channel-to-Channel Crosstalk
Crosstalk is a measure of unwanted signal that is coupled
through from one channel to another as a result of parasitic
capacitance.
Insertion Loss
Insertion loss is the loss due to the on resistance of the switch.
−3 dB Bandwidth
Bandwidth is the frequency at which the output is attenuated
by 3 dB.
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 29 of 34
AC Power Supply Rejection Ratio (ACPSRR)
ACPSRR is the ratio of the amplitude of signal on the output to
the amplitude of the modulation. ACPSRR is a measure of the
ability of the device to avoid coupling noise and spurious signals
that appear on the supply voltage pin to the output of the switch.
The dc voltage on the device is modulated by a sine wave of
0.62 V p-p.
On Response
On response is the frequency response of the on switch.
VT
VT is the voltage threshold at which the overvoltage protection
circuitry engages (see Figure 30).
Total Harmonic Distortion Plus Noise (THD + N)
THD + N is the ratio of the harmonic amplitude plus noise of
the signal to the fundamental.
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 30 of 34
THEORY OF OPERATION
SWITCH ARCHITECTURE
Each channel of the ADG5248F/ADG5249F consists of a parallel
pair of N-channel DMOS (NDMOS) and P-channel DMOS
(PDMOS) transistors. This construction provides excellent
performance across the signal range. The ADG5248F/ADG5249F
channels operate as standard switches when input signals with a
voltage between POSFV and NEGFV are applied. For example,
the on resistance is 250 Ω typically and opening or closing the
switch is controlled using the appropriate address pins.
Additional internal circuitry enables the switch to detect
overvoltage inputs by comparing the voltage on a source pin
(Sx) with POSFV and NEGFV. A signal is considered
overvoltage if it exceeds these secondary supply voltages by the
voltage threshold, VT. The threshold voltage is typically 0.7 V, but
can range from 0.8 V at −40°C down to 0.6 V at +125°C. See
Figure 30 to see the change in VT with operating temperature.
The maximum voltage that can be applied to any source input is
+55 V or −55 V. When the device is powered using a single supply
of 25 V or greater, the maximum negative signal level is reduced. It
reduces from −55 V at VDD = +25 V to −40 V at VDD = +40 V to
remain within the 80 V maximum rating. Construction of the
process allows the channel to withstand 80 V across the switch
when it is opened. These overvoltage limits apply whether the
power supplies are present or not.
ESD
PROTECTION
Sx D/Dx
Ax
POSFV
NEGFV
ESD
ESD
FAULT
DETECTOR SWITCH
DRIVER
LOGIC
BLOCK
13072-049
Figure 52. Switch Channel and Control Function
When an overvoltage condition is detected on a source pin (Sx),
the switch automatically opens regardless of the digital logic
state. The source pin becomes high impedance and ensures that
no current flows through the switch. If a source pin is selected
that is in fault, the drain pin is pulled to the supply that was
exceeded. For example, if the source voltage exceeds POSFV, the
drain output pulls to POSFV. If the source voltage exceeds NEGFV,
the drain output pulls to NEGFV. In Figure 31, the voltage on the
drain pin can be seen to follow the voltage on the source pin
until the switch turns off completely. The drain pin then pulls to
GND due to the 1 kΩ load resistor; otherwise, it pulls to the
POSFV supply. The maximum voltage on the drain is limited by
the internal ESD diodes, and the rate at which the output
voltage discharges is dependent on the load at the pin.
During overvoltage conditions, the leakage current into and out
of the source pins is limited to tens of microamperes. If the
source pin is unselected, only nanoamperes of leakage appear
on the drain pin. However, if the source is selected, the pin is
pulled to the supply rail. The device that pulls the drain pin to
the rail has an impedance of approximately 40 kΩ; thus, the D
or Dx pin current is limited to approximately 1 mA during a
shorted load condition. This internal impedance also determines
the minimum external load resistance required to ensure that
the drain pin is pulled to the desired voltage level during a fault.
When an overvoltage event occurs, the channels undisturbed by
the overvoltage input continue to operate normally without
additional crosstalk.
ESD Performance
The drain pins have ESD protection diodes to the secondary
supply rails and the voltage at these pins must not exceed the
secondary supply voltages, POSFV and NEGFV. The source
pins have specialized ESD protection that allows the signal voltage
to reach ±55 V regardless of supply voltage level. Exceeding
±55 V on any source input may damage the ESD protection
circuitry on the device. See Figure 52 for an overview of the
switch channel.
Trench Isolation
In the ADG5248F and ADG5249F, an insulating oxide layer
(trench) is placed between the NDMOS and the PDMOS
transistors of each switch. Parasitic junctions, which occur
between the transistors in junction isolated switches, are
eliminated, and the result is a switch that is latch-up immune
under all circumstances.
NDMOS PDMOS
P-WELL N-WELL
BURIED OXIDE L AY E R
HANDLE WAF E R
TRENCH
13072-050
Figure 53. Trench Isolation
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 31 of 34
USER DEFINED FAULT PROTECTION
POSFV and NEGFV are required secondary power supplies that
set the level at which the overvoltage protection is engaged. POSFV
can be supplied from 4.5 V to VDD, and NEGFV can be supplied
from VSS to 0 V. If a secondary supply is not available, the POSFV
and NEGFV pins must be connected to VDD (POSFV) and VSS
(NEGFV). The overvoltage protection then engages at the primary
supply voltages. When the voltages at the source inputs exceed
POSFV or NEGFV by VT, the switch turns off or, if the device is
unpowered, the switch remains off. The switch input remains high
impedance regardless of the digital input state and if it is selected,
the drain pulls to either POSFV or NEGFV. Signal levels up to
+55 V and −55 V are blocked in both the powered and unpowered
condition as long as the 80 V limitation between the source and
supply pins is met.
Power-On Protection
The following conditions must be satisfied for the switch to be
in the on condition:
• The primary supply must be VDD to VSS ≥ 8 V
• For POSFV, the secondary supply must be between 4.5 V
and VDD, and for NEGFV, the secondary supply must be
between VSS and 0 V
• The input signal must be between NEGFV − VT and
POSFV + VT
• The digital logic control input has selected the switch
When the switch is turned on, signal levels up to the secondary
supply rails are passed.
The switch responds to an analog input that exceeds POSFV or
NEGFV by a threshold voltage, VT, by turning off. The absolute
input voltage limits are −55 V and +55 V, while maintaining an
80 V limit between the source pin and the supply rails. The
switch remains off until the voltage at the source pin returns to
between POSFV and NEGFV.
The fault response time (tRESPONSE) when powered by a ±15 V dual
supply is typically 90 ns and the fault recovery time (tRECOVERY) is
745 ns. These vary with supply voltages and output load conditions.
The maximum stress across the switch channel is 80 V; therefore,
the user must pay close attention to this limit under a fault
condition.
For example, consider the case where the device is set up in a
multiplexer configuration as shown in Figure 54.
• VDD/VSS and POSFV/NEGFV= ±22 V, S1 = +22 V, S1 is
selected
• S2 has a −55 V fault and S3 has a +55 V fault
• The voltage between S2 and D = +22 V − (−55 V) = +77 V
• The voltage between S3 and D = 55 V− 22 V = 33 V
These calculations are all within device specifications: a 55 V
maximum fault on the source inputs and a maximum of 80 V
across the off switch channel.
S1
S2
S3
S8
ADG5248F
1-OF-8
DECODER
VDD
NEGFV
POSFV
GND
+22V –22V0V
+22V
‒55V
+55V
0V
+5V
D
A0 A1 A2 EN
V
SS
13072-051
Figure 54. ADG5248F in an Overvoltage Condition
Power-Off Protection
When no power supplies are present, the switch remains in the
off condition, and the switch inputs are high impedance. This
state ensures that no current flows and prevents damage to the
switch or downstream circuitry. The switch output is a virtual
open circuit.
The switch remains off regardless of whether the VDD and VSS
supplies are 0 V or floating. A GND reference must always be
present to ensure proper operation. Signal levels of up to ±55 V
are blocked in the unpowered condition.
Digital Input Protection
The ADG5248F and the ADG5249F can tolerate digital input
signals being present on the device without power. When the
device is unpowered, the switch is guaranteed to be in the off
state, regardless of the state of the digital logic signals.
The digital inputs are protected against positive faults of up to
44 V. The digital inputs do not offer protection against negative
overvoltages. ESD protection diodes connected to GND are
present on the digital inputs.
Overvoltage Interrupt Flag
The voltages on the source inputs of the ADG5248F and
ADG5249F are continuously monitored, and the state of the
switches is indicated by an active low digital output pin, FF.
The voltage on the FF pin indicates if any of the source input
pins are experiencing a fault condition. The output of the FF pin
is a nominal 3 V when all source pins are within normal
operating range. If any source pin voltage exceeds the secondary
supply voltage by VT, the FF output reduces to below 0.8 V.
Use the specific fault digital output pin, SF, to decode which
inputs are experiencing a fault condition. The SF pin reduces to
below 0.8 V when a fault condition is detected on a specific pin,
depending on the state of the F0, F1, and F2 pins (see Table 9
and Table 12).
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 32 of 34
APPLICATIONS INFORMATION
The overvoltage protected family of switches and multiplexers
provides robust solutions for instrumentation, industrial,
automotive, aerospace, and other harsh environments where
overvoltage signals can be present and the system must remain
operational both during and after the overvoltage has occurred.
POWER SUPPLY RAILS
To guarantee correct operation of the device, 0.1 µF decoupling
capacitors are required on the primary and secondary supplies.
If they are driven from the same supply, one set of 0.1 µF
decoupling capacitors is sufficient.
The secondary supplies (POSFV and NEGFV) provide the
current required to operate the fault protection and, thus, must
be low impedance supplies. Therefore, they can be derived from
the primary supplies by using a resistor divider and buffer.
The secondary supply rails (POSFV and NEGFV) must not
exceed the primary supply rails (VDD and VSS) because this may
lead to a signal passing through the switch unintentionally.
The ADG5248F and the ADG5249F can operate with bipolar
supplies between ±5 V and ±22 V. The supplies on VDD and VSS
need not be symmetrical but the VDD to VSS range must not exceed
44 V. The ADG5248F and the ADG5249F can also operate with
single supplies between 8 V and 44 V with VSS connected to GND.
The ADG5248F and ADG5249F devices are fully specified at
±15 V, ±20 V, +12 V, and +36 V supply ranges.
POWER SUPPLY SEQUENCING PROTECTION
The switch channel remains open when the devices are unpowered
and signals from −55 V to +55 V can be applied without damaging
the devices. The switch channel closes only when the supplies are
connected, a suitable digital control signal is placed on the address
pins, and the signal is within normal operating range. Placing
the ADG5248F/ADG5249F between external connectors and
sensitive components offers protection in systems where a signal is
presented to the source pins before the supply voltages are available.
SIGNAL RANGE
The primary supplies define the on-resistance profile of the
channel, whereas the secondary supplies define the signal range.
Using voltages on POSFV and NEGFV that are lower than VDD
and VSS, the required signal can benefit from the flat on resistance
in the center of the full signal capabilities of the device.
POWER SUPPLY RECOMMENDATIONS
Analog Devices, Inc., has a wide range of power management
products to meet the requirements of most high performance
signal chains.
An example of a bipolar power solution is shown in Figure 55.
The ADP7118 and ADP7182 can be used to generate clean positive
and negative rails from the ADP5070 (dual switching regulator)
output. These rails can power the ADG5248F, the ADG5249F, an
amplifier, and/or a precision converter in a typical signal chain.
LDO +15V
–15V
12V
INPUT
ADP7182
LDO
ADP5070
ADP7118
+16V
–16V
13072-052
Figure 55. Bipolar Power Solution
Table 13. Recommended Power Management Devices
Product
Description
ADP5070 1 A/0.6 A, dc-to-dc switching regulator with
independent positive and negative outputs
ADP7118 20 V, 200 mA, low noise, CMOS LDO
ADP7142 40 V, 200 mA, low noise, CMOS LDO
ADP7182 −28 V, −200 mA, low noise, linear regulator
HIGH VOLTAGE SURGE SUPPRESSION
The ADG5248F/ADG5249F are not intended for use in very
high voltage applications. The maximum operating voltage of
the transistor is 80 V. In applications where the inputs are likely
to be subject to overvoltages exceeding the breakdown voltage,
use transient voltage suppressors (TVSs) or similar.
Data Sheet ADG5248F/ADG5249F
Rev. A | Page 33 of 34
INTELLIGENT FAULT DETECTION
The ADG5248F and ADG5249F digital output pin, FF, can
interface with a microprocessor or control system and can be
used as an interrupt flag. This feature provides real-time
diagnostic information on the state of the device and the system
to which it connects.
The control system can use the digital interrupt, FF, to start a
variety of actions, as follows:
• Initiating an investigation into the source of an overvoltage
fault.
• Shutting down critical systems in response to the overvoltage
condition.
• Using data recorders to mark data during these events as
unreliable or out of specification.
For systems sensitive during a start-up sequence, the active
low operation of the flag allows the system to ensure that the
ADG5248F or ADG5249F is powered on and that all input
voltages are within the normal operating range before initiating
operation.
The FF pin has a weak internal pull-up resistor, which allows
the signals to combine into a single interrupt for larger modules
that contain multiple devices.
The recovery time, tDIGREC, can be decreased from a typical 65 µs
to 900 ns by using a 1 kΩ pull-up resistor.
The specific fault digital output, SF, decodes which inputs are
experiencing a fault condition. The SF pin reduces to below
0.8 V when a fault condition is detected on a specific pin,
depending on the state of the F0, F1, and F2 pins (see Table 9
and Table 12). The specific fault feature also works with the
switches disabled (EN pin low), which allows the user to cycle
through and check the fault conditions without connecting the
fault to the drain output.
LARGE VOLTAGE, HIGH FREQUENCY SIGNALS
Figure 33 illustrates the voltage range and frequencies that the
ADG5248F/ADG5249F can reliably convey. For signals that
extend across the full signal range from VSS to VDD, keep the
frequency below 1 MHz. If the required frequency is greater
than 1 MHz, decrease the signal range appropriately to ensure
signal integrity.
ADG5248F/ADG5249F Data Sheet
Rev. A | Page 34 of 34
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-153-AC
20
1
11
10
6.40 BSC
4.50
4.40
4.30
PIN 1
6.60
6.50
6.40
SEATING
PLANE
0.15
0.05
0.30
0.19
0.65
BSC
1.20 MAX 0.20
0.09 0.75
0.60
0.45
8°
0°
COPLANARIT
Y
0.10
Figure 56. 20-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-20)
Dimensions shown in millimeters
0.50
BSC
0.50
0.40
0.30
0.30
0.25
0.18
COMPLIANT
TO
JEDEC STANDARDS MO-220-WGGD.
020509-B
BOTTOM VIEWTOP VIEW
EXPOSED
PAD
PIN 1
INDICATOR
4.10
4.00 SQ
3.90
SEATING
PLANE
0.80
0.75
0.70 0.05 MAX
0.02 NOM
0.20 REF
0.25 MIN
COPLANARITY
0.08
PIN 1
INDICATOR
2.75
2.60 SQ
2.35
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
1
20
6
10
11
15
16
5
Figure 57. 20-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-20-8)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADG5248FBCPZ-RL7 −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP] CP-20-8
ADG5248FBRUZ −40°C to +125°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
ADG5248FBRUZ-RL7 −40°C to +125°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
ADG5249FBCPZ-RL7 −40°C to +125°C 20-Lead Lead Frame Chip Scale Package [LFCSP] CP-20-8
ADG5249FBRUZ −40°C to +125°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
ADG5249FBRUZ-RL7 −40°C to +125°C 20-Lead Thin Shrink Small Outline Package [TSSOP] RU-20
1 Z = RoHS Compliant Part.
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registered trademarks are the property of their respective owners.
D13072-0-7/16(A)