PI6C2404A-1 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero-Delay Clock Buffer Features Description * * * * The PI6C2404A-1 is a PLL-based, zero-delay buffer, with the ability to distribute four outputs of up to 133 MHz at 3.3V. Two banks of two outputs exist, OUTA[1-2] and OUTB[1-2]. * * * * Maximum rated frequency: 133 MHz Low cycle-to-cycle jitter Input to output delay, less than 200ps External feedback pin allows outputs to be synchronized to the clock input 5V tolerant input* Operates at 3.3V VDD Test mode allows bypass of the PLL for system testing purposes (e.g., IBIS measurements) Space-saving Packaging (Pb-free and Green Available): -- 8-pin, 150-mil SOIC (W) An external feedback pin is used to synchronize the outputs to the input; the relationship between loading of this signal and the other outputs determines the input-output delay. The PI6C2404A-1 is characterized for both commercial and industrial operation. * FB_IN and CLKIN must reference the same voltage thresholds for the PLL to deliver zero delay skewing Block Diagram FB_IN CLKIN Pin Configuration PLL OUTA1 CLKIN OUTA2 OUTA1 OUTB1 OUTA2 OUTB2 GND 1 8 2 8-Pin 7 W 6 3 4 5 FB_IN VDD OUTB2 OUTB1 Pin Description Pin 1 Signal D e s cription C LK IN Input clock reference frequency (weak pull- down) O UTA[1- 2] C lock output, Bank A 7 VDD 3.3V supply 4 GN D Ground O UTB[1- 2] C lock output, Bank B FB_IN PLL feedback input 2, 3 5, 6 8 08-0298 1 PS8609B 11/12/08 PI6C2404A-1 Zero-Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Zero-Delay and Skew Control CLKIN - Input to OUTA/OUTB Delay (ps) CLKIN Input to Output Bank Delay vs. Difference in Loading between FB_IN pin and OUTA/OUTB pins 800 600 400 200 0 -200 -25 -20 -15 -10 0 -5 -400 5 10 15 20 25 PI6C2404A-1 -600 -800 -900 -1000 Output Load Difference: FB_IN Load - OUTA/OUTB Load (pF) The relationship between loading of the FB_IN signal and other outputs determines the input-output delay. Zero delay is achieved when all outputs, including feedback, are loaded equally. Maximum Ratings Supply Voltage to Ground Potential ............................................................................................................................. -0.5V to +7.0V DC Input Voltage (Except CLKIN) ........................................................................................................................ -0.5V to VDD +0.5V DC Input Voltage CLKIN ...................................................................................................................................................... -0.5 to 7V Storage Temperature ................................................................................................................................................... -65C to +150C Maximum Soldering Temperature (10 seconds) ........................................................................................................................... 260C Junction Temperature .................................................................................................................................................................. 150C Static Discharge Voltage (per MIL-STD-883, Method 3015) .................................................................................................... >2000V Operating Conditions (VCC = 3.3V 0.3V) Parame te r VDD TA CL CIN 08-0298 De s cription M in. M a x. Units 3 .0 3 .6 V 0 70 Industrial Operating Temperature -4 0 85 Load Capacitance, below 100 MHz 30 Load Capacitance, from 100 MHz to 133 MHz 15 Input Capacitance 7.3 Supply Voltage Commerical Operating Temperature 2 C pF PS8609B 11/12/08 PI6C2404A-1 Zero-Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics for Industrial Temperature Devices Parame te r De s cription Te s t Conditions M in. M a x. VIL Input LOW Voltage 0.8 VIH Input HIGH Voltage IIL Input LOW Current VIN = 0V 50 IIH Input HIGH Current VIN = VDD 112 VO L Output LOW Voltage IO L = 8mA 0.4 VO H Output HIGH Voltage IO H = -8mA IDD Supply Current Unloaded outputs 100 MHz, Select inputs at VDD or GND 54 Unloaded outputs 66 MHz, CLKIN 39 Unloaded outputs 33MHz, CLKIN 22 Units V 2.0 A V 2.4 mA AC Electrical Characteristics for Industrial Temperature Devices Parame te rs N ame FO O utput Frequency tDC Duty C ycle(1) tR Rise Time(1) tF tSK(O) Fall Time(1) O utput to O utput Skew within same bank(1) O UTA to O UTB Te s t Conditions 30pF load Measured at VDD/2, FOUT <66.67MHz 30pF load 40 Measured at VDD/2, FOUT <50MHz 15pF load 45 100 133 50 60 55 2.2 Measured between 0.8V and 2.0V, 15pF load 1.5 Measured between 0.8V and 2.0V, 30pF load 2.2 Measured between 0.8V and 2.0V, 15pF load 1.5 tSK(D) Device- to- Device Skew(1) Measured at VDD/2 on FB_IN pins of devices PLL Lock Time(1) % ns 200 Skew(1) Jitter(1) MHz All outputs equally loaded Measured at VDD/2 tLOCK M ax. Units Measured between 0.8V and 2.0V, 30pF load Delay, C LK IN Rising Edge to FB_IN Rising Edge(1) C ycle- to- C ycle Typ. 10 15pF load t0 tJIT M in. ps 275 0 500 Measured at 66.67 MHz, loaded 30pF load 200 Measured at 133 MHz, loaded 15pF load 150 Stable power supply, valid clocks presented on C LK IN and FB_IN pins 1.0 ps ms Notes: 1. CLKIN and FB_IN inputs have a threshhold voltage of VDD/2. 08-0298 3 PS8609B 11/12/08 PI6C2404A-1 Zero-Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 DC Electrical Characteristics for Commercial Temperature Devices Parame te r De s cription Te s t Conditions M in. M a x. VIL Input LOW Voltage 0.8 VIH Input HIGH Voltage 2.0 IIL Input LOW Current VIN = 0V 50 IIH Input HIGH Current VIN = VDD 112 VO L Output LOW Voltage IO L = 8mA 0.4 VO H Output HIGH Voltage IO H = -8mA 2.4 IDD Supply Current Unloaded outputs 100 MHz Select Inputs @ VDD or GND 54 IDD Supply Current Unloaded outputs, 66.67 MHz, Select inputs at VDD or GND 39 Units V A V mA AC Electrial Characteristics for Commercial Temperature Device Parame te rs N ame FO O utput Frequency tDC Duty C ycle(2) tR Rise Time(1) @30pF Rise Time(1) @15pF tF Fall Time(1) @30pF Te s t Conditions 30pF load M in. Typ. 100 10 15pF load, 133 Measured at VDD/2, FO <66.67MHz, 30pF load 40 50 60 Measured at VDD/2, FO <50MHz, 15pF load 45 50 55 tSK(O) O utput to O utput within same bank 1.5 Measured between 0.8V and 2.0V 2.2 200 O UTA to O UTB Skew(1) All outputs equally loaded, VDD/2 200 Input to O utput Delay, C LK IN Rising Edge to FB_IN Rising Edge(1) Measured at VDD/2 275 Device to Device Skew(1) Measured at VDD/2 on FB_IN pins of devices C ycle- to- C ycle Jitter(1) Measured at 66.67 MHz, loaded 30pF outputs 200 Measured at 133 MHz, loaded 15pF outputs 150 Stable power supply, valid clocks presented on C LK IN and FB_IN pins 1.0 tSK(D) tJIT tLOCK PLL Lock Time(1) % ns 1.5 All outputs equally loaded, VDD/2 t0 MHz 2.2 Fall Time(1) @15pF Skew(1) M ax. Units 0 ps 500 ms Notes: 1. CLKIN and FB_IN inputs have a threshhold voltage of VDD/2. 2. tDC = tHIGH tHIGH + tLOW 08-0298 4 PS8609B 11/12/08 PI6C2404A-1 Zero-Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Switching Waveforms tHIGH Duty Cycle Timing VDD/2 All Outputs Rise/Fall Time OUTPUT tLOW VDD/2 2.0V 0.8V tR VDD/2 2.0V 0.8V tF 3.3V 0V Output-Output Skew OUTPUT VDD/2 VDD/2 OUTPUT tSK(O) Device-Device Skew FB_IN Device 1 VDD/2 VDD/2 FB_IN Device 2 tSK(D) Input-Output Propagation Delay INPUT VDD/2 VDD/2 FB_IN t0 Test Circuit 0.1F VDD CLK out OUTPUTS CLOAD 0.1F VDD GND GND Test Circuit for all parameters 08-0298 5 PS8609B 11/12/08 PI6C2404A-1 Zero-Delay Clock Buffer 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012 Packaging Mechanical: 8-Pin SOIC (W) DOCUMENT CONTROL NO. PD - 1001 8 REVISION: F .149 .157 DATE: 03/09/05 3.78 3.99 .0099 .0196 0.25 [U 0.50 1 .189 .196 4.80 5.00 0.19 0.25 .0075 .0098 U 0.40 .016 1.27 .050 1 .016 .026 0.406 0.660 .2284 .2440 5.80 6.20 1.35 1.75 .053 .068 SEATING PLANE REF .050 BSC 1.27 .0040 0.10 .0098 0.25 .013 0.330 .020 0.508 Pericom Semiconductor Corporation 3545 N. 1st Street, San Jose, CA 95134 1-800-435-2335 * www.pericom.com X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS Notes: 1) Controlling dimensions in millimeters. 2) Ref: JEDEC MS-012D/AA DESCRIPTION: 8-Pin, 150-Mil Wide, SOIC PACKAGE CODE: W Ordering Information Orde ring Code Package Code Package De s cription Ope rating Range PI6C2404A- 1WE W Pb- free and Green 8- pin 150- mil SOIC Commercial PI6C2404A- 1WIE W Pb- free and Green 8- pin 150- mil SOIC Industrial Notes: 1. Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. X = Tape/Reel 3. E = Pb-free & Green Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com 08-0298 6 PS8609B 11/12/08