STM32L100x6/8/B-A Ultra-low-power 32-bit MCU ARM(R)-based Cortex(R)-M3, 128KB Flash, 16KB SRAM, 2KB EEPROM, LCD, USB, ADC, DAC Datasheet - production data Features * Ultra-low-power platform - 1.8 V to 3.6 V power supply - -40C to 85C temperature range - 0.28 A Standby mode (2 wakeup pins) - 1.11 A Standby mode + RTC - 0.44 A Stop mode (16 wakeup lines) - 1.38 A Stop mode + RTC - 10.9 A Low-power Run mode - 185 A/MHz Run mode - 10 nA ultra-low I/O leakage - < 8 s wakeup time * Core: ARM(R) Cortex(R)-M3 32-bit CPU - From 32 kHz up to 32 MHz max - 1.25 DMIPS/MHz (Dhrystone 2.1) - Memory protection unit * Reset and supply management - Ultra-safe, low-power BOR (brownout reset) with 5 selectable thresholds - Ultra-low-power POR/PDR - Programmable voltage detector (PVD) * Clock sources - 1 to 24 MHz crystal oscillator - 32 kHz oscillator for RTC with calibration - High Speed Internal 16 MHz - Internal low-power 37 kHz RC - Internal multispeed low-power 65 kHz to 4.2 MHz - PLL for CPU clock and USB (48 MHz) LQFP64 10 x 10 mm * Memories - Up to 128 Kbytes of Flash memory with ECC - Up to 16 Kbytes of RAM - Up to 2 Kbytes of true EEPROM with ECC - 20-byte backup register * LCD Driver for up to 8x28 segments - Support contrast adjustment - Support blinking mode - Step-up converter on board * Rich analog peripherals (down to 1.8 V) - 12-bit ADC 1 Msps up to 24 channels - 12-bit DAC 2 channels with output buffers - 2x ultra-low-power comparators (window mode and wakeup capability) * DMA controller 7x channels * 8x peripheral communication interfaces - 1x USB 2.0 (internal 48 MHz PLL) - 3x USART (ISO 7816, IrDA) - 2x SPI 16 Mbit/s - 2x I2C (SMBus/PMBus) * 10x timers: 6x 16-bit with up to 4 IC/OC/PWM channels, 2x 16-bit basic timers, 2x watchdog timers (independent and window) * CRC calculation unit * Pre-programmed bootloader - USART supported Table 1. Device summary * Development support - Serial wire debug supported - JTAG and trace supported * Up to 51 fast I/Os (42 I/Os 5V tolerant), all mappable on 16 external interrupt vectors August 2017 This is information on a product in full production. UFQFPN48 7 x 7 mm Reference Part number STM32L100C6-A, STM32L100R8-A, STM32L100RB-A STM32L100C6xxA, STM32L100R8xxA, STM32L100RBxxA DocID025966 Rev 6 1/103 www.st.com Contents STM32L100x6/8/B-A Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 2.1 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2 Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2.1 Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.2 Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.3 Common system strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 3.2 ARM(R) Cortex(R)-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.3.4 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 3.5 Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 22 3.6 GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.8 DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 3.9 LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10 ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.10.1 2/103 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3.11 DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.12 Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 25 3.13 Routing interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 3.14 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 3.14.1 General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11) . 27 3.14.2 Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.14.3 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 DocID025966 Rev 6 STM32L100x6/8/B-A 3.15 Contents 3.14.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3.14.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.15.1 IC bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.15.2 Universal synchronous/asynchronous receiver transmitter (USART) . . 28 3.15.3 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.15.4 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 3.16 CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 29 3.17 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 4 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 6.1.7 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.1.8 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.3.2 Embedded reset and power control block characteristics . . . . . . . . . . . 46 6.3.3 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 48 6.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 6.3.5 Wakeup time from Low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 6.3.6 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.3.7 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.3.8 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 6.3.9 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 6.3.10 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 6.3.11 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 DocID025966 Rev 6 3/103 4 Contents 7 STM32L100x6/8/B-A 6.3.12 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 6.3.13 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 6.3.14 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 6.3.15 TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 6.3.16 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 6.3.17 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 6.3.18 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 6.3.19 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 6.3.20 LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 7.1 LQFP64 10 x 10 mm, 64-pin low-profile quad flat package information . . 92 7.2 UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information . . . . . . . . . . . 95 7.3 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 7.3.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 4/103 DocID025966 Rev 6 STM32L100x6/8/B-A List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ultra-low-power STM32L100x6/8/B-A device features and peripheral counts . . . . . . . . . . 10 Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 14 CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 15 Working mode-dependent functionalities (from Run/active down to standby) . . . . . . . . . . 16 VLCD rail decoupling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 STM32L100x6/8/B-A pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 46 Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Current consumption in Run mode, code with data processing running from Flash. . . . . . 50 Current consumption in Run mode, code with data processing running from RAM . . . . . . 51 Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 Current consumption in Low power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Current consumption in Low power sleep mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 55 Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 56 Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Flash memory, data EEPROM endurance and data retention . . . . . . . . . . . . . . . . . . . . . . 68 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 DocID025966 Rev 6 5/103 6 List of tables Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. Table 60. Table 61. Table 62. Table 63. Table 64. Table 65. Table 66. 6/103 STM32L100x6/8/B-A SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . . 78 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Maximum source impedance RAIN max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 LQFP64 10 x 10 mm, 64-pin low-profile quad flat package mechanical data. . . . . . . . . . . 92 UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 96 Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 DocID025966 Rev 6 STM32L100x6/8/B-A List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Ultra-low-power STM32L100x6/8/B-A block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STM32L100RxxxA LQFP64 pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 STM32L100C6xxA UFQFPN48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Maximum dynamic current consumption on VDDA supply pin during ADC conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 LQFP64 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 92 LQFP64 10 x 10 mm, 64-pin low-profile quad flat package recommended footprint . . . . . 93 LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example . . . . . . . . . . 94 UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 UFQFPN48 7 x 7 mm, 0.5 mm pitch, package recommended footprint . . . . . . . . . . . . . . . 96 UFQFPN48 7 x 7 mm, 0.5 mm pitch, package top view example . . . . . . . . . . . . . . . . . . . 97 Thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 DocID025966 Rev 6 7/103 7 Introduction 1 STM32L100x6/8/B-A Introduction This datasheet provides the ordering information and mechanical device characteristics of the STM32L100x6/8/B-A ultra-low-power ARM(R) Cortex(R)-M3 based microcontrollers product line. The ultra-low-power STM32L100x6/8/B-A microcontroller family includes devices in 2 different package types: 48 or 64 pins. Depending on the device chosen, different sets of peripherals are included, the description below gives an overview of the complete range of peripherals proposed in this family. These features make the ultra-low-power STM32L100x6/8/B-A microcontroller family suitable for a wide range of applications: * Medical and handheld equipment * Application control and user interface * PC peripherals, gaming, GPS and sport equipment * Alarm systems, Wired and wireless sensors, Video intercom * Utility metering This STM32L100x6/8/B-A datasheet should be read in conjunction with the STM32L1xxxx reference manual (RM0038). The document "Getting started with STM32L1xxxx hardware development" AN3216 gives a hardware implementation overview. Both documents are available from the STMicroelectronics website www.st.com. For information on the ARM(R) Cortex(R)-M3 core please refer to the Cortex(R)-M3 Technical Reference Manual, available from the ARM website. Figure 1 shows the general block diagram of the device family. Caution: This datasheet does not apply to: - STM32L100x6/8/B covered by a separate datasheet. 8/103 DocID025966 Rev 6 STM32L100x6/8/B-A 2 Description Description The ultra-low-power STM32L100x6/8/B-A devices incorporate the connectivity power of the universal serial bus (USB) with the high-performance ARM(R) Cortex(R)-M3 32-bit RISC core operating at a frequency of 32 MHz (33.3 DMIPS), a memory protection unit (MPU), highspeed embedded memories (Flash memory up to 128 Kbytes and RAM up to 16 Kbytes) and an extensive range of enhanced I/Os and peripherals connected to two APB buses. All the devices offer a 12-bit ADC, 2 DACs and 2 ultra-low-power comparators, six generalpurpose 16-bit timers and two basic timers, which can be used as time bases. Moreover, the STM32L100x6/8/B-A devices contain standard and advanced communication interfaces: up to two I2Cs and SPIs, three USARTs and a USB. They also include a real-time clock with sub-second counting and a set of backup registers that remain powered in Standby mode. Finally, the integrated LCD controller has a built-in LCD voltage generator that allows to drive up to 8 multiplexed LCDs with contrast independent of the supply voltage. The ultra-low-power STM32L100x6/8/B-A devices operate from a 1.8 to 3.6 V power supply. They are available in the -40 to +85 C temperature range. A comprehensive set of powersaving modes allows the design of low-power applications. DocID025966 Rev 6 9/103 40 Description 2.1 STM32L100x6/8/B-A Device overview -- Table 2. Ultra-low-power STM32L100x6/8/B-A device features and peripheral counts Peripheral Flash (Kbytes) STM32L100C6xxA 32 Data EEPROM (Kbytes) RAM (Kbytes) Timers Communication interfaces Generalpurpose 6 Basic 2 SPI 2 I2C 2 USART 3 USB 1 12-bit synchronized ADC Number of channels 16 1 14 channels 1 20 channels 2 2 4x32 8x28 4x16 2 Max. CPU frequency 32 MHz Operating voltage 10/103 8 51 Comparator Operating temperatures 128 37 12-bit DAC Number of channels LCD COM x SEG 64 2 4 GPIOs Packages STM32L100R8/BxxA 1.8 V to 3.6 V Ambient temperatures: -40 to +85 C Junction temperature: -40 to +105C UFQFPN48 DocID025966 Rev 6 LQFP64 STM32L100x6/8/B-A 2.2 Description Ultra-low-power device continuum The ultra-low-power family offers a large choice of cores and features. From a proprietary 8bit core up to the Cortex-M3, including the Cortex-M0+, the STM8Lx and STM32Lx series offer the best range of choices to meet your requirements in terms of ultra-low-power features. The STM32 Ultra-low-power series is an ideal fit for applications like gas/water meters, keyboard/mouse, or wearable devices for fitness and healthcare. Numerous built-in features like LCD drivers, dual-bank memory, low-power Run mode, op-amp, AES-128bit, DAC, crystal-less USB and many others, allow to build highly cost-optimized applications by reducing the BOM. Note: STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible the pin-to-pin compatibility between any STM8Lx and STM32Lx devices and between any of the STM32Lx and STM32Fx series. Thanks to this unprecedented scalability, your existing applications can be upgraded to respond to the latest market features and efficiency demand. 2.2.1 Performance All families incorporate highly energy-efficient cores with both Harvard architecture and pipelined execution: advanced STM8 core for STM8L families and ARM Cortex-M3 core for STM32L family. In addition specific care for the design architecture has been taken to optimize the mA/DMIPS and mA/MHz ratios. This allows the ultra-Low-power performance to range from 5 up to 33.3 DMIPs. 2.2.2 Shared peripherals STM8L15xxx and STM32L1xxxx share identical peripherals which ensure a very easy migration from one family to another: 2.2.3 * Analog peripherals: ADC, DAC and comparators * Digital peripherals: RTC and some communication interfaces Common system strategy To offer flexibility and optimize performance, the STM8L15xxx and STM32L1xxxx families use a common architecture: 2.2.4 * Common power supply range from 1.8 V to 3.6 V * Architecture optimized to reach ultra-low consumption both in low-power modes and Run mode * Fast startup strategy from low-power modes * Flexible system clock * Ultra-safe reset: same reset strategy including power-on reset, power-down reset, brownout reset and programmable voltage detector. Features ST ultra-low-power continuum also lies in feature compatibility: * More than 10 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm * Memory density ranging from 4 to 512 Kbytes DocID025966 Rev 6 11/103 40 Functional overview 3 STM32L100x6/8/B-A Functional overview Figure 1 shows the block diagram. Figure 1. Ultra-low-power STM32L100x6/8/B-A block diagram 6 $$ *4!' 37 6#/2% PBUS 6$$ 6 TO 6 )ODVK REO ,QWHUIDFH &RUWH[0&38 )BUS &MAX -(Z $BUS -05 3YSTEM .6)# %XV0DWUL[ .*4234 *4$) *4#+ 37#,+ *4-3 37$!4 *4$/ AS !& !("0#,+ !0"0#,+ (#,+ &#,+ CHANNELS 62%& /54054 %2595(),17 6$$! 633! 06$ #OMP 0";= '0)/" )7$' 6$$! 3TANDBY INTERFACE 84! , K(Z 24# !75 "ACKUP REGISTER /3#?). /3#?/54 24#?!&). 24#?/54 24#?43 24#?4!-0 "ACKUP INTERFACE 9/&' '0)/! /3#?). /3#?/54 MANAGEMENT 2# ,3 )N T 3RZHUXS 3RZHUGRZQ 0!;= 84!, /3# -(Z 0,, CLOCK 2# -3 0OWER RESET #OMP #/-0?). ). 6$$! 2# (3 $+%)PD[ 0+] 6$$! 3UPPLY MONITORING 6 33 +" &LASH +" DATA %%02/- 5$0 .% '0$-! .234 0/7%2 6/,4 2%' /&'VWHSXS CONVERTER 6,#$ 6 TO 6 0#;= '0)/# 0$;= '0)/$ 4)- #HANNELS 0(;= '0)/( 4)- #HANNELS 4)- #HANNELS $+%" $3% -/3) -)3/ 3#+ .33 AS !& 28 48 #43 243 3MART#ARD AS !& 30) 53!24 6$$! !& $3%)PD[ 0+] %84 )4 7+50 BIT !$# 4EMP SENSOR )& $3%)PD[ 0+] !& $+% !(" $3% 86%5$0% 53!24 28 48 #43 243 3MART#ARD AS !& 53!24 28 48 #43 243 3MART#ARD AS !& 30) ,& ,& 86%)6GHYLFH 77$' ,#$ X X 'ENERAL PURPOSE TIMERS #HANNELS 4)- #HANNEL #HANNEL 4)- 53"?$0 53"?$3%' X #/- X BIT $!# $!#?/54 AS !& BIT $!# $!#?/54 AS !& )& )& 4)- 3#, 3$! AS !& 3#, 3$! 3-"US 0-"US AS !& 6$$! "!3)# 4)-%23 4)- -/3) -)3/ 3#+ .33 !S !& 4)- 06Y9 1. AF = alternate function on I/O port pin. 12/103 DocID025966 Rev 6 STM32L100x6/8/B-A 3.1 Functional overview Low-power modes The ultra-low-power STM32L100x6/8/B-A devices support dynamic voltage scaling to optimize its power consumption in run mode. The voltage from the internal low-drop regulator that supplies the logic can be adjusted according to the system's maximum operating frequency and the external voltage supply: * In Range 1 (VDD range limited to 2.0-3.6 V), the CPU runs at up to 32 MHz (refer to Table 18 for consumption). * In Range 2 (full VDD range), the CPU runs at up to 16 MHz (refer to Table 18 for consumption) * In Range 3 (full VDD range), the CPU runs at up to 4 MHz (generated only with the multispeed internal RC oscillator clock source). Refer to Table 18 for consumption. Seven low-power modes are provided to achieve the best compromise between low-power consumption, short startup time and available wakeup sources: * Sleep mode In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs. Sleep mode power consumption: refer to Table 20. * Low-power Run mode This mode is achieved with the multispeed internal (MSI) RC oscillator set to the MSI range 0 or MSI range 1 clock range (maximum 131 kHz), execution from SRAM or Flash memory, and internal regulator in low-power mode to minimize the regulator's operating current. In the low-power Run mode, the clock frequency and the number of enabled peripherals are both limited. Low-power Run mode consumption: refer to Table 21. * Low-power Sleep mode This mode is achieved by entering the Sleep mode with the internal voltage regulator in low-power mode to minimize the regulator's operating current. In the low-power Sleep mode, both the clock frequency and the number of enabled peripherals are limited; a typical example would be to have a timer running at 32 kHz. When wakeup is triggered by an event or an interrupt, the system reverts to the run mode with the regulator on. Low-power Sleep mode consumption: refer to Table 22. * Stop mode with RTC Stop mode achieves the lowest power consumption while retaining the RAM and register contents and real time clock. All clocks in the VCORE domain are stopped, the PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still running. The voltage regulator is in the low-power mode. The device can be woken up from Stop mode by any of the EXTI line, in 8 s. The EXTI line source can be one of the 16 external lines. It can be the PVD output, the Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp event or the RTC wakeup. * Stop mode without RTC Stop mode achieves the lowest power consumption while retaining the RAM and register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode. The device can be woken up from Stop mode by any of the EXTI line, in 8 s. The EXTI DocID025966 Rev 6 13/103 40 Functional overview STM32L100x6/8/B-A line source can be one of the 16 external lines. It can be the PVD output, the Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can also be wakened by the USB wakeup. Stop mode consumption: refer to Table 23. * Standby mode with RTC Standby mode is used to achieve the lowest power consumption and real time clock. The internal voltage regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched off. The LSE or LSI is still running. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC_CSR). The device exits Standby mode in 60 s when an external reset (NRST pin), an IWDG reset, a rising edge on one of the two WKUP pins, RTC alarm (Alarm A or Alarm B), RTC tamper event, RTC timestamp event or RTC Wakeup event occurs. * Standby mode without RTC Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI, RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After entering Standby mode, the RAM and register contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc, RCC_CSR). The device exits Standby mode in 60 s when an external reset (NRST pin) or a rising edge on one of the two WKUP pin occurs. Standby mode consumption: refer to Table 24. Note: The RTC, the IWDG, and the corresponding clock sources are not stopped by entering the Stop or Standby mode. Table 3. Functionalities depending on the operating power supply range Functionalities depending on the operating power supply range(1) Operating power supply range DAC and ADC operation USB Dynamic voltage scaling range VDD = 1.8 to 2.0 V(2) Conversion time up to 500 Ksps Not functional Range 2 or Range 3 VDD = 2.0 to 2.4 V Conversion time up to 500 Ksps Functional(3) Range 1, Range 2 or Range 3 VDD = 2.4 to 3.6 V Conversion time up to 1 Msps Functional(3) Range 1, Range 2 or Range 3 1. The GPIO speed also depends from VDD voltage and the user has to refer to Table 45: I/O AC characteristics for more information about I/O speed. 2. The CPU frequency changes from initial to final must respect "FCPU initial < 4*FCPU final" to limit VCORE drop due to current consumption peak when frequency increases. It must also respect 5 s delay between two changes. For example to switch from 4.2 MHz to 32 MHz, you can switch from 4.2 MHz to 16 MHz, wait 5 s, then switch from 16 MHz to 32 MHz. 3. Should be USB-compliant from I/O voltage standpoint, the minimum VDD is 3.0 V. 14/103 DocID025966 Rev 6 STM32L100x6/8/B-A Functional overview Table 4. CPU frequency range depending on dynamic voltage scaling CPU frequency range Dynamic voltage scaling range 16 MHz to 32 MHz (1ws) 32 kHz to 16 MHz (0ws) Range 1 8 MHz to 16 MHz (1ws) 32 kHz to 8 MHz (0ws) Range 2 2.1 MHz to 4.2 MHz (1ws) 32 kHz to 2.1 MHz (0ws) Range 3 DocID025966 Rev 6 15/103 40 Functional overview STM32L100x6/8/B-A Table 5. Working mode-dependent functionalities (from Run/active down to standby) Standby Run/Active Sleep CPU Y - Y - - - - - Flash Y Y Y - - - - - RAM Y Y Y Y Y - - - Backup Registers Y Y Y Y Y - Y - EEPROM Y Y Y Y Y - - - Brown-out reset (BOR) Y Y Y Y Y Y Y - DMA Y Y Y Y - - - - Programmable Voltage Detector (PVD) Y Y Y Y Y Y Y - Power On Reset (POR) Y Y Y Y Y Y Y - Power Down Rest (PDR) Y Y Y Y Y - Y - High Speed Internal (HSI) Y Y - - - - - - High Speed External (HSE) Y Y - - - - - - Low Speed Internal (LSI) Y Y Y Y Y - Y - Low Speed External (LSE) Y Y Y Y Y - Y - Multi-Speed Internal (MSI) Y Y Y Y - - - - Inter-Connect Controller Y Y Y Y - - - - RTC Y Y Y Y Y Y Y - RTC Tamper Y Y Y Y Y Y Y Y Auto Wakeup (AWU) Y Y Y Y Y Y Y Y LCD Y Y Y Y Y - - - USB Y Y - - - Y - - - - Ips Lowpower Sleep Stop Lowpower Run Wakeup capability Wakeup capability USART Y Y Y Y Y (1) SPI Y Y Y Y - - - - I2C Y Y - - - (1) - - ADC Y Y - - - - - - 16/103 DocID025966 Rev 6 STM32L100x6/8/B-A Functional overview Table 5. Working mode-dependent functionalities (from Run/active down to standby) (continued) Standby Run/Active Sleep DAC Y Y Y Y Y - - - Comparators Y Y Y Y Y Y - - 16-bit Timers Y Y Y Y - - - - IWDG Y Y Y Y Y Y Y Y WWDG Y Y Y Y - - - - Systick Timer Y Y Y Y - - - - GPIOs Y Y Y Y Y Y - 2 pins 0 s 0.4 s 3 s 46 s Ips Wakeup time to Run mode Lowpower Sleep Stop Lowpower Run Wakeup capability < 8 s Wakeup capability 58 s 0.43 A (No 0.27 A (No RTC) VDD=1.8 V RTC) VDD=1.8 V Consumption VDD=1.8V to 3.6V (Typ) Down to 185 A/MHz (from Flash) Down to 36.9 A/MHz (from Flash) Down to 10.9 A 1.13 A (with 0.87 A (with RTC) V =1.8 V RTC) VDD=1.8 V DD Down to 5.5 A 0.28 A (No 0.44 A (No RTC) VDD=3.0 V RTC) VDD=3.0 V 1.11 A (with 1.38 A (with RTC) VDD=3.0 V RTC) VDD=3.0 V 1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before entering run mode. 3.2 ARM(R) Cortex(R)-M3 core with MPU The ARM(R) Cortex(R)-M3 processor is the industry leading processor for embedded systems. It has been developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced system response to interrupts. The ARM(R) Cortex(R)-M3 32-bit RISC processor features exceptional code-efficiency, delivering the high-performance expected from an ARM core in the memory size usually associated with 8- and 16-bit devices. The memory protection unit (MPU) improves system reliability by defining the memory attributes (such as read/write access permissions) for different memory regions. It provides up to eight different regions and an optional predefined background region. Owing to its embedded ARM core, the STM32L100x6/8/B-A devices are compatible with all ARM tools and software. DocID025966 Rev 6 17/103 40 Functional overview STM32L100x6/8/B-A Nested vectored interrupt controller (NVIC) The ultra-low-power STM32L100x6/8/B-A devices embed a nested vectored interrupt controller able to handle up to 45 maskable interrupt channels (not including the 16 interrupt lines of Cortex-M3) and 16 priority levels. * Closely coupled NVIC gives low-latency interrupt processing * Interrupt entry vector table address passed directly to the core * Closely coupled NVIC core interface * Allows early processing of interrupts * Processing of late arriving, higher-priority interrupts * Support for tail-chaining * Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction overhead This hardware block provides flexible interrupt management features with minimal interrupt latency. 3.3 Reset and supply management 3.3.1 Power supply schemes 3.3.2 * VDD = 1.8 to 3.6 V: external power supply for I/Os and the internal regulator. Provided externally through VDD pins. * VSSA, VDDA = 1.8 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs and PLL. VDDA and VSSA must be connected to VDD and VSS, respectively. Power supply supervisor The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset (PDR) that can be coupled with a brownout reset (BOR) circuitry. After the VDD threshold is reached, the option byte loading process starts, either to confirm or modify default thresholds, or to disable the BOR permanently. BOR ensures proper operation starting from 1.8 V whatever the power ramp-up phase before it reaches 1.8 V. 18/103 DocID025966 Rev 6 STM32L100x6/8/B-A Functional overview Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To reduce the power consumption in Stop mode, it is possible to automatically switch off the internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external reset circuit. Note: The start-up time at power-on is typically 3.3 ms. The device features an embedded programmable voltage detector (PVD) that monitors the VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software. 3.3.3 Voltage regulator The regulator has three operation modes: main (MR), low-power (LPR) and power down. 3.3.4 * MR is used in Run mode (nominal regulation) * LPR is used in the Low-power run, Low-power sleep and Stop modes * Power down is used in Standby mode. The regulator output is high impedance, the kernel circuitry is powered down, inducing zero consumption but the contents of the registers and RAM are lost are lost except for the standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE crystal 32K osc, RCC_CSR). Boot modes At startup, boot pins are used to select one of three boot options: * Boot from Flash memory * Boot from System Memory * Boot from embedded RAM The boot loader is located in System Memory. It is used to reprogram the Flash memory by using USART1 or USART2. See the application note "STM32 microcontroller system memory boot mode" (AN2606) for details. DocID025966 Rev 6 19/103 40 Functional overview 3.4 STM32L100x6/8/B-A Clock management The clock controller distributes the clocks coming from different oscillators to the core and the peripherals. It also manages clock gating for low-power modes and ensures clock robustness. It features: * Clock prescaler: to get the best trade-off between speed and current consumption, the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler * Safe clock switching: clock sources can be changed safely on the fly in run mode through a configuration register. * Clock management: to reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory. * Master clock source: three different clock sources can be used to drive the master clock: * - 1-24 MHz high-speed external crystal (HSE), that can supply a PLL - 16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can supply a PLL - Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7 frequencies (65.5 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz) with a consumption proportional to speed, down to 750 nA typical. When a 32.768 kHz clock source is available in the system (LSE), the MSI frequency can be trimmed by software down to a 0.5% accuracy. Auxiliary clock source: two ultra-low-power clock sources that can be used to drive the LCD controller and the real-time clock: - 32.768 kHz low-speed external crystal (LSE) - 37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog. The LSI clock can be measured using the high-speed internal RC oscillator for greater precision. * RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock the RTC and the LCD, whatever the system clock. * USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply the USB interface. * Startup clock: after reset, the microcontroller restarts by default with an internal 2.1 MHz clock (MSI). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts. * Clock security system (CSS): this feature can be enabled by software. If a HSE clock failure occurs, the master clock is automatically switched to HSI and a software interrupt is generated if enabled. * Clock-out capability (MCO: microcontroller clock output): it outputs one of the internal clocks for external use by the application. Several prescalers allow the configuration of the AHB frequency, the high-speed APB (APB2) and the low-speed APB (APB1) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See Figure 2 for details on the clock tree. 20/103 DocID025966 Rev 6 STM32L100x6/8/B-A Functional overview Figure 2. Clock tree -3) 2# -3) !$##,+ TO !$# 0ERIPHERAL CLOCK ENABLE -(Z (3) 2# (3) -(Z 53"#,+ TO 53" INTERFACE 0,,6#/ 0,,32# /3#?/54 /3#?). -(Z 0,,-5, 0,,$)6 X X X X X X X X X 37 (3) 0,,#,+ 393#,+ -(Z MAX (3% (3% /3# #33 (#,+ TO !(" BUS CORE MEMORY AND $-! -(Z MAX !(" 0RESCALER #LOCK %NABLE !0" 0RESCALER TO #ORTEX 3YSTEM TIMER &#,+ #ORTEX FREE RUNNING CLOCK -(Z MAX 0#,+ TO !0" PERIPHERALS 0ERIPHERAL #LOCK %NABLE )F !0" PRESCALER X ELSE X TO 4)- AND 4)-X#,+ 0ERIPHERAL #LOCK %NABLE !0" 0RESCALER -(Z MAX 0ERIPHERAL #LOCK %NABLE )F !0" PRESCALER X ELSE X TO 4IMER %42 /3#?). /3#?/54 0#,+ PERIPHERALS TO !0" TO 4)- AND 4)-X#,+ 0ERIPHERAL #LOCK %NABLE TO 24# ,3% ,3% /3# K(Z 24##,+ TO ,#$ 24#3%,;= ,3) 2# K(Z -#/ ,3) TO )NDEPENDENT 7ATCHDOG )7$' )7$'#,+ 393#,+ (3) -3) (3% 0,,#,+ ,3) ,3% ,EGEND (3% (IGH SPEED EXTERNAL CLOCK SIGNAL (3) (IGH SPEED INTERNAL CLOCK SIGNAL ,3) ,OW SPEED INTERNAL CLOCK SIGNAL ,3% ,OW SPEED EXTERNAL CLOCK SIGNAL -3) -ULTISPEED INTERNAL CLOCK SIGNAL -#/3%, AIC DocID025966 Rev 6 21/103 40 Functional overview 3.5 STM32L100x6/8/B-A Low-power real-time clock and backup registers The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD (binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the month are made automatically. The RTC provides two programmable alarms and programmable periodic interrupts with wakeup from Stop and Standby modes. The programmable wakeup time ranges from 120 s to 36 hours. The RTC can be calibrated with an external 512 Hz output, and a digital compensation circuit helps reduce drift due to crystal deviation. The RTC can also be automatically corrected with a 50/60Hz stable power line. The RTC calendar can be updated on the fly down to sub second precision, which enables network system synchronization. A time stamp can record an external event occurrence, and generates an interrupt. There are five 32-bit backup registers provided to store 20 bytes of user application data. They are cleared in case of tamper detection. Three pins can be used to detect tamper events. A change on one of these pins can reset backup register and generate an interrupt. To prevent false tamper event, like ESD event, these three tamper inputs can be digitally filtered. 3.6 GPIOs (general-purpose inputs/outputs) Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions, and can be individually remapped using dedicated AFIO registers. All GPIOs are high current capable. The alternate function configuration of I/Os can be locked if needed following a specific sequence in order to avoid spurious writing to the I/O registers. The I/O controller is connected to the AHB with a toggling speed of up to 16 MHz. External interrupt/event controller (EXTI) The external interrupt/event controller consists of 23 edge detector lines used to generate interrupt/event requests. Each line can be individually configured to select the trigger event (rising edge, falling edge, both) and can be masked independently. A pending register maintains the status of the interrupt requests. The EXTI can detect an external line with a pulse width shorter than the Internal APB2 clock period. Up to 51 GPIOs can be connected to the 16 external interrupt lines. The 7 other lines are connected to RTC, PVD, USB or Comparator events. 22/103 DocID025966 Rev 6 STM32L100x6/8/B-A 3.7 Functional overview Memories The STM32L100x6/8/B-A devices have the following features: * Up to 16 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait states. With the enhanced bus matrix, operating the RAM does not lead to any performance penalty during accesses to the system bus (AHB and APB buses). * The non-volatile memory is divided into three arrays: - 32, 64 or 128 Kbytes of embedded Flash program memory - 2 Kbytes of data EEPROM - Options bytes The options bytes are used to write-protect the memory (with 4 Kbytes granularity) and/or readout-protect the whole memory with the following options: - Level 0: no readout protection - Level 1: memory readout protection, the Flash memory cannot be read from or written to if either debug features are connected or boot in RAM is selected - Level 2: chip readout protection, debug features (Cortex-M3 JTAG and serial wire) and boot in RAM selection disabled (JTAG fuse) The whole non-volatile memory embeds the error correction code (ECC) feature. 3.8 DMA (direct memory access) The flexible 7-channel, general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer. Each channel is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent. The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers and ADC. DocID025966 Rev 6 23/103 40 Functional overview 3.9 STM32L100x6/8/B-A LCD (liquid crystal display) The LCD drives up to 8 common terminals and 32 segment terminals to drive up to 224 pixels. * Internal step-up converter to guarantee functionality and contrast control irrespective of VDD. This converter can be deactivated, in which case the VLCD pin is used to provide the voltage to the LCD * Supports static, 1/2, 1/3, 1/4 and 1/8 duty * Supports static, 1/2, 1/3 and 1/4 bias * Phase inversion to reduce power consumption and EMI * Up to 8 pixels can be programmed to blink * Unneeded segments and common pins can be used as general I/O pins * LCD RAM can be updated at any time owing to a double-buffer * The LCD controller can operate in Stop mode * VLCD rail decoupling capability Table 6. VLCD rail decoupling Bias 3.10 Pin 1/2 1/3 1/4 VLCDrail1 1/2 VLCD 2/3 VLCD 1/2 VLCD PB2 VLCDrail2 NA 1/3 VLCD 1/4 VLCD PB12 VLCDrail3 NA NA 3/4 VLCD PB0 ADC (analog-to-digital converter) A 12-bit analog-to-digital converters is embedded into STM32L100x6/8/B-A devices with up to 20 external channels, performing conversions in single-shot or scan mode. In scan mode, automatic conversion is performed on a selected group of analog inputs. The ADC can be served by the DMA controller. An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds. The events generated by the general-purpose timers (TIMx) can be internally connected to the ADC start trigger and injection trigger, to allow the application to synchronize A/D conversions and timers. An injection mode allows high priority conversions to be done by interrupting a scan mode which runs in as a background task. The ADC includes a specific low-power mode. The converter is able to operate at maximum speed even if the CPU is operating at a very low frequency and has an auto-shutdown function. The ADC's runtime and analog front-end current consumption are thus minimized whatever the MCU operating mode. 3.10.1 Internal voltage reference (VREFINT) The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It 24/103 DocID025966 Rev 6 STM32L100x6/8/B-A Functional overview enables accurate monitoring of the VDD value. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode see Table 17: Embedded internal reference voltage. 3.11 DAC (digital-to-analog converter) The two 12-bit buffered DAC channels can be used to convert two digital signals into two analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in non-inverting configuration. This dual digital Interface supports the following features: * two DAC converters: one for each output channel * left or right data alignment in 12-bit mode * synchronized update capability * noise-wave generation * triangular-wave generation * dual DAC channels' independent or simultaneous conversions * DMA capability for each channel (including the underrun interrupt) * external triggers for conversion Eight DAC trigger inputs are used in the STM32L100x6/8/B-A devices. The DAC channels are triggered through the timer update outputs that are also connected to different DMA channels. 3.12 Ultra-low-power comparators and reference voltage The STM32L100x6/8/B-A devices embed two comparators sharing the same current bias and reference voltage. The reference voltage can be internal or external (coming from an I/O). * one comparator with fixed threshold * one comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of the following: - DAC output - External I/O - Internal reference voltage (VREFINT) or VREFINT submultiple (1/4, 1/2, 3/4) Both comparators can wake up from Stop mode, and be combined into a window comparator. The internal reference voltage is available externally via a low-power / low-current output buffer (driving current capability of 1 A typical). 3.13 Routing interface The highly flexible routing interface allows the application firmware to control the routing of different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage VREFINT DocID025966 Rev 6 25/103 40 Functional overview 3.14 STM32L100x6/8/B-A Timers and watchdogs The ultra-low-power STM32L100x6/8/B-A devices include six general-purpose timers, two basic timers and two watchdog timers. Table 7 compares the features of the general-purpose and basic timers. Table 7. Timer feature comparison 26/103 Timer Counter resolution Counter type Prescaler factor DMA request Capture/compare Complementary generation channels outputs TIM2, TIM3, TIM4 16-bit Up, down, up/down Any integer between 1 and 65536 Yes 4 No TIM9 16-bit Up, down, up/down Any integer between 1 and 65536 No 2 No TIM10, TIM11 16-bit Up Any integer between 1 and 65536 No 1 No TIM6, TIM7 16-bit Up Any integer between 1 and 65536 Yes 0 No DocID025966 Rev 6 STM32L100x6/8/B-A 3.14.1 Functional overview General-purpose timers (TIM2, TIM3, TIM4, TIM9, TIM10 and TIM11) There are six synchronizable general-purpose timers embedded in the STM32L100x6/8/B-A devices (see Table 7 for differences). TIM2, TIM3, TIM4 These timers are based on a 16-bit auto-reload up/down-counter and a 16-bit prescaler. They feature 4 independent channels each for input capture/output compare, PWM or onepulse mode output. This gives up to 12 input captures/output compares/PWMs on the largest packages. The TIM2, TIM3, TIM4 general-purpose timers can work together or with the TIM10, TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or event chaining. Their counter can be frozen in debug mode. Any of the general-purpose timers can be used to generate PWM outputs. TIM2, TIM3, TIM4 all have independent DMA request generation. These timers are capable of handling quadrature (incremental) encoder signals and the digital outputs from 1 to 3 hall-effect sensors. TIM10, TIM11 and TIM9 TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one independent channel, whereas TIM9 has two independent channels for input capture/output compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3, TIM4 full-featured general-purpose timers. They can also be used as simple time bases and be clocked by the LSE clock source (32.768 kHz) to provide time bases independent from the main CPU clock. 3.14.2 Basic timers (TIM6 and TIM7) These timers are mainly used for DAC trigger generation. They can also be used as generic 16-bit time bases. 3.14.3 SysTick timer This timer is dedicated to the OS, but could also be used as a standard downcounter. It is based on a 24-bit down-counter with autoreload capability and a programmable clock source. It features a maskable system interrupt generation when the counter reaches 0. 3.14.4 Independent watchdog (IWDG) The independent watchdog is based on a 12-bit down-counter and 8-bit prescaler. It is clocked from an independent 37 kHz internal RC and, as it operates independently of the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free-running timer for application timeout management. It is hardware- or software-configurable through the option bytes. The counter can be frozen in debug mode. DocID025966 Rev 6 27/103 40 Functional overview 3.14.5 STM32L100x6/8/B-A Window watchdog (WWDG) The window watchdog is based on a 7-bit down-counter that can be set as free-running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode. 3.15 Communication interfaces 3.15.1 IC bus Up to two IC bus interfaces can operate in multimaster and slave modes. They can support standard and fast modes. They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master mode. A hardware CRC generation/verification is embedded. They can be served by DMA and they support SM Bus 2.0/PM Bus. 3.15.2 Universal synchronous/asynchronous receiver transmitter (USART) All USART interfaces are able to communicate at speeds of up to 4 Mbit/s. They provide hardware management of the CTS and RTS signals and are ISO 7816 compliant. They support IrDA SIR ENDEC and have LIN Master/Slave capability. All USART interfaces can be served by the DMA controller. 3.15.3 Serial peripheral interface (SPI) Up to two SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC generation/verification supports basic SD Card/MMC modes. Both SPIs can be served by the DMA controller. 3.15.4 Universal serial bus (USB) The STM32L100x6/8/B-A devices embed a USB device peripheral compatible with the USB full speed 12 Mbit/s. The USB interface implements a full speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and supports suspend/resume. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). 28/103 DocID025966 Rev 6 STM32L100x6/8/B-A 3.16 Functional overview CRC (cyclic redundancy check) calculation unit The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit data word and a fixed generator polynomial. Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location. 3.17 Development support Serial wire JTAG debug port (SWJ-DP) The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target. The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP. The JTAG port can be permanently disabled with a JTAG fuse. DocID025966 Rev 6 29/103 40 Pin descriptions 4 STM32L100x6/8/B-A Pin descriptions 3$ 3$ 3& 3& 3& 3' 3% 3% 3% 3% 3% %227 3% 3% 966B 9''B Figure 3. STM32L100RxxxA LQFP64 pinout 9''B 3&:.83 966B 3&26&B,1 3$ 3&26&B287 3$ 3+26&B,1 3$ 3+26&B287 3$ 1567 3$ 3& 3$ 3& 3& 3& 3& 3& 3& 966$ 3& 9''$ 3% 3$:.83 3% 3$ 3% 3$ 3% 966B 3% 3% 3% 3% 3% 3& 3& 3$ 3$ 3$ 3$ 9''B 3$ 966B /4)3 9''B 9/&' DLG 1. This figure shows the package top view. 30/103 DocID025966 Rev 6 STM32L100x6/8/B-A Pin descriptions 0! 6$$? 0# 7+50 633? 0# /3#?). 0! 0# /3#?/54 0! 0( /3#?). 0! 0( /3#?/54 0! .234 0! 633! 0! 6$$! 0" 0! 7+50 0" 0! 0" 0! 0" 0" 5&1&0. 6$$? 633? 0! 0" 0" 0" 0" 0" 0" 0" 0" 0! 0" "//4 0" 0! 0" 0! 633? 0! 6,#$ 0! 6$$? Figure 4. STM32L100C6xxA UFQFPN48 pinout AID 1. This figure shows the package top view. DocID025966 Rev 6 31/103 40 Pin descriptions STM32L100x6/8/B-A Table 8. Legend/abbreviations used in the pinout table Name Pin name Pin type I/O structure Notes Abbreviation Definition Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name S Supply pin I Input only pin I/O Input / output pin FT 5 V tolerant I/O TC Standard 3.3 V I/O B Dedicated BOOT0 pin RST Bidirectional reset pin with embedded weak pull-up resistor Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset Alternate Functions selected through GPIOx_AFR registers functions Pin functions 32/103 Additional Functions directly selected/enabled through peripheral registers functions DocID025966 Rev 6 STM32L100x6/8/B-A Pin descriptions Table 9. STM32L100x6/8/B-A pin definitions Pins LQFP64 UFQFPN48 Pin type(1) I/O structure Pin functions Main function(2) (after reset) 1 1 VLCD S - VLCD - - 2 2 PC13-WKUP2 I/O FT PC13 - RTC_TAMP1/ RTC_TS/ RTC_OUT/WKUP2 3 3 PC14OSC32_IN(3) I/O TC PC14 - OSC32_IN 4 4 PC15OSC32_OUT I/O TC PC15 - OSC32_OUT 5 5 PH0-OSC_IN(4) I/O TC PH0 - OSC_IN 6 6 PH1-OSC_OUT I/O TC PH1 - OSC_OUT 7 7 NRST I/O RST NRST - - 8 - PC0 I/O FT PC0 LCD_SEG18 ADC_IN10/ COMP1_INP 9 - PC1 I/O FT PC1 LCD_SEG19 ADC_IN11/ COMP1_INP 10 - PC2 I/O FT PC2 LCD_SEG20 ADC_IN12/ COMP1_INP 11 - PC3 I/O TC PC3 LCD_SEG21 ADC_IN13/ COMP1_INP 12 8 VSSA S - VSSA - - 13 9 VDDA S - VDDA - - 14 10 PA0-WKUP1 I/O FT PA0 USART2_CTS/ TIM2_CH1_ETR WKUP1/ADC_IN0/ COMP1_INP 15 11 PA1 I/O FT PA1 USART2_RTS/TIM2_CH2/ LCD_SEG0 ADC_IN1/ COMP1_INP 16 12 PA2 I/O FT PA2 USART2_TX/TIM2_CH3/ TIM9_CH1/LCD_SEG1 ADC_IN2/ COMP1_INP 17 13 PA3 I/O TC PA3 USART2_RX/TIM2_CH4/ TIM9_CH2/LCD_SEG2 ADC_IN3/ COMP1_INP 18 - VSS_4 S - VSS_4 - - 19 - VDD_4 S - VDD_4 - - Pin name (4) Alternate functions Additional functions DocID025966 Rev 6 33/103 40 Pin descriptions STM32L100x6/8/B-A Table 9. STM32L100x6/8/B-A pin definitions (continued) Pins LQFP64 UFQFPN48 Pin type(1) I/O structure Pin functions Main function(2) (after reset) 20 14 PA4 I/O TC PA4 SPI1_NSS/USART2_CK ADC_IN4/ DAC_OUT1/ COMP1_INP 21 15 PA5 I/O TC PA5 SPI1_SCK/TIM2_CH1_ETR ADC_IN5/ DAC_OUT2/ COMP1_INP 22 16 PA6 I/O FT PA6 SPI1_MISO/TIM3_CH1/ LCD_SEG3/TIM10_CH1 ADC_IN6/ COMP1_INP 23 17 PA7 I/O FT PA7 SPI1_MOSI/TIM3_CH2/ LCD_SEG4/TIM11_CH1 ADC_IN7/ COMP1_INP 24 - PC4 I/O FT PC4 LCD_SEG22 ADC_IN14/ COMP1_INP 25 - PC5 I/O FT PC5 LCD_SEG23 ADC_IN15/ COMP1_INP 26 18 PB0 I/O TC PB0 TIM3_CH3/LCD_SEG5 ADC_IN8/ COMP1_INP/ VREF_OUT 27 19 PB1 I/O FT PB1 TIM3_CH4/LCD_SEG6 ADC_IN9/ COMP1_INP/ VREF_OUT 28 20 PB2 I/O FT PB2/BOOT1 BOOT1 - 29 21 PB10 I/O FT PB10 I2C2_SCL/USART3_TX/ TIM2_CH3/ LCD_SEG10 - 30 22 PB11 I/O FT PB11 I2C2_SDA/USART3_RX /TIM2_CH4/LCD_SEG11 - 31 23 VSS_1 S - VSS_1 - - 32 24 VDD_1 S - VDD_1 - - Pin name Alternate functions Additional functions 33 25 PB12 I/O FT PB12 SPI2_NSS/I2C2_SMBA/ USART3_CK/ LCD_SEG12/ TIM10_CH1 34 26 PB13 I/O FT PB13 SPI2_SCK/USART3_CTS/ LCD_SEG13/TIM9_CH1 34/103 DocID025966 Rev 6 ADC_IN18/ COMP1_INP/ ADC_IN19/ COMP1_INP STM32L100x6/8/B-A Pin descriptions Table 9. STM32L100x6/8/B-A pin definitions (continued) Pins LQFP64 UFQFPN48 Pin type(1) I/O structure Pin functions Main function(2) (after reset) 35 27 PB14 I/O FT PB14 SPI2_MISO/USART3_RTS/ LCD_SEG14/TIM9_CH2 ADC_IN20/ COMP1_INP 36 28 PB15 I/O FT PB15 SPI2_MOSI/LCD_SEG15/ TIM11_CH1 ADC_IN21/ COMP1_INP/ RTC_REFIN 37 - PC6 I/O FT PC6 TIM3_CH1/LCD_SEG24 - 38 - PC7 I/O FT PC7 TIM3_CH2/LCD_SEG25 - 39 - PC8 I/O FT PC8 TIM3_CH3/LCD_SEG26 - 40 - PC9 I/O FT PC9 TIM3_CH4/LCD_SEG27 - 41 29 PA8 I/O FT PA8 USART1_CK/MCO/LCD_COM0 - 42 30 PA9 I/O FT PA9 USART1_TX/LCD_COM1 - 43 31 PA10 I/O FT PA10 USART1_RX/LCD_COM2 - 44 32 PA11 I/O FT PA11 USART1_CTS/SPI1_MISO USB_DM 45 33 PA12 I/O FT PA12 USART1_RTS/SPI1_MOSI USB_DP 46 34 PA13 I/O FT JTMS-SWDIO JTMS-SWDIO - 47 35 VSS_2 S - VSS_2 - - 48 36 VDD_2 S - VDD_2 - - 49 37 PA14 I/O FT JTCK-SWCLK JCTK-SWCLK - 50 38 PA15 I/O FT JTDI TIM2_CH1_ETR/PA15/ SPI1_NSS/ LCD_SEG17/JTDI - 51 - PC10 I/O FT PC10 USART3_TX/LCD_SEG28/ LCD_SEG40/ LCD_COM4 - 52 - PC11 I/O FT PC11 USART3_RX/LCD_SEG29/ LCD_SEG41/ LCD_COM5 - 53 - PC12 I/O FT PC12 USART3_CK/LCD_SEG30/ LCD_SEG42/ LCD_COM6 - 54 - PD2 I/O FT PD2 TIM3_ETR/LCD_SEG31/ LCD_SEG43/ LCD_COM7 - Pin name Alternate functions Additional functions DocID025966 Rev 6 35/103 40 Pin descriptions STM32L100x6/8/B-A Table 9. STM32L100x6/8/B-A pin definitions (continued) Pins LQFP64 UFQFPN48 Pin type(1) I/O structure Pin functions Main function(2) (after reset) 55 39 PB3 I/O FT JTDO TIM2_CH2/PB3/SPI1_SCK/ LCD_SEG7/JTDO COMP2_INM 56 40 PB4 I/O FT NJTRST TIM3_CH1/PB4/SPI1_MISO/ LCD_SEG8/NJTRST COMP2_INP 57 41 PB5 I/O FT PB5 I2C1_SMBA/TIM3_CH2/ SPI1_MOSI/LCD_SEG9 COMP2_INP 58 42 PB6 I/O FT PB6 I2C1_SCL/TIM4_CH1/ USART1_TX - 59 43 PB7 I/O FT PB7 I2C1_SDA/TIM4_CH2 /USART1_RX PVD_IN 60 44 BOOT0 I B BOOT0 - - 61 45 PB8 I/O FT PB8 TIM4_CH3/I2C1_SCL/ LCD_SEG16/ TIM10_CH1 - 62 46 PB9 I/O FT PB9 TIM4_CH4/I2C1_SDA/ LCD_COM3/ TIM11_CH1 - 63 47 VSS_3 S - VSS_3 - - 64 48 VDD_3 S - VDD_3 - - Pin name Alternate functions Additional functions 1. I = input, O = output, S = supply. 2. Function availability depends on the chosen device. For devices having reduced peripheral counts, it is always the lower number of peripheral that is included. For example, if a device has only one SPI and two USARTs, they will be called SPI1 and USART1 & USART2, respectively. Refer to Table 2 on page 10. 3. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is on (by setting the LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose PC14/PC15 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins section in the STM32L1xxxx reference manual (RM0038). 4. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is on (by setting the HSEON bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os, respectively, when the HSE oscillator is off (after reset, the HSE oscillator is off). The HSE has priority over the GPIO function. 36/103 DocID025966 Rev 6 Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFI O8 AFI O9 AFIO11 AFIO 12 AFIO 13 AFIO14 AFIO15 Port name Alternate function SYSTEM BOOT0 BOOT0 NRST NRST TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 N/A USART 1/2/3 N/A N/A LCD N/A N/A RI SYSTEM - - - - - - - - - - - - - - DocID025966 Rev 6 - - - - - - - - - - - - - - PA0-WKUP1 - TIM2_CH1_ETR - - - - - USART2_CTS - - - - - TIMx_IC1 EVENTOUT PA1 - TIM2_CH2 - - - - - USART2_RTS - - [SEG0] - - TIMx_IC2 EVENTOUT PA2 - TIM2_CH3 - TIM9_CH1 - - - USART2_TX - - [SEG1] - - TIMx_IC3 EVENTOUT PA3 - TIM2_CH4 - TIM9_CH2 - - USART2_RX - - [SEG2] - - TIMx_IC4 EVENTOUT PA4 - - - - - SPI1_NSS - USART2_CK - - - - - TIMx_IC1 EVENTOUT PA5 - TIM2_CH1_ETR - - - SPI1_SCK - - - - - - - TIMx_IC2 EVENTOUT PA6 - - TIM3_CH1 TIM10_CH1 - SPI1_MISO - - - - [SEG3] - - TIMx_IC3 EVENTOUT - TIM3_CH2 TIM11_CH1 - PA7 PA8 MCO - - SPI1_MOSI - - - [SEG4] - - TIMx_IC4 EVENTOUT - - - - - - USART1_CK - - [COM0] - - TIMx_IC1 EVENTOUT - - - - - - - USART1_TX - - [COM1] - - TIMx_IC2 EVENTOUT PA10 - - - - - - - USART1_RX - - [COM2] - - TIMx_IC3 EVENTOUT PA11 - - - - - SPI1_MISO - USART1_CTS - - - - - TIMx_IC4 EVENTOUT PA12 - - - - - SPI1_MOSI - USART1_RTS - - - - - TIMx_IC1 EVENTOUT PA13 JTMSSWDIO - - - - - - - - - - - - TIMx_IC2 EVENTOUT PA14 JTCKSWCLK - - - - - - - - - - - - TIMx_IC3 EVENTOUT PA15 JTDI 37/103 TIM2_CH1_ETR - - - - - - - SEG17 - - TIMx_IC4 EVENTOUT PB0 - - TIM3_CH3 - - - - - - - [SEG5] - - - EVENTOUT PB1 - - TIM3_CH4 - - - - - - - [SEG6] - - - EVENTOUT PB2 BOOT1 - - - - - - - - - - - - EVENTOUT PB3 JTDO - - - - - - - - - - EVENTOUT TIM2_CH2 SPI1_NSS SPI1_SCK [SEG7] Pin descriptions PA9 STM32L100x6/8/B-A Table 10. Alternate function input/output Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFI O8 AFI O9 AFIO11 AFIO 12 AFIO 13 AFIO14 AFIO15 LCD N/A N/A RI SYSTEM Port name Alternate function SYSTEM PB4 NJTRST TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 N/A USART 1/2/3 N/A N/A - TIM3_CH1 - - SPI1_MISO - - - - [SEG8] - - - EVENTOUT SPI1_MOSI - - - - [SEG9] - - - EVENTOUT - - - - - EVENTOUT PB5 - - TIM3_CH2 - I2C1_ SMBA PB6 - - TIM4_CH1 - I2C1_SCL - - USART1_TX - USART1_RX - DocID025966 Rev 6 PB7 - - TIM4_CH2 I2C1_SDA - - - - - - - EVENTOUT PB8 - - TIM4_CH3 TIM10_CH1* I2C1_SCL - - - - - SEG16 - - - - EVENTOUT PB9 - - TIM4_CH4 TIM11_CH1* I2C1_SDA - - - - - [COM3] - - - EVENTOUT PB10 - TIM2_CH3 - - I2C2_SCL - - USART3_TX - - SEG10 - - - EVENTOUT PB11 - TIM2_CH4 - - I2C2_SDA - - USART3_RX - - SEG11 - - - EVENTOUT I2C2_ SMBA SPI2_NSS - USART3_CK - - SEG12 - - - EVENTOUT - - - TIM10_CH1 PB13 - - - TIM9_CH1 - SPI2_SCK - USART3_CTS - - SEG13 - - - EVENTOUT PB14 - - - TIM9_CH2 - SPI2_MISO - USART3_RTS - - SEG14 - - - EVENTOUT PB15 - - - TIM11_CH1 - SPI2_MOSI - - - - SEG15 - - - EVENTOUT PC0 - - - - - - - - - - SEG18 - - TIMx_IC1 EVENTOUT PC1 - - - - - - - - - - SEG19 - - TIMx_IC2 EVENTOUT PC2 - - - - - - - - - - SEG20 - - TIMx_IC3 EVENTOUT PC3 - - - - - - - - - - SEG21 - - TIMx_IC4 EVENTOUT PC4 - - - - - - - - - - SEG22 - - TIMx_IC1 EVENTOUT PC5 - - - - - - - - - - SEG23 - - TIMx_IC2 EVENTOUT PC6 - - TIM3_CH1 - - - - - - - SEG24 - - TIMx_IC3 EVENTOUT PC7 - - TIM3_CH2 - - - - - - - SEG25 - - TIMx_IC4 EVENTOUT PC8 - - TIM3_CH3 - - - - - - - SEG26 - - TIMx_IC1 EVENTOUT PC9 - - TIM3_CH4 - - - - - - - SEG27 - - TIMx_IC2 EVENTOUT STM32L100x6/8/B-A PB12 Pin descriptions 38/103 Table 10. Alternate function input/output (continued) Digital alternate function number AFIO0 AFIO1 AFIO2 AFIO3 AFIO4 AFIO5 AFOI6 AFIO7 AFI O8 AFI O9 AFIO11 AFIO 12 AFIO 13 AFIO14 AFIO15 USART 1/2/3 N/A N/A LCD N/A N/A RI SYSTEM Port name Alternate function DocID025966 Rev 6 SYSTEM TIM2 TIM3/4 TIM9/10/11 I2C1/2 SPI1/2 N/A PC10 - - - - - - - USART3_TX - - COM4 / SEG28 / SEG40 - - TIMx_IC3 EVENTOUT PC11 - - - - - - - USART3_RX - - COM5 / SEG29 / SEG41 - - TIMx_IC4 EVENTOUT PC12 - - - - - - - USART3_CK - - COM6 / SEG30 / SEG42 - - TIMx_IC1 EVENTOUT PC13WKUP2 - - - - - - - - - - - - - TIMx_IC2 EVENTOUT PC14OSC32_IN - - - - - - - - - - - - - TIMx_IC3 EVENTOUT PC15OSC32_OUT - - - - - - - - - - - - - TIMx_IC4 EVENTOUT PD2 - - TIM3_ETR - - - - - - - - - TIMx_IC3 EVENTOUT PH0OSC_IN - - - - - - - - - - - - - - - PH1OSC_OUT - - - - - - - - - - - - - - - COM7 / SEG31 / SEG43 STM32L100x6/8/B-A Table 10. Alternate function input/output (continued) Pin descriptions 39/103 Memory mapping 5 STM32L100x6/8/B-A Memory mapping The memory map is shown in the following figure. Figure 5. Memory map $3%PHPRU\VSDFH [)))))))) UHVHUYHG [( UHVHUYHG [ UHVHUYHG [ '0$ [ UHVHUYHG [ )ODVK,QWHUI DFH [& 5&& [ UHVHUYHG [ &5& [ [)))))))) [( [( #RUWH[ 0,QWHUQDO 3HULSKHUDOV [ [ [ [& [& UHVHUYHG 3RUW+ UHVHUYHG 3RUW' [ 3RUW& [ 3RUW% [ 3RUW$ UHVHUYHG [& [ [ [$ [ [ [ [ [ [& [ [ [))) [)) $'& 2SWLRQ%\WHV [ UHVH UYH G 7,0 7,0 7,0 (;7, 6<6&)* UHVHUYHG RESE UYHG [ [& [)) RESE RVED 6\VWHPPHPRU\ [ [ [ 3HULSKHUDOV [& [ UHVH RVED 65$0 [ [& [ [ [ [ UHVHUYHG '$& 3:5 [ &2035, UHVHUYHG [)) [ [ 63, UHVHUYHG [ [ 86$57 UHVHUYHG 'DWD((3520 [ RESE UYHG [& [ [ [ [ E\WH 86% 86%5HJ LVWHUV ,& ,& UHVHUYHG 86$57 86$57 UHVHUYHG 63, UHVHUYHG ,:'* ::'* [& )ODVKPHPRU\ 5HVHUYHG [ [ [ $OLDVHGWR)ODVKRUV\VWHP PHPRU\GHSHQGLQJRQ [ %227SLQV [& [ [ [& [ [ [ 57& /&' UHVHUYHG 7,0 7,0 UHVHUYHG 7,0 7,0 7,0 069 40/103 DocID025966 Rev 6 STM32L100x6/8/B-A Electrical characteristics 6 Electrical characteristics 6.1 Parameter conditions Unless otherwise specified, all voltages are referenced to VSS. 6.1.1 Minimum and maximum values Unless otherwise specified the minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage and frequencies by tests in production on 100% of the devices with an ambient temperature at TA = 25 C and TA = TAmax (given by the selected temperature range). Data based on characterization results, design simulation and/or technology characteristics are indicated in the table footnotes. Based on characterization, the minimum and maximum values refer to sample tests and represent the mean value plus or minus three times the standard deviation (mean3). Please refer to device ErrataSheet for possible latest changes of electrical characteristics. 6.1.2 Typical values Unless otherwise specified, typical data are based on TA = 25 C, VDD = 3.0 V (for the 1.8 V VDD 3.6 V voltage range). They are given only as design guidelines and are not tested. Typical ADC accuracy values are determined by characterization of a batch of samples from a standard diffusion lot over the full temperature range, where 95% of the devices have an error less than or equal to the value indicated (mean2). 6.1.3 Typical curves Unless otherwise specified, all typical curves are given only as design guidelines and are not tested. 6.1.4 Loading capacitor The loading conditions used for pin parameter measurement are shown in Figure 6. 6.1.5 Pin input voltage The input voltage measurement on a pin of the device is described in Figure 7. Figure 6. Pin loading conditions Figure 7. Pin input voltage 0&8SLQ 0&8SLQ & S) 9,1 DLF DocID025966 Rev 6 DLG 41/103 91 Electrical characteristics 6.1.6 STM32L100x6/8/B-A Power supply scheme Figure 8. Power supply scheme 287 *3,2V ,1 /HYHOVKLIWHU 6WDQGE\SRZHUFLUFXLWU\ 26&.57& :DNHXSORJLF 57&EDFNXSUHJLVWHUV ,2 /RJLF 9'' 9''1 .HUQHO ORJLF &38 'LJLWDO 0HPRULHV 5HJXODWRU 1[Q) [) 9661 9''$ 9''$ 95() Q) ) 95() $'& '$& $QDORJ 5&V3// &203 966$ 069 42/103 DocID025966 Rev 6 STM32L100x6/8/B-A 6.1.7 Electrical characteristics Optional LCD power supply scheme Figure 9. Optional LCD power supply scheme 96(/ 9'' 9''1 6WHSXS &RQYHUWHU 1[Q) [) 2SWLRQ 9/&' Q) 9/&' 2SWLRQ &(;7 /&' 3% 3% 3% &UDLO 9/&'UDLO 9/&'UDLO 9/&'UDLO &UDLO &UDLO 9661 069 1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open. 2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an external capacitance is needed for correct behavior of this converter. 6.1.8 Current consumption measurement Figure 10. Current consumption measurement scheme $ 1[Q) [) 1[9'' 1[966 9/&' 9''$ Q) ) 95() 95() 966$ 069 DocID025966 Rev 6 43/103 91 Electrical characteristics 6.2 STM32L100x6/8/B-A Absolute maximum ratings Stresses above the absolute maximum ratings listed in Table 11: Voltage characteristics, Table 12: Current characteristics, and Table 13: Thermal characteristics may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these conditions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Table 11. Voltage characteristics Symbol VDD-VSS VIN(2) |VDDx| |VSSX - VSS| VESD(HBM) Ratings Min Max -0.3 4.0 Input voltage on five-volt tolerant pin VSS -0.3 VDD+4.0 Input voltage on any other pin VSS - 0.3 4.0 - 50 - 50 External main supply voltage (including VDDA and VDD)(1) Variations between different VDD power pins Variations between all different ground pins(3) Electrostatic discharge voltage (human body model) Unit V mV see Section 6.3.11 - 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. VIN maximum must always be respected. Refer to Table 12 for maximum allowed injected current values. 3. Include VREF- pin. Table 12. Current characteristics Symbol IVDD IVSS(2) IVDD(PIN) IVSS(PIN) IIO IIO(PIN) IINJ(PIN) (3) IINJ(PIN) Ratings Max. Total current into sum of all VDD_x power lines (source)(1) Total current out of sum of all VSS_x ground lines (sink)(1) Maximum current into each VDD_x power pin (source)(1) (1) 100 100 70 Maximum current out of each VSS_x ground pin (sink) -70 Output current sunk by any I/O and control pin 25 Output current sourced by any I/O and control pin 60 Total output current sourced by sum of all IOs and control pins(2) -60 Injected current on five-volt tolerant I/O(4) RST and B pins -5/+0 Injected current on any other Total injected current (sum of all I/O and control mA - 25 Total output current sunk by sum of all IOs and control pins(2) pin(5) Unit 5 pins)(6) 25 1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the permitted range. 2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages. 3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.17. 44/103 DocID025966 Rev 6 STM32L100x6/8/B-A Electrical characteristics 4. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be exceeded. Refer to Table 11 for maximum allowed input voltage values. 5. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be exceeded. Refer to Table 11: Voltage characteristics for the maximum allowed input voltage values. 6. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). Table 13. Thermal characteristics Symbol TSTG Ratings Storage temperature range Value Unit -65 to +150 C 105 C Maximum junction temperature TJ TLEAD Maximum lead temperature during soldering see note (1) C (R) 1. Compliant with JEDEC Std J-STD-020D (for small body, Sn-Pb or Pb assembly), the ST ECOPACK 7191395 specification, and the European directive on Restrictions on Hazardous Substances (ROHS directive 2011/65/EU, July 2011). 6.3 Operating conditions 6.3.1 General operating conditions Table 14. General operating conditions Symbol Parameter Conditions Min Max Unit fHCLK Internal AHB clock frequency - 0 32 fPCLK1 Internal APB1 clock frequency - 0 32 fPCLK2 Internal APB2 clock frequency - 0 32 BOR detector enabled, at power on 1.8 3.6 V Must be the same voltage as VDD(2) 1.8 3.6 V FT pins: 2.0 V VDD -0.3 5.5(3) FT pins: VDD < 2.0 V -0.3 5.25(3) 0 5.5 -0.3 VDD+0.3 LQFP64 package - 444 UFQFPN48 package - 606 VDD VDDA(1) VIN Standard operating voltage Analog operating voltage (ADC and DAC used) I/O input voltage BOOT0 Any other pin PD Power dissipation at TA = 85 C(4) TA Ambient temperature range Maximum power dissipation -40 85 TJ Junction temperature range -40 C TA 85C -40 105 MHz V mW C 1. When the ADC is used, refer to Table 55: ADC characteristics. 2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and VDDA can be tolerated during power-up and operation. 3. To sustain a voltage higher than VDD+0.3 V, the internal pull-up/pull-down resistors must be disabled. DocID025966 Rev 6 45/103 91 Electrical characteristics STM32L100x6/8/B-A 4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 64: Thermal characteristics on page 98). 6.3.2 Embedded reset and power control block characteristics The parameters given in the following table are derived from the tests performed under the ambient temperature condition summarized in the following table. Table 15. Embedded reset and power control block characteristics Symbol Parameter Min Typ Max BOR detector enabled 0 - BOR detector enabled 20 - BOR detector disabled 0 - 1000 Reset temporization VDD rising, BOR enabled - 2 3.3 VPOR/PDR Power on/power down reset threshold Falling edge 1 1.5 1.65 Rising edge 1.3 1.5 1.65 VBOR0 Brown-out reset threshold 0 Falling edge 1.67 1.7 1.74 Rising edge 1.69 1.76 1.8 VBOR1 Brown-out reset threshold 1 Falling edge 1.87 1.93 1.97 Rising edge 1.96 2.03 2.07 VBOR2 Brown-out reset threshold 2 Falling edge 2.22 2.30 2.35 Rising edge 2.31 2.41 2.44 VBOR3 Brown-out reset threshold 3 Falling edge 2.45 2.55 2.60 Rising edge 2.54 2.66 2.7 VBOR4 Brown-out reset threshold 4 Falling edge 2.68 2.8 2.85 Rising edge 2.78 2.9 2.95 VDD rise time rate tVDD(1) TRSTTEMPO 46/103 VDD fall time rate (1) Conditions DocID025966 Rev 6 Unit s/V ms V V STM32L100x6/8/B-A Electrical characteristics Table 15. Embedded reset and power control block characteristics (continued) Symbol Parameter Conditions VPVD0 Programmable voltage detector threshold 0 VPVD1 PVD threshold 1 VPVD2 PVD threshold 2 VPVD3 PVD threshold 3 VPVD4 PVD threshold 4 VPVD5 PVD threshold 5 VPVD6 PVD threshold 6 Vhyst Hysteresis voltage Min Typ Max Falling edge 1.8 1.85 1.88 Rising edge 1.88 1.94 1.99 Falling edge 1.98 2.04 2.09 Rising edge 2.08 2.14 2.18 Falling edge 2.20 2.24 2.28 Rising edge 2.28 2.34 2.38 Falling edge 2.39 2.44 2.48 Rising edge 2.47 2.54 2.58 Falling edge 2.57 2.64 2.69 Rising edge 2.68 2.74 2.79 Falling edge 2.77 2.83 2.88 Rising edge 2.87 2.94 2.99 Falling edge 2.97 3.05 3.09 Rising edge 3.08 3.15 3.20 BOR0 threshold - 40 - All BOR and PVD thresholds excepting BOR0 - 100 - Unit V mV 1. Guaranteed by characterization results. DocID025966 Rev 6 47/103 91 Electrical characteristics 6.3.3 STM32L100x6/8/B-A Embedded internal reference voltage The parameters given in the following table are based on characterization results, unless otherwise specified. Table 16. Embedded internal reference voltage calibration values Calibration value name Description Raw data acquired at temperature of 30 C 5 C, VDDA= 3 V 10 mV VREFINT_CAL Memory address 0x1FF8 0078-0x1FF8 0079 Table 17. Embedded internal reference voltage Symbol Parameter Conditions Min Typ Max Unit VREFINT out(1) Internal reference voltage - 40 C < TJ < +85 C IREFINT Internal reference current consumption - - 1.4 2.3 A Internal reference startup time - - 2 3 ms VVREF_MEAS VDDA voltage during VREFINT factory measure - 2.99 3 3.01 V AVREF_MEAS Accuracy of factory-measured VREF value (2) Including uncertainties due to ADC and VDDA values - - 5 mV TVREFINT TCoeff(3) ACoeff 1.202 1.224 1.242 V Temperature coefficient -40 C < TJ < +85 C - 25 100 ppm/C (3) Long-term stability 1000 hours, T= 25 C - - 1000 ppm (3)(4) Voltage coefficient 3.0 V < VDDA < 3.6 V - - 2000 ppm/V VDDCoeff TS_vrefint(3) ADC sampling time when reading the internal reference voltage - 4 - - s TADC_BUF(3) Startup time of reference voltage buffer for ADC - - - 10 s IBUF_ADC(3) Consumption of reference voltage buffer for ADC - - 13.5 25 A IVREF_OUT(3) VREF_OUT output current(5) - - - 1 A CVREF_OUT(3) VREF_OUT output load - - - 50 pF Consumption of reference voltage buffer for VREF_OUT and COMP - - 730 1200 nA - 24 25 26 ILPBUF(3) VREFINT_DIV1(3) 1/4 reference voltage VREFINT_DIV2 (3) 1/2 reference voltage - 49 50 51 VREFINT_DIV3 (3) 3/4 reference voltage - 74 75 76 1. Guaranteed by test in production. 2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes. 3. Guaranteed by characterization results. 4. Shortest sampling time can be determined in the application by multiple interactions. 5. To guarantee less than 1% VREF_OUT deviation. 48/103 DocID025966 Rev 6 % VREFINT STM32L100x6/8/B-A 6.3.4 Electrical characteristics Supply current characteristics The current consumption is a function of several parameters and factors such as the operating voltage, ambient temperature, I/O pin loading, device software configuration, operating frequencies, I/O pin switching rate, program location in memory and executed binary code. The current consumption is measured as described in Figure 10: Current consumption measurement scheme. All Run-mode current consumption measurements given in this section are performed with a reduced code that gives a consumption equivalent to Dhrystone 2.1 code, unless otherwise specified. The current consumption values are derived from the tests performed under ambient temperature TA=25C and VDD supply voltage conditions summarized in Table 14: General operating conditions, unless otherwise specified. The MCU is placed under the following conditions: * All I/O pins are configured in analog input mode. * All peripherals are disabled except when explicitly mentioned. * The Flash memory access time, 64-bit access and prefetch is adjusted depending on fHCLK frequency and voltage range to provide the best CPU performance. * When the peripherals are enabled fAPB1 = fAPB2 = fAHB. * When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or HSE = 16 MHz (if HSE bypass mode is used). * The HSE user clock applied to OSC_IN input follows the characteristics specified in Table 27: High-speed external user clock characteristics. * For maximum current consumption VDD = VDDA = 3.6 V is applied to all supply pins. * For typical current consumption VDD = VDDA = 3.0 V is applied to all supply pins if not specified otherwise. DocID025966 Rev 6 49/103 91 Electrical characteristics STM32L100x6/8/B-A Table 18. Current consumption in Run mode, code with data processing running from Flash Symbol Parameter fHCLK Typ Max(1) 1 MHz 215 285 2 MHz 400 490 4 MHz 725 1000 4 MHz 0.915 1.3 8 MHz 1.75 2.15 16 MHz 3.4 4 8 MHz 2.1 2.9 16 MHz 4.2 5.2 32 MHz 8.25 9.6 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 3.5 4.4 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 8.2 10.2 65 kHz 0.041 0.085 524 kHz 0.125 0.180 4.2 MHz 0.775 0.935 Conditions Range 3, VCORE=1.2 V VOS[1:0] = 11 IDD (Run from Flash) Supply current in Run mode, code executed from Flash fHSE = fHCLK up to 16 MHz, included Range 2, VCORE=1.5 V fHSE = fHCLK/2 above VOS[1:0] = 10 16 MHz (PLL ON)(2) Range 1, VCORE=1.8 V VOS[1:0] = 01 HSI clock source (16 MHz) MSI clock, 65 kHz MSI clock, 524 kHz Range 3, VCORE=1.2 V VOS[1:0] = 11 MSI clock, 4.2 MHz 1. Guaranteed by characterization results, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). 50/103 DocID025966 Rev 6 Unit A mA STM32L100x6/8/B-A Electrical characteristics Table 19. Current consumption in Run mode, code with data processing running from RAM Symbol Parameter Typ Max(1) 1 MHz 185 255 2 MHz 345 435 4 MHz 645 930 4 MHz 0.755 1.5 8 MHz 1.5 2.2 16 MHz 3.0 3.6 8 MHz 1.8 2.9 16 MHz 3.6 4.3 32 MHz 7.15 8.5 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 2.95 3.7 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 7.15 8.7 65 kHz 39 115 524 kHz 110 205 4.2 MHz 690 870 Conditions Range 3, VCORE=1.2 V VOS[1:0] = 11 fHSE = fHCLK up to 16 MHz, included fHSE = fHCLK/2 above 16 MHz (PLL ON)(2) IDD (Run from RAM) Range 2, VCORE=1.5 V VOS[1:0] = 10 Range 1, VCORE=1.8 V VOS[1:0] = 01 Supply current in Run mode, code executed from RAM, Flash switched off HSI clock source (16 MHz) MSI clock, 65 kHz MSI clock, 524 kHz MSI clock, 4.2 MHz Range 3, VCORE=1.2 V VOS[1:0] = 11 fHCLK Unit A mA A 1. Guaranteed by characterization results, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register). DocID025966 Rev 6 51/103 91 Electrical characteristics STM32L100x6/8/B-A Table 20. Current consumption in Sleep mode Symbol Parameter Conditions Range 3, VCORE=1.2 V VOS[1:0] = 11 fHSE = fHCLK up to 16 MHz included, Range 2, fHSE = fHCLK/2 VCORE=1.5 V above 16 MHz (PLL VOS[1:0] = 10 ON)(2) Supply current in Sleep mode, Flash OFF HSI clock source (16 MHz) MSI clock, 65 kHz MSI clock, 524 kHz MSI clock, 4.2 MHz IDD (Sleep) MSI clock, 65 kHz MSI clock, 524 kHz MSI clock, 4.2 MHz 1 MHz 50 155 2 MHz 78.5 235 4 MHz 140 370(3) 4 MHz 165 375 8 MHz 310 530 16 MHz 590 1000 350 615 16 MHz 680 1200 32 MHz 1600 2350 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 640 970 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 1600 2350 Range 3, VCORE=1.2 V VOS[1:0] = 11 65 kHz 19 60 524 kHz 33 90 4.2 MHz 145 210 1 MHz 60.5 145 2 MHz 89.5 225 4 MHz 150 360 4 MHz 180 370 8 MHz 320 490 16 MHz 605 895 Range 1, VCORE=1.8 V VOS[1:0] = 01 8 MHz 380 565 16 MHz 695 1070 32 MHz 1600 2200 Range 2, VCORE=1.5 V VOS[1:0] = 10 16 MHz 650 970 Range 1, VCORE=1.8 V VOS[1:0] = 01 32 MHz 1600 2320 Range 3, VCORE=1.2V VOS[1:0] = 11 1. Guaranteed by characterization results, unless otherwise specified. 2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register) 3. Guaranteed by test in production. 52/103 Max(1) 8 MHz fHSE = fHCLK up to Range 2, 16 MHz included, VCORE=1.5 V fHSE = fHCLK/2 above 16 MHz (PLL VOS[1:0] = 10 ON)(2) HSI clock source (16 MHz) Typ Range 1, VCORE=1.8 V VOS[1:0] = 01 Range 3, VCORE=1.2 V VOS[1:0] = 11 Supply current in Sleep mode, Flash ON fHCLK DocID025966 Rev 6 65 kHz 29.5 65 524 kHz 44 80 4.2 MHz 155 220 Unit A A STM32L100x6/8/B-A Electrical characteristics Table 21. Current consumption in Low power run mode Symbol IDD (LP Run) IDD Max (LP Run)(2) Parameter Supply current in Low power run mode Typ Max(1) TA = -40 C to 25 C 10.9 12 TA = 85 C 16.5 23 TA = -40 C to 25 C 15 16 TA = 85 C 22 29 TA = -40 C to 25 C 29 37 TA = 55 C 32.5 40 TA = 85 C 35.5 54 TA = -40 C to 25 C 23 24 TA = 85 C 31 34 TA = -40 C to 25 C 29 31 TA = 85 C 38 41 TA = -40 C to 25 C 46 55 TA = 55 C 48 59 TA = 85 C 53.5 72 - 200 Conditions All peripherals OFF, code executed from RAM, Flash switched OFF, VDD from 1.8 V to 3.6 V All peripherals OFF, code executed from Flash, VDD from 1.8 V to 3.6 V Max allowed VDD from current in 1.8 V to Low power 3.6 V run mode MSI clock, 65 kHz fHCLK = 32 kHz MSI clock, 65 kHz fHCLK = 65 kHz MSI clock, 131 kHz fHCLK = 131 kHz MSI clock, 65 kHz fHCLK = 32 kHz MSI clock, 65 kHz fHCLK = 65 kHz MSI clock, 131 kHz fHCLK = 131 kHz - - Unit A 1. Guaranteed by characterization results, unless otherwise specified. 2. This limitation is related to the consumption of the CPU core and the peripherals that are powered by the regulator. Consumption of the I/Os is not included in this limitation. DocID025966 Rev 6 53/103 91 Electrical characteristics STM32L100x6/8/B-A Table 22. Current consumption in Low power sleep mode Symbol Parameter Conditions MSI clock, 65 kHz fHCLK = 32 kHz Flash OFF IDD (LP Sleep) Supply current in Low power sleep mode MSI clock, 65 kHz fHCLK = 32 kHz All peripherals Flash ON OFF, VDD MSI clock, 65 kHz from 1.8 V fHCLK = 65 kHz, to 3.6 V Flash ON MSI clock, 131 kHz fHCLK = 131 kHz, Flash ON TIM9 and USART1 enabled, Flash ON, VDD from 1.8 V to 3.6 V IDD Max (LP Sleep) Max allowed VDD from current in 1.8 V to Low power 3.6 V Sleep mode MSI clock, 65 kHz fHCLK = 32 kHz MSI clock, 65 kHz fHCLK = 65 kHz MSI clock, 131 kHz fHCLK = 131 kHz Typ TA = -40 C to 25 C 5.5 - TA = -40 C to 25 C 15 16 TA = 85 C 20 23 TA = -40 C to 25 C 15 16 20.5 23 TA = -40 C to 25 C 18 20 TA = 55 C 21 22 TA = 85 C 23 27 TA = -40 C to 25 C 15 16 TA = 85 C 20 22 TA = -40 C to 25 C 15 16 20.5 23 TA = -40 C to 25 C 18 20 TA = 55 C 21 22 TA = 85 C 23 27 - 200 TA = 85 C TA = 85 C - 1. Guaranteed by characterization results, unless otherwise specified. 54/103 DocID025966 Rev 6 Max(1) Unit - A STM32L100x6/8/B-A Electrical characteristics Table 23. Typical and maximum current consumptions in Stop mode Symbol Parameter RTC clocked by LSI, regulator in LP mode, HSI and HSE OFF (no independent watchdog) (1)(2) TA = -40C to 25C VDD = 1.8 V 1.13 - LCD OFF TA = -40C to 25C 1.38 4 TA = 55C 1.70 6 TA= 85C 3.30 10 TA = -40C to 25C 1.50 6 TA = 55C 1.80 7 TA= 85C 3.45 12 TA = -40C to 25C 3.80 10 TA = 55C 4.30 11 TA= 85C 6.10 16 TA = -40C to 25C 1.50 - LCD OFF TA = 55C 1.90 - TA= 85C 3.65 - TA = -40C to 25C 1.60 - TA = 55C 2.05 - TA= 85C 3.75 - TA = -40C to 25C 3.90 - TA = 55C 4.55 - TA= 85C 6.35 - TA = -40C to 25C VDD = 1.8 V 1.23 - TA = -40C to 25C VDD = 3.0 V 1.50 - TA = -40C to 25C VDD = 3.6 V 1.75 - TA = -40C to 25C 1.80 2.2 TA = -40C to 25C 0.434 1 TA = 55C 0.735 3 TA= 85C 2.350 9 2 - 1.45 - LCD ON (static duty)(3) LCD ON (1/8 duty)(4) IDD (Stop with RTC) Supply current in Stop mode with RTC enabled RTC clocked by LSE external clock (32.768 kHz), regulator in LP mode, HSI and HSE OFF (no independent watchdog) LCD ON (static duty)(3) LCD ON (1/8 duty)(1) RTC clocked by LSE (no independent watchdog)(5) IDD (Stop) LCD OFF Regulator in LP mode, HSI and HSE OFF, independent watchdog and LSI Supply current in enabled Stop mode ( RTC disabled) Regulator in LP mode, LSI, HSI and HSE OFF (no independent watchdog) IDD (WU from Stop) Max Typ(1) Conditions RMS (root mean MSI = 4.2 MHz square) supply MSI = 1.05 MHz current during wakeup time when exiting MSI = 65 kHz(6) from Stop mode VDD = 3.0 V TA = -40C to 25C DocID025966 Rev 6 Unit A mA 1.45 - 55/103 91 Electrical characteristics STM32L100x6/8/B-A 1. The typical values are given for VDD = 3.0 V and max values are given for VDD = 3.6 V, unless otherwise specified. 2. Guaranteed by characterization results, unless otherwise specified. 3. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected. 4. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected. 5. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF loading capacitors. 6. When MSI = 64 kHz, the RMS current is measured over the first 15 s following the wakeup event. For the remaining time of the wakeup period, the current is similar to the Run mode current. Table 24. Typical and maximum current consumptions in Standby mode Symbol Parameter RTC clocked by LSI (no independent watchdog) IDD (Standby with RTC) Supply current in Standby mode with RTC enabled RTC clocked by LSE (no independent watchdog)(3) Independent watchdog and LSI enabled IDD (Standby) IDD (WU from Standby) Supply current in Standby mode with RTC disabled RMS supply current during wakeup time when exiting from Standby mode Independent watchdog and LSI OFF - Max Typ(1) (1)(2) TA = -40 C to 25 C VDD = 1.8 V 0.865 - TA = -40 C to 25 C 1.11 1.9 TA = 55 C 1.15 2.2 TA= 85 C 1.35 4 TA = -40 C to 25 C VDD = 1.8 V 0.97 - TA = -40 C to 25 C 1.28 - TA = 55 C 1.4 - TA= 85 C 1.7 - TA = -40 C to 25 C 1.0 1.7 TA = -40 C to 25 C 0.277 0.6 TA = 55 C 0.31 0.9 TA = 85 C 0.52 2.75 1 - Conditions VDD = 3.0 V TA = -40 C to 25 C 1. The typical values are given for VDD = 3.0 V and max values are given for VDD = 3.6 V, unless otherwise specified. 2. Guaranteed by characterization results, unless otherwise specified. 3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF loading capacitors. 56/103 DocID025966 Rev 6 Unit A mA STM32L100x6/8/B-A Electrical characteristics On-chip peripheral current consumption The current consumption of the on-chip peripherals is given in the following table. The MCU is placed under the following conditions: * all I/O pins are in input mode with a static value at VDD or VSS (no load) * all peripherals are disabled unless otherwise mentioned * the given value is calculated by measuring the current consumption - with all peripherals clocked off - with only one peripheral clocked on Table 25. Peripheral current consumption(1) Typical consumption, VDD = 3.0 V, TA = 25 C Peripheral APB1 Range 1, Range 2, Range 3, VCORE= VCORE= VCORE= Low-power 1.8 V 1.5 V 1.2 V sleep and run VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11 TIM2 11.3 9.0 7.3 9.0 TIM3 11.4 9.1 7.1 9.1 TIM4 11.3 9.0 7.3 9.0 TIM6 3.9 3.1 2.5 3.1 TIM7 4.2 3.3 2.6 3.3 LCD 4.7 3.6 2.9 3.6 WWDG 3.7 2.9 2.4 2.9 SPI2 5.9 4.8 3.9 4.8 USART2 8.1 6.6 5.1 6.6 USART3 7.9 6.4 5.0 6.4 I2C1 7.8 6.1 4.9 6.1 I2C2 7.2 5.7 4.6 5.7 USB 12.7 10.3 8.1 10.3 PWR 3.1 2.4 2.0 2.4 DAC 6.6 5.3 4.3 5.3 COMP 5.3 4.3 3.4 4.3 DocID025966 Rev 6 Unit A/MHz (fHCLK) 57/103 91 Electrical characteristics STM32L100x6/8/B-A Table 25. Peripheral current consumption(1) (continued) Typical consumption, VDD = 3.0 V, TA = 25 C Peripheral APB2 AHB Range 1, Range 2, Range 3, VCORE= VCORE= VCORE= Low-power 1.8 V 1.5 V 1.2 V sleep and run VOS[1:0] = 01 VOS[1:0] = 10 VOS[1:0] = 11 SYSCFG & RI 2.2 1.9 1.6 1.9 TIM9 9.1 7.3 5.9 7.3 TIM10 6.0 4.9 3.9 4.9 TIM11 5.8 4.6 3.8 4.6 ADC(2) 8.7 7.0 5.6 7.0 SPI1 4.4 3.4 2.8 3.4 USART1 8.1 6.5 5.2 6.5 GPIOA 4.4 3.5 2.9 3.5 GPIOB 4.4 3.5 2.9 3.5 GPIOC 3.7 3.0 2.5 3.0 GPIOD 3.6 2.8 2.4 2.8 GPIOH 3.7 2.9 2.4 2.9 CRC 0.6 0.4 0.4 0.4 FLASH 12.2 10.2 7.8 -(3) DMA1 12.4 10.1 8.2 10.1 160 135 103 124.8 All enabled IDD (RTC) 0.4 IDD (LCD) 3.1 IDD (ADC)(4) IDD (DAC)(5) 1450 IDD (COMP1) 0.16 IDD (COMP2) Unit A/MHz (fHCLK) 340 Slow mode 2 Fast mode 5 IDD (PVD / BOR)(6) 2.6 IDD (IWDG) 0.25 A 1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock enabled, in the following conditions: fHCLK = 32 MHz (Range 1), fHCLK = 16 MHz (Range 2), fHCLK = 4 MHz (Range 3), fHCLK = 64kHz (Lowpower run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. 2. HSI oscillator is OFF for this measure. 3. In low-power sleep and run mode, the Flash memory must always be in power-down mode. 4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion (HSI consumption not included). 5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of VDD/2. DAC is in buffered mode, output is left floating. 6. Including supply current of internal reference voltage. 58/103 DocID025966 Rev 6 STM32L100x6/8/B-A 6.3.5 Electrical characteristics Wakeup time from Low-power mode The wakeup times given in the following table are measured with the MSI RC oscillator. The clock source used to wake up the device depends on the current operating mode: * Sleep mode: the clock source is the clock that was set before entering Sleep mode * Stop mode: the clock source is the MSI oscillator in the range configured before entering Stop mode * Standby mode: the clock source is the MSI oscillator running at 2.1 MHz All timings are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 26. Low-power mode wakeup timings Symbol Parameter tWUSLEEP Wakeup from Sleep mode tWUSLEEP_LP Wakeup from Low-power sleep mode fHCLK = 262 kHz tWUSTDBY Typ Max(1) Unit fHCLK = 32 MHz 0.4 - fHCLK = 262 kHz Flash enabled 46 - fHCLK = 262 kHz Flash switched OFF 46 - fHCLK = fMSI = 4.2 MHz 8.2 - fHCLK = fMSI = 4.2 MHz Voltage Ranges 1 and 2 7.7 8.9 fHCLK = fMSI = 4.2 MHz Voltage Range 3 8.2 13.1 fHCLK = fMSI = 2.1 MHz 10.2 13.4 fHCLK = fMSI = 1.05 MHz 16 20 fHCLK = fMSI = 524 kHz 31 37 fHCLK = fMSI = 262 kHz 57 66 fHCLK = fMSI = 131 kHz 112 123 fHCLK = MSI = 65 kHz 221 236 Wakeup from Standby mode FWU bit = 1 fHCLK = MSI = 2.1 MHz 58 104 Wakeup from Standby mode FWU bit = 0 fHCLK = MSI = 2.1 MHz 2.6 3.25 Wakeup from Stop mode, regulator in Run mode tWUSTOP Conditions Wakeup from Stop mode, regulator in low-power mode s ms 1. Guaranteed by characterization results, unless otherwise specified DocID025966 Rev 6 59/103 91 Electrical characteristics 6.3.6 STM32L100x6/8/B-A External clock source characteristics High-speed external user clock generated from an external source In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO. The external clock signal has to respect the I/O characteristics in Section 6.3.13. However, the recommended clock input waveform is shown in Figure 11. Table 27. High-speed external user clock characteristics(1) Symbol fHSE_ext Parameter User external clock source frequency Conditions Min CSS is on or PLL is used 1 CSS is off, PLL not used 0 VHSEH OSC_IN input pin high level voltage 0.7VDD VHSEL OSC_IN input pin low level voltage VSS tw(HSEH) tw(HSEL) OSC_IN high or low time tr(HSE) tf(HSE) OSC_IN rise or fall time Cin(HSE) - Typ Max Unit 8 32 MHz - VDD 0.3VDD 12 - - - - 20 - 2.6 - ns OSC_IN input capacitance - pF 1. Guaranteed by design. Figure 11. High-speed external clock source AC timing diagram WZ +6(+ 9+6(+ 9+6(/ WU +6( WI +6( WZ +6(/ W 7+6( 069 60/103 DocID025966 Rev 6 STM32L100x6/8/B-A Electrical characteristics Low-speed external user clock generated from an external source The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under ambient temperature and supply voltage conditions summarized in Table 14. Table 28. Low-speed external user clock characteristics(1) Symbol Parameter Min Typ Max Unit fLSE_ext User external clock source frequency 1 32.768 1000 kHz VLSEH OSC32_IN input pin high level voltage 0.7VDD - VDD - VLSEL OSC32_IN input pin low level voltage VSS - 0.3VDD - tw(LSEH) tw(LSEL) OSC32_IN high or low time 465 - - tr(LSE) tf(LSE) OSC32_IN rise or fall time - - 10 OSC32_IN input capacitance - 0.6 - CIN(LSE) ns pF 1. Guaranteed by design. Figure 12. Low-speed external clock source AC timing diagram WZ /6(+ 9/6(+ 9/6(/ WU /6( WI /6( W WZ /6(/ 7/6( 069 High-speed external clock generated from a crystal/ceramic resonator The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 29. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 29. HSE oscillator characteristics(1)(2) Symbol Parameter fOSC_IN Oscillator frequency RF Feedback resistor Conditions - DocID025966 Rev 6 Min Typ 1 200 Max Unit 24 MHz - k 61/103 91 Electrical characteristics STM32L100x6/8/B-A Table 29. HSE oscillator characteristics(1)(2) (continued) Symbol Parameter Conditions C Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) RS = 30 - VDD= 3.3 V, VIN = VSS with 30 pF load C = 20 pF fOSC = 16 MHz IHSE IDD(HSE) gm tSU(HSE) (4) HSE driving current HSE oscillator power consumption Oscillator transconductance Startup time Min Typ Max Unit 20 - pF - - 3 mA - - 2.5 (startup) 0.7 (stabilized) mA C = 10 pF fOSC = 16 MHz - - 2.5 (startup) 0.46 (stabilized) Startup 3.5 - - mA /V VDD is stabilized - 1 - ms 1. Resonator characteristics given by the crystal/ceramic resonator manufacturer. 2. Guaranteed by characterization results. 3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into account if the MCU is used in tough humidity conditions. 4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the 5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match the requirements of the crystal or resonator (see Figure 13). CL1 and CL2 are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF can be used as a rough estimate of the combined pin and board capacitance) when sizing CL1 and CL2. Refer to the application note AN2867 "Oscillator design guide for ST microcontrollers" available from the ST website www.st.com. 62/103 DocID025966 Rev 6 STM32L100x6/8/B-A Electrical characteristics Figure 13. HSE oscillator circuit diagram I+6(WRFRUH 5P 5) &2 /P &/ 26&B,1 &P JP 5HVRQDWRU &RQVXPSWLRQ FRQWURO 5HVRQDWRU 670 26&B287 &/ DLE Low-speed external clock generated from a crystal/ceramic resonator The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All the information given in this paragraph are based on characterization results obtained with typical external components specified in Table 14. In the application, the resonator and the load capacitors have to be placed as close as possible to the oscillator pins in order to minimize output distortion and startup stabilization time. Refer to the crystal resonator manufacturer for more details on the resonator characteristics (frequency, package, accuracy). Table 30. LSE oscillator characteristics (fLSE = 32.768 kHz)(1) Symbol Parameter Conditions Min Typ Max Unit fLSE Low speed external oscillator frequency - - 32.768 - kHz RF Feedback resistor - - 1.2 - M C(2) Recommended load capacitance versus equivalent serial resistance of the crystal (RS)(3) RS = 30 k - 8 - pF ILSE LSE driving current VDD = 3.3 V, VIN = VSS - - 1.1 A VDD = 1.8 V - 450 - VDD = 3.0 V - 600 - VDD = 3.6V - 750 - - 3 - - A/V VDD is stabilized - 1 - s IDD (LSE) Oscillator transconductance gm tSU(LSE) LSE oscillator current consumption (4) Startup time nA 1. Guaranteed by characterization results. 2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 "Oscillator design guide for ST microcontrollers". 3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details. 4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer. DocID025966 Rev 6 63/103 91 Electrical characteristics STM32L100x6/8/B-A Note: For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to 15 pF range selected to match the requirements of the crystal or resonator (see Figure 14 ). CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load capacitance which is the series combination of CL1 and CL2. Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is between 2 pF and 7 pF. Caution: To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended to use a resonator with a load capacitance CL 7 pF. Never use a resonator with a load capacitance of 12.5 pF. Example: if the user chooses a resonator with a load capacitance of CL = 6 pF and Cstray = 2 pF, then CL1 = CL2 = 8 pF. Figure 14. Typical application with a 32.768 kHz crystal 5HVRQDWRUZLWK LQWHJUDWHGFDSDFLWRUV &/ I/6( 26&B,1 N+] UHVRQDWRU 5) 26&B287 %LDV FRQWUROOHG JDLQ 670/[[ &/ DLE 64/103 DocID025966 Rev 6 STM32L100x6/8/B-A 6.3.7 Electrical characteristics Internal clock source characteristics The parameters given in the following table are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. High-speed internal (HSI) RC oscillator Table 31. HSI oscillator characteristics Symbol fHSI TRIM (1)(2) ACCHSI(2) Parameter Conditions Min Typ Max Unit Frequency VDD = 3.0 V - 16 - MHz HSI user-trimmed resolution Trimming code is not a multiple of 16 - 0.4 0.7 % Trimming code is a multiple of 16 - - 1.5 % -10 - +10 % VDDA = 1.8 V to 3.6 V TA = -40 to 85 C - tSU(HSI)(2) HSI oscillator startup time - - 3.7 6 s IDD(HSI)(2) HSI oscillator power consumption - - 100 140 A 1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0). 2. Guaranteed by characterization results. Low-speed internal (LSI) RC oscillator Table 32. LSI oscillator characteristics Symbol Parameter Min Typ Max Unit fLSI(1) LSI frequency 26 38 56 kHz DLSI(2) LSI oscillator frequency drift 0C TA 85C -10 - 4 % LSI oscillator startup time - - 200 s LSI oscillator power consumption - 400 510 nA tsu(LSI)(3) IDD(LSI) (3) 1. Guaranteed by test in production. 2. This is a deviation for an individual part, once the initial frequency has been measured. 3. Guaranteed by design. DocID025966 Rev 6 65/103 91 Electrical characteristics STM32L100x6/8/B-A Multi-speed internal (MSI) RC oscillator Table 33. MSI oscillator characteristics Symbol Condition Typ Max MSI range 0 65.5 - MSI range 1 131 - MSI range 2 262 - MSI range 3 524 - MSI range 4 1.05 - MSI range 5 2.1 - MSI range 6 4.2 - Frequency error after factory calibration - 0.5 - % DTEMP(MSI)(1) MSI oscillator frequency drift 0 C TA 85 C - 10 - % DVOLT(MSI)(1) MSI oscillator frequency drift 1.8 V VDD 3.6 V, TA = 25 C - - 2.5 %/V MSI range 0 0.75 - MSI range 1 1 - MSI range 2 1.5 - MSI range 3 2.5 - MSI range 4 4.5 - MSI range 5 8 - MSI range 6 15 - MSI range 0 30 - MSI range 1 20 - MSI range 2 15 - MSI range 3 10 - MSI range 4 6 - MSI range 5 5 - MSI range 6, Voltage range 1 and 2 3.5 - MSI range 6, Voltage range 3 5 - fMSI ACCMSI IDD(MSI)(2) tSU(MSI) 66/103 Parameter Frequency after factory calibration, done at VDD= 3.3 V and TA = 25 C MSI oscillator power consumption MSI oscillator startup time DocID025966 Rev 6 Unit kHz MHz A s STM32L100x6/8/B-A Electrical characteristics Table 33. MSI oscillator characteristics (continued) Symbol tSTAB(MSI)(2) fOVER(MSI) Parameter Condition MSI oscillator stabilization time MSI oscillator frequency overshoot Typ Max MSI range 0 - 40 MSI range 1 - 20 MSI range 2 - 10 MSI range 3 - 4 MSI range 4 - 2.5 MSI range 5 - 2 MSI range 6, Voltage range 1 and 2 - 2 MSI range 3, Voltage Range 3 - 3 Any range to range 5 - 4 Any range to range 6 - Unit s MHz 6 1. This is a deviation for an individual part, once the initial frequency has been measured. 2. Guaranteed by characterization results. 6.3.8 PLL characteristics The parameters given in Table 34 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 34. PLL characteristics Value Symbol Parameter Unit Min Typ Max(1) PLL input clock(2) 2 - 24 MHz PLL input clock duty cycle 45 - 55 % fPLL_OUT PLL output clock 2 - 32 MHz tLOCK PLL lock time PLL input = 16 MHz PLL VCO = 96 MHz - 115 160 s Jitter Cycle-to-cycle jitter - - 600 ps IDDA(PLL) Current consumption on VDDA - 220 450 IDD(PLL) Current consumption on VDD - 120 150 fPLL_IN A 1. Guaranteed by characterization results. 2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with the range defined by fPLL_OUT. DocID025966 Rev 6 67/103 91 Electrical characteristics 6.3.9 STM32L100x6/8/B-A Memory characteristics The characteristics are given at TA = -40 to 85 C unless otherwise specified. RAM memory Table 35. RAM and hardware registers Symbol VRM Parameter Data retention Conditions mode(1) STOP mode (or RESET) Min Typ Max Unit 1.8 - - V 1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware registers (only in Stop mode). Flash memory and data EEPROM Table 36. Flash memory and data EEPROM characteristics Symbol Parameter Conditions Min Typ Max(1) Unit - 1.8 - 3.6 V - 3.28 3.94 - 3.28 3.94 - 300 - A - 1.5 2.5 mA VDD Operating voltage Read / Write / Erase tprog Programming / erasing time for Erasing byte / word / double word / halfProgramming page Average current during whole program/erase operation IDD Maximum current (peak) during program/erase operation ms TA = 25 C, VDD = 3.6 V 1. Guaranteed by design. Table 37. Flash memory, data EEPROM endurance and data retention Value Symbol NCYC (2) tRET(2) Parameter Cycling (erase / write) Program memory Cycling (erase / write) EEPROM data memory Data retention (program memory) after 1 kcycle at TA = 85 C Data retention (EEPROM data memory) after 100 kcycles at TA = 85 C Conditions TA = -40C to 85 C 1 - - 100 - - 10 - - 10 - - 2. Characterization is done according to JEDEC JESD22-A117. DocID025966 Rev 6 Unit kcycles TRET = +85 C 1. Guaranteed by characterization results. 68/103 Min(1) Typ Max years STM32L100x6/8/B-A 6.3.10 Electrical characteristics EMC characteristics Susceptibility tests are performed on a sample basis during the device characterization. Functional EMS (electromagnetic susceptibility) While a simple application is executed on the device (toggling 2 LEDs through I/O ports). the device is stressed by two electromagnetic events until a failure occurs. The failure is indicated by the LEDs: * Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard. * FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is compliant with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in Table 38. They are based on the EMS levels and classes defined in application note AN1709. Table 38. EMS characteristics Symbol Parameter Conditions Level/ Class VFESD Voltage limits to be applied on any I/O pin to induce a functional disturbance VDD = 3.3 V, LQFP100, TA = +25 C, fHCLK = 32 MHz conforms to IEC 61000-4-2 3B VEFTB Fast transient voltage burst limits to be applied through 100 pF on VDD and VSS pins to induce a functional disturbance VDD = 3.3 V, LQFP100, TA = +25 C, fHCLK = 32 MHz conforms to IEC 61000-4-4 4A Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as: * Corrupted program counter * Unexpected reset * Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1 second. DocID025966 Rev 6 69/103 91 Electrical characteristics STM32L100x6/8/B-A To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015). Electromagnetic Interference (EMI) The electromagnetic field emitted by the device are monitored while a simple application is executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with IEC 61967-2 standard which specifies the test board and the pin loading. Table 39. EMI characteristics Max vs. frequency range Symbol SEMI 6.3.11 Parameter Peak level Conditions VDD = 3.3 V, TA = 25 C, LQFP100 package compliant with IEC 61967-2 Monitored frequency band 4 MHz 16 MHz voltage Range 3 voltage Range 2 32 MHz voltage Range 1 0.1 to 30 MHz -16 -7 -3 30 to 130 MHz -12 2 12 130 MHz to 1GHz -11 0 8 1 1.5 2 SAE EMI Level Unit dBV - Electrical sensitivity characteristics Based on three different tests (ESD, LU) using specific measurement methods, the device is stressed in order to determine its performance in terms of electrical sensitivity. Electrostatic discharge (ESD) Electrostatic discharges (a positive then a negative pulse separated by 1 second) are applied to the pins of each sample according to each pin combination. The sample size depends on the number of supply pins in the device (3 parts x (n+1) supply pins). This test conforms to the JESD22-A114, ANSI/ESD STM5.3.1 standard. Table 40. ESD absolute maximum ratings Symbol Ratings Conditions Packages Class Maximum value(1) Unit VESD(HBM) Electrostatic discharge voltage TA = +25 C, conforming to (human body model) JESD22-A114 All 2 2000 V VESD(CDM) Electrostatic discharge voltage TA = +25 C, conforming to (charge device model) ANSI/ESD STM5.3.1 All C4 500 V 1. Guaranteed by characterization results. 70/103 DocID025966 Rev 6 STM32L100x6/8/B-A Electrical characteristics Static latch-up Two complementary static tests are required on six parts to assess the latch-up performance: * A supply overvoltage is applied to each power supply pin * A current injection is applied to each input, output and configurable I/O pin These tests are compliant with EIA/JESD 78A IC latch-up standard. Table 41. Electrical sensitivities Symbol LU 6.3.12 Parameter Static latch-up class Conditions Class TA = +85 C conforming to JESD78A II level A I/O current injection characteristics As a general rule, current injection to the I/O pins, due to external voltage below VSS or above VDD (for standard pins) should be avoided during normal product operation. However, in order to give an indication of the robustness of the microcontroller in cases when abnormal injection accidentally happens, susceptibility tests are performed on a sample basis during device characterization. Functional susceptibility to I/O current injection While a simple application is executed on the device, the device is stressed by injecting current into the I/O pins programmed in floating input mode. While current is injected into the I/O pin, one at a time, the device is checked for functional failures. The failure is indicated by an out of range parameter: ADC error above a certain limit (higher than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out of -5 A/+0 A range), or other functional failure (for example reset occurrence, oscillator frequency deviation, LCD levels). The test results are given in Table 42. Table 42. I/O current injection susceptibility Functional susceptibility Symbol IINJ Description Negative injection Positive injection Injected current on all 5 V tolerant (FT) pins -5 NA(1) Injected current on BOOT0 -0 NA(1) Injected current on any other pin -5 +5 Unit mA 1. Injection is not possible. Note: It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. DocID025966 Rev 6 71/103 91 Electrical characteristics 6.3.13 STM32L100x6/8/B-A I/O port characteristics General input/output characteristics Unless otherwise specified, the parameters given in Table 43 are derived from tests performed under conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 43. I/O static characteristics Symbol VIL VIH Parameter Input low level voltage Input high level voltage Conditions Ilkg I/O Schmitt trigger voltage hysteresis(2) Input leakage current(4) Typ - Max 0.3 Unit VDD(1)(2) TC and FT I/O - BOOT0 - TC I/O 0.45 VDD+0.38(2) - - FT I/O 0.39 VDD+0.59(2) - - 0.15 VDD+0.56(2) - - BOOT0 Vhys Min 0.14 VDD(2) V TC and FT I/O - 10% VDD(3) - BOOT0 - 0.01 - VSS VIN VDD I/Os with LCD - - 50 VSS VIN VDD I/Os with analog switches - - 50 VSS VIN VDD I/Os with analog switches and LCD - - 50 VSS VIN VDD I/Os with USB - - 250 VSS VIN VDD TC and FT I/O - - 50 FT I/O VDD VIN 5V - - 10 uA nA RPU Weak pull-up equivalent resistor(5)(1) VIN = VSS 25 45 65 k RPD Weak pull-down equivalent resistor(5) VIN = VDD 25 45 65 k CIO I/O pin capacitance - - 5 - pF 1. Guaranteed by test in production. 2. Guaranteed by design. 3. With a minimum of 200 mV. 4. The max. value may be exceeded if negative current is injected on adjacent pins. 5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is minimal (~10% order). 72/103 DocID025966 Rev 6 STM32L100x6/8/B-A Electrical characteristics Output driving current The GPIOs (general purpose input/outputs) can sink or source up to 8 mA, and sink or source up to 20 mA (with the non-standard VOL/VOH specifications given in Table 44. In the user application, the number of I/O pins which can drive current must be limited to respect the absolute maximum rating specified in Section 6.2: * The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating IVDD (see Table 12). * The sum of the currents sunk by all the I/Os on VSS plus the maximum Run consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating IVSS (see Table 12). Output voltage levels Unless otherwise specified, the parameters given in Table 44 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. All I/Os are CMOS and TTL compliant. Table 44. Output voltage characteristics Symbol Parameter VOL(1)(2) Output low level voltage for an I/O pin VOH(3)(2) Output high level voltage for an I/O pin VOL (1)(4) Output low level voltage for an I/O pin VOH (3)(4) Output high level voltage for an I/O pin VOL(1)(4) Output low level voltage for an I/O pin VOH(3)(4) Output high level voltage for an I/O pin Conditions Min Max IIO = 8 mA 2.7 V < VDD < 3.6 V - 0.4 VDD-0.4 - - 0.45 VDD-0.45 - - 1.3 VDD-1.3 - IIO = 4 mA 1.8 V < VDD < 2.7 V IIO = 20 mA 2.7 V < VDD < 3.6 V Unit V 1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVSS. 2. Guaranteed by test in production. 3. The IIO current sourced by the device must always respect the absolute maximum rating specified in Table 12 and the sum of IIO (I/O ports and control pins) must not exceed IVDD. 4. Guaranteed by characterization results. DocID025966 Rev 6 73/103 91 Electrical characteristics STM32L100x6/8/B-A Input/output AC characteristics The definition and values of input/output AC characteristics are given in Figure 15 and Table 45, respectively. Unless otherwise specified, the parameters given in Table 45 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 45. I/O AC characteristics(1) OSPEEDRx [1:0] bit value(1) Symbol Parameter fmax(IO)out Maximum frequency(3) tf(IO)out tr(IO)out Output rise and fall time fmax(IO)out Maximum frequency(3) tf(IO)out tr(IO)out Output rise and fall time 00 01 Fmax(IO)out Maximum frequency(3) 10 tf(IO)out tr(IO)out Output rise and fall time Fmax(IO)out Maximum frequency(3) 11 - Min Max(2) CL = 50 pF, VDD = 2.7 V to 3.6 V - 400 CL = 50 pF, VDD = 1.8 V to 2.7 V - 400 CL = 50 pF, VDD = 2.7 V to 3.6 V - 625 CL = 50 pF, VDD = 1.8 V to 2.7 V - 625 CL = 50 pF, VDD = 2.7 V to 3.6 V - 2 CL = 50 pF, VDD = 1.8 V to 2.7 V - 1 CL = 50 pF, VDD = 2.7 V to 3.6 V - 125 CL = 50 pF, VDD = 1.8 V to 2.7 V - 250 CL = 50 pF, VDD = 2.7 V to 3.6 V - 10 CL = 50 pF, VDD = 1.8 V to 2.7 V - 2 CL = 50 pF, VDD = 2.7 V to 3.6 V - 25 CL = 50 pF, VDD = 1.8 V to 2.7 V - 125 CL = 50 pF, VDD = 2.7 V to 3.6 V - 50 CL = 50 pF, VDD = 1.8 V to 2.7 V - 8 CL = 30 pF, VDD = 2.7 V to 3.6 V - 5 CL = 50 pF, VDD = 1.8 V to 2.7 V - 30 Conditions tf(IO)out tr(IO)out Output rise and fall time tEXTIpw Pulse width of external signals detected by the EXTI controller - 3. The maximum frequency is defined in Figure 15. 74/103 DocID025966 Rev 6 kHz ns MHz ns MHz ns MHz ns 8 - 1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the RM0038 reference manual for a description of GPIO Port configuration register. 2. Guaranteed by design. Unit STM32L100x6/8/B-A Electrical characteristics Figure 15. I/O AC characteristics definition %84%2.!, /54054 /. P& TR)/ OUT TF)/ OUT 4 -AXIMUM FREQUENCY IS ACHIEVED IF T R TF 4 AND IF THE DUTY CYCLE IS WHEN LOADED BY P& AIC 6.3.14 NRST pin characteristics The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up resistor, RPU (see Table 46). Unless otherwise specified, the parameters given in Table 46 are derived from tests performed under ambient temperature and VDD supply voltage conditions summarized in Table 14. Table 46. NRST pin characteristics Symbol VIL(NRST) (1) Parameter Conditions Min Typ Max NRST input low level voltage - - - 0.3 VDD - 0.39 VDD+0.59 - IOL = 2 mA 2.7 V < VDD < 3.6 V - - IOL = 1.5 mA 1.8 V < VDD < 2.7 V - - - - 10%VDD(2) VIH(NRST)(1) NRST input high level voltage VOL(NRST)(1) Vhys(NRST)(1) NRST output low level voltage NRST Schmitt trigger voltage hysteresis Unit V 0.4 mV RPU Weak pull-up equivalent resistor(3) VIN = VSS 25 45 65 k VF(NRST)(1) NRST input filtered pulse - - - 50 ns VNF(NRST)(1) NRST input not filtered pulse - 350 - - ns 1. Guaranteed by design. 2. 200 mV minimum value. 3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series resistance is around 10%. DocID025966 Rev 6 75/103 91 Electrical characteristics STM32L100x6/8/B-A Figure 16. Recommended NRST pin protection ([WHUQDOUHVHWFLUFXLW 1567 9'' 538 ,QWHUQDOUHVHW )LOWHU ) 670/[[ DLE 1. The reset network protects the device against parasitic resets. 0.1 uF capacitor must be placed as close as possible to the chip. 2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in Table 46. Otherwise the reset will not be taken into account by the device. 6.3.15 TIM timer characteristics The parameters given in Table 47 are guaranteed by design. Refer to Section 6.3.13: I/O port characteristics for details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output). Table 47. TIMx(1) characteristics Symbol tres(TIM) fEXT ResTIM tCOUNTER Parameter Conditions Min Max Unit - 1 - tTIMxCLK fTIMxCLK = 32 MHz 31.25 - ns Timer external clock frequency on CH1 to CH4 f TIMxCLK = 32 MHz 0 fTIMxCLK/2 MHz 0 16 MHz Timer resolution - - 16 bit 16-bit counter clock period when internal clock is selected (timer's prescaler disabled) - 1 65536 tTIMxCLK 2048 s Timer resolution time tMAX_COUNT Maximum possible count fTIMxCLK = 32 MHz 0.0312 - - 65536 x 65536 tTIMxCLK fTIMxCLK = 32 MHz - 134.2 s 1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers. 76/103 DocID025966 Rev 6 STM32L100x6/8/B-A 6.3.16 Electrical characteristics Communication interfaces I2C interface characteristics The STM32L100x6/8/B-A product line I2C interface meets the requirements of the standard I2C communication protocol with the following restrictions: SDA and SCL are not "true" open-drain I/O pins. When configured as open-drain, the PMOS connected between the I/O pin and VDD is disabled, but is still present. The I2C characteristics are described in Table 48. Refer also to Section 6.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (SDA and SCL). Table 48. I2C characteristics Symbol Parameter Standard mode I2C(1)(2) Fast mode I2C(1)(2) Unit Min Max Min Max tw(SCLL) SCL clock low time 4.7 - 1.3 - tw(SCLH) SCL clock high time 4.0 - 0.6 - tsu(SDA) SDA setup time 250 - 100 - th(SDA) SDA data hold time - 3450(3) - 900(3) tr(SDA) tr(SCL) SDA and SCL rise time - 1000 - 300 tf(SDA) tf(SCL) SDA and SCL fall time - 300 - 300 th(STA) Start condition hold time 4.0 - 0.6 - tsu(STA) Repeated Start condition setup time 4.7 - 0.6 - tsu(STO) Stop condition setup time 4.0 - 0.6 - s tw(STO:STA) Stop to Start condition time (bus free) 4.7 - 1.3 - s Cb Capacitive load for each bus line - 400 - 400 pF tSP Pulse width of spikes that are suppressed by the analog filter 0 50(4) 0 50(4) ns s ns s 1. Guaranteed by design. 2. fPCLK1 must be at least 2 MHz to achieve standard mode IC frequencies. It must be at least 4 MHz to achieve fast mode IC frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum IC fast mode clock. 3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL signal. 4. The minimum width of the spikes filtered by the analog filter is above tSP(max). DocID025966 Rev 6 77/103 91 Electrical characteristics STM32L100x6/8/B-A Figure 17. I2C bus AC waveforms and measurement circuit s/ s/ ZW ZW ^dD> Z^ ^ / Z^ ^> ^ dZdZWd ^ dZd ^ dZd ^d ^ ^ ^ ^d ^ ^ ^<> ^d^dK ^ dKW ^> ^< ^<, ^dK ^< 1. RS = series protection resistors 2. RP = pull-up resistors 3. VDD_I2C = I2C bus supply 4. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. Table 49. SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V)(1)(2) I2C_CCR value fSCL (kHz) RP = 4.7 k 400 0x801B 300 0x8024 200 0x8035 100 0x00A0 50 0x0140 20 0x0320 1. RP = External pull-up resistance, fSCL = I2C speed. 2. For speeds around 200 kHz, the tolerance on the achieved speed is of 5%. For other speed ranges, the tolerance on the achieved speed is 2%. These variations depend on the accuracy of the external components used to design the application. 78/103 DocID025966 Rev 6 STM32L100x6/8/B-A Electrical characteristics SPI characteristics Unless otherwise specified, the parameters given in the following table are derived from tests performed under ambient temperature, fPCLKx frequency and VDD supply voltage conditions summarized in Table 14. Refer to Section 6.3.12: I/O current injection characteristics for more details on the input/output alternate function characteristics (NSS, SCK, MOSI, MISO). Table 50. SPI characteristics(1) Symbol Parameter fSCK 1/tc(SCK) SPI clock frequency tr(SCK)(2) tf(SCK)(2) SPI clock rise and fall time DuCy(SCK) Min Max(2) Master mode - 16 Slave mode - 16 Slave transmitter - 12(3) Capacitive load: C = 30 pF - 6 ns 30 70 % Conditions SPI slave input clock duty Slave mode cycle tsu(NSS) NSS setup time Slave mode 4tHCLK - th(NSS) NSS hold time Slave mode 2tHCLK - SCK high and low time Master mode (2) tw(SCKH) tw(SCKL)(2) tsu(MI)(2) tsu(SI)(2) th(MI)(2) th(SI) (2) Data input setup time Data input hold time Master mode 5 - Slave mode 6 - Master mode 5 - Slave mode 5 - ta(SO) Data output access time Slave mode 0 3tHCLK tv(SO) (2) Data output valid time Slave mode - 33 tv(MO)(2) Data output valid time Master mode - 6.5 Slave mode 17 - Master mode 0.5 - th(SO) th(MO) (2) Data output hold time MHz tSCK/2- 5 tSCK/2+3 (4) (2) Unit ns 1. The characteristics above are given for voltage Range 1. 2. Guaranteed by characterization results. 3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK)) ranging between 40 to 60%. 4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data. DocID025966 Rev 6 79/103 91 Electrical characteristics STM32L100x6/8/B-A Figure 18. SPI timing diagram - slave mode and CPHA = 0 Figure 19. SPI timing diagram - slave mode and CPHA = 1(1) 166LQSXW 6&.LQSXW W68 166 &3+$ &32/ &3+$ &32/ WZ 6&.+ WZ 6&./ WK 62 WY 62 WD 62 0,62 287387 06%287 %,7287 WU 6&. WI 6&. WGLV 62 /6%287 WK 6, WVX 6, 026, ,1387 WK 166 WF 6&. 06%,1 %,7,1 /6%,1 DLE 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. 80/103 DocID025966 Rev 6 STM32L100x6/8/B-A Electrical characteristics Figure 20. SPI timing diagram - master mode(1) +LJK 166LQSXW 6&.2XWSXW &3+$ &32/ 6&.2XWSXW WF 6&. &3+$ &32/ &3+$ &32/ &3+$ &32/ WZ 6&.+ WZ 6&./ WVX 0, 0,62 ,13 87 WU 6&. WI 6&. %,7,1 06%,1 /6%,1 WK 0, 026, 287387 06%287 % , 7287 WY 02 /6%287 WK 02 DLF 1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD. USB characteristics The USB interface is USB-IF certified (full speed). Table 51. USB startup time Symbol tSTARTUP(1) Parameter USB transceiver startup time Max Unit 1 s 1. Guaranteed by design. DocID025966 Rev 6 81/103 91 Electrical characteristics STM32L100x6/8/B-A Table 52. USB DC electrical characteristics Symbol Parameter Conditions Min.(1) Max.(1) Unit - 3.0 3.6 V 0.2 - Input levels USB operating voltage(2) VDD VDI (3) Differential input sensitivity I(USB_DP, USB_DM) VCM(3) Differential common mode range Includes VDI range 0.8 2.5 VSE(3) Single ended receiver threshold 1.3 2.0 - 0.3 2.8 3.6 - V Output levels VOL(4) Static output level low RL of 1.5 k to 3.6 V(5) VOH(4) Static output level high RL of 15 k to VSS(5) V 1. All the voltages are measured from the local ground potential. 2. To be compliant with the USB 2.0 full speed electrical specification, the USB_DP (D+) pin should be pulled up with a 1.5 k resistor to a 3.0-to-3.6 V voltage range. 3. Guaranteed by characterization results. 4. Guaranteed by test in production. 5. RL is the load connected on the USB drivers. Figure 21. USB timings: definition of data signal rise and fall time &URVVRYHU SRLQWV 'LIIHUHQWLDO GDWDOLQHV 9&56 966 WI WU DLE Table 53. USB: full speed electrical characteristics Driver characteristics(1) Symbol Parameter Conditions Min Max Unit tr Rise time(2) CL = 50 pF 4 20 ns tf (2) CL = 50 pF 4 20 ns tr/tf 90 110 % - 1.3 2.0 V trfm VCRS Fall Time Rise/ fall time matching Output signal crossover voltage 1. Guaranteed by design. 2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB Specification section 7 (version 2.0). 82/103 DocID025966 Rev 6 STM32L100x6/8/B-A 6.3.17 Electrical characteristics 12-bit ADC characteristics Unless otherwise specified, the parameters given in Table 55 are guaranteed by design. Table 54. ADC clock frequency Symbol Parameter fADC ADC clock frequency Conditions Voltage Range 1 & 2 Min 2.4 V VDDA 3.6 V Max Unit 16 1.8 V VDDA 2.4 V 0.480 Voltage Range 3 8 MHz 4 Table 55. ADC characteristics Symbol Parameter Conditions Min Typ Max Unit - 1.8 - 3.6 V VDDA Power supply IVDDA Current on the VDDA input pin Peak - Average - VAIN Conversion voltage range - 0(1) - VDDA Direct channels - - 1 Multiplexed channels - - 0.76 Direct channels - - 1.07 Multiplexed channels - - 0.8 Direct channels - - 1.23 Multiplexed channels - - 0.89 Direct channels - - 1.45 Multiplexed channels - - 1 Direct channels 2.4 V VDDA 3.6 V 0.25 - - Multiplexed channels 2.4 V VDDA 3.6 V 0.56 - - Direct channels 1.8 V VDDA 2.4 V 0.56 - - Multiplexed channels 1.8 V VDDA 2.4 V 1 - - - 4 - 384 1/fADC fADC = 16 MHz 1 - 24.75 s 12-bit sampling rate 10-bit sampling rate fS 8-bit sampling rate 6-bit sampling rate tS Sampling time(2) tCONV Total conversion time (including sampling time) CADC Internal sample and hold capacitor - 2150 1900 A V Msps Msps Msps Msps s 4 to 384 (sampling phase) +12 (successive approximation) Direct channels - Multiplexed channels - DocID025966 Rev 6 1400 16 - 1/fADC pF 83/103 91 Electrical characteristics STM32L100x6/8/B-A Table 55. ADC characteristics (continued) Symbol Parameter fTRIG External trigger frequency Regular sequencer fTRIG External trigger frequency Injected sequencer RAIN Signal source impedance Conditions Min Typ 12-bit conversions - - 6/8/10-bit conversions - - 12-bit conversions - - Tconv+2 1/fADC 6/8/10-bit conversions - - Tconv+1 1/fADC - - - 50 (2) Max Unit Tconv+1 1/fADC Tconv 1/fADC tlat Injection trigger conversion latency fADC = 16 MHz 219 - 281 ns - 3.5 - 4.5 1/fADC tlatr Regular trigger conversion latency fADC = 16 MHz 156 - 219 ns - 2.5 - 3.5 1/fADC - - - 3.5 s Unit tSTAB Power-up time 1. VSSA must be tied to ground. 2. See Table 57: Maximum source impedance RAIN max for RAIN limitations Table 56. ADC accuracy(1)(2) Symbol Parameter ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error ENOB Test conditions 2.4 V VDDA 3.6 V fADC = 8 MHz, RAIN = 50 TA = -40 to 85 C Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion ENOB Effective number of bits SINAD Signal-to-noise and distortion ratio SNR Signal-to-noise ratio THD Total harmonic distortion ET Total unadjusted error EO Offset error EG Gain error ED Differential linearity error EL Integral linearity error 2.4 V VDDA 3.6 V fADC = 16 MHz, RAIN = 50 TA = -40 to 85 C Finput =10 kHz 1.8 V VDDA 2.4 V fADC = 8 MHz or 4 MHz, RAIN = 50 TA = -40 to 85 C Finput =10 kHz 1.8 V VDDA 2.4 V fADC = 4 MHz, RAIN = 50 TA = -40 to 85 C Typ Max(3) - 2.5 4 - 1 2 - 1.5 3.5 - 1 2 - 2 3 9.5 10 - 59 62 - 60 62 - - -72 -69 9.5 10 - 59 62 - 60 62 - - -72 -69 - 2 3 - 1 1.5 - 1.5 2.5 - 1 2 - 1. ADC DC accuracy values are measured after internal calibration. 84/103 Min(3) DocID025966 Rev 6 3 LSB bits dB bits dB LSB STM32L100x6/8/B-A Electrical characteristics 2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents. Any positive injection current within the limits specified for IINJ(PIN) and IINJ(PIN) in Section 6.3.12 does not affect the ADC accuracy. 3. Guaranteed by characterization results. Figure 22. ADC accuracy characteristics 95() >/6%,'($/ 9''$ RUGHSHQGLQJRQSDFNDJH (* ([DPSOHRIDQDFWX DOWUDQVIH UFXUYH 7KHLGHDOWUDQVIHUFX UYH (QGSRLQWFRUUHODWLRQOLQH (7 7RWDOXQDGMXVWHG(UURUPD[LPXPGHYLDWLRQ EHWZHHQWKHDFWXDODQGWKHLGHDOWUDQVIHUFXUYHV (2 2IIVHW(UURUGHYLDWLRQEHWZHHQWKHILUVWDFWXDO WUDQVLWLRQDQGWKHODVWDFWXDORQH (* *DLQ(UURUGHYLDWLRQEHWZHHQWKHODVWLGHDO WUDQVLWLRQDQGWKHODVWDFWXDORQH (' 'LIIHUHQWLDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ EHWZHHQDFWXDOVWHSVDQGWKHLGHDORQH (/ ,QWHJUDO/LQHDULW\(UURUPD[LPXPGHYLDWLRQ EHWZHHQDQ\DFWXDOWUDQVLWLRQDQGWKHHQGSRLQW FRUUHODWLRQOLQH (7 (2 (/ (' /6%,'($/ 966$ 9''$ DLH Figure 23. Typical connection diagram using the ADC 9''$ 670/[[ 6DPSOHDQGKROG $'&FRQYHUWHU 5$,1 9$,1 $,1[ &SDUDVLWLF ,/Q$ ELW FRQYHUWHU &$'& DLH 1. Refer to Table 57: Maximum source impedance RAIN max for the value of RAIN and Table 55: ADC characteristics for the value of CADC 2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy this, fADC should be reduced. DocID025966 Rev 6 85/103 91 Electrical characteristics STM32L100x6/8/B-A Figure 24. Maximum dynamic current consumption on VDDA supply pin during ADC conversion Sampling (n cycles) Conversion (12 cycles) ADC clock IDDA 1700 A 1300 A MS36686V1 Table 57. Maximum source impedance RAIN max(1) RAIN max (kOhm) Ts (s) Multiplexed channels Ts (cycles) Direct channels fADC= 16 MHz(2) 2.4 V < VDDA< 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA< 3.3 V 1.8 V < VDDA < 2.4 V 0.25 Not allowed Not allowed 0.7 Not allowed 4 0.5625 0.8 Not allowed 2.0 1.0 9 1 2.0 0.8 4.0 3.0 16 1.5 3.0 1.8 6.0 4.5 24 3 6.8 4.0 15.0 10.0 48 6 15.0 10.0 30.0 20.0 96 12 32.0 25.0 50.0 40.0 192 24 50.0 50.0 50.0 50.0 384 1. Guaranteed by design. 2. Number of samples calculated for fADC = 16 MHz. For fADC = 8 and 4 MHz the number of sampling cycles can be reduced with respect to the minimum sampling time Ts (us). General PCB design guidelines Power supply decoupling should be performed as shown in Figure 8. The 100 nF capacitors should be ceramic (good quality). They should be placed as close as possible to the chip. 86/103 DocID025966 Rev 6 STM32L100x6/8/B-A 6.3.18 Electrical characteristics DAC electrical specifications Data guaranteed by design, unless otherwise specified. Table 58. DAC characteristics Symbol Parameter Conditions Min Typ Max Unit - 1.8 - 3.6 V No load, middle code (0x800) - 330 540 A No load, worst code (0xF1C) - 540 870 A 5 - - 25 - - VDDA Analog supply voltage IDDA(1) Current consumption on VDDA supply VDDA = 3.3 V RL Resistive load DAC output Connected to VSSA buffer ON Connected to VDDA CL Capacitive load DAC output buffer ON - - 50 pF RO Output impedance DAC output buffer OFF 12 16 20 k DAC output buffer ON 0.2 - VDDA - 0.2 V DAC output buffer OFF 0.5 - VDDA- 1LSB mV CL 50 pF, RL 5 k DAC output buffer ON - 1.5 3 No RL, CL 50 pF DAC output buffer OFF - 1.5 3 CL 50 pF, RL 5 k DAC output buffer ON - 2 4 No RL, CL 50 pF DAC output buffer OFF - 2 4 - 10 25 - 5 8 - 1.5 5 VDDA = 3.3V,TA = 0 to 50 C DAC output buffer OFF -20 -10 0 VDDA = 3.3V, TA = 0 to 50 C DAC output buffer ON 0 20 50 CL 50 pF, RL 5 k DAC output buffer ON - +0.1 / -0.2% +0.2 / 0.5% No RL, CL 50 pF DAC output buffer OFF - +0 / 0.2% +0 / 0.4% Voltage on DAC_OUT output VDAC_OUT DNL(1) INL Differential non linearity(2) (1) Integral non Offset1(1) Gain(1) linearity(3) CL 50 pF, RL 5 k DAC output buffer ON Offset error at code 0x800 (4) No RL, CL 50 pF DAC output buffer OFF Offset(1) dOffset/dT k Offset error at code 0x001(5) (1) Offset error temperature coefficient (code 0x800) Gain error(6) No RL, CL 50 pF DAC output buffer OFF DocID025966 Rev 6 LSB V/C % 87/103 91 Electrical characteristics STM32L100x6/8/B-A Table 58. DAC characteristics (continued) Symbol Min Typ Max VDDA = 3.3V, TA = 0 to 50 C DAC output buffer OFF -10 -2 0 VDDA = 3.3V, TA = 0 to 50 C DAC output buffer ON -40 -8 0 CL 50 pF, RL 5 k DAC output buffer ON - 12 30 No RL, CL 50 pF DAC output buffer OFF - 8 12 tSETTLING Settling time (full scale: for a 12-bit code transition between the lowest and the CL 50 pF, RL 5 k highest input codes till DAC_OUT reaches final value 1LSB - 7 12 s Update rate Max frequency for a correct DAC_OUT change (95% of final value) with 1 LSB variation in the input code CL 50 pF, RL 5 k - - 1 Msps tWAKEUP Wakeup time from off state (setting the ENx bit in the DAC Control register)(7) CL 50 pF, RL 5 k - 9 15 s PSRR+ VDDA supply rejection ratio (static DC measurement) CL 50 pF, RL 5 k - -60 -35 dB dGain/dT(1) (1) TUE Parameter Gain error temperature coefficient Total unadjusted error Conditions Unit V/C LSB 1. Guaranteed by characterization results. 2. Difference between two consecutive codes - 1 LSB. 3. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095. 4. Difference between the value measured at Code (0x800) and the ideal value = VDDA/2. 5. Difference between the value measured at Code (0x001) and the ideal value. 6. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when buffer is OFF, and from code giving 0.2 V and (VDDA - 0.2) V when buffer is ON. 7. In buffered mode, the output can overshoot above the final value for low input code (starting from min value). 88/103 DocID025966 Rev 6 STM32L100x6/8/B-A Electrical characteristics Figure 25. 12-bit buffered /non-buffered DAC %XIIHUHG1RQEXIIHUHG'$& %XIIHU 5/ '$&B287[ ELW GLJLWDOWR DQDORJ FRQYHUWHU &/ AI6 1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external loads directly without the use of an external operational amplifier. The buffer can be bypassed by configuring the BOFFx bit in the DAC_CR register. 6.3.19 Comparator Table 59. Comparator 1 characteristics Symbol Parameter Conditions Min(1) Typ Max(1) Unit 3.6 V VDDA Analog supply voltage - 1.8 R400K R400K value - - 400 - R10K R10K value - - 10 - Comparator 1 input voltage range - 0.6 - VDDA Comparator startup time - - 7 10 - - 3 10 - - 3 10 mV 0 1.5 10 mV/1000 h - 160 260 nA VIN tSTART td Propagation delay Voffset Comparator offset dVoffset/dt ICOMP1 (2) Comparator offset variation in worst voltage stress conditions Current consumption(3) VDDA = 3.6 V VIN+ = 0 V VIN- = VREFINT TA = 25 C - k V s 1. Guaranteed by characterization results. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 3. Comparator consumption only. Internal reference voltage not included. DocID025966 Rev 6 89/103 91 Electrical characteristics STM32L100x6/8/B-A Table 60. Comparator 2 characteristics Symbol VDDA VIN Parameter Min Typ Max(1) Unit Analog supply voltage - 1.8 - 3.6 V Comparator 2 input voltage range - 0 - VDDA V Fast mode - 15 20 Slow mode - 20 25 1.8 V VDDA 2.7 V - 1.8 3.5 2.7 V VDDA 3.6 V - 2.5 6 1.8 V VDDA 2.7 V - 0.8 2 2.7 V VDDA 3.6 V - 1.2 4 - 4 20 mV VDDA = 3.3V TA = 0 to 50 C V- = VREFINT, 3/4 VREFINT, 1/2 VREFINT, 1/4 VREFINT - 15 100 ppm /C Fast mode - 3.5 5 Slow mode - 0.5 2 tSTART Comparator startup time td slow Propagation delay(2) in slow mode td fast Propagation delay(2) in fast mode Voffset Comparator offset error dThreshold/ Threshold voltage temperature dt coefficient ICOMP2 Conditions Current consumption(3) - 1. Guaranteed by characterization results. 2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference. 3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not included. 90/103 DocID025966 Rev 6 s A STM32L100x6/8/B-A 6.3.20 Electrical characteristics LCD controller The STM32L100x6/8/B-A devices embed a built-in step-up converter to provide a constant LCD reference voltage independently from the VDD voltage. An external capacitor Cext must be connected to the VLCD pin to decouple this converter. Table 61. LCD controller characteristics Symbol Parameter Min Typ Max Unit VLCD LCD external voltage - - 3.6 VLCD0 LCD internal reference voltage 0 - 2.6 - VLCD1 LCD internal reference voltage 1 - 2.73 - VLCD2 LCD internal reference voltage 2 - 2.86 - VLCD3 LCD internal reference voltage 3 - 2.98 - VLCD4 LCD internal reference voltage 4 - 3.12 - VLCD5 LCD internal reference voltage 5 - 3.26 - VLCD6 LCD internal reference voltage 6 - 3.4 - VLCD7 LCD internal reference voltage 7 - 3.55 - 0.1 - 2 Supply current at VDD = 2.2 V - 3.3 - Supply current at VDD = 3.0 V - 3.1 - Low drive resistive network overall value 5.28 6.6 7.92 M High drive resistive network total value 192 240 288 k V Cext ILCD(1) RHtot(2) RL (2) VLCD external capacitance V44 Segment/Common highest level voltage - - VLCD V34 Segment/Common 3/4 level voltage - 3/4 VLCD - V23 Segment/Common 2/3 level voltage - 2/3 VLCD - V12 Segment/Common 1/2 level voltage - 1/2 VLCD - V13 Segment/Common 1/3 level voltage - 1/3 VLCD - V14 Segment/Common 1/4 level voltage - 1/4 VLCD - V0 Segment/Common lowest level voltage 0 - - Segment/Common level voltage error TA = -40 to 85 C - - 50 Vxx(2) V F A V mV 1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD connected 2. Guaranteed by characterization results. DocID025966 Rev 6 91/103 91 Package information 7 STM32L100x6/8/B-A Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 7.1 LQFP64 10 x 10 mm, 64-pin low-profile quad flat package information Figure 26. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package outline PP *$8*(3/$1( F $ $ $ 6($7,1*3/$1( & $ FFF & ' ' ' . / / 3,1 ,'(17,),&$7,21 ( ( ( E H :B0(B9 1. Drawing is not to scale. Table 62. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package mechanical data inches(1) millimeters Symbol 92/103 Min Typ Max Typ Min Max A - - 1.600 - - 0.0630 A1 0.050 - 0.150 0.0020 - 0.0059 A2 1.350 1.400 1.450 0.0531 0.0551 0.0571 DocID025966 Rev 6 STM32L100x6/8/B-A Package information Table 62. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package mechanical data (continued) inches(1) millimeters Symbol Min Typ Max Typ Min Max b 0.170 0.220 0.270 0.0067 0.0087 0.0106 c 0.090 - 0.200 0.0035 - 0.0079 D - 12.000 - - 0.4724 - D1 - 10.000 - - 0.3937 - D3 - 7.500 - - 0.2953 - E - 12.000 - - 0.4724 - E1 - 10.000 - - 0.3937 - E3 - 7.500 - - 0.2953 - e - 0.500 - - 0.0197 - K 0 3.5 7 0 3.5 7 L 0.450 0.600 0.750 0.0177 0.0236 0.0295 L1 - 1.000 - - 0.0394 - ccc - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 27. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package recommended footprint AIC 1. Dimensions are in millimeters. DocID025966 Rev 6 93/103 102 Package information STM32L100x6/8/B-A LQFP64 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 28. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example 5HYLVLRQFRGH 3URGXFWLGHQWLILFDWLRQ 5 670/ 5%7$ 'DWHFRGH < :: 3LQ LQGHQWLILHU 06Y9 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. 94/103 DocID025966 Rev 6 STM32L100x6/8/B-A 7.2 Package information UFQFPN48 7 x 7 mm, 0.5 mm pitch, package information Figure 29. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package outline 3LQLGHQWLILHU ODVHUPDUNLQJDUHD ' $ ( ( 7 GGG $ 6HDWLQJ SODQH E H 'HWDLO< ' ([SRVHGSDG DUHD < ' / &[ SLQFRUQHU ( 5W\S 'HWDLO= = $%B0(B9 1. Drawing is not to scale. 2. All leads/pads should also be soldered to the PCB to improve the lead/pad solder joint life. 3. There is an exposed die pad on the underside of the UFQFPN package. It is recommended to connect and solder this back-side pad to PCB ground. DocID025966 Rev 6 95/103 102 Package information STM32L100x6/8/B-A Table 63. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package mechanical data inches(1) millimeters Symbol Min Typ Max Min Typ Max A 0.500 0.550 0.600 0.0197 0.0217 0.0236 A1 0.000 0.020 0.050 0.0000 0.0008 0.0020 D 6.900 7.000 7.100 0.2717 0.2756 0.2795 E 6.900 7.000 7.100 0.2717 0.2756 0.2795 D2 5.500 5.600 5.700 0.2165 0.2205 0.2244 E2 5.500 5.600 5.700 0.2165 0.2205 0.2244 L 0.300 0.400 0.500 0.0118 0.0157 0.0197 T - 0.152 - - 0.0060 - b 0.200 0.250 0.300 0.0079 0.0098 0.0118 e - 0.500 - - 0.0197 - ddd - - 0.080 - - 0.0031 1. Values in inches are converted from mm and rounded to 4 decimal digits. Figure 30. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package recommended footprint 1. Dimensions are in millimeters. 96/103 DocID025966 Rev 6 !"?&0?6 STM32L100x6/8/B-A Package information UFQFPN48 device marking The following figure gives an example of topside marking orientation versus pin 1 identifier location. Other optional marking or inset/upset marks, which identify the parts throughout supply chain operations, are not indicated below. Figure 31. UFQFPN48 7 x 7 mm, 0.5 mm pitch, package top view example 3URGXFW LGHQWLILFDWLRQ 45.$6" 'DWHFRGH : 88 3LQ LGHQWLILFDWLRQ 5HYLVLRQFRGH 3 069 1. Parts marked as ES or E or accompanied by an engineering sample notification letter are not yet qualified and therefore not approved for use in production. ST is not responsible for any consequences resulting from such use. In no event will ST be liable for the customer using any of these engineering samples in production. ST's Quality department must be contacted prior to any decision to use these engineering samples to run a qualification activity. DocID025966 Rev 6 97/103 102 Package information 7.3 STM32L100x6/8/B-A Thermal characteristics The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated using the following equation: TJ max = TA max + (PD max x JA) Where: * TA max is the maximum ambient temperature in C, * JA is the package junction-to-ambient thermal resistance, in C/W, * PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax), * PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power. PI/O max represents the maximum power dissipation on output pins where: PI/O max = (VOL x IOL) + ((VDD - VOH) x IOH), taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the application. Table 64. Thermal characteristics Symbol JA Parameter Value Thermal resistance junction-ambient LQFP64 - 10 x 10 mm / 0.5 mm pitch 45 Thermal resistance junction-ambient UFQFPN48 - 7 x 7 mm / 0.5 mm pitch 33 Unit C/W Figure 32. Thermal resistance )RUELGGHQDUHD 7- !7-PD[ 3' P: /4)3 8)4)31 7HPSHUDWXUH & 069 98/103 DocID025966 Rev 6 STM32L100x6/8/B-A 7.3.1 Package information Reference document JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural Convection (Still Air). Available from www.jedec.org. DocID025966 Rev 6 99/103 102 Ordering information 8 STM32L100x6/8/B-A Ordering information Table 65. Ordering information scheme Example: STM32 L 100 R B T 6 A TR Device family STM32 = ARM-based 32-bit microcontroller Product type L = Low power Device subfamily 100 Pin count C = 48 pins R = 64 pins Flash memory size 6 = 32 Kbytes of Flash memory 8 = 64 Kbytes of Flash memory B = 128 Kbytes of Flash memory Package T = LQFP U = UFQFPN Temperature range 6 = Industrial temperature range, -40 to 85 C Options A = Device generation A Packing TR = tape and reel No character = tray or tube For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST sales office. 100/103 DocID025966 Rev 6 STM32L100x6/8/B-A 9 Revision history Revision history Table 66. Document revision history Date Revision 25-Mar-2014 1 Initial release. 27-Oct-2014 2 Updated DMIPS features in cover page and Section 2: Description Updated current consumption in Table 20: Current consumption in Sleep mode. Updated Table 25: Peripheral current consumption with new measured values. Updated Table 57: Maximum source impedance RAIN max adding note 2. 03-Feb-2015 3 Updated Section 7: Package information with new package device markings. Updated Figure 5: Memory map. 4 Updated Section 7: Package information structure: Paragraph titles and paragraph heading level. Updated Table 62: LQFP64 10 x 10 mm, 64-pin low-profile quad flat package mechanical data. Updated Section 7: Package information for LQFP64 and UFQFPN48 package device markings, adding text for device orientation versus pin 1 identifier. Updated Table 17: Embedded internal reference voltage temperature coefficient at 100ppm/C and table footnote 3: "guaranteed by design" changed by "guaranteed by characterization results". Updated Table 60: Comparator 2 characteristics new maximum threshold voltage temperature coefficient at 100ppm/C. 5 Updated Table 40: ESD absolute maximum ratings CDM class. Updated all the notes, removing `not tested in production'. Updated Table 11: Voltage characteristics adding note about VREFpin. Updated Table 3: Functionalities depending on the operating power supply range LSI and LSE functionalities putting "Y" in Standby mode. Removed note 1 below Figure 2: Clock tree. Updated Section 7: Package information replacing "Marking of engineering samples" by "device marking". Updated Table 58: DAC characteristics resistive load. 30-Apr-2015 25-Apr-2016 Changes DocID025966 Rev 6 101/103 102 Revision history STM32L100x6/8/B-A Table 66. Document revision history (continued) Date 28-Aug-2017 102/103 Revision Changes 6 Updated Table 43: I/O static characteristics pull-up and pull-down values. Updated Table 46: NRST pin characteristics pull-up values. Updated Section 7: Package information adding information about other optional marking or inset/upset marks. Updated note 1 below all the package device marking figures. Updated Nested vectored interrupt controller (NVIC) in Section 3.2: ARM(R) Cortex(R)-M3 core with MPU about process state automatically saved. Updated Table 3: Functionalities depending on the operating power supply range removing I/O operation column and adding note about GPIO speed. Updated Table 42: I/O current injection susceptibility note by `injection is not possible'. Updated Figure 16: Recommended NRST pin protection note about the 0.1uF capacitor. Updated Section 3.1: Low-power modes Low-power run mode (MSI) RC oscillator clock. Updated Table 5: Working mode-dependent functionalities (from Run/active down to standby) disabling I2C functionality in Lowpower Run and Low-power Sleep modes. DocID025966 Rev 6 STM32L100x6/8/B-A IMPORTANT NOTICE - PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST's terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers' products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. (c) 2017 STMicroelectronics - All rights reserved DocID025966 Rev 6 103/103 103