Ter ee OOS) DATA Shllelel 83C51FB/87C51FB CMOS single-chip 8-bit microcontrollers Product specification 1995 Feb 02 IC20 PHILIPS MH 7110826 0047378 403 \Philips Semiconductors ne CMOS single-chip 8-bit microcontrollers Product Specification 83C51FB/87C51FB DESCRIPTION FEATURES PIN CONFIGURATIONS The 83C51FB/87C51FB (hereafter 80C51 central processing unit collectively called 8XC51FB) Single-Chip * 16k x 8 EPROM expandable externally to raP1.0f7 LS a 8-Bit Microcontroller is manufactured in an 64k bytes (87C51FB) voc advanced CMOS process and isa derivative ~ Quick Pulse programming algorithm T2EX/P1.1 [2] [39] P0.0/ADO oee A mcrocontrolet family. The ' Two level program security system EcuP1.2[3| [38] Po.1/AD1 8XC51 as the same instruction set as the B0C5I. 16k x 8 ROM (83C51FB) cexopt.3[4| [37] Po.2/AD2 256 x 8 RAM, expandable externally to CEXUPI fl ae] P0.3/AD3 This device provides architectural 64k bytes , . enhancements that make it applicable in a Three 16-bit timer/counters cexaip.s [6 35] P0.4/AD4 variety of applications for general control T2 is an up/down counter cexaiP1.6[7| 34] PO.S/ADS systems. The 87C51FB contains 16k x 8 Programmable Counter Array (PCA) EPROM memory, the 83C51FB contains High speed output cexer.7[ 6) 39] Po.sians 16k x 8 ROM memory, a volatile 256 x 8 C fi rst [9] [32] PO.7/AD7 read/write data memory, four 8-bit I/O ports ~ Capture/compare RxDIP3. of 0 DUAL 1] EAVpp , , _ HT xl . three 16-bit timer/event counters, a Pulse Width Modulator PACKAGE Programmable Counter Array (PCA), a - Watchdog Timer TxD/P3.1 [11] [30] ALE/PROG multi-source, two-priority-level, nested * Four 8-bit I/O ports ITOPs.2 [12] [29] PSEN interrupt structure, an enhanced UART and * Full-duplex enhanced UART INTHPS.3[13 2a} P2.7/A15 on-chip oscillator and timing circuits. For Framing error detection systems that require extra capability, the - Automatic address recognition Torps.4[14 27] Pe.eiat4 87C51FB can be expanded using standard Power control modes T1P3.5 [15 [26] P2.5/A13 TTL compatible memories and logic. - Idle mode wriPs.e[ 74 aa] po a/A12 Its added features make it an even more Power-down mode RoPS.7[i7 a P2.a/A11 powerful microcontroller for applications that Once (On Circuit Emulation) Mode require pulse width modulation, high-speed * Five package styles XTAL2 |1 23] P2.2/A10 /O and up/down counting capabilities such * OTP package available XTAL1 22 | P2.1/A9 as motor control. It also has a more versatile i] PD.O/AB serial channel that facilitates multiprocessor Vss communications. Suo0021 ORDERING INFORMATION 1 6 FREQ. DRAWING ROM EPROM TEMPERATURE RANGE C AND PACKAGE (MHz) NUMBER $83C51FB4N40 | S87C51FB-4N40 | OTP 0 to +70, 40-Pin Plastic Dual In-line Package 3.51016 | SOT129-1 $87C51FB-4F40 UV 0 to +70, 40-Pin Ceramic Dual In-line Package w/Window 3.5 to 16 0590B S83C51FB-4A44 | S87C51FB-4A44 | OTP 0 to +70, 44-Pin Plastic Leaded Chip Carrier 3.5 to 16 0403G $87C51FB4K44 UV 0 to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window 3.5 to 16 1472A $83C51FB-4B44 | S87C51FB-4B44 | OTP 0 to +70, 44-Pin Plastic Quad Flat Pack 3.5to16 | SOT307-2 $83C51FB-5N40 | S87C51FB-5N40 | OTP ~40 to +85, 40-Pin Plastic Dual In-line Package 3.51016 | SOT129-1 $87C51FB-5F40 UV 40 to +85, 40-Pin Ceramic Dual In-line Package w/Window 3.5 to 16 0590B $83C51FB-5A44 | S87C51FB-5A44 | OTP ~40 to +85, 44-Pin Plastic Leaded Chip Carrier 3.5 to 16 0403G $87C51FB-5K44 UV 40 to +85, 44-Pin Ceramic Leaded Chip Carrier w/Window 3.5 to 16 1472A $83C51FB-5B44 | S87C51FB-5B44 | OTP 40 to +85, 44-Pin Plastic Quad Flat Pack 3.51016 | SOT307-2 S83C51FB-AN40 | S87C51FB-AN40 {| OTP 0 to +70, 40-Pin Plastic Dual In-line Package 3.5to24 | SOT129-1 $87C51FB-AF40 UV 0 to +70, 40-Pin Ceramic Dual In-line Package w/Window 3.5 to 24 0590B $83C51FB-AA44 | S87C51FB-AA44 | OTP 0 to +70, 44-Pin Plastic Leaded Chip Carrier 3.5 to 24 0403G $87C51FB-AK44 UV 0 to +70, 44-Pin Ceramic Leaded Chip Carrier w/Window 3.5 to 24 1472A 83C51FB-BN40 | S87C51FB-BN40 | OTP 40 to +85, 40-Pin Plastic Dual In-line Package 3.5to24 | SOT129-1 $87C51FB-BF40 UV 40 to +85, 40-Pin Ceramic Dual In-line Package w/Window 3.5 to 24 0590B $83C51FB-BA44 | S87C51FB-BA44 | OTP ~40 to +85, 44-Pin Plastic Leaded Chip Carrier 3.5 to 24 0403G $87C51FB-BK44 UV 40 to +85, 44-Pin Ceramic Leaded Chip Carrier wWindow 3.5 to 24 1472A NOTE: 1. OTP = One Time Programmable EPROM. UV = Erasable EPROM. 1995 Feb 02 M@ 7110826 0087379 747 853-1692 14751Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB BLOCK DIAGRAM P0.0-PO.7 P2.0-P2.7 os on PORTO PORT 2 | | DRIVERS DRIVERS | y s < i ! Vssl Yv | | RAM ADDR | PORTO PORT 2 a = | REGISTER F1]_- RAM LATCH LATCH FROMEPROM K | I i U U U I | | | | | U ft | | B | REGISTER ACC PBINTER | | I | | PROGRAM | ADDRESS K | | | TMP2 TMP% REGISTER | | V | BUFFER K\> | ALU > | SFRs | | a TIMERS pC | | PSW PCA MENTER > | | TT | | PROGRAM | COUNTER = | | PSEN<t Bb | ALE/PROG< 44 TIMING 5 w LA DPTR | AND. | 2 2K > EAN pp conTRoL| & 9 it it | RST zt uo | PD PORT 1 PORT 3 | | LATCH LATCH | | it if | | OSCILLATOR | | PORT 1 PORT3 | DRIVERS > DRIVERS | XTALY] TAL fA itt ne fi t ee 4 0] P1.0-P1.7 P3.0-P3.7 su00022 1995 Feb 02 mM 7110826 0047380 4h)Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB Table 1. | 8XC51FB Special Function Registers DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION RESET SYMBOL | DESCRIPTION | appress | MSB LSB VALUE ACC* Accumulator EOH E7 E6 ES E4 E3 E2 E1 EO 00H AUXR# | Auxiliary 8EH - {| - | - | - | - [ - [ - [Ao | xccoox08 B* B register FOH F7 F6 FS F4 F3 F2 FA FO | OOH CCAPOH# | Module 0 Capture High FAH XXXXXXXXB CCAP1H# | Module 1 Capture High FBH XXXXXXXXB CCAP2H# | Module 2 Capture High FCH XXXXXXXXB CCAP3H# | Module 3 Capture High FDH XXXXXXXXB CCAP4H# | Module 4 Capture High FEH XXXXXXXXB CCAPOL# | Module 0 Capture Low EAH XXXXXXXXB CCAP1L# | Module 1 Capture Low EBH XOOCOXXKB CCAP2L# | Module 2 Capture Low ECH XOOKXXXB CCAP3L# | Module 3 Capture Low EDH XXXXXXXXB CCAP4L# | Module 4 Capture Low EEH XXXXXXXXB CCAPMOo# | Module 0 Mode DAH - | com | capp | CAPN | MAT | Toa | PWM | ECCF | x0000000B CCAPM1# | Module 1 Mode DBH - [| =com |} capp | capN | maT | TOG | PWM | ECCF | x0000000B CCAPM2# | Module 2 Mode DCH - | COM} cape | caPpN | MAT | ToG | Pwm | ECCF | x0000000B CCAPM3# | Module 3 Mode DDH - | com | capp | capN | maT | Toa | Pwm | ECCF | xoo00000B CCAPM4# | Module 4 Mode DEH - | Com | capp | CAPN | MAT | ToG | PWM | ECCF | xo000000B DF DE DD DC DB DA __og D8 CCON*# | PCA Counter Control D&H cF | cr | - | ccra | ccr3 | ccF2 | ccFi | CCFO | oox00000B CH# PCA Counter High F9H 00H CL# PCA Counter Low E9H 00H CMOD# | PCA Counter Mode poH | cion | woTe| - | - | - | cpsi | cpso | ECF | coxx000B DPTR: Data Pointer (2 bytes) DPH Data Pointer High 83H 00H DPL Data Pointer Low 82H 00H AF AE AD AC AB AAA AB IE* Interrupt Enable A8H EA | ec | eT2 | ES | eET1 | EXi | ETo | EXO | 00H BF BE BD BC BB BA _si9 B8 IP* interrupt Priority B8H - | ppc | pt2 | ps | peti | Px | PTo | Pxo | xooc0000B 87 86 85 84 83 82.81 80 Pot Port 0 80H | AD7 { ADs | ADS | AD4 | ADs | AD2 | AD1 | ADO | FFH 97 96 95 94 93 929 90 Pit Port 1 90H | CEX4 | CEX3 | CEx2 | cEx1 | cexo | Ec! | T2Ex | Te | FFH A7 AG AS A4 A3 A2 AI AO P2* Port 2 AOH | ADI5 | ADI4 | AD13 | ADI2 | AD11 | ADO | apo | ADB | FFH B7 B6 B5 B4 B3 B2 BI BO P3* Port 3 BOH RD | WR {| ti | To | INT? | INTO | TxD | RxD | FFH PCON | Power Control! 87H | smooi | smopo | - | Port | art | Gro | PD | IDL | coxxooB * SFRs are bit addressable. # SFRs are modified from or added to the 80C51 SFRs. 1995 Feb 02 4 Me 711082b 0087381 376Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB Table 1. 8XC51iFB Special Function Registers (Continued) DIRECT BIT ADDRESS, SYMBOL, OR ALTERNATIVE PORT FUNCTION RESET SYMBOL | DESCRIPTION | anpress | MSB LSB VALUE D7 D6 D5 D4 D3 D2 D1 DO Psw* Program Status Word | DOH | cy | ac | Fo | Rsi {[ RSo | ov [| - | P_ |ooH RACAP2H# | Timer 2 Capture High CBH 00H RACAP2L# | Timer 2 Capture Low CAH 00H SADDR# Slave Address ASH 00H SADEN# | Slave Address Mask B9H 00H SBUF Serial Data Buffer 99H XXXXXXXXB OF 9E 9D 9C 9B 9A 99 98 SCON" | Serial Control 98H | smo | Smt | sm2 | REN | TB8 {| RBs | TI | RI | OOH SP Stack Pointer 81H 07H 8F 8E 8D 8C 8B BA 89 88 TCON* | Timer Control ssH | TF1 | TRI | TFO | TRO | IEt Ti | 1c0 | To | 00H CF CE CD cc CB CA cg C8 T2CON* | Timer 2 Control C8H TF2 | EXF2 | RCLK | TCLK | EXEN2 | TR2 | C/T2 | CPYRL2 | OOH T2MOD# Timer 2 Mode Control C9H ~ - - - - - T20E | DCEN | xxxxxx00B THO Timer High 0 8CH 00H THI Timer High 1 8DH 00H TH2# Timer High 2 CDH 00H TLO Timer Low 0 BAH 00H TL Timer Low 1 8BH 00H TL2# Timer Low 2 CCH 00H TMOD Timer Mode 89H | Gate | ct | mi | mo | Gate | cow | m1 | Mo | 00H C7 C6 C5 C4 C3 C2 C1 co * SFRs are bit addressable. # SFRs are modified from or added to the 80051 SFRs. 1. Reset value depends on reset source. 1995 Feb 02 mM 71108eb 004738e 234Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB CERAMIC AND PLASTIC LEADED PLASTIC QUAD FLAT PACK CHIP CARRIER PIN FUNCTIONS PIN FUNCTIONS 6 1 40 7 BES LCC 7 | 29 18 28 Pin Function Pin Function Pin Function Pin Function 1 NC 23 NC 1 P1.5/CEX2 23 P2.5/A13 2 P1.0/T2 24 P2.0/A8 2 P1.6/CEX3 24 P2,.6/A14 3 PT.A/T2EX 25 P2.1/A9 3 PI.7ICEX4 25 P2.7/A15 4 P1.2/ECI 26 P2.2/A10 4 RST 26 PSEN 5 P1.3/CEXO 27 P2.3/A11 5 P3.0/RxD 27 ALE/PROG 6 P1.4/CEXt 28 = P2.4/A12 6 NC 28 NC 7 PLSICEX2 29 -P2.5/A13 7 P3.1/TxD 29 EAVpp 8 P1.6/CEX3 30 P2.6/A14 8 P3.2/INTO 30 -PO.7/AD7 9 P1.7/CEX4 31 P2.7/A15 9 P3.3/INTI 31 PO.6/AD6 10 RST 32 PSEN 10 P3.4/TO 32 PO.5/AD5 11 P3.0/RxD 33. ALE/PROG 1 P3.5/T1 33 PO.4/AD4 12 NC 34 NG 12 P3.6/WR 34 PO.3/AD3 13 P3.1/TxD 35 EAVpp 13 P3.7/RD 35 PO.2/AD2 14 P3.2/INTO 36 PO.7/AD7 14 XTAL2 36 PO.1/AD1 15 P3.3ANTT 37 PO.6/AD6 15 XTALI 37 PO.O/ADO 16 P3.4/TO 38 PO.S/ADS 16 Vss 38 Voc 17 -P3.8/Tt 39 PO.4/AD4 17 NC 39 NC 18 P3.6/WR 40 PO.S/AD3 18 P2.0/A8 40 P1.0/T2 19 P3.7/RD 41 Po.2/AD2 19 P2.1/A9 41 P1.1/T2EX 20 XTAL2 42 PO.1/AD1 20 P2.2/A10 42 P1.2/ECI 21 XTAL1 43 PO,0/ADO 21 P2.3/A11 43 P1.3/CEX0 22 Vss 44 Voc 22 P2.4/A12 44 P1.4/CEX1 $U00023 suo0024 PIN DESCRIPTIONS PIN NUMBER MNEMONIC; DIP | LCC | QFP | TYPE | NAME AND FUNCTION Ves 20 22 16 | Ground: OV reference. Vec 40 44 38 I Power Supply: This is the power supply voltage for normal, idle, and power-down operation. P0.0-0.7 39-32 | 43-36 | 37-30 | I/O | Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to them float and can be used as high-impedance inputs. Port 0 is also the multiplexed low-order address and data bus during accesses to external program and data memory. In this application, it uses strong internal pull-ups when emitting 1s. Port 0 also outputs the code bytes during program verification and receives code bytes during EPROM programming. External pull-ups are required during program verification. P1.0-P1.7 1-8 2-9 | 40-44,| WO | Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that have is 1-3 written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 1 pins that are externally pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: _). Port 1 also receives the low-order address byte during program memory verification. Alternate functions include: 1 2 40 I T2 (P1.0): Timer/Counter 2 external count input/Clockout 2 3 44 I T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control 3 4 42 I ECI (P1.2): External Clock Input to the PCA 4 5 43 vO CEXO (P1.3): Capture/Compare External 1/O for PCA module 0 5 6 44 VO CEX1 (P1.4): Capture/Compare External I/O for PCA module 1 6 7 1 70 CEX2 (P1.5): Capture/Compare External I/O for PCA module 2 7 8 2 /O CEX3 (P1.6): Capture/Compare External I/O for PCA module 3 8 9 3 0 CEX4 (P1.7): Capture/Compare External I/O for PCA module 4 1995 Feb 02 ME 7110826 0087383 170 mm Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB PIN DESCRIPTIONS (Continued) PIN NUMBER MNEMONIC| DIP | LCC | QFP | TYPE | NAME AND FUNCTION P2.0-P2.7 | 21-28 | 24-31 | 18-25 | 1/0 | Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that have 1s written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 2 pins that are externally being pulled low will source current because of the internal pull-ups. (See DC Electrical Characteristics: ||). Port 2 emits the high-order address byte during fetches from external program memory and during accesses to external data memory that use 16-bit addresses (MOVX @DPTR). In this application, it uses strong internal pull-ups when emitting 1s. During accesses to external data memory that use 8-bit addresses (MOV @Ri), port 2 emits the contents of the P2 special function register. Some Port 2 pins receive the high order address bits during EPROM programming and verification. P3.0-P3.7 | 10-17] 11, 5, VO | Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that have 1s 13-19 | 7-13 written to them are pulled high by the internal pull-ups and can be used as inputs. As inputs, port 3 pins that are externally being pulled low will source current because of the pull-ups. (See DC Electrical Characteristics: |)_). Port 3 also serves the special features of the 80C51 family, as listed below: 10 1 5 | RxD (P3.0): Serial input port 11 13 7 0 TxD (P3.1): Serial output port 12 14 8 | INTO (P3.2): External interrupt 13 15 9 | INTT (P3.3): External interrupt 14 16 10 I TO (P3.4): Timer 0 external input 15 17 11 ! T1 (P3.5): Timer 1 external input 16 18 12 Oo WR (P3.6): External data memory write strobe 17 19 13 Oo RD (P3.7): External data memory read strobe RST 9 10 4 | Reset: A high on this pin for two machine cycles while the oscillator is running, resets the device. An internal diffused resistor to Vsg permits a power-on reset using only an external capacitor to Voc. ALE/PROG | 30 33 27 1/0 | Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the address during an access to external memory. tn normal operation, ALE is emitted ata constant rate of 1/6 the oscillator frequency, and can be used for external timing or clocking. Note that one ALE pulse is skipped during each access to external data memory. This pin is also the program pulse input (PROG) during EPROM programming. PSEN 29 32 26 oO Program Store Enable: The read strobe to external program memory. When the 87C51FB is executing code from the external program memory, is activated twice each machine cycle, except that two PSEN activations are skipped during each access to external data memory. PSEN is not activated during fetches from internal program memory. EAN pp 31 35 29 { External Access Enable/Programming Supply Voltage: EA must be externally held low to enable the device to fetch code from external program memory locations OOOOH and 3FFFH. If EA is held high, the device executes from internal program memory unless the program counter contains an address greater than 3FFFH. This pin also receives the 12.75V programming supply voltage (Vpp) during EPROM programming. If security bit 1 is programmed, EA will be internally latched on Reset. XTAL1 19 21 15 I Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock generator circuits. XTAL2 18 20 14 oO Crystal 2: Output from the inverting oscillator amplifier. NOTE: To avoid latch-up effect at power-on, the voltage on any pin at any time must not be higher than Voc + 0.5V or Vgg 0.5V, respectively. TIMER 2 In the Capture mode Timer 2 can either set POWER OFF FLAG This is a 16-bit up or down counter, which TF2 and generate an interrupt or capture its The Power Off Flag (POF) is set by on-chip can be operated as either a timer or event value. To capture Timer 2 in response to a circuitry when the Vgc level on the 87C51FB counter. It can be operated in one of three 1-to-0 transition on the T2EX input, the rises from 0 to 5V. The POF bit can be set or different modes (autoreload, capture or as EXEN2 bit in the T2CON must be set. Timer _ cleared by software allowing a user to the baud rate generator for the UART). 2 is then captured in SFRs RCAP2H and determine if the reset is the result of a RCAP2L. power-on or a warm start after powerdown. In the autoreload mode the Timer can be set . to count up or down by setting or clearing the As the baud rate generator, Timer 2 is ore level must remain above 3V for the bit DCEN in the T2CON Special Function selected by setting TCLK and/or RCLK in to remain unaffected by the Vcc level. Register. The SFRs RCAP2H and RCAP2L T2CON. As the baud rate generator Timer 2 are used to reload the Timer upon overflow or _ is incremented at '/2 the oscillator frequency. a 1-to-0 transition on the T2EX input (P1.1). 1995 Feb 02 ME 7110826 0087384 OO? oePhilips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB OSCILLATOR CHARACTERISTICS XTAL1 and XTAL2 are the input and output, respectively, of an inverting amplifier. The pins can be configured for use as an on-chip oscillator. To drive the device from an external clock source, XTAL1 should be driven while XTAL2 is left unconnected. There are no requirements on the duty cycle of the external clock signal, because the input to the internal clock circuitry is through a divide-by-two flip-flop. However, minimum and maximum high and low times specified in the data sheet must be observed. Reset A reset is accomplished by holding the RST pin high for at least two machine cycles (24 oscillator periods), while the oscillator is running. To insure a good power-on reset, the RST pin must be high long enough to allow the oscillator time to start up (normally a few milliseconds) plus two machine cycles. At power-on, the voltage on Vcc and RST must come up at the same time for a proper start-up. Idle Mode In the idle mode, the CPU puts itself to sleep while all of the on-chip peripherals stay active. The instruction to invoke the idle mode is the last instruction executed in the normal operating mode before the idle mode is activated. The CPU contents, the on-chip RAM, and all of the special function registers remain intact during this mode. The idle mode can be terminated either by any enabled interrupt (at which time the process is picked up at the interrupt service routine and continued), or by a hardware reset which Starts the processor in the same manner as a power-on reset. Power-Down Mode To save even more power, a Power Down mode can be invoked by software. In this mode, the oscillator is stopped and the instruction that invoked Power Down is the last instruction executed. The on-chip RAM and Special Function Registers retain their values until the Power Down mode is terminated. On the 87C51FB either a hardware reset or external interrupt can use an exit from Power Down. Reset redefines all the SFRs but does not change the on-chip RAM. An external interrupt allows both the SFRs and the on-chip RAM to retain their values. To properly terminate Power Down the reset or external interrupt should not be executed before Vcc is restored to its normat operating level and must be held active long enough for the oscillator to restart and stabilize (normally less than 10ms). With an external interrupt, INTO and INT1 must be enabled and configured as level-sensitive. Holding the pin low restarts the oscillator but bringing the pin back high completes the exit. Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the Table 2. External Pin Status During Idle and Power-Down Mode instruction that put the device into Power Down. Design Consideration e When the idle mode is terminated by a hardware reset, the device normally resumes program execution, from where it left off, up to two machine cycles before the internal rest algorithm takes control. On-chip hardware inhibits access to internal RAM in this event, but access to the port pins is not inhibited. To eliminate the possibility of an unexpected write when Idle is terminated by reset, the instruction following the one that invokes Idle should not be one that writes to a port pin or to external memory. ONCE Mode The ONCE (On-Circuit Emulation) Mode facilitates testing and debugging of systems using the 87C51FB without the 87C51FB having to be removed from the circuit. The ONCE Mode is invoked by: 1. Pull ALE low while the device is in reset and PSEN is high; 2. Hold ALE low as RST is deactivated. While the device is in ONCE Mode, the Port 0 pins go into a float state, and the other port pins and ALE and PSEN are weakly pulled high. The oscillator circuit remains active. While the 87C51FB is in this mode, an emulator or test CPU can be used to drive the circuit. Normal operation is restored when anormal reset is applied. PROGRAM MODE MEMORY ALE PSEN PORT 0 PORT 1 PORT 2 PORT 3 Idie Internal 1 1 Data Data Data Data Idle External 1 1 Float Data Address Data Power-down Internal 0 0 Data Data Data Data Power-down External 0 0 Float Data Data Data 1995 Feb 02 8 MB 7110826 00473945 TH3Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB Programmable Counter Array (PCA) The Programmable Counter Array is a special Timer that has five 16-bit capture/compare modules associated with it. Each of the modules can be programmed to operate in one of four modes: rising and/or falling edge capture, software timer, high-speed output, or pulse width modulator. Each module has a pin associated with it in port 1. Module 0 is connected to P1.3(CEX0), module 1 to P1.4(CEX1), etc. The basic PCA configuration is shown in Figure 1. The PCA timer is a common time base for all five modules and can be programmed to run at: 1/12 the oscillator frequency, 1/4 the oscillator frequency, the Timer 0 overflow, or the input on the ECI pin (P1.2). The timer count source is determined from the CPS1 and CPSO bits in the CMOD SFR as follows (see Figure 4): CPS1 CPSO PCA Timer Count Source 0 0 1/12 oscillator frequency 0 1 1/4oscillator frequency 1 QO Timer 0 overflow 1 1 External Input at ECI pin In the CMOD SFR are three additional bits associated with the PCA. They are CIDL which allows the PCA to stop during idle mode, WOTE which enables or disables the watchdog function on module 4, and ECF which when set causes an interrupt and the PCA overflow flag, CF (in the CCON SFR) to be set when the PCA timer overflows. These functions are shown in Figure 2. The watchdog timer function is implemented in module 4 as implemented in other parts that have a PCA that are available on the market. However, if a watchdog timer is required in the target application, it is recommended to use the hardware watchdog timer that is implemented on the 8XC51FB separately from the PCA (see Figure 12). The CCON SFR contains the run contro} bit for the PCA and the flags for the PCA timer (CF) and each module (refer to Figure 5). To run the PCA the CR bit (CCON.6) must be set by software. The PCA is shut off by clearing this bit. The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the ECF bit in the CMOD register is set, The CF bit can only be cleared by software. Bits 0 through 4 of the CCON register are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by hardware when either a match or a capture occurs. These flags also can only be cleared by software. The PCA interrupt system shown in Figure 3. Each module in the PCA has a special function register associated with it. These registers are: CCAPMO for module 0, CCAPM1 for module 1, etc. (see Figure 6). The registers contain the bits that control the mode in which each module will operate. The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the CCON SFR to generate an interrupt when a match or compare occurs in the associated module. PWM (CCAPMn.1) enables the pulse width modulation mode. The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there is a match between the PCA counter and the modules capture/compare register. The match bit MAT (CCAPMnh.3) when set will cause the CCFn bit in the CCON register to be set when there is a match between the PCA counter and the modules capture/compare register. The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both bits are set both edges will be enabled and a capture will occur for either transition. The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function. Figure 7 shows the CCAPMnh settings for the various PCA functions. There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module is used in the PWM mode these registers are used to control the duty cycle of the output. WATCHDOG TIMER (MODULE 4 ONLY) [ 16BITs >| MODULE 0 ) MODULE 1 | 16 BITS | PCA TIMER/COUNTER MODULE 2 TIME BASE FOR PCA MODULES > MODULE 3 MODULE FUNCTIONS: 16-BIT CAPTURE 16-BIT TIMER MODULE 4 16-BIT HIGH SPEED OUTPUT 8-BIT PWM je __te[7] P1.3/CEXo pe $f] P1.4/CEX1 -< __-e [TJ P1S/CEX2 <i] _pe{7J P1.sicexa <0 $$$") P1.7/cexa $u00032 1995 Feb 02 Figure 1. Programmable Counter Array (PCA) MH 71108cb 0047586 167Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB = YY TO PCA lot } MODULES OSCi2 oF osor al OVERFLOW INTERRUPT 4 [rol CH CL o% : (7: TIMER 0 __ | : 4 16-BIT UP COUNTER : OVERFLOW EXTERNAL INPUT , (P1.2/ECl) O i : 00... 1, ...10...] DECODE WM. IDLE _ _ _ CMOD CIOL | WDTE cPsi cPSo ECF | OoH) x CCON CF cR CCF4 CCF3 ccFe | CCF1 ccFO | (oH) SU00033 Figure 2. PCA Timer/Counter CCON (D8H) PCA TIMER/COUNTER MODULE 0 Teceececeeeectecneen = EC EA MODULE 1 To INTERRUPT PRIORITY DECODER MODULE 2 MODULE 3 MODULE 4 CMOD.0| ECF CCAPMn.0 | ECCFn SU00034 Figure 3. PCA Interrupt System 1995 Feb 02 10 MB 7110826 O0875a7 616Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB CMOD Address = ODSH Reset Value = 00XX X000B Bit Addressable CIDL WDTE - ~ - CPS1 CPSO ECF Bit: 7 6 5 4 3 2 1 0 Symbol Function CIDL Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during idle Mode. CIDL = 1 programs it to be gated off during idle. WDTE Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4. WDTE = 1 enables it. - Not implemented, reserved for future use.* CPS1 PCA Count Puise Select bit 1. CPSO PCA Count Pulse Select bit 0. CPS1 CPSO = Selected PCA Input** 0 0 0 Internal clock, Fose + 12 0 1 1 Internal clock, Fosc + 4 1 0 2 Timer 0 overflow 1 1 3 External clock at ECI/P1.2 pin (max. rate = Fosc + 8) ECF PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an interrupt. ECF = 0 disables that function of CF. NOTE: * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. * Fosc = oscillator frequency SU00035 Figure 4. CMOD: PCA Counter Mode Register CCON Address = OD8H Reset Value = 00X0 0000B Bit Addressable CF CR - CCF4 CCF3 CCF2 CCF1 CCFO Bit: 7 6 5 4 3 2 1 0 Symbol Function CF PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but can only be cleared by software. CR PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared by software to turn the PCA counter off. - Not implemented, reserved for future use*. CCF4 PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF3 PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF2 PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCF1 PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. CCFO PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be cleared by software. NOTE: * User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. SU00036 Figure 5. CCON: PCA Counter Control Register 1995 Feb 02 1 ME 71108eb 0087346 75Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83051FB/87C51FB CCAPMn Address CCAPMO ODAH Reset Value = X000 0000B CCAPM1 ODBH CCAPM2 O0DCH CCAPM3 ODDH CCAPM4 ODEH Not Bit Addressable - ECOMn | CAPPn | CAPNn | MATn TOGn PWMn | ECCFn Bit: 7 6 5 4 3 2 0 Symboi Function - Not implemented, reserved for future use. Enable Comparator. ECOMn = 1 enables the comparator function. Match. When MATn = 1, a match of the PCA counter with this modules compare/capture register causes the CCFn bit Toggle. When TOGn = 1, a match of the PCA counter with this modules compare/capture register causes the CEXn Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width modulated output. Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate an interrupt. ECOMn CAPPn Capture Positive, CAPPn = 1 enables positive edge capture. CAPNn Capture Negative, CAPNn = 1 enables negative edge capture. MATn in CCON to be set, flagging an interrupt. TOGn pin to toggle. PWMn ECCFn NOTE: *User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. 800037 Figure 6. PCA Capture Mode To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the modules capture registers (CCAPnL and CCAPn#H)). If the CCFn bit for the module in the CCON SFR and the ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated. Refer to Figure 8. 16-bit Software Timer Mode The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules CCAPMnh register. The PCA timer will be compared to the modules capture registers and when a match occurs an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set (see Figure 9). 1995 Feb 02 High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs between the PCA counter and the modules capture registers. To activate this mode the TOG, MAT, and ECOM bits in the modules CCAPMn SFR must be set (see Figure 10). Pulse Width Modulator Mode All of the PCA modules can be used as PWM outputs. Figure 11 shows the PWM function. The frequency of the output depends on the source for the PCA timer. All of the modules will have the same frequency of output because they all share the PCA timer. The duty cycle of each module is independently variable using the module's capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the modules CCAPLn SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from FF to 00, CCAPLh is reloaded with the value in CCAPHnh then allows updating the PWM 12 MH 7110826 0087389 99 CCAPMn: PCA Modules Compare/Capture Registers without glitches. The PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode. Enhanced UART The UART operates in all of the usual modes that are described in the first section of this book for the 80C51. In addition the UART can perform framing error detect by looking for missing stop bits, and automatic address recognition. The 8XC51FB UART also fully supports multiprocessor communication as does the standard 80051 UART. When used for framing error detect the UART looks for missing stop bits in the communication. A missing bit will set the FE bitin the SCON register. The FE bit shares the SCON.7 bit with SMO and the function of SCON.7 is determined by PCON.6 (SMODO) (see Figure 13). If SMODO is set then SCON.7 functions as FE. SCON.7 functions as SMO when SMOD0 is cleared. When used as FE SCON.7 can only be cleared by software. Refer to Figure 14.Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB ECOMn | CAPPn | CAPNn | MATn TOGn PWMn | ECCFn MODULE FUNCTION X 0 0 0 0 0 0 0 No operation X x 1 0 0 0 0 xX 16-bit capture by a positive-edge trigger on CEXn xX xX 0 1 0 0 0 X 16-bit capture by a negative trigger on CEXn Xx Xx 1 1 0 0 0 x 16-bit capture by a transition on CEXn X 1 0 0 1 0 0 x 16-bit Software Timer Xx 1 0 0 1 1 0 xX 16-bit High Speed Output X 1 0 0 0 0 1 Q 8-bit PWM x 1 0 0 1 X 0 xX Watchdog Timer Figure 7. PCA Module Modes (CCAPMn Register) Automatic Address Recognition Automatic Address Recognition is a feature which allows the UART to recognize certain addresses in the serial bit stream by using hardware to make the comparisons. This feature saves a great deal of software overhead by eliminating the need for the software to examine every serial address which passes by the serial port. This feature is enabled by setting the SM2 bit in SCON. In the 9 bit UART modes, mode 2 and mode 3, the Receive Interrupt flag (RI) will be automatically set when the received byte contains either the Given address or the Broadcast address. The 9 bit mode requires that the 9th information bit is a 1 to indicate that the received information is an address and not data. Automatic address recognition is shown in Figure 15. The 8 bit mode is called Mode 1. In this mode the RI flag will be set if SM2 is enabled and the information received has a valid stop bit following the 8 address bits and the information is either a Given or Broadcast address. Mode 0 is the Shift Register mode and SM2 is ignored. Using the Automatic Address Recognition feature allows a master to selectively communicate with one or more slaves by invoking the Given slave address or addresses. All of the slaves may be contacted by using the Broadcast address. Two special Function Registers are used to define the slaves address, SADDR, and the address mask, SADEN. SADEN is used to define which bits in the SADDR are to b used and which bits are dont care. The SADEN mask can be logically ANDed with the 1995 Feb 02 SADDR to create the IGiven address which the master will use for addressing each of the slaves. Use of the Given address allows multiple slaves to be recognized while excluding others. The following examples will help to show the versatility of this scheme: Slave 0 SADDR = 1100 0000 SADEN = 4411 1407 Given 1100 00X0 Slave 1 SADDR = 1100 0000 SADEN = 41411 1110 Given = 1100 000X In the above example SADDR is the same and the SADEN data is used to differentiate between the two slaves. Slave 0 requires a 0 in bit 0 and it ignores bit 1. Slave 1 requires a 0 in bit 1 and bit 0 is ignored. A unique address for Slave 0 would be 1100 0010 since slave 1 requires a 0 in bit 1. A unique address for slave 1 would be 1100 0001 since a 1 in bit 0 will exclude slave 0. Both slaves can be selected at the same time by an address which has bit 0 = 0 (for slave 0) and bit 1 = 0 (for slave 1). Thus, both could be addressed with 1100 0000. In amore complex system the following could be used to select slaves 1 and 2 while excluding slave 0: Slave 0 SADDR = 1100 0000 SADEN = 4141 1001 Given = 1100 OXXO Slave 1 SADDR = 1110 0000 SADEN = 1141 101 Given = 1110 OX0X Slave 2 SADDR = 1110 0000 SADEN 41111, 1100 Given = 1110 OOXX 13 M@ 7110826 00487350 300 In the above example the differentiation among the 3 slaves is in the lower 3 address bits. Slave 0 requires that bit 0 = 0 and it can be uniquely addressed by 1110 0110. Slave 1 requires that bit 1 = 0 and it can be uniquely addressed by 1110 and 0101. Slave 2 requires that bit 2 = 0 and its unique address is 1110 0011. To select Slaves 0 and 1 and exclude Slave 2 use address 1110 0100, since it is necessary to make bit 2 = 1 to exclude slave 2. The Broadcast Address for each slave is created by taking the logical OR of SADDR and SADEN. Zeros in this result are teated as don't-cares. In most cases, interpreting the dont-cares as ones, the broadcast address will be FF hexadecimal. Upon reset SADDR (SFR address 0AQH) and SADEN (SFR address OB9H) are leaded with Os. This produces a given address of all don't cares as well as a Broadcast address of all dont cares. This effectively disables the Automatic Addressing mode and allows the microcontroller to use standard 80C51 type UART drivers which do not make use of this feature. Reduced EMI Mode The AO bit (AUXR.O) in the AUXR register when set disables the ALE output. 8XC51FB Reduced EM! Mode AUXR (0X8E) ]|]-J]J-]-|]- ]ao AO: Turns off ALE output.Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB CF CR _ ccra | cers | ccre | ccri | ccFo aah a a re 7 PCA INTERRUPT (TO CCFn) PCA TIMER/COUNTER CH cL Ea PA] fexet | iM CCAPnH CCAPnL cexn [ }-+ foro} CAPTURE ib / CCAPMnh, n= 1 to 4 _ ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn (DAH - DEH) SuU00038 Figure 8. PCA Capture Mode cE cR cera |ccrs | ccre2 |ccri | ccro toon) WRITE TO CCAPnH RESET CCAPnH CCAPhL PCA INTERRUPT WRITE TO a n ro cern) CCAPnL of ENABLE 16-BIT COMPARATOR CH cL PCA TIMER/COUNTER Sl ECOMn | CAPPn | CAPNn | MATn | TOGn | PWMn | ECCEn CONAN DEHN i) Q 0 0 0 SU00039 Figure 9. PCA Compare Mode 1995 Feb 02 14 Mi 7110626 0047351 247Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB CF CR _ CCF4 CCF3 CCF2 CCFi CCFO (oe) WRITE TO CCAPRH RESET Eivnnnntteetccennnnnteeetceesentnpecepesnniietescesnssimasesessnueeeseead CCAPAH CCAPAL PCA INTERRUPT WRITE TO a O CCF CCAPaL (TO CCFn) 0 1 ENABLE MATCH - 16-BIT COMPARATOR Ti ct cH cL a [><}1 ] CEXn PCA TIMER/COUNTER CCAPMnh, n: 1..4 ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn (DAH - DEH) 5 0 0 1 0 su00040 Figure 10. PCA High Speed Output Mode CCAPnH CCAPnhL ENABLE {| CL <CCAPnt 8-BIT COMPARATOR CEXn +P CL >= CCAPnL 1 OVERFLOW ] cL PCA TIMER/COUNTER CCAPMnh, n: 1..4 = ECOMn | CAPPn | GCAPNn [| MATn TOGn PWMn {| ECCFn (DH - DEH) 0 0 0 0 0 SU00041 Figure 11. PCA PWM Mode 1995 Feb 02 Mf 7110826 00873952 133Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB cmoD CIDL WDTE ~ _ _ cPS1 cPSso ECF | ion) WRITE TO CCAP4H RESET WRITE TO CCAP4H CCAP4L CCAP4L - yo ENABLE MATCH * 16-BIT COMPARATOR RESET CH cL PCA TIMER/COUNTER EcOoMn | Capen | CAPNn | MATn | TOG PWMn | ECCFn foun q 0 0 1 x Q x su00042 Figure 12. PCA Watchdog Timer SCON Address = 98H Reset Value = 0000 0000B Bit Addressable SMO/FE SM1 SM2 REN TB8 RB8 Tl Rl Bit: 7 6 5 4 3 2 1 0 (SMODO = 0/1)* Symbol Function FE Framing Error bit. This bit is set by the receiver when an invalid stop bit is detected. The FE bit is not cleared by valid frames but should be cleared by software. The SMODO bit must be set to enable access to the FE bit. SMO Serial Port Mode Bit 0, (SMODO must = 0 to access bit SMO) SM1 Serial Port Mode Bit 1 SMO SM1 Mode Description Baud Rate** 0 0 0 shift register Fosc/12 0 1 1 8-bit UART variable 1 0 2 9-bit UART Fosc/64 or Fosc/32 1 1 3 9-bit UART variable SM2 Enables the Automatic Address Recognition feature in Modes 2 or 3. If SM2 = 1 then RI will not be set unless the received 9th data bit (RB8) is 1, indicating an address, and the received byte is a Given or Broadcast Address. In Mode 1, if SM2 = 1 then RI will not be activated unless a valid stop bit was received, and the received byte is a Given or Broadcast Address. In Mode 0, SM2 should be 0. REN Enables serial reception. Set by software to enable reception. Clear by software to disable reception. TB8 The 9th data bit that will be transmitted in Modes 2 and 3. Set or clear by software as desired. RB8& In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RBS is the stop bit that was received. In Mode 0, RB8 is not used. Tl Transmit interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or at the beginning of the stop bit in the other modes, in any serial transmission. Must be cleared by software. Rl Receive interrupt flag. Set by hardware at the end of the 8th bit time in Mode 0, or halfway through the stop bit time in the other modes, in any serial reception (except see SM2). Must be cleared by software. NOTE: SMOD0 is located at PCON6. **Fosc = oscillator frequency SU00043 Figure 13. SCON: Serial Port Control Register 1995 Feb 02 16 Mme 7110826 0047393 O17Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB 1995 Feb 02 ltl Laat bjt >t | START DATA BYTE ONLY IN STOP BIT MODE 2,3 BIT ? o}<_ SET FE BIT IF STOP BIT IS 0 (FRAMING ERROR) o}_ SM0 TO UART MODE CONTROL SCON SMo/FE | SM1 SM2 REN TBS RBS Tl RI (o8H}) smop1 | smopo | osF Por | ive | Gro | Gt io. | Feary 0: SCON.7 = SMO 1: SCON.7 = FE su00044 Figure 14. UART Framing Error Detection SCON SMO SM1 SM2 REN TBS RBS 1 Rl (98H) 1 1 1 1 x 1 0 T) __) RECEIVED ADDRESS Do TO D7, - PROGRAMMED ADDRESS |_COMPARATOR IN UART MODE 2 OR MODE 3 AND SM2 = 1: INTERRUPT IF REN=1, RB8=1 AND RECEIVED ADDRESS = "PROGRAMMED ADDRESS WHEN OWN ADDRESS RECEIVED, CLEAR SM2 TO RECEIVE DATA BYTES WHEN ALL DATA BYTES HAVE BEEN RECEIVED: SET SM2 TO WAIT FOR NEXT ADDRESS. SU00045 Figure 15. UART Multiprocessor Communication, Automatic Address Recognition 17 Me 7110826 0087394 T5bPhilips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB ABSOLUTE MAXIMUM RATINGS": 2:3 PARAMETER RATING UNIT Operating temperature under bias 0 to +70 or -40 to +85 C Storage temperature range 65 to +150 C Voltage on EA/Vpp pin to Vgg 0 to +13.0 Vv Voltage on any other pin to Vsg 0.5 to +6.5 Vv Maximum Io per I/O pin 15 mA Power dissipation (based on package heat transfer limitations, not 1.5 WwW device power consumption) NOTES: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any conditions other than those described in the AC and DC Electrical Characteristics section of this specification is not implied. 2. This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maxima. 3. Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to Vsg unless otherwise noted. Electrical Deviations from Commercial Specifications for Extended Temperature Range DC and AC parameters not included here are the same as in the commercial temperature range table. DC ELECTRICAL CHARACTERISTICS Tamb = 40C to +85C, Voc = 5V 10%, Vgs = OV TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN MAX UNIT Vie Input low voltage, except EA -0.5 0.2Vec-0.15 V Vind Input low voltage to EA 0 0.2Vcc-0.35 V Vin Input high voltage, except XTAL1, RST 0.2Vect1 Voct0.5 Vv Vina Input high voltage to XTAL1, RST 0.7Vec+0.1 Vect0.5 Vv Ne Logical 0 input current, ports 1, 2,3 Vin = 0.45V 75 pA Ie Logical 1-to-0 transition current, ports 1, 2, 3 Vin = 2.0V -750 pA 1995 Feb 02 Me 7110826 00873595 icPhilips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB DC ELECTRICAL CHARACTERISTICS Tamb = 0C to +70C or 40C to +85C, Voc = 5V 410%, Vgg = OV TEST LIMITS SYMBOL PARAMETER CONDITIONS MIN TYP! MAX UNIT Vit Input low voltage, except EA? -0.5 0.2Vec-0.1 V Vicd Input low voltage to EA? 0 0.2Vec-0.3 Vv VI Input high voltage, except XTAL1, RST? 0.2Vec+0.9 Voct0.5 Vv Vind input high voltage, XTAL1, RST? 0.7Voc Voc+0.5 Vv VoL Output low voltage, ports 1, 2, 39 lol = 100nA 0.3 V loL = 1.6mA?2 0.45 Vv lol = 3.5mA 1.0 Vv Vout Output low voltage, port 0, ALE, PSEN? lor = 200nA 0.3 V lou = 3.2mA2 0.45 Vv lot = 7.0MA 1.0 Vv Vou Output high voltage, ports 1, 2, 3, ALE, PSEN? lon = -60pnA, Veo - 1.5 Vv lon = 30pA Voc 0.7 Vv lon = 10pnA Veco -9. Vv Von Output high voltage (port 0 in external bus mode), loy = 7.0mA, Veco -1.5 Vv ALE19, PSEN? lon =-3.2mMA Voc 0.7 Vv lon = -200nA Voc 0.3 Vv lit Logical 0 input current, ports 1, 2, 37 Vin = 0.45V -50 HA It Logical 1-to-0 transition current, ports 1, 2, 37 See note 4 650 HA 0.45 Vin < lu Input leakage current, port 0 Voo0.3 +10 pA lec Power supply current: See note 6 Active mode @ 16MHz 15 25 mA Idle mode @ 16MHz 3 5 mA Power-down mode: Tamb = 0 to +70C 10 50 HA Tamb = 40 to +85C 75 HA Rast Internal reset pull-down resistor 50 225 kQ Cio Pin capacitance! (except EA) 15 pF NOTES: 1. Typical ratings are not guaranteed. The values listed are at room temperature, 5V. 2. Capacitive loading on ports 0 and 2 may cause spurious noise to be superimposed on the Vos of ALE and ports 1 and 3. The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 transitions during bus operations. In the worst cases (capacitive loading > 100pF), the noise pulse on the ALE pin may exceed 0.8V. In such cases, it may be desirable to qualify ALE with a Schmitt Trigger, or use an address latch with a Schmitt Trigger STROBE input. Io. can exceed these conditions provided that no single output sinks more than 5mA and no more than two outputs exceed the test conditions. 3. Capacitive loading on ports 0 and 2 may cause the Voy on ALE and PSEN to momentarily fall below the 0.9Vcc specification when the address bits are stabilizing. 4. Pins of ports 1, 2 and 3 source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when Vij is approximately 2V. locmax at other frequencies is given by: Active mode: Iccmax = 1.50 x FREQ + 8; Idle mode: lecyax = 0.14 x FREQ +2.31, where FREQ is the external oscillator frequency in MHz. Iccmax is given in mA. See Figure 23. See Figures 24 through 27 for lec test conditions. These values apply only to Tamp = 0C to +70C. For Tamb = 40C to +85C, see table on previous page. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. Under steady state (non-transient) conditions, lo_ must be externally limited as follows: Maximum Io, per port pin: 15mA (*NOTE: This is 85C specification.) Maximum lo: per 8-bit port: 26mA Maximum total lo, for all outputs: 71mA If lo. exceeds the test condition, Vo, may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 10. ALE is tested to Von1, except when ALE is off then Voy is the voltage specification. 11. Pin capacitance is less than 25pF. Pin capacitance of ceramic package is less than 15pF (except EA, it is 25pF). wn OONH 1995 Feb 02 19 Mi 7110826 0087356 429Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB AC ELECTRICAL CHARACTERISTICS Tamb = 0C to +70C or 40C to +85C, Voc = 5V +10%, Vgg = OVI 28 16MHz CLOCK VARIABLE CLOCK SYMBOL | FIGURE PARAMETER MIN MAX MIN MAX UNIT tHtetet 16 Oscillator frequency 4 -5 3.5 16 MHz -A -B 3.5 24 MHz tLHLL 16 ALE pulse width 85 2tcici-40 ns tAVLL 16 Address valid to ALE low 22 tetcL_-40 ns tLLax 16 Address hold after ALE low 32 tetcL-30 ns tiuv 16 ALE low to valid instruction in 150 AtcicL-100 ns {LEPL 16 ALE low to PSEN low 32 toitcL-30 ns tpLPH 16 PSEN pulse width 142 3te_c_-45 ns tpiiv 16 PSEN low to valid instruction in 82 StcLcL-105 ns tpxix 16 Input instruction hold after PSEN 0 0 ns tpxiz 16 Input instruction float after PSEN 37 teicL-25 ns taviv 16 Address to valid instruction in 207 Stei_ci-105 ns teraz 16 PSEN low to address float 10 10 ns Data Memory tRLRH 17,18 | RD pulse width 275 6teLci-100 ns twowH 17,18 | WR pulse width 275 6teLc_-100 ns tRLDV 17,18 | RD low to valid data in 147 5tcLcL-165 ns tRHDX 17,18 | Data hold after RD 0 0 ns trupz 17,18 | Data float after RD 65 2teLo_-60 ns tttpv 17,18 | ALE low to valid data in 350 8toLcoi-150 ns tavov 17,18 | Address to valid data in 397 StoLicL-165 ns tlewe 17,18 | ALE low to RD or WR low 137 237 3teLcL-50 SteLeL+50 ns taywe 17,18 | Address valid to WR low or RD low 175 4teicL-75 ns tovwx 17,18 | Data valid to WR transition 42 tcicL_-20 ns twHox 17,18 | Data hold after WR 42 tetcL-20 ns tevwH 18 Data valid to WR high 287 7teic_-150 ns trLaz 17,18 | RD low to address float 0 0 ns tWHLH 17,18 | RD or WR high to ALE high 40 87 toLoL-20 toLeL+25 ns External Clock tcHex 20 High time 12 20 ns tetex 20 Low time 12 20 ns toLcH 20 Rise time 20 20 ns teHeL 20 Fall time 20 20 ns Shift Register txLXL 19 Serial port clock cycle time 1 12teLeL us tavxH 19 Output data setup to clock rising edge 492 10teLcL_-133 ns txHax 19 Output data hold after clock rising edge 8 2toLci-117 ns txHDx 19 Input data hold after clock rising edge 0 0 ns txypy 19 Clock rising edge to input data valid 492 10te_c_-133 ns NOTES: 1. Parameters are valid over operating temperature range unless otherwise specified. 2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF. 3. Interfacing the 87C51FB to devices with float times up to 45ns is permitted. This limited bus contention will not cause damage to Port 0 drivers. 1995 Feb 02 MH 7110826 0087397 765Philips Semiconductors CMOS single-chip 8-bit microcontrollers Product Specification 83C51FB/87C51FB EXPLANATION OF THE AC SYMBOLS Each timing symbol has five characters. The first character is always t (= time). The other characters, depending on their positions, indicate the name of a signal or the logical status of that signal. The designations are: A Address C Clock D Input data H Logic level high | Instruction (program memory contents) L Logic level low, or ALE P - PSEN Q- Output data R RD signal t Time V Valid W- WR signal X ~ No longer a valid logic level Z Float Examples: tay__ = Time for address valid to fLLPL ALE low. =Time for ALE low to PSEN low. PSEN PORT 0 PORT 2 tLHLL " ALE tee | Tr tiv _/ _>~ <__ taviv > teu tliax tpLPH < tpLaz tpxix Se AN texiz> AO-A7 N INSTR IN A0-A7 -<_ AO-A15 X AB-A15 SU00006 Figure 16. External Program Memory Read Cycle ALE / \ N tWwHLH > tiiwL tLLDV tLLax | y tavi (* AO-A7 FROM RI OR DPL <_ taywL > \| _tRLAZ, 1<_ tR_LRH ] NY < tarpv > tRHDZ_| Yt tRHDx > DATA IN f 7 oN N >< AO-A7 FROM PCL INSTR IN tavpv * / PORT2 x P2.0-P2.7 OR A8-A15 FROM DPF x AQ-A15 FROM PCH Su00026 Figure 17. External Data Memory Read Cycle 1995 Feb 02 21 MH 7110826 0067398 bT]Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB ALE N tWwHLH M tw, >+__ wawH- KY tavwx >| Pr twHax < tow >} Vv y N AO-A7 PORT 0 > FROM RIOR pL DX DATA OUT Kx AO-A7 FROM PCL INSTR IN N t<. taywL > tLLAx | v v tavit |* VY PORT2 xX P2.0-P2.7 OR A8-A15 FROM DPF x A0-A15 FROM PCH SU00026 Figure 18. External Data Memory Write Cycle INSTRUCTION || 0 | 1 | 2 | 3 | 4 | ALE PLILILILILILILILILILI LILI LIAL] be ta | clock LI LI LILI LI LI LI LI > txHOX tavxH QUTPUT DATA a ES Ee ED SE EE WRITE TO SBUF INPUT DATA 1 CLEAR Al 800027 Figure 19. Shift Register Mode Timing Voc-0.5 ~~ - = 0.45V SU00009 Figure 20. External Clock Drive 1995 Feb 02 22 Mi 71104826 0087399 535Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB Voc-0.5 O.2Voct0.9 0.2V, 1 0.45V co NOTE: AC inputs during testing are driven at Voc 0.5 for a logic 1 and 0.45V for a logic 0. Timing measurements are made at Vy min for a logic 1 and Vi_ max for a logic 0. SU00010 Figure 21. AC Testing Input/Output VLOAD+0-1V TIMING VOH-0.1V VLOAD as REFERENCE a VLOAD-0.1V POINTS VOL+t0.1V NOTE: For timing purposes, a port is no longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded VoH/Vo, level occurs. lon/toL = +20mA. SU00071 Figure 22. Float Waveform 45 MAX ACTIVE MODE L. ICCMAX = 1.50 X FREQ. + 8 40 YY 35 Y 30 4. 4 TYP ACTIVE MODE 25 0.9 X FREQ. + 2.5 tcc mA . a4 < 15 ZO JL c c toy MAX IDLE MODE 5 va oo |_| TYP IDLE MODE La een eee | 4MHz 8MHz 12MHz 16MHz 20MHz 24MHz FREQ AT XTAL1 U00046 Figure 23. icc vs. FREQ Valid only within frequency specifications of the device under test 1995 Feb 02 23 M@ 7110626 0087400 OFTPhilips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB Yoo lec Voc Voc Yeo RST Po IN| EA (NC) XTAL2 CLOCK SIGNAL >J XTAL1 Vss SU00013 Figure 24. Icc Test Condition, Active Mode All other pins are disconnected Voc loc Voc | RST Voc = EA (NC) XTAL2 CLOCK SIGNAL _]_ XTAL1 = Vgs SU00014 Figure 25. Ice Test Condition, Idle Mode All other pins are disconnected Vv Bo coo O.7Vcc 0.45V 0.2Voc-0.1 suo0009 Figure 26. Clock Signal Waveform for lec Tests in Active and Idle Modes tocu = toner = 5ns fsoFeb0 ma 7120826 0087401 Tlb mmPhilips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB Vee icc Voc ! RST Voc Po i = NI EA (NG) XTAL2 Vss Figure 27. Icc Test Condition, Power Down Mode All other pins are disconnected. Voc = 2V to 5.5V 1995 Feb 02 25 Me 7110826 OO8740e 152Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB EPROM CHARACTERISTICS The 87C51FB is programmed by using a modified Quick-Pulse Programming algorithm. It differs from older methods in the value used for Vpp (programming supply voltage) and in the width and number of the ALE/PROG pulses. The 87C51FB contains two signature bytes that can be read and used by an EPROM programming system to identify the device. The signature bytes identify the device as an 87C51FB manufactured by Philips. Table 3 shows the logic levels for reading the signature byte, and for programming the program memory, the encryption table, and the security bits. The circuit configuration and waveforms for quick-pulse programming are shown in Figures 28 and 29. Figure 30 shows the circuit configuration for normal program memory verification. Quick-Pulse Programming The setup for microcontroller quick-pulse programming is shown in Figure 28. Note that the 87C51FB is running with a 4 to BMHz oscillator. The reason the oscillator needs to be running is that the device is executing internal address and program data transfers. The address of the EPROM location to be programmed is applied to ports 1 and 2, as shown in Figure 28. The code byte to be programmed into that location is applied to port 0. RST, PSEN and pins of ports 2 and 3 specified in Table 3 are held at the Program Code Data levels indicated in Table 3. The ALE/PROG is pulsed low 25 times as shown in Figure 29. To program the encryption table, repeat the 25 pulse programming sequence for addresses 0 through 1FH, using the Pgm Encryption Table levels. Do not forget that after the encryption table is programmed, verification cycles will produce only encrypted data. To program the security bits, repeat the 25 pulse programming sequence using the Pgm Security Bit levels. After one security bit is programmed, further programming of the code memory and encryption table is disabled. However, the other security bit can still be programmed. Note that the EA/Vpp pin must not be allowed to go above the maximum specified Vpp level for any amount of time. Even a narrow glitch above that voltage can cause permanent damage to the device. The Vpp source should be well regulated and free of glitches and overshoot. Program Verification If security bit 2 has not been programmed, the on-chip program memory can be read out for program verification. The address of the program memory locations to be read is applied to ports 1 and 2 as shown in Figure 30. The other pins are held at the Verify Code Data levels indicated in Tabie 3. The contents of the address location will be emitted on port 0. External pull-ups are required on port 0 for this operation. If the encryption table has been programmed, the data presented at port 0 will be the exclusive NOR of the program byte with one of the encryption bytes. The user will have to know the encryption table contents in order to correctly decode the verification data. The encryption table itself cannot be read out. Table 3. EPROM Programming Modes Reading the Signature Bytes The signature bytes are read by the same procedure as a normal verification of locations 030H and 031H, except that P3.6 and P3.7 need to be pulled to a logic low. The values are: (030H) = 15H indicates manufactured by Philips (031H) = B2H indicates 87C51FB Program/Verify Algorithms Any algorithm in agreement with the conditions listed in Table 3, and which satisfies the timing specifications, is suitable. Erasure Characteristics Erasure of the EPROM begins to occur when the chip is exposed to light with wavelengths shorter than approximately 4,000 angstroms. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3 years in room level fluorescent lighting) could cause inadvertent erasure. For this and secondary effects, it is recommended that an opaque label be placed over the window. For elevated temperature or environments where solvents are being used, apply Kapton tape Fluorglas part number 2345-5, or equivalent. The recommended erasure procedure is exposure to ultraviolet light (at 2537 angstroms) to an integrated dose of at least 15W-s/cm?. Exposing the EPROM to an ultraviolet lamp of 12,000,W/cm? rating for 20 to 39 minutes, at a distance of about 1 inch, should be sufficient. Erasure leaves the array in an all {s state. MODE RST PSEN ALE/PROG | EA/Vpp P2.7 P2.6 P3.7 P3.6 Read signature 1 0 1 1 0 0 0 0 Program code data 1 0 0* Vpp 1 0 1 1 Verify code data 1 0 1 1 Q 0 1 1 Pgm encryption table 1 0 0* Vpp 1 0 1 0 Pgm security bit 1 1 0 o* Vpp 1 1 1 1 Pgm security bit 2 1 0 0* Vpp 1 1 0 0 NOTES: 1. 0 = Valid low for that pin, 1 = valid high for that pin. 2. Vpp = 12.75V +0.25V. 3. Voc = 5V+10% during programming and verification. minimum of 10us. Trademark phrase of Intel Corporation. 1995 Feb 02 26 M@ 7110826 0087403 499 ALE/PROG receives 25 programming pulses while Vpp is held at 12.75V. Each programming pulse is low for 100us (10us) and high for aPhilips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB +5V Voc AO-A7 A Pi PO K PGM DATA 1 -} RST EAVpp (*__ +12.75V 1 >] P36 ALEFPROG _. 25 100s PULSES TO GROUND 1 ___+>} P37 87C51FB PSEN *#_____ 0 2 XTAL2 P2.7 }<___ 1 4-6MHz C_) p26 __ 0 | stat + P2.0-P2.5 \ A8-A13 Vss SU00047 Figure 28. Programming Configuration let 25 PULSES >| | | ALE/PROG: Q | | | | | | | | | wee eee . 10us MIN Ko 100p1s+10 | 1 ALE/PROG: 0 | | SU00018 Figure 29. PROG Waveform +5V Vec AO-A7 A Pi PO PGM DATA 1 RST EAVpp [{*___ 1 1 P3.6 ALEPROG <-_ 1 1 P37 87C51FB PSEN }#-_ 0 * XTAL2 P2.7 }*#_ 0 ENABLE [ ae 4-6MH2 C] p26 [<__ 0 XTAL1 P2.0-P2.5 K AB-A13 Vss SU00048 Figure 30. Program Verification 1995 Feb 02 M@@ 7110826 0087404 725Philips Semiconductors Product Specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB EPROM PROGRAMMING AND VERIFICATION CHARACTERISTICS Tamb = 21C to +27C, Voc = 5V410%, Vg = OV (See Figure 31) SYMBOL PARAMETER MIN MAX UNIT Vpp Programming supply voltage 12.5 13.0 Vv Ipp Programming supply current 50 mA TActeL Oscillator frequency 4 6 MHz taveL Address setup to PROG low 48tcLoL teHax Address hold after PROG 48tcieL toveL Data setup to PROG low 48tcioL teHox Data hold after PROG 48teicL teHsH P2.7 (ENABLE) high to Vpp 48tcicL tsHaL Vpp setup to PROG low 10 ps teHsL Vpp hold after PROG 10 ps t6LGH PROG width 90 110 ps tavav Address to data valid 48tcicL teLaz ENAELE low to data valid 48tcLoL teHoz Data float after ENABLE 0 48tcLeL tGHGL PROG high to PROG tow 10 ps PROGRAMMING* pagepee ADDRESS ) f* tavav PORT Qs pF oateour | taHpx ALE/PROG TGHAX tGHSL LOGIC 1 LOGIC 1 EA pp _........._.L 2... eee! he tEHSH teLav teHaz Su00020 NOTE: * FOR PROGRAMMING VERIFICATION SEE FIGURE 28. FOR VERIFICATION CONDITIONS SEE FIGURE 30. Figure 31. EPROM Programming and Verification 1995 Feb 02 8 2 M 711082b o0487405 bblPhilips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB DIP40: plastic dual in-line package; 40 leads (600 mil) SOT129-1 2 . 52.50 15.80 = 51.50 - 15.24 2 y+ | $ ee 40 47 EL i PHO oo 4_max max | 3.50 4 * 4 ' 308 vn | jax ~~ de y | max POOP OOP OPPO) eq 10.254] ore | MSA266 jg 17.15 ~~ 15.90 - we eee _ 14.1 13.7 Dimensions in mm. 1 20 2) Sees 1995 Feb 02 MH 7110826 OO8740b STS 29Product specification Philips Semiconductors 83C51FB/87C51FB CMOS single-chip 8-bit microcontrollers 40-PIN (600 mils wide) CERAMIC DUAL IN-LINE (F) PACKAGE (WITH WINDOW (FA) PACKAGE) 0590B z' resco oe (s9'21) se90 (vy SLON) t (p2"S1) 009'0 osa . . ; A (15'0) 020O {or') sso'o I (g9) SPLO (Spy) S210 (p SLON) (66'y1) 0650 (SzS1) 0z90 s}onpold WOUdg JO} uoHTeo0| MOpUIM sajouEg 9 doy ey} Woy POMAIA USM Op# Ul O} OSIMYOO}OJ9]UNOD OeNuqUod pue | # Ul WIM Leys SISQUINU Ug *S 1 aueld 0} JejNoIPuadied aq 0} peuleAsUCO Spee] oy} UIM pounseelw SUOCISUBUUIP BSOUL F yoyewsILu aseq 0} pl| pue aul fees oy] UC SNOSIUGW PUB UNA sseib Joy BOUeEMO]!E EpNjoul pue Apog ey} uc swnyep eouaJajad ale 4, PUB "Qn aly ' Z8G6L-WS PLA ISNV 49d Bulouelejo) pue UoIsuaWIq *Z sasaujualed ul UMOUS Se SIBJOWIIW Seyou| :uoIsuaWIP Bulyjoyuoy *| SALON (81') SZL'0 (61) SOLO XV (22'9) Szz'0 + @(osz'0) 10 |@ a] a | 1 [| (2219) 8602 (g0) SL0'O (80) ezo'o (42'1) 0g0'0 (824) 0200 ai ON NW1d (LV3S -1- (L0es) 280% 988 (rS"2) OOL'O and (os"PL) L290 (61'St) g650 r ALAAMMAKLARMAAAAAAKAA Vey rrr (Z0'L) ovO'0 (6r'z) 8600 9 S3LON 34S TY (Z0'L) Ov0'O (6p2) 8600 853-0590B 06688 30 1995 Feb 02 M@@ 7110626 0087407 434 MeProduct specification Philips Semiconductors 83C51FB/87C51FB CMOS single-chip 8-bit microcontrollers 44-PIN PLASTIC LEADED CHIP CARRIER (A) PACKAGE 0403G (66'rL) O690 9'0) SLO'O1<p + | [@3-a| lee) Lp | (00'9+) 09'0 (salsv] Geoff} 89 F vy (tz'Z) p820 e | a INV1d SNILVSS +t Pea outta wisatad " . : (40) sooo NIW (50) 0Z00 aealsioo WwW Aluo jeyseped uyim sebeyord 0} ajqeayddy JEqUUNU JoNpold auy JOYE ,y, XIJNS BU} S199 1d 2B Ul pabexoed Jonpoud 104 pod Japlo soyeUubis (MalA dO}) pr Uld 0} BSIMYOO[OIEJUNGO enNuUUCD sIEquUINU Ug cH-, aueid ye Apog ayy Woy yWxa Spea| 196]U80 BSeU} B1OYyM PSUILUEJEp ae .O4,, pue ,q-G,, winyeq apis Aue uo (wilug2'0) .010'0 pasoxe jOU |[eYs UOISNJjo1d YseY PJOYY 'YSeY Plow epnjou! jou op sluNnyep @SOUL *,-H-, eueld ye PeulWUayEp aq O} ,-G-,, PUB ,-y-,, LUIN}Ep Oo} UOReI07 Apoq osejd syixe peg] aaym peg] jo do} uM quapioulos pue aur Buied pow jo do} ay} ye payeoo| ,-H-, oueld winyeg "286 L-NS' PLA ISNV Jed Bulouesejo} pue Bujuoisuswiiq seseuyjueled ul UMOYS Ose LU U] SUOISUSLUIP SLEW SeYOU! :suOIsUSWUIP BuUI]OJUOD Z (P8/LE/OL v eNnss]) erenbs Buloeds pea) (ww ZZ' +) you! Og0'O spee| Pp JaLUED dIYD pepee] oNseI\q JO} OV-ZP0-OW UONeoyoeds OAGAr O} wuOjUCO suoIsuLUID eBeyoed | SALON No sg G (oES ICCC CT OH Muro mT]s S30V1d u (v9'0) $z0'0 (66'1) 0650 (PL'b) Spo'o (0091) o90 (e'0) 10'0 (50) 1z00 iA [-9-| 3Nv1d (or [(o1'0) 700] 00'0 ONWLWIS (61"y) S91'0 f (2Sp) O81 0 rl {622) 060 | (990) 9z00 _ SbX mA b) epo'0 (soe) aro 80) 00 zeo'0 @ reso 1) 9900 "NIN (p90) S200 NIW (25) coo 4 WV ro [a [NI/NIZoo'o] T- ( 3-a[@a [ (er-0) 2000 [GB W [-a-| (bS91) os9'o vy [NI/NI2000| | (9991) 9490 41l1Ov (810) 000 282218 21 | esis (Ze17 6800) YE a SbX (20L) zP00 (22'1) BPO'0 a3 D } q p WY 4 5 e &p . q (OP*21) S89'0 q 0 [= l# Nid |. . (s921) $69'0 fog | (1991) 0S90 qd (9991) 9s90 [(oz'zt) o0s"0 | f q ; e D | @ S30V1d +a]Oa [Oler0) 20010 |G a XW G20) 0100 [(oz'@1) 0050 | (ov) $890 tl 9-4|v |GXe! 0) 2000 (g921) s690 853-0403G 05402 31 1995 Feb 02 MH 7110826 0067408 370Product specification Philips Semiconductors 83C51FB/87C51FB CMOS single-chip 8-bit microcontrollers 44-PIN CERQUAD J-BEND (K) PACKAGE 1472A (youl) ju a 1ivlad (9000) SLO | [7 (jroo szo NIW (0200) 80S"0 a l& e NIW (00'0) 9200 "NI (900'0) S40 [NIA XY (0100) Sz0 ok ot 06 AluO BOUsIEJAs JO} Be SUOCISUBLUIP pue jeuojdo si jayas sapjos episyoeg We "ysiuy Guiyeyd pea; pue jasyo wu) peo} @PN[OUI S8OULIBJO} PUB SUCISUSLUIDP II Ss se}euU| UOISUeLUIp Bulljo4UCD p apis yore UO WINWIXBLU SSYDU! GO0'O 8q O} LOISMujOld sse{E) uoisnyjoid sse|6 apnjoul jou op sucIsualuIg 7 reuondo sl MOPUIM AQ CW C861L-S'VLA ISNV O} WUOJUOD 0} S8OULs9/0} PUB SUOISUBUIP IIy 1. "SALON (yours SAIS Tlv dAL Vv MvLad (2000 6L0'0) 28r0 | } \ ANV1d 3Sva an SA90V1d 7 dALoSP ANV1d SNILVAS (0L00 F OF0'0) $z'0 F ZO'L dad (0900) 25} (e00'0 F 620'0) 80'0 F E20 LK L gat (0500) zz"t SNVId ONLWAS vWwlad Aas (o6z'0) zez | (06z'0) ze2 (ozero) 1'8 | (Ozeo) Et'8 | TWNIWON j}- (009'0) Lz | 4 1Iv130 43S JNVId ONILWAS (SS1'0) v6'e (0610) es" LI rd xOr 44 (oararzet}+| | (S890) OF'Z1 (999'0) SOZ1 _.| serx tooo - vy =et (S10'0) s0 _' fF 1 (SS1'0) ree | (061-0) eer NIW 8 (Sz0'0) 90 XE nnn mmo mmm m y df 0 Wig (090) 0091 q aA P (s990) 6881 (| P 4 - + - = (g890) ov'Zt q XG A (S69'0) SOL1 q b q b q 1 b q O STSSEpSoooo (060'0) 622 _| (0Z1'0) soe | loco (0) 0091 ($990) 6891 ($890) OP*Z1 (S690) GOZ1 SP HadWVHO Let oSb X (OF0'O) ZO'L 853-1472A 05854 32 1995 Feb 02 MB 711082b 0087409 207Philips Semiconductors Product specification CMOS single-chip 8-bit microcontrollers 83C51FB/87C51FB QFP44: plastic quad flat package; 44 leads (lead length 1.3 mm); body 10 x 10 x 1.75 mm SOT307-2 aN Lf | } a \ J UU ! N / F HABARARRARA 1] E =} | fet S|!) Be |) mm, 1 Q =}# - ----- |= FE Me A Aa (As) om I ar } \ oe > Brg) 1 oS ! i - opt cc pin 1 index TI Orn" oA i hero -bi-] sper 0 ] Hp a=] v @/ 8] 0 2.5 Smm scale DIMENSIONS (mm are the original dimensions) A UNIT | max. | At | Ae | As | bp | | DG | EM) e | Hp | He} Lj Lp] @ v w y | ZpM) ze) 6 0.25 | 1.85 0.40 | 0.25 | 10.1 | 10.1 12.9] 12.9 0.95 | 0.85 1.2 1 1.2 | 10 mm 12-191) 905 | 1.65] %25] o20}014| 99 | 99 | %8 1423! 123/ +3 | 055] 075/215) 915) O1 | os | og 0 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE REFERENCES EUROPEAN VERSION IEC JEDEC EIAJ PROJECTION $OT307-2 on 95-02-04 ISSUE DATE 1995 Feb 02 33 Me 7110626 0067410 Teo