Si3226/7 Si3208/9 D U A L P R O S L I C (R) W I T H DC-DC C O N T R O L L E R Features Performs all BORSCHT functions Ideal for short- or long-loop applications Internal balanced or unbalanced ringing Low power consumption Software-programmable parameters: Ringing frequency, amplitude, cadence, and waveshape Two-wire ac impedance Transhybrid balance DC current loop feed (10-45 mA) Loop closure and ring trip thresholds Ground key detect threshold Integrated dc-dc controller Wideband CODEC (Si3227) Low-power sleep mode On-hook transmission Loop or ground start operation Smooth polarity reversal DTMF generator/decoder A-Law/-Law companding, linear PCM PCM and SPI bus digital interfaces with programmable interrupts GCI/IOM-2 mode support 3.3 V operation GR-909 loop diagnostics Audio diagnostics with loopback Pb-free/RoHS-compliant packaging Applications Customer Premises Equipment (CPE) Optical Network Terminals (ONT) Private Branch Exchange (PBX) Cable EMTAs, ATAs, VoIP Gateways Description The Dual ProSLIC(R) is a family of low-voltage CMOS devices that integrate both SLIC and CODEC functionality into a single IC. In combination with a linefeed IC (LFIC), they provide a complete two-channel analog telephone interface in accordance with all relevant LSSGR, ITU, and ETSI specifications. The Dual ProSLIC devices (Si3226/7) operate from a single 3.3 V supply and interface to standard PCM/SPI or GCI bus digital interfaces. The LFICs (Si3208/9) perform all high-voltage functions and operate from a 3.3 V supply as well as high-voltage battery supplies. The Si3208 is rated for -110 V, and the Si3209 is rated for - 135 V. The Dual ProSLIC devices are available in a 64-pin thin quad flat package (TQFP), and the LFICs are available in a 40-pin, quad flat no-lead package (QFN). Ordering Information See page 33. Patents pending Functional Block Diagram Caller ID CS SDI SDO SCLK INT SPI Control Interface Ringing Generator DSP CODEC SLIC ADC Linefeed Control DAC Linefeed Monitor CODEC SLIC ADC Linefeed Control Line Diagnostics RST PCLK DTMF & Tone Gen DC-DC DC-DCControllers Controller PLL DAC Linefeed Monitor TIP Linefeed DTX PCM/ GCI Interface Si3206 Si3208/9 Channel 1 Linefeed FSYNC DRX Programmable Programmable AC ACImpedance Impedance and Hybrid Si3226 Si3226/7 Channel 2 RING TIP RING VBAT VDC Preliminary Rev. 0.33 6/07 DC-DC BOM Copyright (c) 2007 by Silicon Laboratories Si3226/7 Si3208/9 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si3226/7 Si3208/9 2 Preliminary Rev. 0.33 Si3226/7 Si3208/9 TA B L E O F C O N T E N TS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.2. Linefeed Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.3. Line Voltage and Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4. Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.5. Thermal Overload Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4.7. Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.8. Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.9. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.10. Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.11. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.12. Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.13. Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.14. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.15. DC-DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.16. Wideband Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.17. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.18. PCM Interface and Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.19. General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.20. Metallic Loop Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. Pin Descriptions: Si3226/7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6. Pin Descriptions: Si3208/9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 8. Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 9. Package Outline: 40-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 Preliminary Rev. 0.33 3 Si3226/7 Si3208/9 1. Electrical Specifications Table 1. Absolute Maximum Ratings and Thermal Information1 Parameter Operating Temperature Range Storage Temperature Range Thermal Resistance, Typical2 TQFP-64 Symbol Test Condition Value Unit TA -40 to 85 C TSTG -55 to 150 C JA 25 C/W 1.6 W 32 C/W 1.7 W VDD1 - VDD4 -0.5 to 4.0 V VIND -0.3 to 3.6 V -0.5 to 4.0 V Continuous +0.4 to -110 V Pulse < 10 s +0.4 to -118 V 100 mA -0.5 to 4.0 V Continuous +0.4 to -135 V Pulse < 10 s +0.4 to -143 V 100 mA Continuous Power Dissipation3 TQFP-64 PD Thermal Resistance, Typical2 QFN-40 JA Continuous Power Dissipation4 QFN-40 PD TA = 85 C TA = 85 C Si3226/7 Supply Voltage Digital Input Voltage Si3208 Supply Voltage Battery Supply Voltage5 TIP, RING Current VDD VBAT ITIP, IRING Si3209 Supply Voltage VDD High Battery Supply Voltage5 VBAT TIP, RING Current ITIP, IRING Notes: 1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet. 2. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed copper surface of at least equal size and that multiple vias are added to enable heat transfer between the top-side copper surface and a large internal/bottom copper plane. 3. Operation of the Si3226 or Si3227 above 125 C junction temperature may degrade device reliability. 4. Si3208 and Si3209 are equipped with on-chip thermal limiting circuitry that shuts down the circuit when the junction temperature exceeds the thermal shutdown threshold. The thermal shutdown threshold should normally be set to 145 C; when in the ringing state the thermal shutdown may be set to 200 C. For optimal reliability long term operation of the Si3208/Si3209 above 150 C junction temperature should be avoided. 5. The dv/dt of the voltage applied to the VBAT pins must be limited to 10 V/s. 4 Preliminary Rev. 0.33 Si3226/7 Si3208/9 Table 2. Recommended Operating Conditions Parameter Ambient Temperature Symbol Test Condition Min* Typ Max* Unit TA F-grade 0 25 70 o C -40 25 85 oC VDD1-VDD4 3.13 3.3 3.47 V Supply Voltage, Si3208/Si3209 VDD 3.13 3.3 3.47 V Battery Voltage, Si3208 VBAT -9 -- -110 V Battery Voltage, Si3209 VBAT -9 -- -135 V Ambient Temperature TA Supply Voltage, Si3226/7 G-grade *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 C unless otherwise stated. Table 3. 3.3 V Power Supply Characteristics1 (VDD = 3.3 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade) Parameter High Impedance, Reset High Impedance, Open Current Forward/Reverse Sleep, On-hook Current Forward/Reverse Active, On-hook Current Forward/Reverse Active, Off-hook Current Forward/Reverse OHT, On-hook Current Tip/Ring Open, On-hook Current Ringing Current Symbol Test Condition Min Typ Max Unit IDD VT and VR = Hi-Z RST = 0 -- 2.4 -- mA -- 0 -- mA VT and VR = Hi-Z -- 9.7 -- mA -- 0.6 -- mA -- 15 -- mA -- 1.2 -- mA -- 24 -- mA -- 1.2 -- mA -- 43 -- mA IVBAT ILOOP = 30 mA RLOAD = 50 -- 3.1 + ILOOP -- mA IDD VTR = -48 V -- 43 -- mA -- 1.6 -- mA -- 23 -- mA -- 0.6 -- mA -- 26 -- mA -- 2.3 + IAVE -- mA IVBAT IDD IVBAT IDD VTR = -48 V IVBAT IDD VTR = -48 V IVBAT IDD IVBAT IDD IVBAT IDD IVBAT VT or VR = -48 V VR or VT = Hi-Z VTR = 55 VRMS + 0 VDC balanced, sinusoidal, f = 20 Hz RLOAD = 5 REN = 1400 Notes: 1. All specifications are for a single channel of Si3226/7 using Si3208/9 linefeed IC and based on measurements with all channels in the same operating state. 2. ILOOP is the dc current in the subscriber loop during the off-hook state. 3. IAVE is the average of the full-wave rectified current in the subscriber loop during ringing (IAVE = IPEAK x 2/). Preliminary Rev. 0.33 5 Si3226/7 Si3208/9 Table 4. AC Characteristics (VDD = 3.13 to 3.47 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade) Parameter Test Condition Min Typ Max Unit 2.5 Figure 6 -- -- -- -- -- -- -65 VPK -- -- -65 dB Figure 5 -- -- 46 -- -- dB -- -- -41 dB -0.2 -- 0.2 dB TX/RX Performance Overload Level Overload Compression Single Frequency Distortion1 Signal-to-(Noise + Distortion) Ratio2 Audio Tone Generator Signal-toDistortion Ratio2 Intermodulation Distortion Gain Accuracy2 Attenuation Distortion vs. Freq. Group Delay vs. Frequency Gain Tracking3 Round-Trip Group Delay Crosstalk between channels TX or RX to TX TX or RX to RX 2-Wire Return Loss4 Transhybrid Balance4 Idle Channel Noise5 PSRR from VDD1-VDD4 2-Wire - PCM 2-Wire - PCM or PCM - 2-Wire: 200 Hz to 3.4 kHz PCM - 2-Wire - PCM: 200 Hz - 3.4 kHz, 16-bit Linear mode 200 Hz to 3.4 kHz D/A or A/D 8-bit Active off-hook, and OHT, any ZT 0 dBm0, Active off-hook, and OHT, any ZT 2-Wire to PCM or PCM to 2-Wire 1014 Hz, Any gain setting VDD1 - VDD4 = 3.3 V 5% 0 dBm 0 1014 Hz sine wave, reference level -10 dBm Signal level: 3 dB to -37 dB -37 dB to -50 dB -50 dB to -60 dB 1014 Hz, Within same time-slot 0 dBm0, 300 Hz to 3.4 kHz 300 Hz to 3.4 kHz 200 Hz to 3.4 kHz 300 Hz to 3.4 kHz Noise Performance C-Message weighted Psophometric weighted RX and TX, dc to 3.4 kHz dB See AN317 -- -- -- -- -- -- -- -- -- -- -- 450 0.25 0.5 1.0 500 dB dB dB s -- -- 26 26 -- -- 30 30 -75 -75 -- -- dB dB dB dB -- -- 40 8 -80 -- 12 -78 -- dBrnC dBmP dB Notes: 1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be -10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified. 2. Analog signal measured as VTIP - VRING. Assumes ideal line impedance matching. 3. The quantization errors inherent in the /A-law companding process can generate slightly worse gain tracking performance in the signal range of 3 to -37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate. 4. VDD1-VDD4 = 3.3 V, VBAT = -52 V, no fuse resistors; RL = 600 , ZS = 600 synthesized using RS register coefficients. 5. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed -55 dBm. 6 Preliminary Rev. 0.33 Si3226/7 Si3208/9 Table 4. AC Characteristics (Continued) (VDD = 3.13 to 3.47 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade) Parameter Longitudinal to Metallic/PCM Balance (forward or reverse) Metallic/PCM to Longitudinal Balance Longitudinal Impedance Longitudinal Current per Pin DC Current Test Condition Min Typ Max Unit Longitudinal Performance 200 Hz to 1 kHz 1 kHz to 3.4 kHz 200 Hz to 3.4 kHz 58 53 40 60 58 -- -- -- -- dB dB dB 200 Hz to 3.4 kHz at TIP or RING -- 50 -- Active off-hook 200 Hz to 3.4 kHz -- -- 30 mA Differential -- -- 45 mA Common Mode -- -- 30 mA Differential + Common Mode -- -- 45 mA Notes: 1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be -10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified. 2. Analog signal measured as VTIP - VRING. Assumes ideal line impedance matching. 3. The quantization errors inherent in the /A-law companding process can generate slightly worse gain tracking performance in the signal range of 3 to -37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate. 4. VDD1-VDD4 = 3.3 V, VBAT = -52 V, no fuse resistors; RL = 600 , ZS = 600 synthesized using RS register coefficients. 5. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed -55 dBm. Preliminary Rev. 0.33 7 Si3226/7 Si3208/9 Table 5. Linefeed Characteristics (VDD = 3.13 to 3.47 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade) Parameter Symbol Test Condition Min Typ Max Unit RLOOP RDC,MAX = 430 ILOOP = 18 mA, VBAT = -52V -- -- 2000 ILIM = 18 mA -- -- 10 % Active Mode; VOC = 48 V, VTIP - VRING -- -- 4 V RDO ILOOP < ILIM 160 -- 640 DC On-Hook Voltage Accuracy--Ground Start VOHTO IRING<ILIM; VRING wrt ground, VRING = -51 V -- -- 4 V DC Output Resistance--Ground Start RROTO IRING<ILIM; RING to ground 160 -- 640 DC Output Resistance-- Ground Start RTOTO TIP to ground 400 -- -- k Loop Closure Detect Threshold Accuracy ITHR = 13 mA -- -- 10 % Ground Key Detect Threshold Accuracy ITHR = 13 mA -- -- 10 % Ring Trip Threshold Accuracy AC detection, VRING = 70 Vpk, no offset, ITH = 80mA -- -- 4 mA DC detection, 20 V dc offset, ITH = 13 mA -- -- 1 mA DC Detection, 48 V DC offset, Rloop = 1500 -- -- 3 mA Open circuit, VBAT = -110 V 108 -- -- VPK 5 REN load, RLOOP = 0 , VBAT = -110 V, RDO = 160 99 -- -- VPK Open Circuit, VBAT = -135 V 133 -- -- VPK 5 REN load, RLOOP = 0 , VBAT = -130 V, RDO = 160 121 -- -- VPK -- 2 -- % f = 16 Hz to 100 Hz -- -- 1 % Accuracy of ON/OFF times -- -- 50 ms CAL to CAL bit -- -- TBD ms Accuracy of boundaries for each output Code; VTIP - VRING = 48 V -- 2 4 % Maximum Loop Resistance DC Loop Current Accuracy DC Open Circuit Voltage Accuracy DC Differential Output Resistance Ringing Amplitude Sinusoidal Ringing Total Harmonic Distortion Ringing Frequency Accuracy Ringing Cadence Accuracy Calibration Time Loop Voltage Sense Accuracy VRING RTHD *Note: Ringing amplitude is set for 93 V peak and measured at TIP-RING using no series protection resistance. 8 Preliminary Rev. 0.33 Si3226/7 Si3208/9 Table 5. Linefeed Characteristics (Continued) (VDD = 3.13 to 3.47 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade) Parameter Symbol Test Condition Min Typ Max Unit Loop Current Sense Accuracy Accuracy of boundaries for each output code; ILOOP = 18 mA -- 7 10 % Power Alarm Threshold Accuracy Power Threshold = 300 mW -- -- 25 % *Note: Ringing amplitude is set for 93 V peak and measured at TIP-RING using no series protection resistance. Table 6. Monitor ADC Characteristics (VDD = 3.13 to 3.47 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade) Parameter Symbol Test Condition Min Typ Max Unit Differential Nonlinearity (8-bit resolution) DNLE -- -- 1 LSB Integral Nonlinearity (8-bit resolution) INLE -- -- 1 LSB -- -- 5 % Gain Error Table 7. Si3208/Si3209 Characteristics (VDD = 3.13 to 3.47 V, VBAT = -15 to -130 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade) Parameter TIP/RING Pull-down Transistor Saturation Voltage TIP/RING Pull-up Transistor Saturation Voltage OPEN State TIP/RING Leakage Current Symbol Test Condition Min Typ Max Unit VCM VRING - VBAT (Forward) VTIP - VBAT (Reverse) VAC = 2.5 VPK IOUT = 22 mA IOUT = 60 mA 3 3.5 V V GND - VTIP (Forward) GND - VRING (Reverse) VAC = 2.5 VPK IOUT = 22 mA IOUT = 60 mA 3 3.5 V V RL = 0 150 A VOV ILKG Preliminary Rev. 0.33 9 Si3226/7 Si3208/9 Table 8. DC Characteristics (VDD = 3.13 to 3.47 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade) Parameter Symbol High Level Input Voltage Test Condition Min Typ Max Unit VIH 0.7 x VDD -- 5.25 V Low Level Input Voltage VIL -- -- 0.3 x VDD V High Level Output Voltage VOH IO = 4 mA VDD - 0.6 -- -- V Low Level Output Voltage VOL DTX, SDO, INT, SDITHRU: IO = -4 mA -- -- 0.4 V GPIO1 a/b, GPIO2 a/b: IO = -40 mA -- -- 0.72 35 50 -- k SDITHRU internal pullup resistance Relay Driver Source Impedance Relay Driver Sink Impedance ROUT VDD1-VDD4 = 3.13 V IO < 28 mA -- 63 -- RIN VDD1-VDD4 = 3.13 V IO < 85 mA -- 11 -- -- -- 10 A Input Leakage Current IL Table 9. Switching Characteristics--General Inputs1 (VDD = 3.13 to 5.25 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade, CL = 20 pF) Parameter Rise Time, RESET RESET Pulse Width, GCI Mode2,3 RESET Pulse Width, SPI Daisy Chain Mode 3 Symbol Min Typ Max Unit tr -- -- 5 ns trl 33/PCLK -- -- s trl 33/PCLK -- -- s Notes: 1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are VIH = VDD - 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform. 2. The minimum RESET pulse width assumes the SDITHRU pin is tied to ground via a pulldown resistor no greater than 10 k per device. 3. The minimum RESET pulse width is 33/PCLK frequency (i.e. 33/8.192 MHz = 4 s). 10 Preliminary Rev. 0.33 Si3226/7 Si3208/9 Table 10. Switching Characteristics--SPI (VDDA = 3.13 to 5.25 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade, CL = 20 pF) Parameter Symbol Test Conditions Min Typ Max Unit Cycle Time SCLK tc 62 -- -- ns Rise Time, SCLK tr -- -- 25 ns Fall Time, SCLK tf -- -- 25 ns Delay Time, SCLK Fall to SDO Active td1 -- -- 20 ns Delay Time, SCLK Fall to SDO Transition td2 -- -- 20 ns Delay Time, CS Rise to SDO Tri-state td3 -- -- 20 ns Setup Time, CS to SCLK Fall tsu1 25 -- -- ns Hold Time, CS to SCLK Rise th1 20 -- -- ns Setup Time, SDI to SCLK Rise tsu2 25 -- -- ns Hold Time, SDI to SCLK Rise th2 20 -- -- ns Delay Time between Chip Selects tcs 220 -- -- ns SDI to SDITHRU Propagation Delay td4 -- 4 10 ns Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VDDD -0.4 V, VIL = 0.4 V tr tc tf SCLK tsu1 th1 CS tcs tsu2 th2 SDI td1 td3 td2 SDO td4 SDITHRU Figure 1. SPI Timing Diagram Preliminary Rev. 0.33 11 Si3226/7 Si3208/9 Table 11. Switching Characteristics--PCM Highway Interface (VDD = 3.13 to 5.25 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade, CL = 20 pF) Parameter PCLK Period Symbol Test Conditions tp Valid PCLK Inputs Min1 Typ1 Max1 Units 122 -- 3906 ns -- -- -- -- -- -- -- -- 512 768 1.024 1.536 1.544 2.048 4.096 8.192 -- -- -- -- -- -- -- -- kHz kHz MHz MHz MHz MHz MHz MHz FSYNC Period2 tfs -- 125 -- s PCLK Duty Cycle Tolerance tdty 40 50 60 % FSYNC Jitter Tolerance tjitter -- -- 120 ns Rise Time, PCLK tr -- -- 25 ns Fall Time, PCLK tf -- -- 25 ns Delay Time, PCLK Rise to DTX Active td1 -- -- 20 ns Delay Time, PCLK Rise to DTX Transition td2 -- -- 20 ns Delay Time, PCLK Rise to DTX Tristate3 td3 -- -- 20 ns Setup Time, FSYNC to PCLK Fall tsu1 25 -- -- ns Hold Time, FSYNC to PCLK Fall th1 20 -- -- ns Setup Time, DRX to PCLK Fall tsu2 25 -- -- ns Hold Time, DRX to PCLK Fall th2 20 -- -- ns FSYNC Pulse Width twfs tp -- 125 s-tp Notes: 1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH - VI/O - 0.4 V, VIL = 0.4 V. 2. FSYNC source is assumed to be 8 kHz under all operating conditions. 3. Spec applies to PCLK fall to DTX tristate when that mode is selected. 12 Preliminary Rev. 0.33 Si3226/7 Si3208/9 tr tp tf PCLK th1 twfs tsu1 FSYNC tfs tsu2 th2 DRX td1 td2 td3 DTX Figure 2. PCM Highway Interface Timing Diagram Table 12. Switching Characteristics--GCI Highway Serial Interface (VDD = 3.13 to 5.25 V, TA = 0 to 70 C for F-Grade, -40 to 85 C for G-Grade) Parameter1 Symbol Test Conditions Min Typ Max Units PCLK Period (2.048 MHz PCLK Mode) tp -- 488 -- ns PCLK Period (4.096 MHz PCLK Mode) tp -- 244 -- ns tfs -- 125 -- s PCLK Duty Cycle Tolerance tdty 40 50 60 % FSYNC Jitter Tolerance tjitter -- -- 120 ns Rise Time, PCLK tr -- -- 25 ns Fall Time, PCLK tf -- -- 25 ns Delay Time, PCLK Rise to DTX Active td1 -- -- 20 ns Delay Time, PCLK Rise to DTX Transition td2 -- -- 20 ns Delay Time, PCLK Rise to DTX Tristate3 td3 -- -- 20 ns Setup Time, FSYNC Rise to PCLK Fall tsu1 25 -- -- ns Hold Time, PCLK Fall to FSYNC Fall th1 20 -- -- ns Setup Time, DRX Transition to PCLK Fall tsu2 25 -- -- ns Hold Time, PCLK Falling to DRX Transition th2 20 -- -- ns FSYNC Pulse Width twfs tp/2 -- -- ns FSYNC Period 2 Notes: 1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH = VO - 0.4 V and VIL = 0.4 V. Rise and fall times are referenced to the 20% and 80% levels of the waveform. 2. FSYNC source is assumed to be 8 kHz under all operating conditions. 3. Specification applies to PCLK fall to DTX tristate when that mode is selected. Preliminary Rev. 0.33 13 Si3226/7 Si3208/9 tr tp tf PCLK th1 tsu1 tfs FSYNC tsu2 th2 Frame 0, Bit 0 DRX td1 td2 td3 Frame 0, Bit 0 DTX Figure 3. GCI Highway Interface Timing Diagram (2.048 MHz PCLK Mode) tr tf tc PCLK th1 tfs tsu1 FSYNC tsu2 DRX td1 DTX th2 Frame 0, Bit 0 td2 td3 Frame 0, Bit 0 Figure 4. GCI Highway Interface Timing Diagram (4.096 MHz PCLK Mode) 14 Preliminary Rev. 0.33 Si3226/7 Si3208/9 Acceptable Figure 5. Transmit and Receive Path SNDR 9 8 7 6 Fundamental Output Power 5 (dBm0) Acceptable Region 4 3 2.6 2 1 0 1 2 3 4 5 6 7 8 9 Fundamental Input Power (dBm0) Figure 6. Overload Compression Performance Preliminary Rev. 0.33 15 SDCH SDCL VOUT PCLK FSYNC DTX DRX VBATa R16 GND VCC x GND GND Preliminary Rev. 0.33 VCC /RESET /INT PCM MODE GCI MODE - 2x PCLK (4.096 MHz) R15 10K SDCH SDCL DCFF DCDRV VIN R19 10K R16 10K 1% VOUT VCC_JUMPER 825K R200 DCDC SVBATb SDCHb SDCLb DCFFb DCDRVb GCI MODE - 1x PCLK (2.048 MHz) MODE SELECT PCM MODE SELECT SCLK /CS SDO SDI SDITHRU R15 SPI BUS PCM BUS 825K R100 1% DCDC SVBATa SDCHa SDCLa GND DCFF DCDRV VIN GND DCFFa DCDRVa GPIO1b GPIO2b GPIO1a GPIO2a C8 49.9K R2 R13 10K 10% 4.7nF VBATb 0.5% VCC SVDC GPIO1b/STIPCb GPIO2b/SRINGCb C3 C7 0.1uF CAPMb CAPPb DCDRVb DCFFb SDCHb SDCLb SVBATb UTIPb DTIPb URINGb DRINGb STIPACb SRINGACb STIPDCb SRINGDCb IBIASb PWROb HVDATA HVCLKa HVCLKb ISNS CAPMa CAPPa DCDRVa DCFFa SDCHa SDCLa SVBATa UTIPa DTIPa URINGa DRINGa STIPACa SRINGACa STIPDCa SRINGDCa IBIASa PWROa VDDREG L1 10uF 10uF C1 C200 0.1uF 10% 0.1uF C4 C5 DCDRVb DCFFb SDCHb SDCLb SVBATb C100 10% 0.1uF C6 10uF C2 0.1uF VDDA VDDC VDDD DC/DC Converter B DC/DC Converter A 0.1uF DCDRVa DCFFa SDCHa SDCLa SVBATa 10uH 180mA Figure 7. Si3226/7 (2 Lines) RESETB INTB CAPLB VCC SI3226 GPIO1a/STIPCa GPIO2a/SRINGCa IREF QGND SCLK CSB SDO SDI SDITHRU DTXENB PCLK FSYNC DTX DRX R17 137K 1% VIN VDDC VDDC DCDC2 TIPa RINGa UTIPb DTIPb URINGb DRINGb STIPACb SRINGACb STIPDCb SRINGDCb IBIASb HVDATA HVCLKa HVCLKb ISNS TIPb RINGb LINE INTERFACE UTIPa DTIPa URINGa DRINGa STIPACa SRINGACa STIPDCa SRINGDCa IBIASa LFI VBATa DC/DC Converter B VCC VCC VIN VBATb VBATa DCDC1 GNDA VBATa Protection TIP RING Protection TIP RING VBAT DC/DC Converter A VDDD VDDA VDDD VDDA GNDD PROT1 GPIO1a PROT2 GPIO1b GPIO2a TIP_ext RING _ext VBATb GPIO2b TIP_ext RING _ext VBAT VBATb GND VBRNG VBRNG EGND VBRNG VBRNG 16 EGND VIN 1.58M R206 R207 1.58M 1.58M R107 1.58M R106 6 5 4 3 2 1 6 5 4 3 2 1 J1 RJ-11 6 5 4 3 2 1 J2 RJ-11 6 5 4 3 2 1 Si3226/7 Si3208/9 2. Typical Application Circuits Preliminary Rev. 0.33 R125 R124 C128 C127 R123 2 5 Vin Notes: 1) Component values and ratings are shown in the bill of materials. 2) Vin and Vout are defined in the bill of materials. GND SDCL SDCH DCDRV Vin 4 3 6 1 MOSFET DRIVER Q121A Q121B R126 C121 R121 Q120 L120 C122 Figure 8. DC-DC Converter (A) C126 C120 D121 D122 C123 R127 + Vin C124 R122 C125 VOUT Si3226/7 Si3208/9 17 Preliminary Rev. 0.33 R225 R224 C228 C227 R223 2 5 Vin Notes: 1) Component values and ratings are shown in the bill of materials. 2) Vin and Vout are defined in the bill of materials. GND SDCL SDCH DCDRV Vin 4 3 6 18 1 MOSFET DRIVER Q221A Q221B R226 C221 R221 Q220 L220 C222 Figure 9. DC-DC Converter (B) C226 C220 D221 D222 C223 R22 R227 + Vin C224 R222 C225 VOUT Si3226/7 Si3208/9 Preliminary Rev. 0.33 STIPDCb SRINGDCb STIPACb SRINGACb TIPb RINGb TIPa RINGa SRINGACa STIPACa SRINGDCa 10% C203 10nF 10% C204 10nF 10% 10% 10nF C104 10nF C103 R201 681K R202 681K 590K R205 681K R102 R105 590K 10% 10% R203 301K R204 301K 301K R104 301K R103 C201 10nF C202 10nF 10% C102 10nF HW PCB3 HW_epad TIP_2 RING_2 TIP_1 RING_1 U100 SI3208 Si3208/QFN32 HVDATA HVCLK_1 HVCLK_2 ISNS ITIPP_2 ITIPN_2 IRINGP_2 IRINGN_2 IBIAS_2 ITIPP_1 ITIPN_1 IRINGP_1 IRINGN_1 IBIAS_1 0.1uF C107 VCC All Resistors are 1% unless otherwise noted. Figure 10. Linefeed (2 Lines) C101 10nF VBATb VBAT_2 10% VBATa 681K AGND VBAT_1 R101 VDD DGND STIPDCa 0.1uF VBATa HVDATA HVCLKa HVCLKb ISNS UTIPb DTIPb URINGb DRINGb IBIASb UTIPa DTIPa URINGa DRINGa IBIASa C105 VBATb VBATb GND VBATa VBATa VCC Global Port Connections C205 VCC 0.1uF VBATb Si3208 VBAT decoupling Si3226/7 Si3208/9 19 20 Preliminary Rev. 0.33 C1, C6 C100, C200 C2, C4, C5, C7 C3* C8 L1* R2 R13, R15, R16, R19 R17 R100, R200 R106*, R107*, R206*, R207* U1 2 2 4 1 1 1 1 4 1 2 4 1 *Note: Denotes optional component. Reference Quantity Si3226 1.58 M 825 k 137 k 10 k 49.9 k 10 H 4.7 nF 10F 0.1F 0.1 F 10 F Value Table 13. Bill of Materials for Si3226/7 (2 Lines) 3. Bill of Materials 1/10 W, 100 V 1/10 W, 100 V 1/16 W 1/10 W 1/16 W 180 mA 6.3 V 6.3 V 6.3 V 6.3 V 6.3 V Rating 5% 1% 1% 5% 0.5% 10% 10% 20% 20% 10% 20% Tolerance X7R Y5V X7R X7R Y5V Dielectric TQFP64 RC0805 RC0805 RC0603 RC0603 RC0603 IND-NLC3225 CC0603 CC1210 CC0603 CC0603 CC1210 PCB Footprint SiLabs Venkel Venkel Venkel Venkel Venkel TDK Venkel Venkel Venkel Venkel Venkel Manufacturer Si3226/7 Si3208/9 Preliminary Rev. 0.33 Q121, Q221 R121, R221 R122, R222 R123, R223 R124, R224 R125, R225 R126, R226 R127, R227 C107 2 2 2 2 2 2 2 2 1 *Note: Denotes optional component. Q120, Q220 2 C123, C223 2 L120, L220 C122, C222 2 2 C125*, C225* 2 D121, D221 C124, C224 2 2 C126, C226 2 D122, D222 C121, C221 2 2 C220* 1 C127, C128, C227, C228 C120 1 4 Reference Quantity VIN = +12 V nominal, |Vout| < 90 V 25 V 1/8 W 2 0.1 F 1/16 W 1/16 W 1/16 W 100 k 150 k 1 k 1/16 W 220 10% 5% 5% 5% 5% 5% CC0603 RC0402 RC0402 RC0402 RC0402 RC0402 RC1206 1/4 W 15 5% RC1210 SOT-223 CDR74 DO-214AC SOD-323 CC0402 C2.5X6.3MM-RAD CC1812 CC1210 CC1210 CC0603 CC0603 CC1210 CC1210 PCB Footprint 1/4 W X7R X7R Al X7R X7R X7R X7R X7R X7R X7R Dielectric 0.1 1% 10% 20% 20% 20% 20% 20% 10% 20% 20% Tolerance SOT-363 100 V, 2 W 150 V, 2.0 A 250 V,200 mA 25 V 100 V 100 V 100 V 100 V 25 V 25 V 25 V 25 V Rating MMDT3946 FQT7N10 15 H STPS2150A BAS21HT1 470 pF 3.3 F 0.22 F 0.1 F 0.1 F 0.1 F 0.1 F 10 F 10 F Value Table 14. Bill of Materials for Linefeed and DC-DC Converters with |VOUT| < 90 V (2 Lines) Venkel Venkel Venkel Venkel Venkel Venkel Venkel Venkel Diodes Inc. Fairchild SUMIDA STMicro ON SEMI Venkel Panasonic Venkel Venkel Venkel Venkel Venkel Venkel Venkel Manufacturer Si3226/7 Si3208/9 21 22 C101, C102, C201, C202 C103, C104, C203, C204 C105, C205 R101, R102, R201, R202 R103, R104, R203, R204 R105, R205 U100 4 4 2 4 4 2 1 *Note: Denotes optional component. Reference Quantity VIN = +12 V nominal, |Vout| < 90 V Si3208 or Si3209 590 k 301 k 681 k 0.1 F 10 nF 10 nF Value 1/10 W, 150 V 1/16 W, 75 V 1/10 W, 150 V 100 V 100 V 100 V Rating 1% 1% 1% 20% 10% 10% Tolerance X7R X7R X7R Dielectric QFN-40 RC0805 RC0603 RC0805 CC1210 CC0805 CC0805 PCB Footprint Table 14. Bill of Materials for Linefeed and DC-DC Converters with |VOUT| < 90 V (2 Lines) (Continued) Silicon Laboratories Venkel Venkel Venkel Venkel Venkel Venkel Manufacturer Si3226/7 Si3208/9 Preliminary Rev. 0.33 Preliminary Rev. 0.33 Q121, Q221 R121, R221 R122, R222 R123, R223 R124, R224 R125, R225 R126, R226 R127, R227 C107 2 2 2 2 2 2 2 2 1 *Note: Denotes optional component. Q120, Q220 2 C123,C223 2 L120, L220 C122,C222 2 2 C125*,C225* 2 D121, D221 C124,C224 2 2 C126,C226 2 D122, D222 C121,C221 2 2 C220* 1 C127, C128, C227, C228 C120 1 4 Reference Quantity VIN = +12 V nominal, |Vout| < 135 V 25 V 1/8 W 2 0.1 F 1/16 W 1/16 W 1/16 W 100 k 150 k 1 k 1/16 W 220 10% 5% 5% 5% 5% 5% CC0603 RC0402 RC0402 RC0402 RC0402 RC0402 RC1206 1/4 W 15 5% RC1210 D-PAK CDRH125 DO-214AC SOD-323 CC0402 C2.5X6.3MM-RAD CC1812 CC1210 CC1210 CC0603 CC0603 CC1210 CC1210 PCB Footprint 1/4 W X7R X7R Al X7R X7R X7R X7R X7R X7R X7R Dielectric 0.1 1% 10% 20% 20% 20% 20% 20% 10% 20% 20% Tolerance SOT-363 200 V, 2.5 W 150 V, 2.0 A 250 V,200 mA 25 V 160 V 200 V 200 V 200 V 25 V 25 V 25 V 25 V Rating MMDT3946 FQD7N20L 15 H STPS2150A BAS21HT1 470 pF 3.3 F 0.22 F 0.1 F 0.1 F 0.1 F 0.1 F 10 F 10 F Value Table 15. Bill of Materials for Linefeed and DC-DC Converters with |VOUT| < 135 V (2 Lines) Venkel Venkel Venkel Venkel Venkel Venkel Venkel Venkel Diodes Inc. Fairchild SUMIDA STMicro ON SEMI Venkel Panasonic Venkel Venkel Venkel Venkel Venkel Venkel Venkel Manufacturer Si3226/7 Si3208/9 23 24 C101, C102, C201, C202 C103, C104, C203, C204 C105, C205 R101, R102, R201, R202 R103, R104, R203, R204 R105, R205 U100 4 4 2 4 4 2 1 *Note: Denotes optional component. Reference Quantity VIN = +12 V nominal, |Vout| < 135 V Si3209 590 k 301 k 681 k 0.1 F 10 nF 10 nF Value 1/10 W, 150 V 1/16 W, 75 V 1/10 W, 150 V 200 V 100 V 200 V Rating 1% 1% 1% 20% 10% 10% Tolerance X7R X7R X7R Dielectric QFN-40 RC0805 RC0603 RC0805 CC1210 CC0805 CC0805 PCB Footprint Venkel Venkel Venkel Venkel Venkel Venkel Manufacturer Silicon Laboratories Table 15. Bill of Materials for Linefeed and DC-DC Converters with |VOUT| < 135 V (2 Lines) (Continued) Si3226/7 Si3208/9 Preliminary Rev. 0.33 Si3226/7 Si3208/9 The Dual ProSLIC(R) chipset includes the Si3226/7 lowvoltage IC and the Si3208/9 high-voltage linefeed IC. The Dual ProSLIC provides all SLIC, codec, DTMF detection, and signal generation functions needed for two complete analog telephone interfaces. The Dual ProSLIC performs all battery, over-voltage, ringing, supervision, codec, hybrid, and test (BORSCHT) functions; it also supports extensive metallic loop testing capabilities. The Si3226 provides a standard voice-band (200 Hz- 3.4 kHz) audio codec. The Si3227 provides an audio CODEC with both wideband (50 Hz-7 kHz) and standard voice-band (200 Hz- 3.4 kHz) modes. The wideband mode provides an expanded audio band with a 16 kHz sample rate for enhanced audio quality while the standard voice-band mode provides standard telephony audio compatibility. The Si3226/7 provides two independent, programmable, dc-dc converter controllers, each of which reacts to line conditions to provide the optimal battery voltage required for each line-state. The linefeed chips (Si3208/9) provide programmable on-hook voltage, programmable off-hook loop current, reverse battery operation, loop or ground start operation, and on-hook transmission. Loop current and voltage are continuously monitored using an A/D converter in the Si3226/7. The Si3208 supports battery voltages up to 110 V, sufficient for most ringing signals. The Si3209 supports battery voltages up to 130 V for higher-voltage ringing applications. The Dual ProSLIC supports balanced 5 REN ringing with or without a programmable dc offset. The available offset, frequency, waveshape, and cadence options are designed to ring the widest variety of terminal devices and to reduce external controller requirements. A complete audio transmit and receive path is integrated, including ac impedance and hybrid gain. These features are software-programmable, allowing a single hardware design to meet global requirements. Digital voice data transfer occurs over a standard PCM bus. Control data is transferred using a standard SPI. The Si3226/7 is available in a 64-pin TQFP; the Si3208 is available in a 32-pin QFN, and the Si3209 is available in a 40-pin QFN or a 48-pin eTQFP. 4.1. DC Feed Characteristics Dual ProSLIC internal linefeed circuitry provides completely programmable dc feed characteristics. Linefeed characteristics for each channel are independently configurable. When in the active state, each ProSLIC channel operates in one of three dc linefeed operating regions: a constant-voltage region, a constant-current region, or a resistive region, as shown in Figure 11. The constantvoltage region has a low resistance, typically 160 . The constant-current region approximates infinite resistance. I_VLIM I_RFEED I_ILIM I LOOP (mA) Constant I Region 4. Functional Description V_ILIM Resistive Region V_RFEED V_VLIM Constant V Region V TR(V) Figure 11. Dual ProSLIC DC Feed Characteristics 4.2. Linefeed Operating States The linefeed interface includes eight different registerprogrammable operating states as listed in Table 16. The Open state is the default condition in the absence of any preloaded register settings. The device may also automatically enter the open state in the event of a linefeed fault condition. 4.3. Line Voltage and Current Monitoring The Dual ProSLIC continuously monitors the TIP, RING, and battery voltages and currents via an on-chip ADC and stores the resulting values in individual register addresses. Additionally, the loop voltage (VTIP-VRING), loop current, and longitudinal current values are calculated based on the TIP and RING measurements and are stored in unique register locations for further processing. The ADC updates all registers at a rate of 2 kHz or greater. 4.4. Power Monitoring and Power Fault Detection The Dual ProSLIC's line monitoring functions are used to continuously protect the linefeed IC (LFIC) against excessive power conditions. The LFIC contains an onchip, analog sensing diode that provides real-time temperature data to the Si3226/7 and turns off the LFIC when a preset threshold is exceeded. The LFIC status is reflected in a Si3226/7 register bit. Preliminary Rev. 0.33 25 Si3226/7 Si3208/9 If the Si3226/7 detects a fault condition or overpower condition on any channel, it automatically sets that channel to the open state and generates a "power alarm" interrupt. The interrupt can be masked, but the automatic transition to open cannot be masked. The various power alarms and linefeed faults supporting automatic intervention are described below. 1. LFIC total power exceeded. 2. Power exceeded in one or more transistors of a LFIC internal transistor group (if capable of measuring individual power consumption). 4.5. Thermal Overload Shutdown If the LFIC die temperature exceeds the maximum junction temperature threshold, TJmax, of 145 C or 200 C or other programmed temperature threshold range, the LFIC has the ability to shut itself down to a low-power state without any assistance from the Si3226/7. The thermal shutdown circuit contains a sufficient amount of hysteresis and/or turn-on delay time so as to remain shut down during a power cross event, where 50 Hz or 60 Hz, 600 V, is connected to TIP and/ or RING. 3. Excessive foreign current or voltage on TIP and/or RING. 4. LFIC thermal shutdown event; this event is automatically performed, and no intervention by the Si3226/7 is required. Table 16. Linefeed Operating States Linefeed State Description Open Output is high-impedance, and all line supervision functions are powered down. Audio is powered down. This is the default state after powerup or following a hardware reset. This state can also be used in the presence of line fault conditions and to generate open switch intervals (OSIs). This state is used in line diagnostics mode as a high-Z state during linefeed testing. A power fault condition may also force the device into the open state. Forward Active Reverse Active Linefeed circuitry and audio are active. In Forward Active state, the TIP lead is more positive than the RING lead; in Reverse Active state, the RING lead is more positive than the TIP lead. Loop closure and ground key detect circuitry are active. Forward OHT Reverse OHT Provides data transmission during an on-hook loop condition (e.g., transmitting caller ID data between ringing bursts). Linefeed circuitry and audio are active. In Forward OHT state, the TIP lead is more positive than the RING lead; in Reverse OHT state, the RING lead is more positive than the TIP lead. TIP Open Provides an active linefeed on the RING lead and sets the TIP lead to high impedance (>400 k) for ground start operation in forward polarity. Loop closure and ground key detect circuitry are active. RING Open Provides an active linefeed on the TIP lead and sets the RING lead to high impedance (>400 k) for ground start operation in reverse polarity. Loop closure and ground key detect circuitry are active. Ringing Drives programmable ringing signal onto TIP and RING leads with or without dc offset. Line Diagnostics The channel selected is put into diagnostic mode. In this mode, the selected channel has special diagnostic resources available. 4.6. Power Dissipation Considerations 4.7. Loop Closure Detection The Dual ProSLIC is designed to source loops up to 20 kft as well as short loop applications. The LFIC provides all battery sourcing functions and is, therefore, the determining factor regarding power dissipation in a specific application. The Dual ProSLIC provides an onchip dc-dc controller that can dynamically reduce the battery supply to ideally match the required line feed voltage. The Dual ProSLIC provides a completely programmable loop closure detection mechanism. The loop closure detection scheme provides two unique thresholds to allow hysteresis, and also includes a programmable debounce filter to eliminate false detection. A loop closure detect status bit provides continuous status, and a maskable interrupt bit is also provided. 26 Preliminary Rev. 0.33 Si3226/7 Si3208/9 4.8. Ground Key Detection 4.13. Tone Generators The Dual ProSLIC provides a ground key detect mechanism using a programmable architecture similar to the loop closure scheme. The ground key detect scheme provides two unique thresholds to allow hysteresis and also includes a programmable debounce filter to eliminate false detection. A ground key detect status bit provides continuous status, and a maskable interrupt bit is also provided. The Dual ProSLIC includes two digital tone generators that allow a wide variety of single- or dual-tone frequency and amplitude combinations. Each tone generator has its own set of registers that hold the desired frequency, amplitude, and cadence to allow generation of DTMF and call progress tones for different requirements. The tones can be directed to either receive or transmit paths. 4.9. Ringing Generation 4.14. DTMF Detection The Dual ProSLIC provides the ability to generate a programmable sinusoidal or trapezoidal ringing waveform, with or without dc offset. The ringing frequency, wave shape, cadence, and offset are all register-programmable. Using a balanced ringing scheme, the ringing signal is applied to both the TIP and RING leads using dual ringing waveforms that are 180 out of phase with each other. The resulting ringing signal seen across TIP-RING is twice the amplitude of the ringing waveform on either the TIP or RING lead, which allows the ringing circuitry to be forced to withstand only half the total ringing amplitude seen across TIP-RING. In DTMF, two tones generate a DTMF digit. One tone is chosen from the four possible row tones, and one tone is chosen from the four possible column tones. The sum of these tones constitutes one of 16 possible DTMF digits. The Dual ProSLIC performs DTMF detection using an algorithm to compute the DFT for each of the eight DTMF frequencies and their second harmonics. At the end of the DFT computation, the squared magnitudes of the DFT results for the 8 DTMF fundamental tones are computed. The row and column results are sorted to determine the strongest tones, and checks are made to determine if the strongest row and column tones constitute a DTMF digit. 4.10. Polarity Reversal 4.15. DC-DC Controller The Dual ProSLIC supports polarity reversal for message waiting and various other signaling modes. The ramp rate can be programmed for a smooth or abrupt transition to accommodate different application requirements. The controller converts a single positive dc input voltage into an independent negative battery voltage for each channel. The controller operates a dc-dc converter circuit that converts a single positive dc input voltage into an independent negative battery voltage for each channel. In addition to eliminating external high-voltage power supplies, the dc-dc controller allows the Dual ProSLIC to dynamically control the battery voltage to the minimum required for any given operating state according to the programmed linefeed parameters. 4.11. Two-Wire Impedance Synthesis The ac two-wire impedance synthesis is generated onchip using a DSP-based scheme to optimally match the output impedance of the Dual ProSLIC to the impedance of the subscriber loop and minimize the receive path signal reflected back onto the transmit path. Most real or complex two-wire impedances can be generated by using the coefficient generator software to simulate the desired line conditions and generate the required register coefficients. 4.12. Transhybrid Balance Filter The trans-hybrid balance function is implemented onchip using a DSP-based scheme to effectively cancel the reflected receive path signal from the transmit path. The coefficient generator software is used to optimize the filter coefficients. 4.16. Wideband Audio The Si3226 supports a narrowband (200 Hz-3.4 kHz) audio codec. The Si3227 supports a softwareselectable wideband (50 Hz-7 kHz) and narrowband (200 Hz-3.4 kHz) audio codec. The Si3227 wideband mode provides an expanded audio band at a 16-bit, 16 kHz sample rate for enhanced audio quality while maintaining standard telephony audio compatibility. Wideband audio samples are transmitted and received on the PCM interface using two consecutive 8 kHz frames. Preliminary Rev. 0.33 27 Si3226/7 Si3208/9 4.17. SPI Control Interface 4.20. Metallic Loop Testing The controller interface to the Dual ProSLIC is a 4-wire interface modeled after microcontroller and serial peripheral devices. The interface consists of a clock (SCLK), chip select (CS), serial data input (SDI), and serial data output (SDO). In addition, the Dual ProSLIC devices feature a serial data through output (SDITHRU) to support operation of up to eight devices (up to 16 channels) using a single chip select line. The device operates with both 8-bit and 16-bit SPI controllers. The Dual ProSLIC includes the ability to detect multiple fault conditions within the line card as well as on the T/R pair. 4.18. PCM Interface and Companding The Dual ProSLIC contains a flexible, programmable interface for the transmission and reception of digital PCM samples. PCM data transfer is controlled by the PCM clock (PCLK) and frame sync (FSYNC) inputs as well as the PCM Mode Select, PCM Transmit Start, and PCM Receive Start settings. The interface can be configured to support from four to 128 8-bit time slots in each 125 s frame, corresponding to a PCM clock (PCLK) frequency range of 256 kHz to 8.192 MHz. 1.544 MHz is also supported. The Dual ProSLIC supports both -255 Law (-Law) and A-law companding formats in addition to 16-bit linear data mode with no companding. 4.19. General Circuit Interface The Dual ProSLIC supports an alternative communication interface to the SPI and PCM control and data interface. The General Circuit Interface (GCI) is used for transmission and reception of both control and data information onto a GCI bus. The PCM and GCI interfaces are both 4-wire interfaces and share the same pins. In GCI mode, the four-wire SPI control interface is used as hard-wired channel selector pins. The selection between PCM and GCI modes is performed when coming out of reset using the SDITHRU pin. 1. Hazardous Potential Test--This test checks for ac voltage >50 Vrms or dc voltage >135 V on T-G or RG. If a hazardous voltage is encountered, test access MUST release within two seconds of the time when it was initiated using a preset threshold. 2. Foreign ElectroMotive Force Test--Checks T-G or R-G for ac voltage >10 Vrms, dc voltage >6 V. Uses same threshold as for hazardous voltage test. 3. Resistive Faults Test--Checks for dc resistance from T-R, T-G or R-G. Any measurement <150 k is considered a resistive fault. 4. Receiver-Off-Hook Test--Distinguishes between a T-R resistive fault and an off-hook condition. 5. Ringers Test--Checks for the presence of REN across T-R. Result are >0.175REN and <5REN for a valid load. 6. AC Line Impedance (line length)--T-R, T-G, and R-G. Generate a tone at several specific frequencies (audio band) and measure the reflected signal amplitude (complex spectrum) that comes back (with transhybrid balance filter disabled). The reflected signal is then used to calculate the line impedance based on certain assumptions of wire gauge, etc. 7. Line Capacitance--T-R, T-G, R-G. Generate a linear ramp function with polarity reversal, and measure the time constant. 8. Ringer Capacitance--This test uses the same procedure as the ringer test above but also measures the V/I phase relationship of the received signal (dc path) and then subtracts the delay to calculate the ringer capacitance. 9. Ringing Voltage Verification--Uses current voltage sensing capability. 10.Test-In Diagnostics--The Dual ProSLIC can switch in a preset load impedance to test the SLIC/codec functionality using a known set of conditions. 28 Preliminary Rev. 0.33 Si3226/7 Si3208/9 5. Pin Descriptions: Si3226/7 Table 17. Si3226/7 Pin Descriptions Pin Number Symbol I/O Description 1 SRINGDCa I RING DC Sense Input. 2 SRINGACa I RING AC Sense Input. 3 STIPACa I TIP AC Sense Input. 4 STIPDCa I TIP DC Sense Input. 5 CAPPa I/O Metallic Loop Filter Capacitor-Positive Terminal. 6 CAPMa I/O Metallic Loop Filter Capacitor-Negative Terminal. 7 SVBATa I Battery Sensing Input. 8 SVDC I DC-DC Input Power Rail Sensor. 9 GPIO3a / PWROa I/O General Purpose I/O / Power Offloading Output. 10 GPIO2a / SRINGCa / TRD2a I/O General Purpose I/O / TIP Course Sense Input / Test Relay Driver. 11 GPIO1a / STIPCa / TRD1a I/O General Purpose I/O / TIP Course Sense Input / Test Relay Driver. 12 CS I Chip Select Input. 13 FSYNC I Frame Sync Clock Input. 14 SDI I Serial Port Data Input. 15 HVCLKa O Line-Driver IC Clock Output. 16 SCLK I Serial Port Bit Clock Input. 17 HVDATA O Line-Driver IC Data Output 18 SDITHRU O Serial Data Daisy Chain Output. 19 SDO O Serial Port Data Output. 20 DCFFa I/O DC-DC BJT Drive Monitor. 21 SDCHa I DC-DC Current Monitor Input-High Terminal. 22 SDCLa I DC-DC Current Monitor Input-Low Terminal. 23 DCDRVa I/O 24 VDDC PWR 25 DCDRVb O DC-DC Drive Output. 26 SDCLb I DC-DC Current Monitor Input-Low Terminal. 27 SDCHb I DC-DC Current Monitor Input-High Terminal. 28 DCFFb I/O 29 GNDD GND Digital Ground. 30 VDDD PWR Digital Supply Voltage. 31 PCLK I PCM Bus Clock Input. 32 HVCLKb O Line-Driver IC Clock Output. DC-DC Drive Output. DC-DC Switch Driver Power Supply. DC-DC BJT Drive Monitor. Preliminary Rev. 0.33 29 Si3226/7 Si3208/9 Table 17. Si3226/7 Pin Descriptions (Continued) Pin Number Symbol I/O 33 DTXEN O Transmit PCM Enable Output. 34 DTX O Transmit PCM Data Output. 35 DRX I Receive PCM Data Input. 36 INT O Interrupt Output. 37 RST I Reset Input. 38 VDDREG I/O Regulated Core Power Supply. 39 GPIO1b / STIPCb / TRD1b I/O General Purpose I/O / TIP Course Sense Input / Test Relay Driver. 40 GPIO2b / SRINGCb / TRD2b I/O General Purpose I/O / TIP Course Sense Input / Test Relay Driver. 41 GPIO3b / PWROb I/O General Purpose I/O / Power Offloading Output. 42 SVBATb I 43 CAPMb I/O Differential Loop Filter Capacitor-Negative Term. 44 CAPPb I/O Differential Loop Filter Capacitor-Positive Term. 45 STIPDCb I TIP DC Sense Input. 46 STIPACb I TIP AC Sense Input. 47 SRINGACb I RING AC Sense Input. 48 SRINGDCb I RING DC Sense Input. 49 DRINGb O RING Pull-Down Current Driver Output. 50 URINGb O RING Pull-Up Current Driver Output. 51 DTIPb O TIP Pull-Down Current Driver Output. 52 UTIPb O TIP Pull-Up Current Driver Output. 53 IBIASb O Line Driver IC Bias Current Output. 54 CAPLB O Longitudinal Balance Calibration Capacitor. 55 IREF I Current Reference Input. 56 QGND I Quiet Ground Reference Input. 57 GNDA GND Analog Ground. 58 VDDA PWR Analog Supply Voltage. 59 ISNS I/O Line Current Sense Input. 60 IBIASa O Line Driver IC Bias Current Output. 61 UTIPa O TIP Pull-Up Current Driver Output. 62 DTIPa O TIP Pull-Down Current Driver Output. 63 URINGa O RING Pull-Up Current Driver Output. 64 DRINGa O RING Pull-Down Current Driver Output. 30 Description Battery Sensing Input. Preliminary Rev. 0.33 Si3226/7 Si3208/9 6. Pin Descriptions: Si3208/9 Table 18. Si3208/9 Pin Descriptions QFN Pin # Symbol I/O 1 IC Internal connection; leave to float. 2 NC No Connect. 3 RING_1 4 NC 5 TIP_1 6 NC No Connect. 7 IC Internal connection; leave to float. 8 IRINGN_1 I Negative Ring Current Control Channel 1 Input. 9 IRINGP_1 I Positive Ring Current Control Channel 1 Input. 10 ITIPN_1 I Negative Tip Current Control Channel 1 Input. 11 ITIPP_1 I Positive Tip Current Control Channel 1 Input. 12 IBIAS_1 I Current Bias Channel 1 Input. 13 ISNS O Current Sense Output. 14 VDD I IC Supply Voltage Input. 15 HVCLK_1 I High-Voltage IC Clock Channel 1 Input. 16 HVDATA I/O 17 HVCLK_2 I High-Voltage IC Clock Channel 2 Input. 18 DGND I Digital Ground. 19 IBIAS_2 I Current Bias Channel 2 Input. 20 ITIPP_2 I Positive Tip Current Control Channel 1 Input. 21 ITIPN_2 I Negative Tip Current Control Channel 2 Input. 22 IRINGP_2 I Positive Ring Current Control Channel 2 Input. 23 IRINGN_2 I Negative Ring Current Control Channel 2 Input. 24 IC Internal connection; leave to float. 25 NC No Connect. 26 TIP_2 27 NC 28 RING_2 29 NC No Connect. 30 IC Internal connection; leave to float. 31 IC Internal connection; leave to float. 32 VBAT_2 33 NC No Connect. 34 IC Internal connection; leave to float. I/O Description Ring Channel 1 Input/Output. No Connect. I/O I/O Tip Channel 1 Input/Output. High-Voltage IC Data Input/Output. Tip Channel 2 Input/Output. No Connect. I/O I Ring Channel 2 Input/Output. Operating Battery Voltage Channel 2 Input. Preliminary Rev. 0.33 31 Si3226/7 Si3208/9 Table 18. Si3208/9 Pin Descriptions (Continued) QFN Pin # Symbol 35 NC 36 AGND 37 IC Internal connection; leave to float. 38 IC Internal connection; leave to float. 39 VBAT_1 40 IC epad 32 I/O Description No Connect. I I Analog Ground. Operating Battery Voltage Channel 1 Input. Internal connection; leave to float. Exposed Die Attach Paddle. For adequate thermal management, the exposed die paddle should be soldered to a printed circuit board pad that is connected to an electrically-isolated low-impedance inner layer and/or backside thermal plane(s) using multiple thermal vias. Do not connect this pad to ground. Preliminary Rev. 0.33 Si3226/7 Si3208/9 7. Ordering Guide Device Description Wideband Audio Package Temp Range Si3226-X-FQ Dual ProSLIC No TQFP-64 0 to 70 C Si3226-X-GQ Dual ProSLIC No TQFP-64 -40 to 85 C Si3227-X-FQ Dual ProSLIC Yes TQFP-64 0 to 70 C Si3227-X-GQ Dual ProSLIC Yes TQFP-64 -40 to 85 C Si3208-X-FM 110 V Dual LFIC -- QFN-40 0 to 70 C Si3208-X-GM 110 V Dual LFIC -- QFN-40 -40 to 85 C Si3209-X-FM 135 V Dual LFIC -- QFN-40 0 to 70 C Si3209-X-GM 135 V Dual LFIC -- QFN-40 -40 to 85 C Notes: 1. All devices are lead-free and RoHS compliant. 2. "X" denotes product revision (A, B, C, etc.). 3. Add an R at the end of the device to denote tape and reel options. Preliminary Rev. 0.33 33 Si3226/7 Si3208/9 8. Package Outline: 64-Pin TQFP Figure 12 illustrates the package details for the Si3226/7. Table 19 lists the values for the dimensions shown in the illustration. Figure 12. 64-Pin Thin Quad Flat Package (TQFP) 34 Preliminary Rev. 0.33 Si3226/7 Si3208/9 Table 19. 64-Pin TQFP Package Dimensions Dimension Min Nom Max A -- -- 1.20 A1 0.05 -- 0.15 A2 0.95 1.00 1.05 b 0.17 0.22 0.27 c 0.09 -- 0.20 D 12.00 BSC. D1 10.00 BSC. e 0.50 BSC. E 12.00 BSC. E1 10.00 BSC. L 0.45 0.60 0.75 aaa -- -- 0.20 bbb -- -- 0.20 ccc -- -- 0.08 ddd -- -- 0.08 Q 0 3.5 7 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. This package outline conforms to JEDEC MS-026, variant ACD. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for small body components. Preliminary Rev. 0.33 35 Si3226/7 Si3208/9 9. Package Outline: 40-Pin QFN Figure 13 illustrates the package details for the Si3208/9. Table 20 lists the values for the dimensions shown in the illustration. Figure 13. 40-Pin QFN Package Table 20. 40-Pin QFN Package Dimensions Dimension Min Nom Max Dimension Min Nom Max A 0.80 0.90 1.00 E2 4.10 4.30 4.40 A1 0.00 0.02 0.05 L 0.30 0.40 0.50 b 0.18 0.25 0.30 L1 0.03 0.05 0.08 aaa -- -- 0.10 bbb -- -- 0.10 D D2 6.00 BSC. 4.10 4.30 4.40 e 0.50 BSC. ccc -- -- 0.08 E 6.00 BSC. ddd -- -- 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to JEDEC outline MO-220, variation VJJD-2. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for small body components. 36 Preliminary Rev. 0.33 Si3226/7 Si3208/9 DOCUMENT CHANGE LIST Revision 0.2 to Revision 0.32 Added Si3208 and Si3209. Removed Si3203, Si3205, and Si3206. Added pin-outs and package drawings for Si3208 and Si3209. Updated pin-out for Si3226. Updated bill of materials. Updated "2. Typical Application Circuits" and added dc-dc converter schematics. Updated tables. Revision 0.32 to Revision 0.33 Changed package type for Si3208. Deleted QFN-32 drawing. Updated dc-dc converter schematic. Updated bills of materials. Updated max VBAT values. Updated thermal shutdown thresholds. Updated Si3208/9 pin descriptions. Preliminary Rev. 0.33 37 Si3226/7 Si3208/9 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: ProSLICinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where personal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized application, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages. Silicon Laboratories, Silicon Labs, and ProSLIC are trademarks of Silicon Laboratories Inc. Other products or brand names mentioned herein are trademarks or registered trademarks of their respective holders. 38 Preliminary Rev. 0.33