Preliminary Rev. 0.33 6/07 Copyright © 2007 by Silicon Laboratories Si3226/7 Si3208/9
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
Si3226/7
Si3208/9
DUAL PROSLIC® WITH DC-DC CONTROLLER
Features
Applications
Description
The Dual ProSLIC® is a family of low-voltage CMOS devices that integrate both
SLIC and CODEC functionality into a single IC. In combination with a linefeed IC
(LFIC), they provide a complete two-channel analog telephone interface in
accordance with all relevant LSSGR, ITU, and ETSI specifications. The Dual
ProSLIC devices (Si3226/7) operate from a single 3.3 V supply and interface to
standard PCM/SPI or GCI bus digital interfaces. The LFICs (Si3208/9) perform all
high-voltage functions and operate from a 3.3 V supply as well as high-voltage
battery supplies. The Si3208 is rated for –110 V, and the Si3209 is rated for –
135 V. The Dual ProSLIC devices are available in a 64-pin thin quad flat package
(TQFP), and the LFICs are available in a 40-pin, quad flat no-lead package
(QFN).
Functional Block Diagram
Performs all BORSCHT functions
Ideal for short- or long-loop applications
Internal balanced or unbalanced ringing
Low power consumption
Software-programmable parameters:
Ringing frequency, amplitude,
cadence, and waveshape
Two-wire ac impedance
Transhybrid balance
DC current loop feed (10–45 mA)
Loop closure and ring trip thresholds
Ground key detect threshold
Integrated dc-dc controller
Wideband CODEC (Si3227)
Low-power sleep mode
On-hook transmission
Loop or ground start operation
Smooth polarity reversal
DTMF generator/decoder
A-Law/µ-Law companding,
linear PCM
PCM and SPI bus digital interfaces
with programmable interrupts
GCI/IOM-2 mode support
3.3 V operation
GR-909 loop diagnostics
Audio diagnostics with loopback
Pb-free/RoHS-compliant packaging
Customer Premises Equipment (CPE)
Optical Network Terminals (ONT)
Private Branch Exchange (PBX)
Cable EMTAs, ATAs, VoIP
Gateways
Linefeed
RING
TIP
RING
TIP
Linefeed
SPI
Control
Interface
PCM/
GCI
Interface
DSP
DTMF &
Tone Gen
Programmable
AC Impedance
and Hybrid
Caller ID
Ringing
Generator
ADC
DAC
CODEC
ADC
DAC
CODEC
SLIC
Linefeed
Control
Linefeed
Monitor
SLIC
Linefeed
Control
Linefeed
Monitor
Channel 1
Channel 2
DC-DC Controller
Line Diagnostics
PLL
PCLK
FSYNC
DRX
DTX
CS
SDI
SDO
SCLK
INT
RST
Si3226 Si3206
DC-DC BOM
VDC
VBAT
Linefeed
RING
TIP
RING
TIP
Linefeed
SPI
Control
Interface
PCM/
GCI
Interface
DSP
DTMF &
Tone Gen
Programmable
AC Impedance
and Hybrid
Caller ID
Ringing
Generator
ADC
DAC
CODEC
ADC
DAC
CODEC
ADC
DAC
CODEC
ADC
DAC
CODEC
SLIC
Linefeed
Control
Linefeed
Monitor
SLIC
Linefeed
Control
Linefeed
Monitor
Channel 1
Channel 2
DC-DC Controllers
Line Diagnostics
PLL
PCLK
FSYNC
DRX
DTX
CS
SDI
SDO
SCLK
INT
RST
Si3226/7
DC-DC BOM
VDC
VBAT
Si3208/9
Patents pending
Ordering Information
See page 33.
Si3226/7
Si3208/9
2 Preliminary Rev. 0.33
Si3226/7
Si3208/9
Preliminary Rev. 0.33 3
TABLE OF CONTENTS
Section Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Application Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3. Bill of Materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
4. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.1. DC Feed Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.2. Linefeed Operating States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.3. Line Voltage and Current Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.4. Power Monitoring and Power Fault Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
4.5. Thermal Overload Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.6. Power Dissipation Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.7. Loop Closure Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
4.8. Ground Key Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.9. Ringing Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.10. Polarity Reversal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.11. Two-Wire Impedance Synthesis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.12. Transhybrid Balance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.13. Tone Generators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.14. DTMF Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.15. DC-DC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.16. Wideband Audio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
4.17. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.18. PCM Interface and Companding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.19. General Circuit Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
4.20. Metallic Loop Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
5. Pin Descriptions: Si3226/7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
6. Pin Descriptions: Si3208/9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31
7. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
8. Package Outline: 64-Pin TQFP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34
9. Package Outline: 40-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38
Si3226/7
Si3208/9
4 Preliminary Rev. 0.33
1. Electrical Specifications
Table 1. Absolute Maximum Ratings and Thermal Information1
Parameter Symbol Test Condition Value Unit
Operating Temperature Range TA–40 to 85 °C
Storage Temperature Range TSTG –55 to 150 °C
Thermal Resistance, Typical2
TQFP-64 θJA 25 °C/W
Continuous Power Dissipation3
TQFP-64 PDTA=85°C 1.6 W
Thermal Resistance, Typical2
QFN-40 θJA 32 °C/W
Continuous Power Dissipation4
QFN-40 PDTA=85°C 1.7 W
Si3226/7
Supply Voltage VDD1 – VDD4 –0.5 to 4.0 V
Digital Input Voltage VIND –0.3 to 3.6 V
Si3208
Supply Voltage VDD –0.5 to 4.0 V
Battery Supply Voltage5VBAT Continuous +0.4 to –110 V
Pulse < 10 µs +0.4 to –118 V
TIP, RING Current ITIP
, IRING ±100 mA
Si3209
Supply Voltage VDD –0.5 to 4.0 V
High Battery Supply Voltage5VBAT
Continuous +0.4 to –135 V
Pulse < 10 µs +0.4 to –143 V
TIP, RING Current ITIP
, IRING ±100 mA
Notes:
1. Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to the conditions as specified in the operational sections of this data sheet.
2. The thermal resistance of an exposed pad package is assured when the recommended printed circuit board layout
guidelines are followed correctly. The specified performance requires that the exposed pad be soldered to an exposed
copper surface of at least equal size and that multiple vias are added to enable heat transfer between the top-side
copper surface and a large internal/bottom copper plane.
3. Operation of the Si3226 or Si3227 above 125 °C junction temperature may degrade device reliability.
4. Si3208 and Si3209 are equipped with on-chip thermal limiting circuitry that shuts down the circuit when the junction
temperature exceeds the thermal shutdown threshold. The thermal shutdown threshold should normally be set to 145
°C; when in the ringing state the thermal shutdown may be set to 200 °C. For optimal reliability long term operation of
the Si3208/Si3209 above 150 °C junction temperature should be avoided.
5. The dv/dt of the voltage applied to the VBAT pins must be limited to 10 V/µs.
Si3226/7
Si3208/9
Preliminary Rev. 0.33 5
Table 2. Recommended Operating Conditions
Parameter Symbol Test
Condition
Min*Typ Max*Unit
Ambient Temperature TAF-grade 0 25 70 oC
Ambient Temperature TAG-grade –40 25 85 oC
Supply Voltage, Si3226/7 VDD1–VDD4 3.13 3.3 3.47 V
Supply Voltage, Si3208/Si3209 VDD 3.13 3.3 3.47 V
Battery Voltage, Si3208 VBAT –9 — –110 V
Battery Voltage, Si3209 VBAT –9 — –135 V
*Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated.
Table 3. 3.3 V Power Supply Characteristics1
(VDD =3.3V, T
A= 0 to 70 ºC for F-Grade, –40 to 85 ºC for G-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
High Impedance,
Reset
IDD VT and VR= Hi-Z
RST =0
—2.4—mA
IVBAT —0—mA
High Impedance,
Open Current
IDD VT and VR= Hi-Z — 9.7 — mA
IVBAT —0.6—mA
Forward/Reverse Sleep,
On-hook Current
IDD VTR = –48 V — 15 — mA
IVBAT —1.2—mA
Forward/Reverse Active,
On-hook Current
IDD VTR = –48 V — 24 — mA
IVBAT —1.2—mA
Forward/Reverse Active,
Off-hook Current
IDD ILOOP =30mA
RLOAD =50Ω
—43—mA
IVBAT — 3.1 + ILOOP —mA
Forward/Reverse OHT,
On-hook Current
IDD VTR = –48 V — 43 — mA
IVBAT —1.6—mA
Tip/Ring Open,
On-hook Current
IDD VT or VR= –48 V
VR or VT= Hi-Z
—23—mA
IVBAT —0.6—mA
Ringing Current IDD VTR =55V
RMS + 0 VDC
balanced, sinusoidal, f = 20 Hz
RLOAD = 5 REN = 1400 Ω
—26—mA
IVBAT —2.3 + I
AVE —mA
Notes:
1. All specifications are for a single channel of Si3226/7 using Si3208/9 linefeed IC and based on measurements with all
channels in the same operating state.
2. ILOOP is the dc current in the subscriber loop during the off-hook state.
3. IAVE is the average of the full-wave rectified current in the subscriber loop during ringing (IAVE = IPEAK x 2/π).
Si3226/7
Si3208/9
6 Preliminary Rev. 0.33
Table 4. AC Characteristics
(VDD = 3.13 to 3.47 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter Test Condition Min Typ Max Unit
TX/RX Performance
Overload Level 2.5 — — VPK
Overload Compression 2-Wire – PCM Figure 6 — —
Single Frequency Distortion12-Wire – PCM or PCM – 2-Wire:
200Hz to 3.4kHz
——–65dB
PCM – 2-Wire – PCM:
200 Hz – 3.4 kHz,
16-bit Linear mode
——–65dB
Signal-to-(Noise + Distortion)
Ratio2
200Hz to 3.4kHz
D/A or A/D 8-bit
Active off-hook, and OHT, any ZT
Figure 5 — —
Audio Tone Generator Signal-to-
Distortion Ratio2
0 dBm0, Active off-hook, and
OHT, any ZT
46 — — dB
Intermodulation Distortion — — –41 dB
Gain Accuracy22-Wire to PCM or PCM to 2-Wire
1014 Hz, Any gain setting
VDD1 –V
DD4 = 3.3 V ± 5% –0.2 — 0.2 dB
Attenuation Distortion vs. Freq. 0 dBm 0 See AN317
Group Delay vs. Frequency
Gain Tracking31014 Hz sine wave,
reference level –10 dBm
Signal level:
————
3 dB to –37 dB — — 0.25 dB
–37 dB to –50 dB — — 0.5 dB
–50 dB to –60 dB — — 1.0 dB
Round-Trip Group Delay 1014 Hz, Within same time-slot — 450 500 µs
Crosstalk between channels
TX or RX to TX
TX or RX to RX
0dBm0,
300Hz to 3.4kHz
300Hz to 3.4kHz
—
—
—
—
–75
–75
dB
dB
2-Wire Return Loss4200Hz to 3.4kHz 26 30 — dB
Transhybrid Balance4300Hz to 3.4kHz 26 30 — dB
Noise Performance
Idle Channel Noise5C-Message weighted — 8 12 dBrnC
Psophometric weighted — –80 –78 dBmP
PSRR from VDD1–VDD4 RX and TX, dc to 3.4 kHz 40 — — dB
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING
. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. VDD1–VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors; RL= 600 Ω, ZS=600Ω synthesized using RS register
coefficients.
5. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
Si3226/7
Si3208/9
Preliminary Rev. 0.33 7
Longitudinal Performance
Longitudinal to Metallic/PCM
Balance (forward or reverse)
200 Hz to 1 kHz 58 60 — dB
1kHz to 3.4kHz 53 58 — dB
Metallic/PCM to Longitudinal Bal-
ance
200 Hz to 3.4 kHz 40 — — dB
Longitudinal Impedance 200 Hz to 3.4 kHz at TIP or RING — 50 — Ω
Longitudinal Current per Pin Active off-hook
200Hz to 3.4kHz
——30mA
DC Current Differential — — 45 mA
Common Mode — — 30 mA
Differential + Common Mode — — 45 mA
Table 4. AC Characteristics (Continued)
(VDD = 3.13 to 3.47 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter Test Condition Min Typ Max Unit
Notes:
1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should
be –10 dBm0. The output signal magnitude at any other frequency is smaller than the maximum value specified.
2. Analog signal measured as VTIP – VRING
. Assumes ideal line impedance matching.
3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking
performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM
sampling rate.
4. VDD1–VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors; RL= 600 Ω, ZS=600Ω synthesized using RS register
coefficients.
5. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm.
Si3226/7
Si3208/9
8 Preliminary Rev. 0.33
Table 5. Linefeed Characteristics
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
Maximum Loop Resistance RLOOP RDC,MAX =430Ω
ILOOP =18mA, V
BAT = –52V
— — 2000 Ω
DC Loop Current Accuracy ILIM =18mA — — 10 %
DC Open Circuit Voltage
Accuracy
Active Mode; VOC =48V,
VTIP – VRING
—— 4 V
DC Differential Output
Resistance
RDO ILOOP < ILIM 160 — 640 Ω
DC On-Hook Voltage
Accuracy—Ground Start
VOHTO IRING<ILIM; VRING wrt ground,
VRING =–51V
—— 4 V
DC Output
Resistance—Ground Start
RROTO IRING<ILIM; RING to ground 160 — 640 Ω
DC Output Resistance—
Ground Start
RTOTO TIP to ground 400 — — kΩ
Loop Closure Detect
Threshold Accuracy
ITHR =13mA — — 10 %
Ground Key Detect
Threshold Accuracy
ITHR =13mA — — 10 %
Ring Trip
Threshold Accuracy
AC detection,
VRING = 70 Vpk, no offset,
ITH =80mA
—— 4mA
DC detection,
20 V dc offset, ITH =13mA
—— 1mA
DC Detection,
48 V DC offset, Rloop = 1500 Ω
—— 3mA
Ringing Amplitude VRING Open circuit, VBAT =–110V 108 — — V
PK
5 REN load, RLOOP =0Ω,
VBAT =–110V, R
DO =160Ω
99 — — VPK
Open Circuit, VBAT = –135 V 133 — — VPK
5 REN load, RLOOP =0Ω,
VBAT = –130 V, RDO =160Ω
121 — — VPK
Sinusoidal Ringing Total
Harmonic Distortion
RTHD —2—%
Ringing Frequency Accuracy f = 16 Hz to 100 Hz — — 1 %
Ringing Cadence Accuracy Accuracy of ON/OFF times — — 50 ms
Calibration Time ↑CAL to ↓CAL bit — — TBD ms
Loop Voltage Sense
Accuracy
Accuracy of boundaries for
each output Code;
VTIP – VRING =48V
—2 4%
*Note: Ringing amplitude is set for 93 V peak and measured at TIP-RING using no series protection resistance.
Si3226/7
Si3208/9
Preliminary Rev. 0.33 9
Loop Current
Sense Accuracy
Accuracy of boundaries for
each output code;
ILOOP =18mA
—710%
Power Alarm
Threshold Accuracy
Power Threshold = 300 mW — — 25 %
Table 6. Monitor ADC Characteristics
(VDD = 3.13 to 3.47 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
Differential Nonlinearity
(8-bit resolution)
DNLE — — 1 LSB
Integral Nonlinearity
(8-bit resolution)
INLE — — 1 LSB
Gain Error — — 5 %
Table 7. Si3208/Si3209 Characteristics
(VDD = 3.13 to 3.47 V, VBAT = –15 to –130 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
TIP/RING Pull-down Transistor
Saturation Voltage
VCM VRING – VBAT (Forward)
VTIP – VBAT (Reverse)
VAC =2.5V
PK
IOUT =22mA
IOUT =60mA
⎯
⎯
3
⎯
⎯
3.5
V
V
TIP/RING Pull-up Transistor
Saturation Voltage
VOV GND – VTIP (Forward)
GND – VRING (Reverse)
VAC =2.5V
PK
IOUT =22mA
IOUT =60mA
⎯
⎯
3
⎯
⎯
3.5
V
V
OPEN State TIP/RING Leakage Current ILKG RL=0Ω⎯⎯150 µA
Table 5. Linefeed Characteristics (Continued)
(VDD = 3.13 to 3.47 V, TA = 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
*Note: Ringing amplitude is set for 93 V peak and measured at TIP-RING using no series protection resistance.
Si3226/7
Si3208/9
10 Preliminary Rev. 0.33
Table 8. DC Characteristics
(VDD = 3.13 to 3.47 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter Symbol Test Condition Min Typ Max Unit
High Level Input Voltage VIH 0.7 x VDD —5.25V
Low Level Input Voltage VIL — — 0.3 x VDD V
High Level Output
Voltage
VOH IO=4mA V
DD –0.6 — — V
Low Level Output
Voltage
VOL DTX, SDO, INT,
SDITHRU:
IO=–4mA
——0.4V
GPIO1 a/b, GPIO2 a/b:
IO=–40mA
— — 0.72
SDITHRU internal pullup
resistance
35 50 — kΩ
Relay Driver Source
Impedance
ROUT VDD1–VDD4 =3.13V
IO < 28 mA
—63—Ω
Relay Driver Sink
Impedance
RIN VDD1–VDD4 =3.13V
IO < 85 mA
—11—Ω
Input Leakage Current IL——10µA
Table 9. Switching Characteristics—General Inputs1
(VDD = 3.13 to 5.25 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL=20pF)
Parameter Symbol Min Typ Max Unit
Rise Time, RESET tr—— 5 ns
RESET Pulse Width, GCI Mode2,3 trl 33/PCLK — — µs
RESET Pulse Width, SPI Daisy Chain Mode3trl 33/PCLK — — µs
Notes:
1. All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are
VIH =V
DD – 0.4 V, VIL = 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform.
2. The minimum RESET pulse width assumes the SDITHRU pin is tied to ground via a pulldown resistor no greater than
10 kΩ per device.
3. The minimum RESET pulse width is 33/PCLK frequency (i.e. 33/8.192 MHz = 4 µs).
Si3226/7
Si3208/9
Preliminary Rev. 0.33 11
Figure 1. SPI Timing Diagram
Table 10. Switching Characteristics—SPI
(VDDA = 3.13 to 5.25 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL=20pF)
Parameter Symbol Test Conditions Min Typ Max Unit
Cycle Time SCLK tc62 — — ns
Rise Time, SCLK tr— — 25 ns
Fall Time, SCLK tf— — 25 ns
Delay Time, SCLK Fall to SDO Active td1 — — 20 ns
Delay Time, SCLK Fall to SDO
Transition
td2 — — 20 ns
Delay Time, CS Rise to SDO Tri-state td3 — — 20 ns
Setup Time, CS to SCLK Fall tsu1 25 — — ns
Hold Time, CS to SCLK Rise th1 20 — — ns
Setup Time, SDI to SCLK Rise tsu2 25 — — ns
Hold Time, SDI to SCLK Rise th2 20 — — ns
Delay Time between Chip Selects tcs 220 — — ns
SDI to SDITHRU Propagation Delay td4 — 4 10 ns
Note: All timing is referenced to the 50% level of the waveform. Input test levels are VIH =V
DDD –0.4 V, VIL =0.4V
SCLK
CS
SDI
th1
td3
SDO
td1 td2
tsu1
trtf
tsu2 th2
tcs
tc
SDITHRU
td4
Si3226/7
Si3208/9
12 Preliminary Rev. 0.33
Table 11. Switching Characteristics—PCM Highway Interface
(VDD = 3.13 to 5.25 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade, CL=20pF)
Parameter Symbol Test
Conditions Min1Typ1Max1Units
PCLK Period tp122 — 3906 ns
Valid PCLK Inputs —
—
—
—
—
—
—
—
512
768
1.024
1.536
1.544
2.048
4.096
8.192
—
—
—
—
—
—
—
—
kHz
kHz
MHz
MHz
MHz
MHz
MHz
MHz
FSYNC Period2tfs —125 —µs
PCLK Duty Cycle Tolerance tdty 40 50 60 %
FSYNC Jitter Tolerance tjitter — — ±120 ns
Rise Time, PCLK tr— — 25 ns
Fall Time, PCLK tf— — 25 ns
Delay Time, PCLK Rise to DTX Active td1 — — 20 ns
Delay Time, PCLK Rise to DTX
Transition
td2 — — 20 ns
Delay Time, PCLK Rise to DTX
Tristate3
td3 — — 20 ns
Setup Time, FSYNC to PCLK Fall tsu1 25 — — ns
Hold Time, FSYNC to PCLK Fall th1 20 — — ns
Setup Time, DRX to PCLK Fall tsu2 25 — — ns
Hold Time, DRX to PCLK Fall th2 20 — — ns
FSYNC Pulse Width twfs tp—125µs–t
p
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH – VI/O –0.4V, V
IL =0.4V.
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Spec applies to PCLK fall to DTX tristate when that mode is selected.
Si3226/7
Si3208/9
Preliminary Rev. 0.33 13
Figure 2. PCM Highway Interface Timing Diagram
Table 12. Switching Characteristics—GCI Highway Serial Interface
(VDD = 3.13 to 5.25 V, TA= 0 to 70 °C for F-Grade, –40 to 85 °C for G-Grade)
Parameter1Symbol Test
Conditions
Min Typ Max Units
PCLK Period (2.048 MHz PCLK Mode) tp—488— ns
PCLK Period (4.096 MHz PCLK Mode) tp—244— ns
FSYNC Period2 t
fs —125— µs
PCLK Duty Cycle Tolerance tdty 40 50 60 %
FSYNC Jitter Tolerance tjitter — — ±120 ns
Rise Time, PCLK tr— — 25 ns
Fall Time, PCLK tf— — 25 ns
Delay Time, PCLK Rise to DTX Active td1 — — 20 ns
Delay Time, PCLK Rise to DTX Transition td2 — — 20 ns
Delay Time, PCLK Rise to DTX Tristate3td3 — — 20 ns
Setup Time, FSYNC Rise to PCLK Fall tsu1 25 — — ns
Hold Time, PCLK Fall to FSYNC Fall th1 20 — — ns
Setup Time, DRX Transition to PCLK Fall tsu2 25 — — ns
Hold Time, PCLK Falling to DRX Transition th2 20 — — ns
FSYNC Pulse Width twfs tp/2 — — ns
Notes:
1. All timing is referenced to the 50% level of the waveform. Input test levels are VIH =V
O – 0.4 V and VIL =0.4V.
Rise and fall times are referenced to the 20% and 80% levels of the waveform.
2. FSYNC source is assumed to be 8 kHz under all operating conditions.
3. Specification applies to PCLK fall to DTX tristate when that mode is selected.
PCLK
DRX
FSYNC
DTX
td1 td2
tsu2 th2
td3
tr
tp
tsu1
th1
tf
tfs
twfs
Si3226/7
Si3208/9
14 Preliminary Rev. 0.33
Figure 3. GCI Highway Interface Timing Diagram (2.048 MHz PCLK Mode)
Figure 4. GCI Highway Interface Timing Diagram (4.096 MHz PCLK Mode)
tsu1
th1
tp
trtf
th2
td3
td2
td1
PCLK
FSYNC
DRX
DTX
tfs
tsu2
Frame 0,
Bit 0
Frame 0,
Bit 0
tsu1
th1
tc
trtf
tsu2 th2
td3
td2
td1
PCLK
FSYNC
DRX
DTX
tfs
Frame 0,
Bit 0
Frame 0,
Bit 0
Si3226/7
Si3208/9
Preliminary Rev. 0.33 15
Figure 5. Transmit and Receive Path SNDR
Figure 6. Overload Compression Performance
Acceptable
123456789
1
2
3
4
5
6
7
8
9
0
2.6
Acceptable
Region
Fundamental Input Power (dBm0)
Fundamental
Output Power
(dBm0)
Si3226/7
Si3208/9
16 Preliminary Rev. 0.33
2. Typical Application Circuits
GPIO1a
DCDRVa
DCFFa
VDDA
SVBATb
DCFFb
DCDRVb
SDCHb
SDCLb
GPIO1aGPIO1aGPIO1aGPIO1aGPIO1aGPIO1a
GPIO2aGPIO2aGPIO2aGPIO2aGPIO2aGPIO2aGPIO2aGPIO2a
SDCHa
VDDD
VDDC
SDCLa
VDDD
GPIO2b
VDDA
SVBATa
GPIO2bGPIO2bGPIO2bGPIO2bGPIO2bGPIO2bGPIO2bGPIO2b
SVBATa
VDDC
GPIO1bGPIO1bGPIO1bGPIO1bGPIO1bGPIO1bGPIO1bGPIO1b
DCDRVb
DCFFa
DCDRVa
DCFFb
SDCHa
SDCLa
SDCHb
GPIO2aGPIO2aGPIO2aGPIO2aGPIO2aGPIO2aGPIO2aGPIO2aGPIO2aGPIO2a
SDCLb
SVBATb
GPIO1b
VCC_JUMPER
VCC
VBATa
VCC
VIN
VBATb
VBATa
VIN
VBATb
VCC
VBRNG
VBATb
VIN
VBRNG
VBATa
DRX
PCLK
FSYNC
/RESET
DTX
/CS
SDI
SCLK
SDITHRU
SDO
/INT
PCM BUS
SPI BUS
DC/DC Converter BDC/DC Converter A
PCM MODE SELECT
R15
DC/DC Converter A
DC/DC Converter B
R16 MODE SELECT
GND
VCC
x
GCI MODE - 1x PCLK
(2.048 MHz)
GCI MODE - 2x PCLK
(4.096 MHz)
PCM MODE
GND
GND
VCC
C7
0.1uF
C7
0.1uF
R17
137K
±1%
R17
137K
±1%
R15
10K
R15
10K
DCDC2
DCDC
VOUT
VIN
DCFF
DCDRV
SDCH
SDCL
GND
R16
10K
R16
10K
R13
10K
R13
10K
R2
49.9K ±0.5%
R2
49.9K ±0.5%
1
12
23
34
45
56
6
J1
RJ-11
J1
RJ-11
R206
1.58M
R206
1.58M
C3
10uF
C3
10uF
C100
0.1uF
±10%
C100
0.1uF
±10%
R200
825K
±1%
R200
825K
±1%
PROT2
Protection
TIP
RING TIP_ext
RING _ext
VBAT
EGND
VBRNG
R207
1.58M
R207
1.58M
R100
825K
±1%
R100
825K
±1%
C2
0.1uF
C2
0.1uF
PROT1
Protection
TIP
RING TIP_ext
RING _ext
VBAT
EGND VBRNG
R107
1.58M
R107
1.58M
C5
0.1uF
C5
0.1uF
C200
0.1uF
±10%
C200
0.1uF
±10%
1
12
23
34
45
56
6
J2
RJ-11
J2
RJ-11
L1
10uH
180mA
L1
10uH
180mA
C1
10uF
C1
10uF
C4
0.1uF
C4
0.1uF
C6
10uF
C6
10uF
R106
1.58M
R106
1.58M
PWROa
SRINGDCa
SRINGACa
STIPACa
STIPDCa
CAPPa
CAPMa
SVBATa
GPIO1a/STIPCa
GPIO2a/SRINGCa
SVDC
CSB
FSYNC
SDI
HVCLKa
SCLK
HVDATA
SDITHRU
SDO
DCFFa
SDCHa
SDCLa
DCDRVa
VDDC
DCDRVb
SDCLb
SDCHb
DCFFb
GNDD
VDDD
VDDREG
DTX
DTXENB
HVCLKb
PCLK
DRX
INTB
RESETB
GPIO2b/SRINGCb
GPIO1b/STIPCb
SVBATb
CAPMb
CAPPb
STIPDCb
STIPACb
SRINGACb
SRINGDCb
PWROb
DRINGb
URINGb
DTIPb
UTIPb
IBIASbCAPLB
IREF
QGND
GNDA
VDDA
ISNS
IBIASa
UTIPa
DTIPa
URINGa
DRINGa
SI3226SI3226
R19
10K
R19
10K
C8
4.7nF
±10%
C8
4.7nF
±10%
DCDC1
DCDC
VOUT
VIN
DCFF
DCDRV
SDCH
SDCL
GND
LFI
LINE INTERFACE
ISNS
HVDATA
GND
VCC
VBATa
VBATb
IBIASb
SRINGDCb
DTIPa
UTIPa
DTIPb
UTIPb
HVCLKa
DRINGa
URINGa
STIPACa
HVCLKb
DRINGb
URINGb
STIPACb
SRINGACa
SRINGACb
STIPDCa
STIPDCb
IBIASa
SRINGDCa
TIPa
TIPb
RINGa
RINGb
Figure 7. Si3226/7 (2 Lines)
Si3226/7
Si3208/9
Preliminary Rev. 0.33 17
VOUT
DCDRV
SDCH
SDCL
GND
Vin
Vin
Vin
Notes:
1) Component values and ratings are shown in the bill of materials.
2) Vin and Vout are defined in the bill of materials.
MOSFET DRIVER
C120C120
R125R125
R126R126
D121D121
C121C121
L120L120
D122D122
C122C122
R122R122
Q120Q120
C127C127
C125C125
C128C128
+
C123
+
C123
6
2
1
Q121AQ121A
C126C126
R123R123
R121R121
3
5
4
Q121BQ121B
R124R124
C124C124
R127
Figure 8. DC-DC Converter (A)
Si3226/7
Si3208/9
18 Preliminary Rev. 0.33
VOUT
DCDRV
SDCH
SDCL
GND
Vin
Vin
Vin
Notes:
1) Component values and ratings are shown in the bill of materials.
2) Vin and Vout are defined in the bill of materials.
MOSFET DRIVER
6
2
1
Q221AQ221A
L220L220
R224R224
3
5
4
Q221BQ221B
C220C220
C226C226
C222C222
C227C227
R222R222
R226R226
D221D221 C225C225
D222
R225R225
Q220Q220
+
C223
+
C223
C221C221
C224C224
C228C228
R223R223
R221R221
R227R22
Figure 9. DC-DC Converter (B)
Si3226/7
Si3208/9
Preliminary Rev. 0.33 19
HW
VCC
TIPa
RINGa
TIPb
RINGb GND
VBATa
VBATb
STIPACa
SRINGACa
STIPDCa
SRINGDCa
UTIPa
DTIPa
URINGa
DRINGa
IBIASa
ISNS
HVDATA
HVCLKa
STIPACb
SRINGACb
STIPDCb
SRINGDCb
UTIPb
DTIPb
URINGb
DRINGb
IBIASb
HVCLKb
VBATb
VBATa
VBATa
VBATb
VCC
VBATa
VBATb
VCC
Si3208 VBAT decoupling
All Resistors are 1% unless otherwise noted.
Global Port Connections
C103
10nF
±10%
C103
10nF
±10%
C104
10nF
±10%
C104
10nF
±10%
C202
10nF
±10% C202
10nF
±10%
R205
590K
R205
590K
R101
681K
R101
681K
IRINGN_1
RING_1
TIP_1
IRINGP_1
ITIPN_1
ITIPP_1
IBIAS_1
ISNS
VDD
HVCLK_1
HVDATA
ITIPP_2
ITIPN_2
IRINGP_2
IRINGN_2
IBIAS_2
HVCLK_2
TIP_2
RING_2
VBAT_1
VBAT_2
DGND
AGND
HW_epad
SI3208
U100 Si3208/QFN32
SI3208
U100 Si3208/QFN32
R201
681K
R201
681K
R203
301K
R203
301K
R104
301K
R104
301K
C203
10nF
±10% C203
10nF
±10%
C102
10nF
±10%
C102
10nF
±10%
C101
10nF
±10%
C101
10nF
±10%
C201
10nF
±10%
C201
10nF
±10%
R102
681K
R102
681K
C204
10nF
±10%C204
10nF
±10%
R202
681K
R202
681K
C107
0.1uF
C107
0.1uF
PCB3PCB3
R103
301K
R103
301K C205
0.1uF
C205
0.1uF
R204
301K
R204
301K
R105
590K
R105
590K
C105
0.1uF
C105
0.1uF
Figure 10. Linefeed (2 Lines)
Si3226/7
Si3208/9
20 Preliminary Rev. 0.33
3. Bill of Materials
Table 13. Bill of Materials for Si3226/7 (2 Lines)
Quantity Reference Value Rating Tolerance Dielectric PCB Footprint Manufacturer
2 C1, C6 10 µF 6.3 V ±20% Y5V CC1210 Venkel
2 C100, C200 0.1 µF 6.3 V ±10% X7R CC0603 Venkel
4 C2, C4, C5, C7 0.1µF 6.3 V ±20% X7R CC0603 Venkel
1 C3* 10µF 6.3 V ±20% Y5V CC1210 Venkel
1 C8 4.7 nF 6.3 V ±10% X7R CC0603 Venkel
1 L1* 10 µH 180 mA ±10% IND-NLC3225 TDK
1 R2 49.9 kΩ1/16 W ±0.5% RC0603 Venkel
4 R13, R15, R16, R19 10 kΩ1/10 W ±5% RC0603 Venkel
1R17137kΩ1/16 W ±1% RC0603 Venkel
2 R100, R200 825 kΩ1/10 W, 100 V ±1% RC0805 Venkel
4 R106*, R107*, R206*, R207* 1.58 MΩ1/10 W, 100 V ±5% RC0805 Venkel
1 U1 Si3226 TQFP64 SiLabs
*Note: Denotes optional component.
Si3226/7
Si3208/9
Preliminary Rev. 0.33 21
Table 14. Bill of Materials for Linefeed and DC-DC Converters with |VOUT| < 90 V (2 Lines)
VIN = +12 V nominal, |Vout| < 90 V
Quantity Reference Value Rating Tolerance Dielectric PCB Footprint Manufacturer
1 C120 10 µF 25 V ±20% X7R CC1210 Venkel
1 C220* 10 µF 25 V ±20% X7R CC1210 Venkel
2 C121, C221 0.1 µF 25 V ±10% X7R CC0603 Venkel
2 C126, C226 0.1 µF 25 V ±20% X7R CC0603 Venkel
2 C124, C224 0.1 µF 100 V ±20% X7R CC1210 Venkel
2 C125*, C225* 0.1 µF 100 V ±20% X7R CC1210 Venkel
2 C122, C222 0.22 µF 100 V ±20% X7R CC1812 Venkel
2 C123, C223 3.3 µF 100 V ±20% Al C2.5X6.3MM-RAD Panasonic
4 C127, C128, C227, C228 470 pF 25 V ±10% X7R CC0402 Venkel
2 D122, D222 BAS21HT1 250 V,200 mA SOD-323 ON SEMI
2 D121, D221 STPS2150A 150 V, 2.0 A DO-214AC STMicro
2 L120, L220 15 µH CDR74 SUMIDA
2 Q120, Q220 FQT7N10 100 V, 2 W SOT-223 Fairchild
2 Q121, Q221 MMDT3946 SOT-363 Diodes Inc.
2 R121, R221 0.1 Ω1/4 W ±1% RC1210 Venkel
2 R122, R222 15 Ω1/4 W ±5% RC1206 Venkel
2 R123, R223 220 Ω1/16 W ±5% RC0402 Venkel
2 R124, R224 1 kΩ1/16 W ±5% RC0402 Venkel
2 R125, R225 150 kΩ1/16 W ±5% RC0402 Venkel
2 R126, R226 100 kΩ1/16 W ±5% RC0402 Venkel
2 R127, R227 2 Ω1/8 W ±5% RC0402 Venkel
1 C107 0.1 µF 25 V ±10% X7R CC0603 Venkel
*Note: Denotes optional component.
Si3226/7
Si3208/9
22 Preliminary Rev. 0.33
4 C101, C102, C201, C202 10 nF 100 V ±10% X7R CC0805 Venkel
4 C103, C104, C203, C204 10 nF 100 V ±10% X7R CC0805 Venkel
2 C105, C205 0.1 µF 100 V ±20% X7R CC1210 Venkel
4 R101, R102, R201, R202 681 kΩ1/10 W, 150 V ±1% RC0805 Venkel
4 R103, R104, R203, R204 301 kΩ1/16 W, 75 V ±1% RC0603 Venkel
2 R105, R205 590 kΩ1/10 W, 150 V ±1% RC0805 Venkel
1 U100 Si3208 or
Si3209
QFN-40 Silicon Laboratories
Table 14. Bill of Materials for Linefeed and DC-DC Converters with |VOUT| < 90 V (2 Lines) (Continued)
VIN = +12 V nominal, |Vout| < 90 V
Quantity Reference Value Rating Tolerance Dielectric PCB Footprint Manufacturer
*Note: Denotes optional component.
Si3226/7
Si3208/9
Preliminary Rev. 0.33 23
Table 15. Bill of Materials for Linefeed and DC-DC Converters with |VOUT| < 135 V (2 Lines)
VIN = +12 V nominal, |Vout| < 135 V
Quantity Reference Value Rating Tolerance Dielectric PCB Footprint Manufacturer
1 C120 10 µF 25 V ±20% X7R CC1210 Venkel
1 C220* 10 µF 25 V ±20% X7R CC1210 Venkel
2 C121,C221 0.1 µF 25 V ±10% X7R CC0603 Venkel
2 C126,C226 0.1 µF 25 V ±20% X7R CC0603 Venkel
2 C124,C224 0.1 µF 200 V ±20% X7R CC1210 Venkel
2 C125*,C225* 0.1 µF 200 V ±20% X7R CC1210 Venkel
2 C122,C222 0.22 µF 200 V ±20% X7R CC1812 Venkel
2 C123,C223 3.3 µF 160 V ±20% Al C2.5X6.3MM-RAD Panasonic
4 C127, C128, C227, C228 470 pF 25 V ±10% X7R CC0402 Venkel
2 D122, D222 BAS21HT1 250 V,200 mA SOD-323 ON SEMI
2 D121, D221 STPS2150A 150 V, 2.0 A DO-214AC STMicro
2 L120, L220 15 µH CDRH125 SUMIDA
2 Q120, Q220 FQD7N20L 200 V, 2.5 W D-PAK Fairchild
2 Q121, Q221 MMDT3946 SOT-363 Diodes Inc.
2 R121, R221 0.1 Ω1/4 W ±1% RC1210 Venkel
2 R122, R222 15 Ω1/4 W ±5% RC1206 Venkel
2 R123, R223 220 Ω1/16 W ±5% RC0402 Venkel
2 R124, R224 1 kΩ1/16 W ±5% RC0402 Venkel
2 R125, R225 150 kΩ1/16 W ±5% RC0402 Venkel
2 R126, R226 100 kΩ1/16 W ±5% RC0402 Venkel
2 R127, R227 2 Ω1/8 W ±5% RC0402 Venkel
1 C107 0.1 µF 25 V ±10% X7R CC0603 Venkel
*Note: Denotes optional component.
Si3226/7
Si3208/9
24 Preliminary Rev. 0.33
4 C101, C102, C201, C202 10 nF 200 V ±10% X7R CC0805 Venkel
4 C103, C104, C203, C204 10 nF 100 V ±10% X7R CC0805 Venkel
2 C105, C205 0.1 µF 200 V ±20% X7R CC1210 Venkel
4 R101, R102, R201, R202 681 kΩ1/10 W, 150 V ±1% RC0805 Venkel
4 R103, R104, R203, R204 301 kΩ1/16 W, 75 V ±1% RC0603 Venkel
2 R105, R205 590 kΩ1/10 W, 150 V ±1% RC0805 Venkel
1 U100 Si3209 QFN-40 Silicon Laboratories
Table 15. Bill of Materials for Linefeed and DC-DC Converters with |VOUT| < 135 V (2 Lines) (Continued)
VIN = +12 V nominal, |Vout| < 135 V
Quantity Reference Value Rating Tolerance Dielectric PCB Footprint Manufacturer
*Note: Denotes optional component.
Preliminary Rev. 0.33 25
Si3226/7
Si3208/9
4. Functional Description
The Dual ProSLIC® chipset includes the Si3226/7 low-
voltage IC and the Si3208/9 high-voltage linefeed IC.
The Dual ProSLIC provides all SLIC, codec, DTMF
detection, and signal generation functions needed for
two complete analog telephone interfaces. The Dual
ProSLIC performs all battery, over-voltage, ringing,
supervision, codec, hybrid, and test (BORSCHT)
functions; it also supports extensive metallic loop testing
capabilities.
The Si3226 provides a standard voice-band (200 Hz–
3.4 kHz) audio codec. The Si3227 provides an audio
CODEC with both wideband (50 Hz–7 kHz) and
standard voice-band (200 Hz– 3.4 kHz) modes. The
wideband mode provides an expanded audio band with
a 16 kHz sample rate for enhanced audio quality while
the standard voice-band mode provides standard
telephony audio compatibility. The Si3226/7 provides
two independent, programmable, dc-dc converter
controllers, each of which reacts to line conditions to
provide the optimal battery voltage required for each
line-state.
The linefeed chips (Si3208/9) provide programmable
on-hook voltage, programmable off-hook loop current,
reverse battery operation, loop or ground start
operation, and on-hook transmission. Loop current and
voltage are continuously monitored using an A/D
converter in the Si3226/7. The Si3208 supports battery
voltages up to 110 V, sufficient for most ringing signals.
The Si3209 supports battery voltages up to 130 V for
higher-voltage ringing applications.
The Dual ProSLIC supports balanced 5 REN ringing
with or without a programmable dc offset. The available
offset, frequency, waveshape, and cadence options are
designed to ring the widest variety of terminal devices
and to reduce external controller requirements.
A complete audio transmit and receive path is
integrated, including ac impedance and hybrid gain.
These features are software-programmable, allowing a
single hardware design to meet global requirements.
Digital voice data transfer occurs over a standard PCM
bus. Control data is transferred using a standard SPI.
The Si3226/7 is available in a 64-pin TQFP; the Si3208
is available in a 32-pin QFN, and the Si3209 is available
in a 40-pin QFN or a 48-pin eTQFP.
4.1. DC Feed Characteristics
Dual ProSLIC internal linefeed circuitry provides
completely programmable dc feed characteristics.
Linefeed characteristics for each channel are
independently configurable.
When in the active state, each ProSLIC channel
operates in one of three dc linefeed operating regions: a
constant-voltage region, a constant-current region, or a
resistive region, as shown in Figure 11. The constant-
voltage region has a low resistance, typically 160 Ω.
The constant-current region approximates infinite
resistance.
Figure 11. Dual ProSLIC DC Feed
Characteristics
4.2. Linefeed Operating States
The linefeed interface includes eight different register-
programmable operating states as listed in Table 16.
The Open state is the default condition in the absence
of any preloaded register settings. The device may also
automatically enter the open state in the event of a
linefeed fault condition.
4.3. Line Voltage and Current Monitoring
The Dual ProSLIC continuously monitors the TIP, RING,
and battery voltages and currents via an on-chip ADC
and stores the resulting values in individual register
addresses. Additionally, the loop voltage (VTIP–VRING),
loop current, and longitudinal current values are
calculated based on the TIP and RING measurements
and are stored in unique register locations for further
processing. The ADC updates all registers at a rate of
2 kHz or greater.
4.4. Power Monitoring and Power Fault
Detection
The Dual ProSLIC's line monitoring functions are used
to continuously protect the linefeed IC (LFIC) against
excessive power conditions. The LFIC contains an on-
chip, analog sensing diode that provides real-time
temperature data to the Si3226/7 and turns off the LFIC
when a preset threshold is exceeded. The LFIC status
is reflected in a Si3226/7 register bit.
ILOOP (mA)
I_RFEED
VTR(V)
I_ILIM
I_VLIM
Resistive Region
Constant I Region
Constant V Region
V_VLIM
V_RFEED
V_ILIM
Si3226/7
Si3208/9
26 Preliminary Rev. 0.33
If the Si3226/7 detects a fault condition or overpower
condition on any channel, it automatically sets that
channel to the open state and generates a "power
alarm" interrupt. The interrupt can be masked, but the
automatic transition to open cannot be masked. The
various power alarms and linefeed faults supporting
automatic intervention are described below.
1. LFIC total power exceeded.
2. Power exceeded in one or more transistors of a LFIC
internal transistor group (if capable of measuring
individual power consumption).
3. Excessive foreign current or voltage on TIP and/or
RING.
4. LFIC thermal shutdown event; this event is
automatically performed, and no intervention by the
Si3226/7 is required.
4.5. Thermal Overload Shutdown
If the LFIC die temperature exceeds the maximum
junction temperature threshold, TJmax, of 145 °C or
200 ºC or other programmed temperature threshold
range, the LFIC has the ability to shut itself down to a
low-power state without any assistance from the
Si3226/7. The thermal shutdown circuit contains a
sufficient amount of hysteresis and/or turn-on delay time
so as to remain shut down during a power cross event,
where 50 Hz or 60 Hz, 600 V, is connected to TIP and/
or RING.
4.6. Power Dissipation Considerations
The Dual ProSLIC is designed to source loops up to
20 kft as well as short loop applications. The LFIC
provides all battery sourcing functions and is, therefore,
the determining factor regarding power dissipation in a
specific application. The Dual ProSLIC provides an on-
chip dc-dc controller that can dynamically reduce the
battery supply to ideally match the required line feed
voltage.
4.7. Loop Closure Detection
The Dual ProSLIC provides a completely programmable
loop closure detection mechanism. The loop closure
detection scheme provides two unique thresholds to
allow hysteresis, and also includes a programmable
debounce filter to eliminate false detection. A loop
closure detect status bit provides continuous status, and
a maskable interrupt bit is also provided.
Table 16. Linefeed Operating States
Linefeed State Description
Open Output is high-impedance, and all line supervision functions are powered down. Audio is
powered down. This is the default state after powerup or following a hardware reset. This
state can also be used in the presence of line fault conditions and to generate open switch
intervals (OSIs). This state is used in line diagnostics mode as a high-Z state during line-
feed testing. A power fault condition may also force the device into the open state.
Forward Active
Reverse Active
Linefeed circuitry and audio are active. In Forward Active state, the TIP lead is more posi-
tive than the RING lead; in Reverse Active state, the RING lead is more positive than the
TIP lead. Loop closure and ground key detect circuitry are active.
Forward OHT
Reverse OHT
Provides data transmission during an on-hook loop condition (e.g., transmitting caller ID
data between ringing bursts). Linefeed circuitry and audio are active. In Forward OHT
state, the TIP lead is more positive than the RING lead; in Reverse OHT state, the RING
lead is more positive than the TIP lead.
TIP Open Provides an active linefeed on the RING lead and sets the TIP lead to high impedance
(>400 kΩ) for ground start operation in forward polarity. Loop closure and ground key
detect circuitry are active.
RING Open Provides an active linefeed on the TIP lead and sets the RING lead to high impedance
(>400 kΩ) for ground start operation in reverse polarity. Loop closure and ground key
detect circuitry are active.
Ringing Drives programmable ringing signal onto TIP and RING leads with or without dc offset.
Line Diagnostics The channel selected is put into diagnostic mode. In this mode, the selected channel has
special diagnostic resources available.
Preliminary Rev. 0.33 27
Si3226/7
Si3208/9
4.8. Ground Key Detection
The Dual ProSLIC provides a ground key detect
mechanism using a programmable architecture similar
to the loop closure scheme. The ground key detect
scheme provides two unique thresholds to allow
hysteresis and also includes a programmable debounce
filter to eliminate false detection. A ground key detect
status bit provides continuous status, and a maskable
interrupt bit is also provided.
4.9. Ringing Generation
The Dual ProSLIC provides the ability to generate a
programmable sinusoidal or trapezoidal ringing
waveform, with or without dc offset. The ringing
frequency, wave shape, cadence, and offset are all
register-programmable. Using a balanced ringing
scheme, the ringing signal is applied to both the TIP and
RING leads using dual ringing waveforms that are 180°
out of phase with each other. The resulting ringing
signal seen across TIP-RING is twice the amplitude of
the ringing waveform on either the TIP or RING lead,
which allows the ringing circuitry to be forced to
withstand only half the total ringing amplitude seen
across TIP-RING.
4.10. Polarity Reversal
The Dual ProSLIC supports polarity reversal for
message waiting and various other signaling modes.
The ramp rate can be programmed for a smooth or
abrupt transition to accommodate different application
requirements.
4.11. Two-Wire Impedance Synthesis
The ac two-wire impedance synthesis is generated on-
chip using a DSP-based scheme to optimally match the
output impedance of the Dual ProSLIC to the
impedance of the subscriber loop and minimize the
receive path signal reflected back onto the transmit
path. Most real or complex two-wire impedances can be
generated by using the coefficient generator software to
simulate the desired line conditions and generate the
required register coefficients.
4.12. Transhybrid Balance Filter
The trans-hybrid balance function is implemented on-
chip using a DSP-based scheme to effectively cancel
the reflected receive path signal from the transmit path.
The coefficient generator software is used to optimize
the filter coefficients.
4.13. Tone Generators
The Dual ProSLIC includes two digital tone generators
that allow a wide variety of single- or dual-tone
frequency and amplitude combinations. Each tone
generator has its own set of registers that hold the
desired frequency, amplitude, and cadence to allow
generation of DTMF and call progress tones for different
requirements. The tones can be directed to either
receive or transmit paths.
4.14. DTMF Detection
In DTMF, two tones generate a DTMF digit. One tone is
chosen from the four possible row tones, and one tone
is chosen from the four possible column tones. The sum
of these tones constitutes one of 16 possible DTMF
digits. The Dual ProSLIC performs DTMF detection
using an algorithm to compute the DFT for each of the
eight DTMF frequencies and their second harmonics. At
the end of the DFT computation, the squared
magnitudes of the DFT results for the 8 DTMF
fundamental tones are computed. The row and column
results are sorted to determine the strongest tones, and
checks are made to determine if the strongest row and
column tones constitute a DTMF digit.
4.15. DC-DC Controller
The controller converts a single positive dc input voltage
into an independent negative battery voltage for each
channel. The controller operates a dc-dc converter
circuit that converts a single positive dc input voltage
into an independent negative battery voltage for each
channel. In addition to eliminating external high-voltage
power supplies, the dc-dc controller allows the Dual
ProSLIC to dynamically control the battery voltage to
the minimum required for any given operating state
according to the programmed linefeed parameters.
4.16. Wideband Audio
The Si3226 supports a narrowband (200 Hz–3.4 kHz)
audio codec. The Si3227 supports a software-
selectable wideband (50 Hz–7 kHz) and narrowband
(200 Hz–3.4 kHz) audio codec. The Si3227 wideband
mode provides an expanded audio band at a 16-bit,
16 kHz sample rate for enhanced audio quality while
maintaining standard telephony audio compatibility.
Wideband audio samples are transmitted and received
on the PCM interface using two consecutive 8 kHz
frames.
Si3226/7
Si3208/9
28 Preliminary Rev. 0.33
4.17. SPI Control Interface
The controller interface to the Dual ProSLIC is a 4-wire
interface modeled after microcontroller and serial
peripheral devices. The interface consists of a clock
(SCLK), chip select (CS), serial data input (SDI), and
serial data output (SDO). In addition, the Dual ProSLIC
devices feature a serial data through output (SDITHRU)
to support operation of up to eight devices (up to 16
channels) using a single chip select line. The device
operates with both 8-bit and 16-bit SPI controllers.
4.18. PCM Interface and Companding
The Dual ProSLIC contains a flexible, programmable
interface for the transmission and reception of digital
PCM samples. PCM data transfer is controlled by the
PCM clock (PCLK) and frame sync (FSYNC) inputs as
well as the PCM Mode Select, PCM Transmit Start, and
PCM Receive Start settings.
The interface can be configured to support from four to
128 8-bit time slots in each 125 µs frame,
corresponding to a PCM clock (PCLK) frequency range
of 256 kHz to 8.192 MHz. 1.544 MHz is also supported.
The Dual ProSLIC supports both µ-255 Law (µ-Law)
and A-law companding formats in addition to 16-bit
linear data mode with no companding.
4.19. General Circuit Interface
The Dual ProSLIC supports an alternative
communication interface to the SPI and PCM control
and data interface. The General Circuit Interface (GCI)
is used for transmission and reception of both control
and data information onto a GCI bus. The PCM and GCI
interfaces are both 4-wire interfaces and share the
same pins. In GCI mode, the four-wire SPI control
interface is used as hard-wired channel selector pins.
The selection between PCM and GCI modes is
performed when coming out of reset using the
SDITHRU pin.
4.20. Metallic Loop Testing
The Dual ProSLIC includes the ability to detect multiple
fault conditions within the line card as well as on the T/R
pair.
1. Hazardous Potential Test—This test checks for ac
voltage >50 Vrms or dc voltage >135 V on T-G or R-
G. If a hazardous voltage is encountered, test access
MUST release within two seconds of the time when it
was initiated using a preset threshold.
2. Foreign ElectroMotive Force Test—Checks T-G or
R-G for ac voltage >10 Vrms, dc voltage >6 V. Uses
same threshold as for hazardous voltage test.
3. Resistive Faults Test—Checks for dc resistance from
T-R, T-G or R-G. Any measurement <150 kΩ is
considered a resistive fault.
4. Receiver-Off-Hook Test—Distinguishes between a
T-R resistive fault and an off-hook condition.
5. Ringers Test—Checks for the presence of REN
across T-R. Result are >0.175REN and <5REN for a
valid load.
6. AC Line Impedance (line length)—T-R, T-G, and
R-G. Generate a tone at several specific frequencies
(audio band) and measure the reflected signal
amplitude (complex spectrum) that comes back (with
transhybrid balance filter disabled). The reflected
signal is then used to calculate the line impedance
based on certain assumptions of wire gauge, etc.
7. Line Capacitance—T-R, T-G, R-G. Generate a linear
ramp function with polarity reversal, and measure
the time constant.
8. Ringer Capacitance—This test uses the same
procedure as the ringer test above but also
measures the V/I phase relationship of the received
signal (dc path) and then subtracts the delay to
calculate the ringer capacitance.
9. Ringing Voltage Verification—Uses current voltage
sensing capability.
10.Test-In Diagnostics—The Dual ProSLIC can switch
in a preset load impedance to test the SLIC/codec
functionality using a known set of conditions.
Si3226/7
Si3208/9
Preliminary Rev. 0.33 29
5. Pin Descriptions: Si3226/7
Table 17. Si3226/7 Pin Descriptions
Pin
Number
Symbol I/O Description
1 SRINGDCa I RING DC Sense Input.
2 SRINGACa I RING AC Sense Input.
3 STIPACa I TIP AC Sense Input.
4 STIPDCa I TIP DC Sense Input.
5 CAPPa I/O Metallic Loop Filter Capacitor-Positive Terminal.
6 CAPMa I/O Metallic Loop Filter Capacitor-Negative Terminal.
7 SVBATa I Battery Sensing Input.
8 SVDC I DC-DC Input Power Rail Sensor.
9 GPIO3a / PWROa I/O General Purpose I/O / Power Offloading Output.
10 GPIO2a / SRINGCa /
TRD2a
I/O General Purpose I/O / TIP Course Sense Input / Test Relay
Driver.
11 GPIO1a / STIPCa / TRD1a I/O General Purpose I/O / TIP Course Sense Input / Test Relay
Driver.
12 CS I Chip Select Input.
13 FSYNC I Frame Sync Clock Input.
14 SDI I Serial Port Data Input.
15 HVCLKa O Line-Driver IC Clock Output.
16 SCLK I Serial Port Bit Clock Input.
17 HVDATA O Line-Driver IC Data Output
18 SDITHRU O Serial Data Daisy Chain Output.
19 SDO O Serial Port Data Output.
20 DCFFa I/O DC-DC BJT Drive Monitor.
21 SDCHa I DC-DC Current Monitor Input-High Terminal.
22 SDCLa I DC-DC Current Monitor Input-Low Terminal.
23 DCDRVa I/O DC-DC Drive Output.
24 VDDC PWR DC-DC Switch Driver Power Supply.
25 DCDRVb O DC-DC Drive Output.
26 SDCLb I DC-DC Current Monitor Input-Low Terminal.
27 SDCHb I DC-DC Current Monitor Input-High Terminal.
28 DCFFb I/O DC-DC BJT Drive Monitor.
29 GNDD GND Digital Ground.
30 VDDD PWR Digital Supply Voltage.
31 PCLK I PCM Bus Clock Input.
32 HVCLKb O Line-Driver IC Clock Output.
Si3226/7
Si3208/9
30 Preliminary Rev. 0.33
33 DTXEN O Transmit PCM Enable Output.
34 DTX O Transmit PCM Data Output.
35 DRX I Receive PCM Data Input.
36 INT O Interrupt Output.
37 RST I Reset Input.
38 VDDREG I/O Regulated Core Power Supply.
39 GPIO1b / STIPCb / TRD1b I/O General Purpose I/O / TIP Course Sense Input / Test Relay
Driver.
40 GPIO2b / SRINGCb /
TRD2b
I/O General Purpose I/O / TIP Course Sense Input / Test Relay
Driver.
41 GPIO3b / PWROb I/O General Purpose I/O / Power Offloading Output.
42 SVBATb I Battery Sensing Input.
43 CAPMb I/O Differential Loop Filter Capacitor-Negative Term.
44 CAPPb I/O Differential Loop Filter Capacitor-Positive Term.
45 STIPDCb I TIP DC Sense Input.
46 STIPACb I TIP AC Sense Input.
47 SRINGACb I RING AC Sense Input.
48 SRINGDCb I RING DC Sense Input.
49 DRINGb O RING Pull-Down Current Driver Output.
50 URINGb O RING Pull-Up Current Driver Output.
51 DTIPb O TIP Pull-Down Current Driver Output.
52 UTIPb O TIP Pull-Up Current Driver Output.
53 IBIASb O Line Driver IC Bias Current Output.
54 CAPLB O Longitudinal Balance Calibration Capacitor.
55 IREF I Current Reference Input.
56 QGND I Quiet Ground Reference Input.
57 GNDA GND Analog Ground.
58 VDDA PWR Analog Supply Voltage.
59 ISNS I/O Line Current Sense Input.
60 IBIASa O Line Driver IC Bias Current Output.
61 UTIPa O TIP Pull-Up Current Driver Output.
62 DTIPa O TIP Pull-Down Current Driver Output.
63 URINGa O RING Pull-Up Current Driver Output.
64 DRINGa O RING Pull-Down Current Driver Output.
Table 17. Si3226/7 Pin Descriptions (Continued)
Pin
Number
Symbol I/O Description
Si3226/7
Si3208/9
Preliminary Rev. 0.33 31
6. Pin Descriptions: Si3208/9
Table 18. Si3208/9 Pin Descriptions
QFN Pin # Symbol I/O Description
1 IC Internal connection; leave to float.
2 NC No Connect.
3 RING_1 I/O Ring Channel 1 Input/Output.
4 NC No Connect.
5 TIP_1 I/O Tip Channel 1 Input/Output.
6 NC No Connect.
7 IC Internal connection; leave to float.
8 IRINGN_1 I Negative Ring Current Control Channel 1 Input.
9 IRINGP_1 I Positive Ring Current Control Channel 1 Input.
10 ITIPN_1 I Negative Tip Current Control Channel 1 Input.
11 ITIPP_1 I Positive Tip Current Control Channel 1 Input.
12 IBIAS_1 I Current Bias Channel 1 Input.
13 ISNS O Current Sense Output.
14 VDD I IC Supply Voltage Input.
15 HVCLK_1 I High-Voltage IC Clock Channel 1 Input.
16 HVDATA I/O High-Voltage IC Data Input/Output.
17 HVCLK_2 I High-Voltage IC Clock Channel 2 Input.
18 DGND I Digital Ground.
19 IBIAS_2 I Current Bias Channel 2 Input.
20 ITIPP_2 I Positive Tip Current Control Channel 1 Input.
21 ITIPN_2 I Negative Tip Current Control Channel 2 Input.
22 IRINGP_2 I Positive Ring Current Control Channel 2 Input.
23 IRINGN_2 I Negative Ring Current Control Channel 2 Input.
24 IC Internal connection; leave to float.
25 NC No Connect.
26 TIP_2 I/O Tip Channel 2 Input/Output.
27 NC No Connect.
28 RING_2 I/O Ring Channel 2 Input/Output.
29 NC No Connect.
30 IC Internal connection; leave to float.
31 IC Internal connection; leave to float.
32 VBAT_2 I Operating Battery Voltage Channel 2 Input.
33 NC No Connect.
34 IC Internal connection; leave to float.
Si3226/7
Si3208/9
32 Preliminary Rev. 0.33
35 NC No Connect.
36 AGND I Analog Ground.
37 IC Internal connection; leave to float.
38 IC Internal connection; leave to float.
39 VBAT_1 I Operating Battery Voltage Channel 1 Input.
40 IC Internal connection; leave to float.
epad Exposed Die Attach Paddle.
For adequate thermal management, the exposed die paddle
should be soldered to a printed circuit board pad that is connected
to an electrically-isolated low-impedance inner layer and/or back-
side thermal plane(s) using multiple thermal vias. Do not connect
this pad to ground.
Table 18. Si3208/9 Pin Descriptions (Continued)
QFN Pin # Symbol I/O Description
Si3226/7
Si3208/9
Preliminary Rev. 0.33 33
7. Ordering Guide
Device Description Wideband
Audio
Package Temp Range
Si3226-X-FQ Dual ProSLIC No TQFP-64 0 to 70 °C
Si3226-X-GQ Dual ProSLIC No TQFP-64 –40 to 85 °C
Si3227-X-FQ Dual ProSLIC Yes TQFP-64 0 to 70 °C
Si3227-X-GQ Dual ProSLIC Yes TQFP-64 –40 to 85 °C
Si3208-X-FM 110 V Dual LFIC — QFN-40 0 to 70 °C
Si3208-X-GM 110 V Dual LFIC — QFN-40 –40 to 85 °C
Si3209-X-FM 135 V Dual LFIC — QFN-40 0 to 70 °C
Si3209-X-GM 135 V Dual LFIC — QFN-40 –40 to 85 °C
Notes:
1. All devices are lead-free and RoHS compliant.
2. “X” denotes product revision (A, B, C, etc.).
3. Add an R at the end of the device to denote tape and reel options.
Si3226/7
Si3208/9
Preliminary Rev. 0.33 35
Table 19. 64-Pin TQFP Package Dimensions
Dimension Min Nom Max
A——1.20
A1 0.05 — 0.15
A2 0.95 1.00 1.05
b 0.17 0.22 0.27
c 0.09 — 0.20
D 12.00 BSC.
D1 10.00 BSC.
e 0.50 BSC.
E 12.00 BSC.
E1 10.00 BSC.
L 0.45 0.60 0.75
aaa — — 0.20
bbb — — 0.20
ccc — — 0.08
ddd — — 0.08
Q0°3.5°7°
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. This package outline conforms to JEDEC MS-026, variant ACD.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C
specification for small body components.
Si3226/7
Si3208/9
36 Preliminary Rev. 0.33
9. Package Outline: 40-Pin QFN
Figure 13 illustrates the package details for the Si3208/9. Table 20 lists the values for the dimensions shown in the
illustration.
Figure 13. 40-Pin QFN Package
Table 20. 40-Pin QFN Package Dimensions
Dimension Min Nom Max Dimension Min Nom Max
A 0.80 0.90 1.00 E2 4.10 4.30 4.40
A1 0.00 0.02 0.05 L 0.30 0.40 0.50
b 0.18 0.25 0.30 L1 0.03 0.05 0.08
D 6.00 BSC. aaa — — 0.10
D2 4.10 4.30 4.40 bbb — — 0.10
e 0.50 BSC. ccc — — 0.08
E 6.00 BSC. ddd — — 0.10
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MO-220, variation VJJD-2.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for small body components.
Preliminary Rev. 0.33 37
Si3226/7
Si3208/9
DOCUMENT CHANGE LIST
Revision 0.2 to Revision 0.32
Added Si3208 and Si3209.
Removed Si3203, Si3205, and Si3206.
Added pin-outs and package drawings for Si3208
and Si3209.
Updated pin-out for Si3226.
Updated bill of materials.
Updated “2. Typical Application Circuits” and added
dc-dc converter schematics.
Updated tables.
Revision 0.32 to Revision 0.33
Changed package type for Si3208.
Deleted QFN-32 drawing.
Updated dc-dc converter schematic.
Updated bills of materials.
Updated max VBAT values.
Updated thermal shutdown thresholds.
Updated Si3208/9 pin descriptions.
Si3226/7
Si3208/9
38 Preliminary Rev. 0.33
CONTACT INFORMATION
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