Product Specification PE4307 75 RF Digital Attenuator 5-bit, 15.5 dB, 1 - 2000 MHz Product Description Features Attenuation: 0.5 dB steps to 15.5 dB Flexible parallel and serial programming interfaces Latched or direct mode Unique power-up state selection Positive CMOS control logic High attenuation accuracy and linearity over temperature and frequency Very low power consumption Single-supply operation 75 impedance Pin compatible with PE430x series Packaged in a 20-lead 4x4 mm QFN The PE4307 is a high linearity, 5-bit RF Digital Step Attenuator (DSA) covering a 15.5 dB attenuation range in 0.5 dB steps. The device is pin compatible with the PE430x series. This 75-ohm RF DSA provides both parallel (latched or direct mode) and serial CMOS control interface, operates on a single 3-volt supply and maintains high attenuation accuracy over frequency and temperature. It also has a unique control interface that allows the user to select an initial attenuation state at power-up. The PE4307 exhibits very low insertion loss and low power consumption. This functionality is delivered in a 4x4 mm QFN footprint. The PE4307 is manufactured on Peregrine's UltraCMOS(R) process, a patented variation of silicon-on-insulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. Figure 1. Functional Schematic Diagram Figure 2. Package Type Switched Attenuator Array 20-lead 4x4 mm QFN RF Input RF Output Parallel Control 5 Serial Control 3 Power-Up Control 1 Control Logic Interface 71-0007 Table 1. Electrical Specifications @ +25C, VDD = 3.0V Parameter Test Condition Frequency Operation Frequency Insertion Loss Typical 1 1 Attenuation Accuracy Minimum Any Bit or Bit Combination 1 dB Compression3,4 Maximum Unit 2000 MHz 1 MHz 1.2 GHz - 1.4 1.95 dB 1 MHz 1.2 GHz - - (0.15 + 4% of atten setting) Not to exceed +0.25 dB dB dB 1 MHz 1.2 GHz 30 34 - dBm Input IP3 Two-tone inputs up to +18 dBm 1 MHz 1.2 GHz - 52 - dBm Return Loss Zo = 75 ohms 1 MHz 1.2 GHz 10 13 - dB Switching Speed 50% control to 0.5 dB of final value - - 1 s 1,2,4 Notes: 1. Device Linearity will begin to degrade below 1 MHz 2. Max input rating in Table 3 & Figures on Pages 4 to 6 for data across frequency 3. Note Absolute Maximum in Table 3 4. Measured in a 50 system Document No. 70-0161-05 www.psemi.com (c)2003-2013Peregrine Semiconductor Corp. All rights reserved. Page 1 of 11 PE4307 Product Specification LE 5 C4 16 C2 17 GND 18 Exposed Solder Pad N/C VDD V V Storage temperature range -65 150 C Input power (50) +30 dBm ESD voltage (Human Body Model) 500 V TST PIN 13 P/S 12 Vss/GND 11 GND VESD Table 4. Operating Ranges Parameter Min Typ Max Unit VDD Power Supply Voltage 2.7 3.0 3.3 V 100 A IDD Power Supply Current Digital Input High N/C No connect 2 RF1 RF port (Note 1) 3 Data Serial interface data input (Note 4) 4 Clock Serial interface clock input 5 LE Latch Enable input (Note 2) 6 VDD Power supply pin Description No connect Power-up selection bit 9 VDD 10 GND Ground connection 11 GND Ground connection 12 Vss/GND Power supply pin Negative supply voltage or GND connection (Note 3) 13 P/S Parallel/Serial mode select 14 RF2 RF port (Note 1) 15 C8 Attenuation control bit, 8 dB 16 C4 Attenuation control bit, 4 dB 17 C2 Attenuation control bit, 2 dB 18 GND 19 C1 20 C0.5 Attenuation control bit, 0.5 dB Paddle GND Ground for proper operation Ground connection. Attenuation control bit, 1 dB Notes: 1. Both RF ports must be held at 0 VDC or DC blocked with an external series capacitor 2. Latch Enable (LE) has an internal 100 k resistor to VDD 3. Connect pin 12 to GND to enable internal negative voltage generator. Connect pin 12 to VSS (-VDD) to bypass and disable internal negative voltage generator 4. Place a 10 k resistor in series, as close to pin as possible to avoid frequency resonance. See "Resistor on 3" paragraph (c)2003-2013 Peregrine Semiconductor Corp. All rights reserved. Page 2 of 11 4.0 -0.3 RF2 1 N/C -0.3 Voltage on any input 14 Pin Name PUP2 Unit VI C8 Pin No. 8 Power supply voltage Max VDD+ 0.3 15 Table 2. Pin Descriptions 7 Min 10 4 VDD Parameter/Condition GND Clock 9 3 VDD Data Table 3. Absolute Maximum Ratings Symbol 20-lead QFN 4x4mm 8 2 PUP2 RF1 7 1 6 N/C 19 20 C1 C0.5 Figure 15. Pin Configuration (Top View) 0.7xVDD Digital Input Low Digital Input Leakage Input Power Temperature range -40 V 0.3xVDD V 1 A +24 dBm 85 C Exposed Solder Pad Connection The exposed solder pad on the bottom of the package must be grounded for proper device operation. Electrostatic Discharge (ESD) Precautions When handling this UltraCMOS(R) device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the rate specified in Table 3. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOS(R) devices are immune to latch-up. Switching Frequency The PE4307 has a maximum 25 kHz switching rate. Resistor on Pin 3 A 10 k resistor on the input to Pin 3 (see Figure 5) will eliminate package resonance between the RF input pin and the digital input. Specified attenuation error versus frequency performance is dependent upon this condition. Document No. 70-0161-05 UltraCMOS(R) RFIC Solutions PE4307 Product Specification Figure 4. Evaluation Board Layout Evaluation Kit The Digital Attenuator Evaluation Kit was designed to ease customer evaluation of the PE4307 DSA. Peregrine Specification 101/0112 J9 is used in conjunction with the supplied DC cable to supply VDD, GND, and -VDD. If use of the internal negative voltage generator is desired, then connect - VDD (black banana plug) to ground. If an external -VDD is desired, then apply -3V. J1 should be connected to the LPT1 port of a PC with the supplied control cable. The evaluation software is written to operate the DSA in serial mode, so switch 7 (P/S) on the DIP switch SW1 should be ON with all other switches off. Using the software, enable or disable each attenuation setting to the desired combined attenuation. The software automatically programs the DSA each time an attenuation state is enabled or disabled. Note: Jumper J6 supplies power to the evaluation board support circuits. To evaluate the Power Up options, first disconnect the control cable from the evaluation board. The control cable must be removed to prevent the PC port from biasing the control pins. During power up with P/S=1 high and LE=1, the default power-up signal attenuation is set to the value present on the five control bits on the five parallel data inputs (C0.5 to C8). This allows any one of the 32 attenuation settings to be specified as the power-up state. During power up with P/S=0 high and LE=0, the control bits are automatically set to one of two possible values presented through the PUP interface. These two values are selected by the power-up control bit, PUP2, as shown in Table 6. Figure 5. Evaluation Board Schematic Peregrine Specification 102/0142 Pins 1 and 7 are open and may be connected to any bias. Note: Resistor on pin 3 is required and should be placed as close to the part as possible to avoid package resonance and meet error specifications over frequency. Document No. 70-0161-05 www.psemi.com (c)2003-2013 Peregrine Semiconductor Corp. All rights reserved. Page 3 of 11 PE4307 Product Specification Typical Performance Data @ 25C, VDD = 3.0V Figure 6. Insertion Loss (Zo = 75 ohms) Figure 7. Attenuation at Major steps 0 16 -0.5 15.5dB 14 -40C 12 25C 85C -1.5 Attenuation (dB) Insertion Loss (dB) -1 -2 -2.5 10 8dB 8 1dB 6 0.5dB -3 4 -3.5 2 -4 2dB 0 0 500 1000 1500 2000 0 500 RF Frequency (MHz) 1000 1500 2000 RF Frequency (MHz) Figure 8. Input Return Loss at Major Attenuation Steps (Zo = 75 ohms) Figure 9. Output Return Loss at Major Attenuation Steps (Zo = 75 ohms) 0 0 -5 -10 Output Return loss (dB) Input Return Loss (dB) 4dB -10 -15 -20 4dB 8dB -20 -30 -40 -25 15.5dB -50 -30 0 500 1000 1500 RF Frequency (MHz) (c)2003-2013 Peregrine Semiconductor Corp. All rights reserved. Page 4 of 11 2000 0 500 1000 1500 2000 RF Frequency (MHz) Document No. 70-0161-05 UltraCMOS(R) RFIC Solutions PE4307 Product Specification Typical Performance Data @ 25C, VDD = 3.0V Figure 11. Attenuation Error Vs. Attenuatio Setting Figure 10. Attenuation Error Vs. Frequency 1 0.5 10Mhz 250Mhz 500Mhz 750Mhz 1010Mhz 1210Mhz 0 Attenuation Error (dB) Attenuation Error (dB) 0.5 -0.5 8dB 15.5dB -1 0 -0.5 -1.5 -1 -2 0 500 1000 1500 0 2000 2 4 8 10 12 14 16 Attenuation Setting (dB) RF Frequency (MHz) Figure 12. Input IP3 vs. Frequency (Zo = 50 ohms) Figure 13. Input 1 dB Compression (Zo = 50 ohms) 60 40 55 35 50 30 1dB Compression (dBm) Input IP3 (dBm) 6 45 40 35 25 20 15 30 10 25 5 0 20 0 500 1000 1500 RF Frequency (MHz) 2000 0 500 1000 1500 2000 RF Frequency (MHz) Note: Positive attenuation error indicates higher attenuation than target value Document No. 70-0161-05 www.psemi.com (c)2003-2013 Peregrine Semiconductor Corp. All rights reserved. Page 5 of 11 PE4307 Product Specification Typical Performance Data @ 25C, VDD = 3.0V Figure 15. Attenuation Error Vs. Attenuation Setting 0.4 0.4 0.3 0.3 0.2 0.2 Attenuation Error (dB) Attenuation Error (dB) Figure 14. Attenuation Error Vs. Attenuation Setting 0.1 0 -0.1 10MHz, -40C 10MHz, 25C -0.2 0.1 0 -0.1 500MHz, -40C -0.2 10MHz, 85C 500MHz, 25C -0.3 -0.3 -0.4 500MHz, 85C -0.4 0 2 4 6 8 10 12 14 16 0 2 4 Attenuation Setting (dB) 0.4 0.3 0.3 0.2 0.2 1000MHz, -40C 1000MHz, 25C -0.1 -0.2 Attenuation Error (dB) Attenuation Error (dB) 10 12 14 16 Figure 17. Attenuation Error Vs. Attenuation Setting 0.4 0 8 Attenuation Setting (dB) Figure 16. Attenuation Error Vs. Attenuation Setting 0.1 6 0.1 0 1200MHz, -40C -0.1 -0.2 -0.3 -0.3 1200MHz, 85C 1200MHz, 25C 1000MHz, 85C -0.4 -0.4 0 2 4 6 8 10 12 14 Attenuation Setting (dB) 16 0 2 4 6 8 10 12 14 16 Attenuation Setting (dB) Note: Positive attenuation error indicates higher attenuation than target value (c)2003-2013 Peregrine Semiconductor Corp. All rights reserved. Page 6 of 11 Document No. 70-0161-05 UltraCMOS(R) RFIC Solutions PE4307 Product Specification Programming Options Parallel/Serial Selection Either a parallel or serial interface can be used to control the PE4307. The P/S bit provides this selection, with P/S = LOW selecting the parallel interface and P/S = HIGH selecting the serial interface. Parallel / Direct Mode Interface The parallel interface consists of five CMOScompatible control lines that select the desired attenuation state, as shown in Table 5. The parallel interface timing requirements are defined by Figure 19 (Parallel Interface Timing Diagram), Table 9 (Parallel Interface AC Characteristics), and switching speed (Table 1). For latched parallel programming, the Latch Enable (LE) should be held LOW while changing attenuation state control values, then pulse LE HIGH to LOW (per Figure 19) to latch new attenuation state into device. For direct parallel programming, the Latch Enable (LE) line should be pulled HIGH. Changing attenuation state control values will change device state to new attenuation. Direct Mode is ideal for manual control of the device (using hardwire, switches, or jumpers). Table 5. Truth Table P/S C8 C4 C2 C1 C0.5 Attenuation State 0 0 0 0 0 0 Reference Loss 0 0 0 0 0 1 0.5 dB 0 0 0 0 1 0 1 dB 0 0 0 1 0 0 2 dB 0 0 1 0 0 0 4 dB 0 1 0 0 0 0 8 dB 0 1 1 1 1 1 15.5 dB Note: Not all 32 possible combinations of C0.5-C8 are shown in table Serial Interface The PE4307's serial interface is a 6-bit serial-in, parallel-out shift register buffered by a transparent latch. The latch is controlled by three CMOScompatible signals: Data, Clock, and Latch Enable (LE). The Data and Clock inputs allow data to be Document No. 70-0161-05 www.psemi.com serially entered into the shift register, a process that is independent of the state of the LE input. The LE input controls the latch. When LE is HIGH, the latch is transparent and the contents of the serial shift register control the attenuator. When LE is brought LOW, data in the shift register is latched. The shift register should be loaded while LE is held LOW to prevent the attenuator value from changing as data is entered. The LE input should then be toggled HIGH and brought LOW again, latching the new data. The start bit (B5) of the data should always be low to prevent an unknown state in the device. The timing for this operation is defined by Figure 18 (Serial Interface Timing Diagram) and Table 8 (Serial Interface AC Characteristics). Power-up Control Settings The PE4307 always assumes a specifiable attenuation setting on power-up. This feature exists for both the Serial and Parallel modes of operation, and allows a known attenuation state to be established before an initial serial or parallel control word is provided. When the attenuator powers up in Serial mode (P/S = 1), the five control bits are set to whatever data is present on the five parallel data inputs (C0.5 to C8). This allows any one of the 32 attenuation settings to be specified as the power-up state. When the attenuator powers up in Parallel mode (P/S = 0) with LE = 0, the control bits are automatically set to one of two possible values. These two values are selected by the power-up control bit, PUP2, as shown in Table 6 (Power-Up Truth Table, Parallel Mode). Table 6. Power-Up Truth Table, Parallel Interface Mode P/S LE 0 0 PUP2 Attenuation State 0 0 0 1 8 dB 0 1 X Defined by C0.5-C8 Reference Loss Note: Power up with LE=1 provides normal parallel operation with C0.5-C8, and PUP2 is not active (c)2003-2013 Peregrine Semiconductor Corp. All rights reserved. Page 7 of 11 PE4307 Product Specification Figure 18. Serial Interface Timing Diagram Table 7. 5-Bit Attenuator Serial Programming Register Map LE Clock Data MSB tLESUP tSDHLD B4 B3 B2 B1 B0 0 C8 C4 C2 C1 C0.5 MSB (first in) LSB tSDSUP B5 tLEPW LSB (last in) Note: The start bit (B5) must always be low to prevent an unknown state in the device Figure 19. Parallel Interface Timing Diagram LE Parallel Data C8:C0.5 tPDSUP tLEPW tPDHLD Table 8. Serial Interface AC Characteristics Table 9. Parallel Interface AC Characteristics VDD = 3.0V, -40C < TA < 85C, unless otherwise specified VDD = 3.0V, -40C < TA < 85C, unless otherwise specified Symbol Parameter Min Max Unit Symbol 10 MHz fClk Serial data clock frequency (Note 1) tClkH Serial clock HIGH time 30 ns tClkL Serial clock LOW time 30 ns tLESUP LE set-up time after last clock falling edge 10 ns tLEPW LE minimum pulse width 30 ns tSDSUP Serial data set-up time before clock rising edge 10 ns tSDHLD Serial data hold time after clock falling edge 10 ns Parameter Min Max Unit tLEPW LE minimum pulse width 10 -- ns tPDSUP Data set-up time before rising edge of LE 10 -- ns tPDHLD Data hold time after falling edge of LE 10 -- ns Note 1: fClk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify fclk specification (c)2003-2013 Peregrine Semiconductor Corp. All rights reserved. Page 8 of 11 Document No. 70-0161-05 UltraCMOS(R) RFIC Solutions PE4307 Product Specification Figure 20. Package Drawing 20-lead 4x4 mm QFN 0.10 C A 4.00 2.150.05 (2X) 11 0.28 (x20) 0.550.05 (x20) B 15 0.75 (x20) 0.50 10 16 2.150.05 4.00 0.230.05 (x20) 0.10 C 6 0.18 0.18 TOP VIEW 4.40 1 2.00 Pin #1 Corner 2.20 20 5 (2X) 0.50 0.435 SQ REF BOTTOM VIEW 2.20 4.40 RECOMMENDED LAND PATTERN 181-0023 0.10 C 0.90 MAX 0.05 C 0.10 0.05 C A B C ALL FEATURES SEATING PLANE 0.203 SIDE VIEW 0.05 Document No. 70-0161-05 www.psemi.com C (c)2003-2013 Peregrine Semiconductor Corp. All rights reserved. Page 9 of 11 PE4307 Product Specification Figure 21. Top Marking Specifications 4307 YYWW ZZZZZ YYWW = Date Code ZZZZZ = Last five digits of PSC Lot Number Figure 22. Tape and Reel Drawing Table 10. Ordering Information Order Code Part Marking Description Package Shipping Method 4307-01 4307 PE4307-20MLP 4x4mm-75A 20-lead 4x4 mm QFN 75 units / Tube 4307-02 4307 PE4307-20MLP 4x4mm-3000C 20-lead 4x4 mm QFN 3000 units / T&R 4307-00 PE4307-EK PE4307-20MLP 4x4mm-EK Evaluation Kit 1 / Box 4307-52 4307 PE4307G-20MLP 4x4mm-3000C Green 20-lead 4x4 mm QFN 3000 units / T&R (c)2003-2013 Peregrine Semiconductor Corp. All rights reserved. Page 10 of 11 Document No. 70-0161-05 UltraCMOS(R) RFIC Solutions PE4307 Product Specification Sales Contact and Information For Sales and contact information please visit www.psemi.com. Advance Information: The product is in a formative or design stage. The datasheet contains design target specifications for product development. Specifications and features may change in any manner without notice. Preliminary Specification: The datasheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product. Product Specification: The datasheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification Form). The information in this datasheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. Document No. 70-0161-05 www.psemi.com No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and DuNE are trademarks of Peregrine Semiconductor Corp. (c)2003-2013 Peregrine Semiconductor Corp. All rights reserved. Page 11 of 11