PE4307-02 - Peregrine Semiconductor Corp.

Document No. 70-0161-05 │www.psemi.com

Page 1 of 11

The PE4307 is a high linearity, 5-bit RF Digital Step

Attenuator (DSA) covering a 15.5 dB attenuation range in

0.5 dB steps. The device is pin compatible with the PE430x

series. This 75-ohm RF DSA provides both parallel (latched

or direct mode) and serial CMOS control interface, operates

on a single 3-volt supply and maintains high attenuation

accuracy over frequency and temperature. It also has a

unique control interface that allows the user to select an

initial attenuation state at power-up. The PE4307 exhibits

very low insertion loss and low power consumption. This

functionality is delivered in a 4x4 mm QFN footprint.

The PE4307 is manufactured on Peregrine’s UltraCMOS®

process, a patented variation of silicon-on-insulator (SOI)

technology on a sapphire substrate, offering the performance

of GaAs with the economy and integration of conventional

CMOS.

Product Specification

75Ω RF Digital Attenuator

5-bit, 15.5 dB, 1 – 2000 MHz

Product Description

Figure 1. Functional Schematic Diagram

PE4307

Features

 Attenuation: 0.5 dB steps to 15.5 dB

 Flexible parallel and serial programming

interfaces

 Latched or direct mode

 Unique power-up state selection

 Positive CMOS control logic

 High attenuation accuracy and linearity

over temperature and frequency

 Very low power consumption

 Single-supply operation

 75Ω impedance

 Pin compatible with PE430x series

 Packaged in a 20-lead 4x4 mm QFN

Table 1. Electrical Specifications @ +25°C, VDD = 3.0V

Notes: 1. Device Linearity will begin to degrade below 1 MHz

2. Max input rating in Table 3 & Figures on Pages 4 to 6 for data across frequency

3. Note Absolute Maximum in Table 3

4. Measured in a 50Ω system

Control Logic Interface

Parallel Control

Power-Up Control

Serial Control

RF Input RF Output

Switched Attenuator Array

5

3

1

Parameter Test Condition Frequency Minimum Typical Maximum Unit

Operation Frequency 1 2000 MHz

Insertion Loss1 1 MHz ≤ 1.2 GHz - 1.4 1.95 dB

Attenuation Accuracy Any Bit or Bit

Combination 1 MHz ≤ 1.2 GHz - - ±(0.15 + 4% of atten setting)

Not to exceed +0.25 dB

dB

1 dB Compression3,4 1 MHz ≤ 1.2 GHz 30 34 - dBm

Input IP31,2,4 Two-tone inputs up to

+18 dBm 1 MHz ≤ 1.2 GHz - 52 - dBm

Return Loss Zo = 75 ohms 1 MHz ≤ 1.2 GHz 10 13 - dB

Switching Speed 50% control to 0.5 dB

of final value - - 1

s

Figure 2. Package Type

20-lead 4x4 mm QFN

71-0007

Product Specification

PE4307

Page 2 of 11

Table 2. Pin Descriptions

Electrostatic Discharge (ESD) Precautions

When handling this UltraCMOS® device, observe the

same precautions that you would use with other

ESD-sensitive devices. Although this device

contains circuitry to protect it from damage due to

ESD, precautions should be taken to avoid

exceeding the rate specified in Table 3.

Exposed Solder Pad Connection

The exposed solder pad on the bottom of the

package must be grounded for proper device

operation.

Notes: 1. Both RF ports must be held at 0 VDC or DC blocked with an external

series capacitor

2. Latch Enable (LE) has an internal 100 kΩ resistor to VDD

3. Connect pin 12 to GND to enable internal negative voltage

generator. Connect pin 12 to VSS (-VDD) to bypass and disable

internal negative voltage generator

4. Place a 10 kΩ resistor in series, as close to pin as possible to avoid

frequency resonance. See “Resistor on 3” paragraph

Figure 15. Pin Configuration (Top View)

Latch-Up Avoidance

Unlike conventional CMOS devices, UltraCMOS®

devices are immune to latch-up.

Switching Frequency

The PE4307 has a maximum 25 kHz switching rate.

VDD

N/C

PUP2

VDD

GND

1

20

19

18

17

16

15

14

13

12

11

6

7

8

9

10

2

3

4

5

N/C

RF1

Data

Clock

LE GND

Vss/GND

P/S

RF2

C8

C4

C2

GND

C1

C0.5

20-lead

QFN

4x4mm

Exposed Solder Pad

Pin No. Pin

Name Description

1 N/C No connect

2 RF1 RF port (Note 1)

3 Data Serial interface data input (Note 4)

4 Clock Serial interface clock input

5 LE Latch Enable input (Note 2)

6 VDD Power supply pin

7 N/C No connect

8 PUP2 Power-up selection bit

9 VDD Power supply pin

10 GND Ground connection

11 GND Ground connection

12 Vss/GND Negative supply voltage or GND

connection (Note 3)

13 P/S Parallel/Serial mode select

14 RF2 RF port (Note 1)

15 C8 Attenuation control bit, 8 dB

16 C4 Attenuation control bit, 4 dB

17 C2 Attenuation control bit, 2 dB

18 GND Ground connection.

19 C1 Attenuation control bit, 1 dB

20 C0.5 Attenuation control bit, 0.5 dB

Paddle GND Ground for proper operation

Resistor on Pin 3

A 10 kΩ resistor on the input to Pin 3 (see Figure 5)

will eliminate package resonance between the RF

input pin and the digital input. Specified attenuation

error versus frequency performance is dependent

upon this condition.

Table 3. Absolute Maximum Ratings

Table 4. Operating Ranges

Symbol Parameter/Condition Min Max Unit

VDD Power supply voltage -0.3 4.0 V

VI Voltage on any input -0.3 VDD+

0.3 V

TST Storage temperature range -65 150 °C

PIN Input power (50Ω) +30 dBm

VESD ESD voltage (Human Body

Model) 500 V

Parameter Min Typ Max Unit

VDD Power Supply

Voltage 2.7 3.0 3.3 V

IDD Power Supply

Current 100 μA

Digital Input High 0.7xVDD V

Digital Input Low 0.3xVDD V

Digital Input Leakage 1 μA

Input Power +24 dBm

Temperature range -40 85 °C

Product Specification

PE4307

Document No. 70-0161-05 │www.psemi.com

Page 3 of 11

Evaluation Kit

The Digital Attenuator Evaluation Kit was designed to

ease customer evaluation of the PE4307 DSA.

J9 is used in conjunction with the supplied DC cable to

supply VDD, GND, and –VDD. If use of the internal

negative voltage generator is desired, then connect –

VDD (black banana plug) to ground. If an external –VDD

is desired, then apply -3V.

J1 should be connected to the LPT1 port of a PC with

the supplied control cable. The evaluation software is

written to operate the DSA in serial mode, so switch 7

(P/S) on the DIP switch SW1 should be ON with all

other switches off. Using the software, enable or

disable each attenuation setting to the desired

combined attenuation. The software automatically

programs the DSA each time an attenuation state is

enabled or disabled.

Note: Jumper J6 supplies power to the evaluation

board support circuits.

To evaluate the Power Up options, first disconnect the

control cable from the evaluation board. The control

cable must be removed to prevent the PC port from

biasing the control pins.

During power up with P/S=1 high and LE=1, the default

power-up signal attenuation is set to the value present

on the five control bits on the five parallel data inputs

(C0.5 to C8). This allows any one of the 32 attenuation

settings to be specified as the power-up state.

During power up with P/S=0 high and LE=0, the control

bits are automatically set to one of two possible values

presented through the PUP interface. These two values

are selected by the power-up control bit, PUP2, as

shown in Table 6.

Pins 1 and 7 are open and may be connected to any

bias.

Figure 4. Evaluation Board Layout

Figure 5. Evaluation Board Schematic

Note: Resistor on pin 3 is required and

should be placed as close to the part as

possible to avoid package resonance and

meet error specifications over frequency.

Peregrine Specification 102/0142

Figure 4. Evaluation Board Layout

Peregrine Specification 101/0112

Product Specification

PE4307

Page 4 of 11

-50

-40

-30

-20

-10

0

0 500 1000 1500 2000

Output Return loss (dB)

RF Frequency (MHz)

-30

-25

-20

-15

-10

-5

0

0 500 1000 1500 2000

Input Return Loss (dB)

RF Frequency (MHz)

15.5dB

8dB

4dB

0

2

4

6

8

10

12

14

16

0 500 1000 1500 2000

Attenuation (dB)

RF Frequency (MHz)

15.5dB

8dB

4dB

2dB

1dB

0.5dB

-4

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

0

0 500 1000 1500 2000

Insertion Loss (dB)

RF Frequency (MHz)

-40C

25C

85C

Typical Performance Data @ 25°C, VDD = 3.0V

Figure 7. Attenuation at Major steps

Figure 9. Output Return Loss at Major

Attenuation Steps (Zo = 75 ohms)

Figure 8. Input Return Loss at Major

Attenuation Steps (Zo = 75 ohms)

Figure 6. Insertion Loss (Zo = 75 ohms)

Product Specification

PE4307

Document No. 70-0161-05 │www.psemi.com

Page 5 of 11

0

5

10

15

20

25

30

35

40

0 500 1000 1500 2000

1dB Compression (dBm)

RF Frequency (MHz)

20

25

30

35

40

45

50

55

60

0 500 1000 1500 2000

Input IP3 (dBm)

RF Frequency (MHz)

-1

-0.5

0

0.5

1

0246810121416

10Mhz

250Mhz

500Mhz

750Mhz

1010Mhz

1210Mhz

Attenuation Error (dB)

Attenuation Setting (dB)

-2

-1.5

-1

-0.5

0

0.5

0 500 1000 1500 2000

Attenuation Error (dB)

RF Frequency (MHz)

15.5dB

8dB

Figure 11. Attenuation Error Vs. Attenuatio

Setting

Figure 13. Input 1 dB Compression (Zo = 50 ohms) Figure 12. Input IP3 vs. Frequency (Zo = 50 ohms)

Figure 10. Attenuation Error Vs. Frequency

Note: Positive attenuation error indicates higher attenuation than target value

Typical Performance Data @ 25°C, VDD = 3.0V

Product Specification

PE4307

Page 6 of 11

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0246810121416

Attenuation Error (dB)

Attenuation Setting (dB)

1000MHz, -40C

1000MHz, 85C

1000MHz, 25C

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0246810121416

Attenuation Error (dB)

Attenuation Setting (dB)

1200MHz, -40C

1200MHz, 25C

1200MHz, 85C

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0246810121416

Attenuation Error (dB)

Attenuation Setting (dB)

10MHz, -40C 10MHz, 25C

10MHz, 85C

-0.4

-0.3

-0.2

-0.1

0

0.1

0.2

0.3

0.4

0246810121416

Attenuation Error (dB)

Attenuation Setting (dB)

500MHz, 85C

500MHz, -40C

500MHz, 25C

Figure 15. Attenuation Error Vs. Attenuation

Setting

Figure 14. Attenuation Error Vs. Attenuation

Setting

Figure 16. Attenuation Error Vs. Attenuation

Setting

Figure 17. Attenuation Error Vs. Attenuation

Setting

Note: Positive attenuation error indicates higher attenuation than target value

Typical Performance Data @ 25°C, VDD = 3.0V

Product Specification

PE4307

Document No. 70-0161-05 │www.psemi.com

Page 7 of 11

Programming Options

Parallel/Serial Selection

Either a parallel or serial interface can be used to

control the PE4307. The P/S bit provides this

selection, with P/S = LOW selecting the parallel

interface and P/S = HIGH selecting the serial

interface.

Parallel / Direct Mode Interface

The parallel interface consists of five CMOS-

compatible control lines that select the desired

attenuation state, as shown in Table 5.

The parallel interface timing requirements are

defined by Figure 19 (Parallel Interface Timing

Diagram), Table 9 (Parallel Interface AC

Characteristics), and switching speed (Table 1).

For latched parallel programming, the Latch Enable

(LE) should be held LOW while changing attenuation

state control values, then pulse LE HIGH to LOW

(per Figure 19) to latch new attenuation state into

device.

For direct parallel programming, the Latch Enable

(LE) line should be pulled HIGH. Changing

attenuation state control values will change device

state to new attenuation. Direct Mode is ideal for

manual control of the device (using hardwire,

switches, or jumpers).

Table 5. Truth Table

Serial Interface

The PE4307’s serial interface is a 6-bit serial-in,

parallel-out shift register buffered by a transparent

latch. The latch is controlled by three CMOS-

compatible signals: Data, Clock, and Latch Enable

(LE). The Data and Clock inputs allow data to be

serially entered into the shift register, a process that

is independent of the state of the LE input.

The LE input controls the latch. When LE is HIGH,

the latch is transparent and the contents of the serial

shift register control the attenuator. When LE is

brought LOW, data in the shift register is latched.

The shift register should be loaded while LE is held

LOW to prevent the attenuator value from changing

as data is entered. The LE input should then be

toggled HIGH and brought LOW again, latching the

new data. The start bit (B5) of the data should

always be low to prevent an unknown state in the

device. The timing for this operation is defined by

Figure 18 (Serial Interface Timing Diagram) and

Table 8 (Serial Interface AC Characteristics).

Power-up Control Settings

The PE4307 always assumes a specifiable

attenuation setting on power-up. This feature exists

for both the Serial and Parallel modes of operation,

and allows a known attenuation state to be

established before an initial serial or parallel control

word is provided.

When the attenuator powers up in Serial mode

(P/S = 1), the five control bits are set to whatever

data is present on the five parallel data inputs (C0.5

to C8). This allows any one of the 32 attenuation

settings to be specified as the power-up state.

When the attenuator powers up in Parallel mode

(P/S = 0) with LE = 0, the control bits are

automatically set to one of two possible values.

These two values are selected by the power-up

control bit, PUP2, as shown in Table 6 (Power-Up

Truth Table, Parallel Mode).

Table 6. Power-Up Truth Table, Parallel

Interface Mode

Note: Power up with LE=1 provides normal parallel operation with C0.5-C8,

and PUP2 is not active

P/S C8 C4 C2 C1 C0.5 Attenuation

State

0 0 0 0 0 0 Reference Loss

0 0 0 0 0 1 0.5 dB

0 0 0 0 1 0 1 dB

0 0 0 1 0 0 2 dB

0 0 1 0 0 0 4 dB

0 1 0 0 0 0 8 dB

0 1 1 1 1 1 15.5 dB

Note: Not all 32 possible combinations of C0.5-C8 are shown in table P/S LE PUP2 Attenuation State

0 0 0 Reference Loss

0 0 1 8 dB

0 1 X Defined by C0.5-C8

Product Specification

PE4307

Page 8 of 11

Table 7. 5-Bit Attenuator Serial Programming

Register Map

Table 9. Parallel Interface AC Characteristics

Figure 19. Parallel Interface Timing Diagram

Table 8. Serial Interface AC Characteristics

Figure 18. Serial Interface Timing Diagram

VDD = 3.0V, -40°C < TA < 85°C, unless otherwise specified VDD = 3.0V, -40°C < TA < 85°C, unless otherwise specified

Note: The start bit (B5) must always be low to prevent an unknown state in the

device

Note 1: fClk is verified during the functional pattern test. Serial programming

sections of the functional pattern are clocked at 10 MHz to verify fclk

specification

LE

Clock

Data MSB LSB

t

LESUP

t

SDSUP

t

SDHLD

t

LEPW

B5 B4 B3 B2 B1 B0

0 C8C4C2C1C0.5



LSB (last in)MSB (first in)

t

PDSUP

t

PDHLD

LE

t

LEPW

Parallel Data

C8:C0.5

Symbol Parameter Min Max Unit

fClk Serial data clock

frequency (Note 1) 10 MHz

tClkH Serial clock HIGH time 30 ns

tClkL Serial clock LOW time 30 ns

tLESUP LE set-up time after last

clock falling edge 10 ns

tLEPW LE minimum pulse width 30 ns

tSDSUP Serial data set-up time

before clock rising edge 10 ns

tSDHLD Serial data hold time

after clock falling edge 10 ns

Symbol Parameter Min Max Unit

tLEPW LE minimum pulse width 10 -- ns

tPDSUP Data set-up time before

rising edge of LE 10 -- ns

tPDHLD Data hold time after

falling edge of LE 10 -- ns

Product Specification

PE4307

Document No. 70-0161-05 │www.psemi.com

Page 9 of 11

Figure 20. Package Drawing

20-lead 4x4 mm QFN

TOP VIEW BOTTOM VIEW

SIDE VIEW

4.00

0.90 MAX

Pin #1 Corner

RECOMMENDED LAND PATTERN

0.50

2.15±0.05

0.55±0.05

(x20)

2.15±0.05

0.18

0.435 SQ

REF

0.28

(x20)

0.75

(x20)

0.50

4.40

2.20

A

0.10 C

(2X)

C

0.10 C

0.05 C

SEATING PLANE

B

0.10 C

(2X)

0.10 C A B

0.05 C

ALL FEATURES

0.05

0.203

0.23±0.05

(x20)

2.00

0.18

1

5

6

10

11 15

16

20

181-0023

Product Specification

PE4307

Page 10 of 11

Figure 21. Top Marking Specifications

Figure 22. Tape and Reel Drawing

4307

YYWW

ZZZZZ YYWW = Date Code

ZZZZZ = Last five digits of PSC Lot Number

Table 10. Ordering Information

Order Code Part Marking Description Package Shipping Method

4307-01 4307 PE4307-20MLP 4x4mm-75A 20-lead 4x4 mm QFN 75 units / Tube

4307-02 4307 PE4307-20MLP 4x4mm-3000C 20-lead 4x4 mm QFN 3000 units / T&R

4307-00 PE4307-EK PE4307-20MLP 4x4mm-EK Evaluation Kit 1 / Box

4307-52 4307 PE4307G-20MLP 4x4mm-3000C Green 20-lead 4x4 mm QFN 3000 units / T&R

Product Specification

PE4307

Document No. 70-0161-05 │www.psemi.com

Page 11 of 11

Advance Information: The product is in a formative or design stage. The datasheet contains

design target specifications for product development. Specifications and features may change in

any manner without notice. Preliminary Specification: The datasheet contains preliminary data.

Additional data may be added at a later date. Peregrine reserves the right to change specifications

at any time without notice in order to supply the best possible product. Product Specification:

The datasheet contains final data. In the event Peregrine decides to change the specifications,

Peregrine will notify customers of the intended changes by issuing a CNF (Customer Notification

Form).

The information in this datasheet is believed to be reliable. However, Peregrine assumes no

liability for the use of this information. Use shall be entirely at the user’s own risk.

No patent rights or licenses to any circuits described in this datasheet are implied or granted to any third

party.

Peregrine’s products are not designed or intended for use in devices or systems intended for surgical

implant, or in other applications intended to support or sustain life, or in any application in which the

failure of the Peregrine product could create a situation in which personal injury or death might occur.

Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of

the use of its products in such applications.

The Peregrine name, logo, UltraCMOS and UTSi are registered trademarks and HaRP, MultiSwitch and

DuNE are trademarks of Peregrine Semiconductor Corp.

Sales Contact and Information

For Sales and contact information please visit www.psemi.com.