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FSB50550UTD Rev. A
FSB50550UTD Smart Power Module (SPM®)
Motion-SPM
April 2010
TM
FSB50550UTD
Smart Power Module (SPM®)
Features
• 500V RDS(on)=1.4W(max) 3-phase FRFET inverter including
high voltage integrated circuit (HVIC)
• 3 divided negative dc-link terminals for inverter current sens-
ing applications
• HVIC for gate driving and undervoltage protection
• 3/5V CMOS/TTL compatible, active-high interface
• Optimized for low electromagnetic interference
• Isolation voltage rating of 1500Vrms for 1min.
• Extended VB pin for PCB isolatio
• Embedded bootstrap diode in the package
General Description
FSB50550UTD is a tiny smart power module (SPM®) based on
FRFET technology as a compact inverter solution for small
power motor drive applications such as fan motors and water
suppliers. It is composed of 6 fast-recovery MOSFET (FRFET),
and 3 half-bridge HVICs for FRFET gate driving.
FSB50550UTD provides low electromagnetic interference (EMI)
characteristics with optimized switching speed. Moreover, since
it employs FRFET as a power switch, it has much better
ruggedness and larger safe operation area (SOA) than that of
an IGBT-based power module or one-chip solution. The
package is optimized for the thermal performance and
compactness for the use in the built-in motor application and
any other application where the assembly space is concerned.
FSB50550UTD is the most solution for the compact inverter
providing the energy efficiency, compactness, and low
electromagnetic interference.
Absolute Maximum Ratings
Symbol Parameter Conditions Rating Units
VPN
DC Link Input Voltage,
Drain-source Voltage of each FRFET 500 V
ID25 Each FRFET Drain Current, Continuous TC = 25°C 2.0 A
ID80 Each FRFET Drain Current, Continuous TC = 80°C 1.5 A
IDP Each FRFET Drain Current, Peak TC = 25°C, PW < 100ms 5 A
PDMaximum Power Dissipation TC = 25°C, Each FRFET 14.5 W
VCC Control Supply Voltage Applied between VCC and COM 20 V
VBS High-side Bias Voltage Applied between VB(U)-U, VB(V)-V, VB(W)-W 20 V
VIN Input Signal Voltage Applied between IN and COM -0.3 ~ VCC+0.3 V
TJOperating Junction Temperature -40 ~ 150 °C
TSTG Storage Temperature -40 ~ 125 °C
RqJC Junction to Case Thermal Resistance Each FRFET under inverter operating con-
dition (Note 1) 8.6 °C/W
VISO Isolation Voltage 60Hz, Sinusoidal, 1 minute, Connection
pins to heatsink 1500 Vrms
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FSB50550UTD Rev. A
FSB50550UTD Smart Power Module (SPM®)
Pin Descriptions
Note:
Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside SPM®. External connections should be made as indicated in Fig-
ure 2 and 5.
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
Pin Number Pin Name Pin Description
1 COM IC Common Supply Ground
2 VB(U) Bias Voltage for U Phase High Side FRFET Driving
3 VCC(U) Bias Voltage for U Phase IC and Low Side FRFET Driving
4 IN(UH) Signal Input for U Phase High-side
5 IN(UL) Signal Input for U Phase Low-side
6 NC No Connection
7 VB(V) Bias Voltage for V Phase High Side FRFET Driving
8 VCC(V) Bias Voltage for V Phase IC and Low Side FRFET Driving
9 IN(VH) Signal Input for V Phase High-side
10 IN(VL) Signal Input for V Phase Low-side
11 NC No Connection
12 VB(W) Bias Voltage for W Phase High Side FRFET Driving
13 VCC(W) Bias Voltage for W Phase IC and Low Side FRFET Driving
14 IN(WH) Signal Input for W Phase High-side
15 IN(WL) Signal Input for W Phase Low-side
16 NC No Connection
17 P Positive DC–Link Input
18 U, VS(U) Output for U Phase & Bias Voltage Ground for High Side FRFET Driving
19 NUNegative DC–Link Input for U Phase
20 NVNegative DC–Link Input for V Phase
21 V, VS(V) Output for V Phase & Bias Voltage Ground for High Side FRFET Driving
22 NWNegative DC–Link Input for W Phase
23 W, VS(W) Output for W Phase & Bias Voltage Ground for High Side FRFET Driving
COM
VCC
LIN
HIN
VB
HO
VS
LO
COM
VCC
LIN
HIN
VB
HO
VS
LO
COM
VCC
LIN
HIN
VB
HO
VS
LO
(1) COM
(2) VB(U)
(3) VCC(U)
(4) IN(UH)
(5) IN(UL)
(6) NC
(7) VB(V)
(8) VCC(V)
(9) IN(VH)
(10) IN(VL)
(11) NC
(12) VB(W)
(13) VCC(W)
(14) IN(WH)
(15) IN(WL)
(16) NC
(17) P
(18) U,Vs(u)
(19) NU
(20) NV
(21) V,Vs(v)
(22) NW
(23) W,Vs(w)
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FSB50550UTD Rev. A
FSB50550UTD Smart Power Module (SPM®)
Electrical Characteristics (TJ = 25°C, VCC=VBS=15V Unless Otherwise Specified)
Inverter Part (Each FRFET Unless Otherwise Specified)
Control Part (Each HVIC Unless Otherwise Specified)
Bootstrap Diode Part
Note:
1. For the measurement point of case temperature TC, please refer to Figure 4 in page 5.
2. BVDSS is the absolute maximum voltage rating between drain and source terminal of each FRFET inside SPM®. VPN should be sufficiently less than this value considering the
effect of the stray inductance so that VDS should not exceed BVDSS in any case.
3. tON and tOFF include the propagation delay time of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the
field applcations due to the effect of different printed circuit boards and wirings. Please see Figure 5 for the switching time definition with the switching test circuit of Figure 6.
4. The peak current and voltage of each FRFET during the switching operation should be included in the safe operating area (SOA). Please see Figure 6 for the RBSOA test cir-
cuit that is same as the switching test circuit.
Symbol Parameter Conditions Min Typ Max Units
BVDSS
Drain-Source Breakdown
Voltage VIN= 0V, ID = 250mA (Note 2) 500 - - V
DBVDSS/
DTJ
Breakdown Voltage Tem-
perature Coefficient ID = 250mA, Referenced to 25°C - 0.53 - V
IDSS
Zero Gate Voltage
Drain Current VIN= 0V, VDS = 500V - - 250 mA
RDS(on)
Static Drain-Source
On-Resistance VCC = VBS = 15V, VIN = 5V, ID = 1.2A - 1.0 1.4 W
VSD
Drain-Source Diode
Forward Voltage VCC = VBS = 15V, VIN = 0V, ID = -1.2A - - 1.2 V
tON
Switching Times
VPN = 300V, VCC = VBS = 15V, ID = 1.2A
VIN = 0V « 5V
Inductive load L=3mH
High- and low-side FRFET switching
(Note 3)
- 600 - ns
tOFF - 500 - ns
trr - 100 - ns
EON - 60 - mJ
EOFF - 10 - mJ
RBSOA Reverse-bias Safe Oper-
ating Area
VPN = 400V, VCC = VBS = 15V, ID = IDP, VDS=BVDSS,
TJ = 150°C
High- and low-side FRFET switching (Note 4)
Full Square
Symbol Parameter Conditions Min Typ Max Units
IQCC Quiescent VCC Current VCC=15V, VIN=0V Applied between VCC and COM - - 160 mA
IQBS Quiescent VBS Current VBS=15V, VIN=0V Applied between VB(U)-U,
VB(V)-V, VB(W)-W - - 100 mA
UVCCD Low-side Undervoltage
Protection (Figure 7)
VCC Undervoltage Protection Detection Level 7.4 8.0 9.4 V
UVCCR VCC Undervoltage Protection Reset Level 8.0 8.9 9.8 V
UVBSD High-side Undervoltage
Protection (Figure 8)
VBS Undervoltage Protection Detection Level 7.4 8.0 9.4 V
UVBSR VBS Undervoltage Protection Reset Level 8.0 8.9 9.8 V
VIH ON Threshold Voltage Logic High Level Applied between IN and COM 2.9 - - V
VIL OFF Threshold Voltage Logic Low Level - - 0.8 V
IIH Input Bias Current VIN = 5V Applied between IN and COM - 10 20 mA
IIL VIN = 0V - - 2 mA
Symbol Parameter Conditions Rating Units
VRRM Maixmum Repetitive Reverse Voltage 500 V
IFForward Current TC = 25°C 0.5 A
IFP Forward Current (Peak) TC = 25°C, Under 1ms Pulse Width 2 A
TJOperating Junction Temperature -40 ~ 150 °C
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FSB50550UTD Rev. A
FSB50550UTD Smart Power Module (SPM®)
Bootstrap Diode Part
Note:
Built in bootstrap diode includes around 15 Ωresistance characteristic.
Figure 2. Built in Bootstrap Diode Characteristics
Package Marking & Ordering Information
Symbol Parameter Conditions Min. Typ. Max. Units
VFForward Voltage IF = 0.1A, TC = 25°C - 2.0 - V
trr Reverse Recovery Time IF = 0.1A, TC = 25°C - 80 - ns
Device Marking Device Package Reel Size Packing Type Quantity
FSB50550UTD FSB50550UTD SPM23-ED _ _ 15
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1.0
Built in Bootstrap Diode VF-IF Characteristic
TC=25℃
IF [A]
VF [V]
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FSB50550UTD Rev. A
FSB50550UTD Smart Power Module (SPM®)
Recommended Operating Conditions
Note:
(1) It is recommended the bootstrap diode D1 to have soft and fast recovery characteristics with 500-V rating
(2) Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above.
(3) RC coupling(R5 and C5) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. Signal input of SPM®is compatible with
standard CMOS or LSTTL outptus.
(4) Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. Bypass capacitors such as C1, C2
and C3 should have good high-frequency characteristics to absorb high-frequency ripple current.
Figure 3. Recommended CPU Interface and Bootstrap Circuit with Parameters
Note:
Attach the thermocouple on top of the heatsink-side of SPM® (between SPM® and heatsink if applied) to get the correct temperature measurement.
Figure 4. Case Temperature Measurement
Symbol Parameter Conditions Value Units
Min. Typ. Max.
VPN Supply Voltage Applied between P and N - 300 400 V
VCC Control Supply Voltage Applied between VCC and COM 13.5 15 16.5 V
VBS High-side Bias Voltage Applied between VB and output(U, V, W) 13.5 15 16.5 V
VIN(ON) Input ON Threshold Voltage Applied between IN and COM 3.0 - VCC V
VIN(OFF) Input OFF Threshold Voltage 0 - 0.6 V
tdead
Blanking Time for Preventing
Arm-short VCC=VBS=13.5 ~ 16.5V, TJ £ 150°C 1.0 - - ms
fPWM PWM Switching Frequency TJ £ 150°C - 15 - kHz
COM
VCC
LIN
HIN
VB
HO
VS
LO
P
NR3
Inverter
Output
C3
C1
Micom
15-V Line
10mFOne-Leg Diagram of SPM
These values depend on PWM
control algorithm
* Example of bootstrap paramters:
C1 = C2 = 1mF ceramic capacitor,
R5
C5
HIN LIN
VDC
0 0
0 1
1 0
1 1
Open Open
Output
Z
0
VDC
Forbidden
Z
Note
Both FRFET Off
Low-side FRFET On
High-side FRFET On
Shoot-through
Same as (0, 0)
C2
Case Temperature(Tc)
Detecting Point
14.50mm
3.80mm
MOSFET Case Temperature(Tc)
Detecting Point
14.50mm
3.80mm
MOSFET
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FSB50550UTD Rev. A
FSB50550UTD Smart Power Module (SPM®)
Figure 5. Switching Time Definition
Figure 6. Switching and RBSOA(Single-pulse) Test Circuit (Low-side)
Figure 7. Undervoltage Protection (Low-side)
Figure 8. Undervoltage Protection (High-side)
tON trr
Irr
100% of ID120% of ID
(a) Turn-on
tOFF
(b) Turn-off
ID
VDS
VDS
ID
VIN VIN
10% of ID
COM
VCC
LIN
HIN
VB
HO
VS
LO
One-leg Diagram of SPM
ID
VCC
CBS
L VDC
+
VDS
-
UVCCD
UVCCR
Input Signal
UV Protection
Status
Low-side Supply, VCC
MOSFET Current
RESET DETECTION RESET
UVBSD
UVBSR
Input Signal
UV Protection
Status
High-side Supply, VBS
MOSFET Current
RESET DETECTION RESET
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FSB50550UTD Rev. A
FSB50550UTD Smart Power Module (SPM®)
Figure 9. Example of Application Circuit
COM
VCC
LIN
HIN
VB
HO
VS
LO
COM
VCC
LIN
HIN
VB
HO
VS
LO
COM
VCC
LIN
HIN
VB
HO
VS
LO
(1) COM
(2) VB(U)
(3) VCC(U)
(4) IN(UH)
(5) IN(UL)
(6) NC
(7) VB(V)
(8) VCC(V)
(9) IN(VH)
(10) IN(VL)
(11) NC
(12) VB(W)
(13) VCC(W)
(14) IN(WH)
(15) IN(WL)
(16) NC
(17) P
(18) U,Vs(u)
(19) NU
(20) NV
(21) V,Vs(v)
(22) NW
(23) W,Vs(w)
Micom
C1
15-V
Supply
M
C3VDC
C2
C2
C2
R3
R4
C4
R5
C5
For 3-phase current sensing and protection
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FSB50550UTD Rev. A
FSB50550UTD Smart Power Module (SPM®)
Detailed Package Outline Drawings
0.60±0.10
Max 1.00
12.00±0.20
29.00±0.20
(1.165) 15*1.778=26.67±0.30
0.60±0.10
Max 1.00
(1.80)
(1.30)
(2.275) 4x3.90=15.60±0.30
#1 #16
#17 #23
2x3.90=7.80±0.30
12.23±0.30 13.13±0.30
13.34±0.30 13.34±0.30
14.00
19.00
14.58±0.30
19.58±0.30
0.50
+0.10
-0.05
5°
3°
R0.40
R0.40
(1.00)
(1.80)
3.10±0.20
6.20±0.20
1.95±0.30
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FSB50550UTD Rev. A
FSB50550UTD Smart Power Module (SPM®)
Rev. I15
