TB5D1M, TB5D2H www.ti.com SLLS579C - SEPTEMBER 2003 - REVISED JANUARY 2008 QUAD DIFFERENTIAL PECL DRIVERS FEATURES 1 * * * * * * * * * * * * Functional Replacements for the Agere BDG1A, BPNGA and BDGLA Pin-Equivalent to the General-Trade 26LS31 Device 2.0 ns Maximum Propagation Delays 0.15 ns Output Skew Typical Between Pairs Capable of Driving 50- Loads 5.0-V or 3.3-V Supply Operation TB5D1M Includes Surge Protection on Differential Outputs TB5D2H No Line Loading When VCC = 0 Third State Output Capability -40C to 85C Operating Temp Range ESD Protection HBM > 3 kV and CDM > 2 kV Available in Gull-Wing SOIC (JEDEC MS-013, DW) and SOIC (D) Packages APPLICATIONS * The TB5D1M device is a pin and functional replacement for the Agere systems BDG1A and BPNGA quad differential drivers. The TB5D1M has a built-in lightning protection circuit to absorb large transitions on the transmission lines without destroying the device. When the circuit is powered down it loads the transmission line, because of the protection circuit. The TB5D2H device is a pin and functional replacement for the Agere systems BDG1A and BDGLA quad differential drivers. Upon power down the TB5D2H output circuit appears as an open circuit and does not load the transmission line. Both drivers feature a 3-state output with a third-state level of less than 0.1 V. The packaging options available for these quad differential line drivers include a 16-pin SOIC gull-wing (DW) and a 16-pin SOIC (D) package. Both drivers are characterized for operation from -40C to 85C The logic inputs of this device include internal pull-up resistors of approximately 40 k that are connected to VCC to ensure a logical high level input if the inputs are open circuited. Digital Data or Clock Transmission Over Balanced Transmission Lines DESCRIPTION These quad differential drivers are TTL input to pseudo-ECL differential output used for digital data transmission over balanced transmission lines. DW AND D PACKAGE (TOP VIEW) AI AO AO E1 BO BO BI GND FUNCTIONAL DIAGRAM AO 1 16 V CC 2 15 3 14 4 13 5 12 6 11 7 10 8 9 DI DO DO E2 CO CO CI AI AO BO BI BO ENABLE TRUTH TABLE CO E1 E2 Condition CO 0 0 1 0 Active 0 1 1 1 Disabled Active CI DO DI DO Active E1 E2 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2003-2008, Texas Instruments Incorporated TB5D1M, TB5D2H www.ti.com SLLS579C - SEPTEMBER 2003 - REVISED JANUARY 2008 These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION PART NUMBER PART MARKING PACKAGE LEAD FINISH STATUS TB5D1MDW TB5D1M Gull-wing SOIC NiPdAu Production TB5D1MD TB5D1M SOIC NiPdAu Production TB5D2HDW TB5D2H Gull-wing SOIC NiPdAu Production TB5D2HD TB5D2H SOIC NiPdAu Production PACKAGE DISSIPATION RATINGS PACKAGE D THERMAL RESISTANCE, JUNCTION-TO-AMBIENT WITH NO AIR FLOW DERATING FACTOR (1) ABOVE TA = 25C TA = 85C POWER RATING Low-K (2) 754 mW 132.6 C/W 7.54 mW/C 301 mW High-K (3) 1166 mW 85.8 C/W 11.7 mW/C 466 mW 816 mW 122.5 C/W 8.17 mW/C 326 mW 1206 mW 82.9 C/W 12.1 mW/C 482 mW Low-K DW (1) (2) (3) TA 25C POWER RATING CIRCUIT BOARD MODEL (2) High-K (3) This is the inverse of the junction-to-ambient thermal resistance when board-mounted with no air flow. In accordance with the low-K thermal metric definitions of EIA/JESD51-3. In accordance with the high-K thermal metric definitions of EIA/JESD51-7. THERMAL CHARACTERISTICS PARAMETER JB PACKAGE VALUE UNITS Junction-to-board thermal resistance JC Junction-to-case thermal resistance D 51.4 C/W DW 56.6 C/W D 45.7 C/W DW 49.2 C/W ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range unless otherwise noted (1) TB5D1M, TB5D2H Supply voltage, VCC 0 V to 6 V Input voltage ESD - 0.3 V to (VCC + 0.3 V) Human Body Model (2) Charged-Device Model All Pins (3) 3 kV All Pins 2 kV Continuous power dissipation See Dissipation Rating Table Storage temperature, Tstg -65C to 130C Junction temperature, TJ 130C Lightning surge, TB5D1M only, see Figure 6 (1) (2) (3) 2 D Package -80 V to 100 V DW Package -100 V to 100 V Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Tested in accordance with JEDEC Standard 22, Test Method A114-A. Tested in accordance with JEDEC Standard 22, Test Method C101. Submit Documentation Feedback Copyright (c) 2003-2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H TB5D1M, TB5D2H www.ti.com SLLS579C - SEPTEMBER 2003 - REVISED JANUARY 2008 RECOMMENDED OPERATING CONDITIONS (1) Supply voltage, VCC MIN NOM MAX UNIT 5.0-V nominal supply 4.5 5 5.5 V 3.3-V nominal supply 3.0 3.3 3.6 V 85 C Operating free-air temperature, TA (1) -40 The algebraic convention, in which the least positive (most negative) limit is designated as minimum is used in this data sheet, unless otherwise stated. ELECTRICAL CHARACTERISTICS over recommended operating conditions unless otherwise noted parameter ICC test conditions Supply current PD Power dissipation VOH min typ (1) max VCC = 4.5 V to 5.5 V, no loads 40 VCC = 3.0 V to 3.6 V, no loads 40 unit mA VCC = 4.5 V to 5.5 V, Figure 3 loads all outputs 290 360 VCC = 3.0 V to 3.6 V, Figure 4 loads all outputs 280 360 VCC - 1.8 VCC - 1.3 VCC - 0.8 V Output high voltage VCC = 4.5 V to 5.5 V, Figure 3 mW VOL Output low voltage VOH - 1.4 VOH - 1.2 VOH - 0.7 V VOD Differential output voltage |VOH - VOL| 0.7 1.2 1.4 V VOH Output high voltage VCC - 1.8 VCC - 1.3 VCC - 0.8 V VOL Output low voltage VOH - 1.4 VOH - 1.1 VOH - 0.5 V VOD Differential output voltage |VOH - VOL| 0.5 1.1 1.4 V VOC(PP) Peak-to-peak common-mode output voltage CL= 5 pF, Figure 5 230 600 mV VOZ Third-state output voltage Figure 3 or Figure 4 load 0.1 V VIL Low level input voltage (2) 0.8 V VIH High level input voltage VIK VCC = 3.0 V to 3.6 V, Figure 4 2 Enable input clamp voltage V (3) VCC = 4.5 V, II = -5 mA -1 VCC = 5.5 V, VO = 0 V -250 (3) VCC = 5.5 V, VOD = 0 V 10 (3) V IOS Output short-circuit current (4) IIL Input low current, enable or data VCC = 5.5 V, VI = 0.4 V -400 (3) A Input high current, enable or data VCC = 5.5 V, VI =2.7 V 20 A Input reverse current, enable or data VCC = 5.5 V, VI =5.5 V 100 IIH CIN (1) (2) (3) (4) Input capacitance 5 mA A pF All typical values are at 25C and with a 3.3-V or 5-V supply. The input level provides no noise immunity and should be tested only in a static, noise-free environment. This parameter is listed using a magnitude and polarity/direction convention, rather than an algebraic convention, to match the original Agere data sheet. Test must be performed one output at a time to prevent damage to the device. No test circuit attached. Copyright (c) 2003-2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H Submit Documentation Feedback 3 TB5D1M, TB5D2H www.ti.com SLLS579C - SEPTEMBER 2003 - REVISED JANUARY 2008 THIRD STATE--A TB5D1M (or TB5D2H) driver produces pseudo-ECL levels, and has a third-state mode, which is different than a conventional TTL device. When a TB5D1M (or TB5D2H) driver is placed in the third state, the base of the output transistors is pulled low, bringing the outputs below the active-low level of standard PECL devices. [For example: The TB5D1M low output level is typically 2.7 V, while the third state output level is less than 0.1 V.] In a bidirectional, multipoint, bus application, the driver of one device, which is in its third state, may be back driven by another driver on the bus whose voltage in the low state is lower than the third-stated device. This could come about due to differences in the driver's independent power supplies. In this case, the device in the third state controls the line, thus clamping the line and reducing the signal swing. If the difference voltage between the independent driver power supplies is small, this consideration can be ignored. Again using the TB5D1M driver as an example, a typical supply voltage difference between separate drivers of > 2 V can exist without significantly affecting the amplitude of the signal. SWITCHING CHARACTERISTICS, 5-V NOMINAL SUPPLY over recommended operating conditions unless otherwise noted parameter test conditions (2) tP1 Propagation delay time, input high to output tP2 Propagation delay time, input low to output (2) tP Capacitive delay tPHZ Propagation delay time, high-level-to-high-impedance output tPLZ Propagation delay time, low-level-to-high-impedance output tPZH Propagation delay time, high-impedance-to-high-level output tPZL Propagation delay time, high-impedance-to-low-level output tskew1 tshew2 unit 1.2 2 0.01 0.03 7 12 7 12 5 12 4 12 Output skew, |tP1 - tP2| 0.15 0.3 Output skew, |tPHH - tPHL|, |tPLH - tPLL| CL = 5 pF, See Figure 1 and Figure 3 0.15 1.1 0.1 1 CL = 5 pF, See Figure 1 and Figure 3 0.7 2 0.7 2 CL = 5 pF, See Figure 1 and Figure 3 CL = 5 pF, See Figure 2 and Figure 3 (3) tskew Output skew, difference between drivers (4) tTLH Rise time (20% - 80%) tTHL Fall time (80% - 20%) 4 max 2 Part-to-part skew (4) typ (1) 1.2 tskew(pp) (1) (2) (3) min ns ns/pF ns ns 0.3 ns All typical values are at 25C and with a 5-V supply. Parameters tP1 and tP2 are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure 1). tskew(pp) is the magnitude of the difference in differential propagation delay times, tP1 or tP2, between any specified outputs of two devices when both devices operate with the same supply voltage, at the same temperature, and have identical packages and test circuits. tskew is the magnitude of the difference in differential skew tskew1 between any specified outputs of a single device. Submit Documentation Feedback Copyright (c) 2003-2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H TB5D1M, TB5D2H www.ti.com SLLS579C - SEPTEMBER 2003 - REVISED JANUARY 2008 SWITCHING CHARACTERISTICS, 3.3-V NOMINAL SUPPLY over recommended operating conditions unless otherwise noted parameter test conditions Propagation delay time, input high to output (2) tP1 (2) tP2 Propagation delay time, input low to output tP Capacitive delay tPHZ Propagation delay time, high-level-to-high-impedance output tPLZ Propagation delay time, low-level-to-high-impedance output tPZH Propagation delay time, high-impedance-to-high-level output tPZL Propagation delay time, high-impedance-to-low-level output tskew1 Output skew, |tP1 - tP2| tshew2 Output skew, |tPHH - tPHL|, |tPLH - tPLL| tskew(pp) Part-to-part skew (3) tskew Output skew, difference between drivers (4) tTLH Rise time (20% - 80%) tTHL Fall time (80% - 20%) (1) (2) (3) (4) min CL = 5 pF, See Figure 1 and Figure 4 CL = 5 pF, See Figure 2 and Figure 4 CL = 5 pF, See Figure 1 and Figure 4 typ (1 ) max unit 1.2 3.5 1.2 3.5 0.01 0.03 8 12 5 12 5 12 8 12 0.15 0.3 0.15 1.2 0.1 1 ns ns/pF ns ns 0.3 CL = 5 pF, See Figure 1 and Figure 4 0.7 2 0.7 2 ns All typical values are at 25C and with a 3.3-V supply. Parameters tP1 and tP2 are measured from the 1.5 V point of the input to the crossover point of the outputs (see Figure 1). tskew(pp) is the magnitude of the difference in differential propagation delay times, tP1 or tP2, between any specified outputs of two devices when both devices operate with the same supply voltage, at the same temperature, and have identical packages and test circuits. tskew is the magnitude of the difference in differential skew tskew1 between any specified outputs of a single device. Copyright (c) 2003-2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H Submit Documentation Feedback 5 TB5D1M, TB5D2H www.ti.com SLLS579C - SEPTEMBER 2003 - REVISED JANUARY 2008 2.4 V 1.5 V INPUT 0.4 V tP1 tP2 VOH OUTPUTS VOL tPHH tPLL VOH OUTPUT (VOH + VOL)/2 VOL tPHL tPLH VOH OUTPUT (VOH + VOL)/2 VOL 80% OUTPUT VOH 80% 20% 20% ttLH VOL ttHL Figure 1. Propagation Delay Time Waveforms 2.4 V E1(1) 1.5 V 0.4 V 2.4 V E2(2) 1.5 V 0.4 V tPHZ tPZH VOH VOL + 0.2 V VOL OUTPUT VOL - 0.1 V tPLZ tPZL VOL OUTPUT VOL - 0.1 V (1) E2 = 1 while E1 changes state E1 = 0 while E2 changes state NOTE: In the third state, both outputs (OUTPUT and OUTPUT) are 0.1 V (max). (2) Figure 2. Enable and Disable Delay Time Waveforms 6 Submit Documentation Feedback Copyright (c) 2003-2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H TB5D1M, TB5D2H www.ti.com SLLS579C - SEPTEMBER 2003 - REVISED JANUARY 2008 TEST CONDITIONS Parametric values specified under the Electrical Characteristics and Switching Characteristics sections are measured with the following output load circuit. 100 OUTPUT 200 CL OUTPUT 200 CL Figure 3. Driver Test Circuits, 5-V Nominal Supplies 100 OUTPUT 75 CL OUTPUT 75 CL Figure 4. Driver Test Circuits, 3.3-V Nominal Supplies VOC 50 OUTPUT CL 200 VOC 50 200 CP = 2 pF OUTPUT OUTPUT CL CL Note: VOC(PP) load circuit for 5-V nominal supplies. 50 75 OUTPUT 50 CP = 2 pF 75 CL Note: VOC(PP) load circuit for 3.3-V nominal supplies. VOH OUTPUT VOL VOC VOC(PP) Note: All input pulses are supplied by a generator having the following characteristics: tr or tf = 1 ns, pulse repetition rate (PRR) = 0.25 Mbps, pulse width = 500 10 ns. CP includes the instrumentation and fixture capacitance within 0,06 m of the D.U.T. The measurement of VOC(PP) is made on test equipment with a -3 dB bandwidth of at least 1 GHz. Figure 5. Test Circuits and Definitions for the Driver Common-Mode Output Voltage Copyright (c) 2003-2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H Submit Documentation Feedback 7 TB5D1M, TB5D2H www.ti.com SLLS579C - SEPTEMBER 2003 - REVISED JANUARY 2008 VCC 110 DUT 110 + _ Lightning Surge Test Generators + _ Note: Surges may be applied simultaneously, but never in opposite polarities. Surge test pulses have tr = tf = 2 s, pulse width = 7 s (50% points), and period = 250 ms. Figure 6. Lightning-Surge Testing Configuration for TB5D1M TYPICAL CHARACTERISTICS OUTPUT VOLTAGE RELATIVE TO VCC vs OUTPUT CURRENT OUTPUT VOLTAGE RELATIVE TO VCC vs FREE-AIR TEMPERATURE 0 0 VCC = 4.5 V to 5.5 V, Figure 3 Load VO - Output Voltage Relative To VCC - V VO - Output Voltage Relative To VCC - V TA = 255C -0.5 VOH -1 -1.5 -2 -2.5 VOL -3 -3.5 -50 -40 -30 -20 -10 0 -0.5 VOH Max -1 VOH Min -1.5 -2 VOL Max VOL Min -2.5 -3 -50 0 50 100 TA - Free-Air Temperature - C IO - Output Current - mA Figure 7. 8 Submit Documentation Feedback 150 Figure 8. Copyright (c) 2003-2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H TB5D1M, TB5D2H www.ti.com SLLS579C - SEPTEMBER 2003 - REVISED JANUARY 2008 TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE RELATIVE TO VCC vs FREE-AIR TEMPERATURE DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE 1.6 VCC = 3 V to 3.6 V, Figure 4 Load VOD - Differential Output Voltage - V VO - Output Voltage Relative To VCC - V 0 -0.5 VOH Max -1 VOH Min -1.5 -2 VOL Max VOL Min -2.5 -3 -50 0 50 100 TA - Free-Air Temperature - C 1.4 VOD Nom 1.2 VOD Min 1 Figure 10. DIFFERENTIAL OUTPUT VOLTAGE vs FREE-AIR TEMPERATURE PROPAGATION DELAY TIME tP1 or tP2 vs FREE-AIR TEMPERATURE VCC = 4.5 V to 5.5 V, Figure 3 Load t P - Propagation Delay Time - ns VOD Nom 1 VOD Min 0.8 VCC = 3 V to 3.6 V, Figure 4 Load 0.6 -50 150 1.6 VOD Max 1.2 0 50 100 TA - Free-Air Temperature - C Figure 9. 1.4 VOD - Differential Output Voltage - V VOD Max 0.8 -50 150 VCC = 4.5 V to 5.5 V, Figure 3 Load 0 50 100 TA - Free-Air Temperature - C 150 1.4 1.2 Max Delay 1 Min Delay 0.8 0 -50 Figure 11. 50 100 0 TA - Free-Air Temperature - 5C 150 Figure 12. Copyright (c) 2003-2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H Submit Documentation Feedback 9 TB5D1M, TB5D2H www.ti.com SLLS579C - SEPTEMBER 2003 - REVISED JANUARY 2008 TYPICAL CHARACTERISTICS (continued) PROPAGATION DELAY TIME tP1 or tP2 vs FREE-AIR TEMPERATURE 3.5 t P - Propagation Delay Time - ns VCC = 3 V to 3.6 V, Figure 4 Load 3 2.5 Max Delay 2 1.5 Min Delay 1 0.5 0 -50 50 100 0 TA - Free-Air Temperature - 5C 150 Figure 13. 10 Submit Documentation Feedback Copyright (c) 2003-2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H TB5D1M, TB5D2H www.ti.com SLLS579C - SEPTEMBER 2003 - REVISED JANUARY 2008 APPLICATION INFORMATION Power Dissipation The power dissipation rating, often listed as the package dissipation rating, is a function of the ambient temperature, TA, and the airflow around the device. This rating correlates with the device's maximum junction temperature, sometimes listed in the absolute maximum ratings tables. The maximum junction temperature accounts for the processes and materials used to fabricate and package the device, in addition to the desired life expectancy. There are two common approaches to estimating the internal die junction temperature, TJ. In both of these methods, the device's internal power dissipation, PD, needs to be calculated. This is done by totaling the supply power(s) to arrive at the system power dissipation: S(V Sn I Sn ) (1) and then subtracting the total power dissipation of the external load(s): S(V Ln I Ln ) (2) The first TJ calculation uses the power dissipation and ambient temperature, along with one parameter: JA, the junction-to-ambient thermal resistance, in degrees Celsius per watt. The product of PD and JA is the junction temperature rise above the ambient temperature. Therefore: T J + T A ) (PD q JA ) (3) 140 the device and PCB. JEDEC/EIA has defined standardized test conditions for measuring JA. Two commonly used conditions are the low-K and the high-K boards, covered by EIA/JESD51-3 and EIA/JESD51-7 respectively. Figure 14 shows the low-K and high-K values of JA versus air flow for this device and its package options. The standardized JA values may not accurately represent the conditions under which the device is used. This can be due to adjacent devices acting as heat sources or heat sinks, to nonuniform airflow, or to the system PCB having significantly different thermal characteristics than the standardized test PCBs. The second method of system thermal analysis is more accurate. This calculation uses the power dissipation and ambient temperature, along with two device and two system-level parameters: * JC, the junction-to-case thermal resistance, in degrees Celsius per watt * JB, the junction-to-board thermal resistance, in degrees Celsius per watt * CA, the case-to-ambient thermal resistance, in degrees Celsius per watt * BA, the board-to-ambient thermal resistance, in degrees Celsius per watt. In this analysis, there are two parallel paths, one through the case (package) to the ambient, and another through the device to the PCB to the ambient. The system-level junction-to-ambient thermal impedance,JA(S), is the equivalent parallel impedance of the two parallel paths: T J + T A ) (PD q JA(S) ) (4) where Thermal Impedance - C/W 120 D, Low-K q JA(S) + DW, Low-K 80 DW, High-K 40 0 D, High-K 100 200 (q JB ) q BA ) (q JC ) q CA ) q JB ) q BA ) The device parameters JC and JB account for the internal structure of the device. The system-level parameters CA and BA take into account details of the PCB construction, adjacent electrical and mechanical components, and the environmental conditions including airflow. Finite element (FE), finite difference (FD), or computational fluid dynamics (CFD) programs can determine CA and BA. Details on using these programs are beyond the scope of this data sheet, but are available from the software manufacturers. 100 60 (q JC ) q CA ) 300 400 500 Air Flow - LFM Figure 14. Thermal Impedance vs Air Flow Note that JA is highly dependent on the PCB on which the device is mounted, and on the airflow over Copyright (c) 2003-2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H Submit Documentation Feedback 11 TB5D1M, TB5D2H www.ti.com SLLS579C - SEPTEMBER 2003 - REVISED JANUARY 2008 Load Circuits Transmission Line The test load circuits shown in Figure 3 and Figure 4 are based on a recommended pi type of load circuit shown in Figure 15. The 100- differential load resistor RT at the receiver provide proper termination for the interconnecting transmission line, assuming it has a 100- characteristic impedance. The two resistors RS to ground at the driver end of the transmission line link provide dc current paths for the emitter follower output transistors. The two resistors to ground normally should not be placed at the receiver end, as they shunt the termination resistor, potentially creating an impedance mismatch with undesirable reflections. INPUT OUTPUT Recommended Resistor Values: For 5 V Nom Supplies, RT = 200 , RS = 90 For 3.3 V Nom Supplies, RT = 100 , RS = 30 RT/2 RT/2 RS Figure 16. A Recommended Y Load Circuit An additional load circuit, similar to one commonly used with ECL and PECL, is shown in Figure 17. Transmission Line INPUT OUTPUT Transmission Line INPUT RT = 100 W RS RS OUTPUT RT/2 RT/2 + _ VT Recommended Resistor Values: For 5-V Nominal Supplies, RS = 200 W For 3.3-V Nominal Supplies, RS = 75 W Figure 15. A Recommended pi Load Circuit Another common load circuit, a Y load, is shown in Figure 16. The receiver-end line termination of RT is provided by the series combination of the two RT/2 resistors, while the dc current path to ground is provided by the single resistor RS. Recommended values, as a function of the nominal supply voltage range, are indicated in the figure. 12 Recommended Resistor Values: For 5 V and 3.3 V Nom Supplies, RT = 100 , VT = VCC - 2.55 V Submit Documentation Feedback Figure 17. A Recommended PECL-Style Load Circuit An important feature of all of these recommended load circuits is that they ensure that both of the emitter follower output transistors remain active (conducting current) at all times. When deviating from these recommended values, it is important to make sure that the low-side output transistor does not turn off. Failure to do so increases the tskew2 and VOC(PP) values, increasing the potential for electromagnetic radiation. Copyright (c) 2003-2008, Texas Instruments Incorporated Product Folder Link(s): TB5D1M TB5D2H PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) Samples (Requires Login) TB5D1MD ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Request Free Samples TB5D1MDE4 ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Request Free Samples TB5D1MDW ACTIVE SOIC DW 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Request Free Samples TB5D1MDWE4 ACTIVE SOIC DW 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Request Free Samples TB5D1MDWR ACTIVE SOIC DW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Purchase Samples TB5D1MDWRE4 ACTIVE SOIC DW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Purchase Samples TB5D2HD ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Request Free Samples TB5D2HDE4 ACTIVE SOIC D 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Request Free Samples TB5D2HDR ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Purchase Samples TB5D2HDRE4 ACTIVE SOIC D 16 2500 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Purchase Samples TB5D2HDW ACTIVE SOIC DW 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Request Free Samples TB5D2HDWE4 ACTIVE SOIC DW 16 40 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Request Free Samples TB5D2HDWR ACTIVE SOIC DW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Purchase Samples TB5D2HDWRE4 ACTIVE SOIC DW 16 2000 Pb-Free (RoHS) CU NIPDAU Level-2-250C-1YEAR/ Level-1-220C-UNLIM Purchase Samples (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. Addendum-Page 1 PACKAGE OPTION ADDENDUM www.ti.com 28-Aug-2010 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TB5D1MDWR SOIC TB5D2HDR TB5D2HDWR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.75 10.7 2.7 12.0 16.0 Q1 DW 16 2000 330.0 16.4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TB5D1MDWR SOIC DW 16 2000 367.0 367.0 38.0 TB5D2HDR SOIC D 16 2500 367.0 367.0 38.0 TB5D2HDWR SOIC DW 16 2000 367.0 367.0 38.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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