64K x 32 Synchronous-Pipe lined Cache RAM
CY7C1329
Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05279 Rev. *A Revised April 10, 2002
Features
• Supports 133-MHz bus for Pentium® and PowerPC™
operations with zero wait states
•Fully registered inputs and outputs for pipelined
operation
•64K x 32 common I/O architecture
•Single 3.3V power supply
•Fast clock-to-output times
—4.2 ns (for 133-MHz device)
—5.5 ns (for 100-MHz device)
•User-selectable burst counter supporting Intel®
Pentium interleaved or linear burst sequences
•Separate processor and controller address strobes
•Synchronous self-timed writes
•Asynchronous output enable
•JEDEC-standard 100-lead TQFP pinout
•“ZZ” Sleep Mode option and Stop Clock option
Functional Description
The CY7C1329 is a 3.3V, 64K by 32 synchronous-pipelined
cache SRAM designed to support zero wait state secondary
cache with minimal glue logic.
All sync hronous inpu ts pas s thro ugh i nput reg isters c ontroll ed
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise is 4.2 ns (133-MHz
device).
The CY7C1329 supports either the interleaved burst
sequence used by the Intel Pentium processor or a linear burst
sequence used by processors such as the PowerPC. The
burst sequence is selected through the MODE pin. Accesses
can be initiated by asserting either the Processor Address
Strobe (ADSP) or the Controller Address Strobe (ADSC) at
clock rise. Address ad va nce me nt t hrou gh the burst sequence
is controlled by the ADV input. A 2-bit on-chip wraparound
burst counter captures the first address in a burst sequence
and automatically increments the address for the rest of the
burst access.
Byte Write operations are qualified with the four Byte Write
Select (BW[3:0]) inputs. A Glob al Write Enab le (GW) o verrides
all Byte Write i nputs and writes data t o all fo ur bytes. All w rites
are conducted with on-chip synchronous self-timed Write
circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. In order to provide
prop er data during depth expa nsion , OE is masked during the
first clock of a Read cycle when emerging from a deselected
state.
CLK
ADV
ADSC
A[15:0]
GW
BWE
BW3
BW2
BW1
BW0
CE1
CE3
CE2
OE
ZZ
BURST
COUNTER
DQ[31:24]
BYTEWRITE
REGISTERS
ADDRESS
REGISTER
DQ
OUTPUT
REGISTERS INPUT
REGISTERS
64K × 32
Memory
Array
CLK CLK
Q0
Q1
Q
D
CE
CE
CLR
SLEEP
CONTROL
DQ[23:16]
BYTEWRITE
REGISTERS
D Q
DQ
DQ[15:8]
BYTEWRITE
REGISTERS
DQ[7:0]
BYTEWRITE
REGISTERS
D Q
ENABLE
REGISTER
DQ
CE
CLK
ENABLE DELAY
REGISTER
D Q
CLK
32 32
16
14
14
16
(A[1:0])2
MODE
ADSP
Logic Block Diagram
DQ[31:0]
CY7C1329
Document #: 38-05279 Rev. *A Page 2 of 15
Pin Configuration
A
5
A
4
A
3
A
2
A
1
A
0
NC
NC
V
SS
V
DD
NC
NC
A
10
A
11
A
12
A
13
A
14
A
15
NC
NC
DQ15
DQ14
VDDQ
VSSQ
DQ13
DQ12
DQ11
DQ10
VSSQ
VDDQ
DQ9
DQ8
VSS
NC
VDD
ZZ
DQ7
DQ6
VDDQ
VSSQ
DQ5
DQ4
DQ3
DQ2
VSSQ
VDDQ
DQ1
DQ0
NC
NC
DQ16
DQ17
VDDQ
VSSQ
DQ18
DQ19
DQ20
DQ21
VSSQ
VDDQ
DQ22
DQ23
NC
VDD
NC
VSS
DQ24
DQ25
VDDQ
VSSQ
DQ26
DQ27
DQ28
DQ29
VSSQ
VDDQ
DQ30
DQ31
NC
A6
A7
CE
1
CE
2
BW
3
BW
2
BW
1
BW
0
CE
3
V
DD
V
SS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
8
A
9
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
MODE
BYTE0
BYTE1
BYTE3
BYTE2
100-pin TQFP
CY7C1329
Selection Gu ide
7C1329-133 7C1329-100 Unit
Maximum Access Time 4.2 5.5 ns
Maximum Operating Current Commercial 325 310 mA
Maximum CMOS Standby Current Commercial 5 5 mA
CY7C1329
Document #: 38-05279 Rev. *A Page 3 of 15
Pin Definitions
Pin Number Name I/O Description
49–44, 81,82,
99, 100,
32–37
A[15:0] Input-
Synchronous Address Inputs u sed to select one of th e 64K a ddres s locat ions. Sampl ed at
the rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and
CE3 are sampled active. A[1:0] feed the 2-bit counter.
96–93 BW[3:0] Input-
Synchronous Byte Write Select Inputs, active LOW. Qualified with BWE to conduct Byte Writes
to the SRAM. Sampled on the rising edge of CLK.
88 GW Input-
Synchronous Global Write Enable Input, active LOW . When asserted LOW on the rising edge
of CLK, a global Write is conducted (ALL bytes are written, regardless of the values
on BW[3:0] and BWE).
87 BWE Input-
Synchronous Byte Write Ena ble Input, active LOW. Sampled on the rising edg e of CLK. Thi s
signal must be asserted LOW to conduct a Byte Write.
89 CLK Input-Clock Cloc k input. Used to c apture all synch ronous inputs to the device. Al so used
to increment the burst counter when ADV is asserted LOW, during a burst
operation.
98 CE1Input-
Synchronous Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3 to select/deselect the device. ADSP is ignored if
CE1 is HIGH.
97 CE2Input-
Synchronous Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3 to select/deselect the device.
92 CE3Input-
Synchronous Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE2 to select/deselect the device.
86 OE Input-
Asynchronous Outpu t Enable, a synchrono us input, a ctive LOW. Controls the dire ction o f the
I/O pins. When LOW , the I/O pins behave as outputs. When deasserted HIGH, I/O
pins are three-stated, and act as input data pins. OE is masked during the first
clock of a Read cycle when emerging from a deselected state.
83 ADV Input-
Synchronous Advance Input signal, sampled on the rising edge of CLK. When asserted, it
automatically increments the address in a burst cycle.
84 ADSP Input-
Synchronous Address Strobe from Processor, sampled on the rising edge of CLK. When
asserted LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized. ASDP is ignored when CE1 is deasserted HIGH.
85 ADSC Input-
Synchronous Address Strobe from Controller, sampled on the rising edge of CLK. When
asserted LOW, A[15:0] is captured in the address registers. A[1:0] are also loaded
into the burst counter. When ADSP and ADSC are both asserted, only ADSP is
recognized.
64 ZZ Input-
Asynchronous ZZ “sleep” Input. This ac tiv e HIG H i npu t pl ace s t he d ev ic e in a no n-ti me -cri tic al
“sleep” condition with data integrity preserved.
29, 28,
25–22, 19,
18,13,12,
9–6, 3, 2, 79,
78, 75–72,
69, 68, 63 , 62
59–56, 53, 52
DQ[31:0] I/O-
Synchronous Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggere d by the risin g edge of CLK. As outpu ts, they deli ver the data co ntained
in the memory location specified by A[15:0] during the previous clock rise of the
Read cycle. The direction of the pins is controlled by OE. When OE is asserted
LOW , the pins behave as outputs. When HIGH, DQ[31:0] are placed in a three-state
condition.
15, 41, 65, 91 VDD Pow er Supply Power supply inputs to the core of the device. Should be connected to 3.3V
power supply.
17, 40, 67, 90 VSS Ground Ground for the core of the device. Should be connected to ground of the system.
4, 11, 20, 27,
54, 61, 70, 77 VDDQ I/O Power
Supply Power supply for th e I/O circ uitry. Should be connect ed to a 3.3V power supply.
5, 10, 21, 26,
55, 60, 71, 76 VSSQ I/O Ground Ground for the I/O circuitry. Should be connected to ground of the syste m.
31 MODE Input-
Static Selects burst orde r . When tied to GND sel ects linear burs t sequence. Whe n tied
to VDDQ or le ft floa ting s elec ts inte rleav ed burs t seq uence . This is a strap pin a nd
should remain static during device operation.
1, 14, 16, 30,
38, 39, 42, 43,
50, 51, 66, 80
NC –No Conn ect s.
CY7C1329
Document #: 38-05279 Rev. *A Page 4 of 15
Introduction
Functional Overview
All synchron ous i nputs pass through in put reg isters cont rolled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock.
Maximum access delay from the clock rise (tCO) is 4.2 ns
(133-MHz device).
The CY7C1329 sup ports secondary cache in systems utilizing
either a linear or interleaved burst sequence. The interleaved
burst order supports Pentium and i486 processors. The
linear burst sequence is suited for processors that utilize a
linear burst sequence. The burst order is user selectable, and
is dete rmi ned by s am pl ing the M O D E inp ut. Ac ce ss es can be
initiated with either the Processor Address Strobe (ADSP) or
the Controller Address Strobe (ADSC). Address advancement
through the burst sequence is controlled by the ADV input. A
two-bit on-chip wraparound burst counter captures the first
addr ess in a burst s equence and automatical ly incremen ts the
address for the rest of the burst access.
Byte W ri te opera tions a re q ualified w ith th e Byte W r ite Enab le
(BWE) and Byte Write Select (BW[3:0]) inputs. A Global Write
Enab le (GW) overri des all Byte Write i nputs and writes d ata to
all four bytes. All writes are simplified with on-chip
synchronous self-timed Write circuitry.
Three synchronous Chip Selects (CE1, CE2, CE3) and an
asynchronous Output Enable (OE) provide for easy bank
selection and output three-state control. ADSP is ignored if
CE1 is HIGH.
Sing le Read Acces se s
This access is initiated when the following conditions are
sat isfied at clo ck rise: (1) ADSP or ADSC is asserted LOW , (2)
CE1, CE2, CE3 are all asserted active, and (3) the Write
signal s (GW , BWE) are all deas serted HIGH. ADSP is ignored
if CE1 is HIGH. The address presented to the address inputs
(A[15:0]) is stored into the address advancement logic and the
Address Register while being presented to the memory core.
The corres ponding data is all owed to propagate to the input of
the Output Registers. At the rising edge of the next clock the
data is allowed to propagate through the output register and
onto the data bus within 4.2 ns (133-MHz device) if OE is
active LOW. The only exception occurs when the SRAM is
emerging from a deselected state to a selected state, its
outputs are always three-stated during the first cycle of the
access. After the first cycle of the access, the outputs are
controlled by the OE signal . Consec utive si ngle Re ad cycles
are supported. Once the SRAM is deselected at clock rise by
the chip select and either ADSP or ADSC signals, its output
will three-state immediately.
Single Write Accesses Ini tiat ed by ADSP
This access is initiated when both of the following conditions
are sat isfied at clo ck rise: (1) ADSP is asserted LOW, and (2)
CE1, CE2, CE3 are all asserted a ctive. The addre ss pres ented
to A[15:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
W rite s ignal s (GW, BWE, and BW0–BW3) and ADV inpu ts are
ignored during this first cycle.
ADSP triggered Write accesses require two clock cycles to
complete. If GW is a sserted LOW on th e second clock rise, the
data presented to the DQ[31:0] inputs is written into the corre-
sponding address location in the RAM core. If GW is HIGH,
then the Write operation is controlled by BWE and BW[3:0]
signals. The CY7C1329 provides Byte Write capability that is
described in the Write Cycle Description table. Asserting the
Byte Write Enable input (BWE) with the selected Byte Write
(BW[3:0]) input will selectively write to only the desired bytes.
Bytes not selected during a Byte Write operation will remain
unaltered. A synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because the CY7C1329 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ[31:0] inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ[31:0] are automatically
three -stated whenever a W rite cycl e is detec ted, regardless of
the state of OE.
Single Write Accesses Initiated by ADSC
ADSC Write acce sses are ini tia ted w hen the fo llowi ng cond i-
tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is
deasserted HIGH, (3) CE1, CE2, C E3 are all asserted active,
and (4) the appropriate combination of the Write inputs (GW,
BWE, and BW[3:0]) are asserted active to conduct a Write to
the desi red b yte (s). ADSC tri gge red Write accesses re quire a
single clock cycle to complete. The address presented to
A[15:0] is loaded into the address register and the address
advancement logic while being delivered to the RAM core. The
ADV input is ignored during this cycle. If a global Write is
conducted, the data presented to the DQ[31:0] is written into the
corresponding address location in the RAM core. If a Byte
Write is conducted, only the selected bytes are written. Bytes
not selected during a Byte Write operation will remain
unaltered. A Synchronous self-timed Write mechanism has
been provided to simplify the Write operations.
Because the CY7C1329 is a common I/O device, the Output
Enable (OE) must be deasserted HIGH before presenting data
to the DQ[31:0] inputs. Doing so will three-state the output
drivers. As a safety precaution, DQ[31:0] are automatically
three -stated whenever a W rite cycl e is detec ted, regardless of
the state of OE.
Burst Sequences
The CY7C 1329 provide s a two-bit wraparou nd counter , fed by
A[1:0], that implements either an interleaved or linear burst
sequen ce. The interleaved burst se quence is designe d specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MO D E inpu t.
Asserting ADV LOW at clock ris e will aut om ati cal ly incre me nt
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Interleaved Burst Sequence
First
Address Second
Address Third
Address Fourth
Address
A[1:0] A[1:0] A[1:0] A[1:0]
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
CY7C1329
Document #: 38-05279 Rev. *A Page 5 of 15
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a pow e r cons erv ati on “sleep” mode. Two
clock cycles are required to enter into or exit from this “sleep”
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the “sleep” mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the “sleep” mode. CE1, CE2, CE3, ADSP, and ADSC must
remain inactive for the duration of tZZREC after the ZZ input
returns LOW.
Linear Burst Sequence
First
Address Second
Address Third
Address Fourth
Address
A[1:0] A[1:0] A[1:0] A[1:0]
00 01 10 11
01 10 11 00
10 11 00 01
11 00 01 10
ZZ Mode Electrical Characteristics
Parameter Description Test Conditions Min. Max. Unit
IDDZZ Snooze mode standby
current ZZ > VDD − 0.2V 3 mA
tZZS Device operation to ZZ ZZ > VDD − 0.2V 2tCYC ns
tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns
Cycle Descripti ons [1,2,3]
Next Cycle Add. Used ZZ CE3CE2CE1ADSP ADSC ADV OE DQ Write
Unselected None L X X 1 X 0 X X Hi-Z X
Unselected None L 1 X 0 0 X X X Hi-Z X
Unselected None L X 0 0 0 X X X Hi-Z X
Unselected None L 1 X 0 1 0 X X Hi-Z X
Unselected None L X 0 0 1 0 X X Hi-Z X
Begin Read External L 0 1 0 0 X X X Hi-Z X
Begin Read External L 0 1 0 1 0 X X Hi-Z Read
Continue Read Next L X X X 1 1 0 1 Hi-Z Read
Continue Read Next L X X X 1 1 0 0 DQ Read
Continue Read Next L X X 1 X 1 0 1 Hi-Z Read
Continue Read Next L X X 1 X 1 0 0 DQ Read
Suspend Read Current L X X X 1 1 1 1 Hi-Z Read
Suspend Read Current L X X X 1 1 1 0 DQ Read
Suspend Read Current L X X 1 X 1 1 1 Hi-Z Read
Suspend Read Current L X X 1 X 1 1 0 DQ Read
Begin Write Curr ent L X X X 1 1 1 X Hi-Z Write
Begin Write Curr ent L X X 1 X 1 1 X Hi-Z Write
Begin Write External L 0 1 0 1 0 X X Hi-Z Write
Continue Write Next L X X X 1 1 0 X Hi-Z Write
Continue Write Next L X X 1 X 1 0 X Hi-Z Write
Suspend Write Cur rent L X X X 1 1 1 X Hi-Z Write
Suspend Write Cur rent L X X 1 X 1 1 X Hi-Z Write
ZZ “sleep” None H X X X X X X X Hi-Z X
Notes:
1. X = “Don't Care,” 1 = HIGH, 0 = LOW.
2. Write is defined by BWE, BW[3:0], and GW. See Write Cycle Descriptions table.
3. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
CY7C1329
Document #: 38-05279 Rev. *A Page 6 of 15
Maximum Ratings
(Abov e wh ic h th e useful life may be im pa ired. For user guide-
lines, not tested.)
Storage Temperature .....................................−65°C to +150°C
Ambient Temperature with
Pow er Applied..................................................−55°C to +125°C
Supply Voltage on VDD Relative to GND.........−0.5V to +4.6V
DC Voltage Applied to Outputs
in High-Z State[7] .....................................−0.5V to VDDQ + 0.5V
DC Input Voltage[7]..................................−0.5V to VDDQ + 0.5V
Current into Outputs (LOW).........................................20 mA
Static Discharge Voltage .......................................... >2001V
(per MIL-STD-883, Method 3015)
Latch-up Current..................................................... >200 mA
Notes:
4. X = “Don't Care,” 1 = Logic HIGH, 0 = Logic LOW.
5. The SRAM always initiates a Read cycle when ADSP asserted, regardless of the state of GW, BWE, or BW[3:0]. Writes may occur only on subsequent clocks
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to three-state. OE
is a “don't care” for the remainder of the Write cycle.
6. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle DQ = High-Z when OE is inactive
or when the device is deselected, and DQ = data when OE is active.
7. Minimu m volt a ge equ als –2.0V for pulse durations of less than 20 ns.
8. TA is the case temperature.
W rite Cycle Descriptions[4,5,6]
Function GW BWE BW3BW2BW1BW0
Read 11XXXX
Read 101111
Write B yte 0 – DQ[7:0] 101110
Write B yte 1 – DQ[15:8] 101101
Write Bytes 1, 0 101100
Write B yte 2 – DQ[23:16] 101011
Write Bytes 2, 0 101010
Write Bytes 2, 1 101001
Write Bytes 2, 1, 0 1 0 1 0 0 0
Write B yte 3 - DQ[31:24] 100111
Write Bytes 3, 0 100110
Write Bytes 3, 1 100101
Write Bytes 3, 1, 0 1 0 0 1 0 0
Write Bytes 3, 2 100011
Write Bytes 3, 2, 0 1 0 0 0 1 0
Write Bytes 3, 2, 1 1 0 0 0 0 1
Write All Bytes 1 0 0 0 0 0
Write All Bytes 0 X X X X X
Operating Range
Range Ambient Temperature[8] VDD VDDQ
Commercial 0°C to +70°C 3.3V
−5%/+10% 3.3V
−5%/+10%
CY7C1329
Document #: 38-05279 Rev. *A Page 7 of 15
Electri cal Characteristics Over the Operat ing Range
Parameter Description Test Conditions Min. Max. Unit
VDD Power Supply Voltage 3.3V −5%/+10% 3.135 3.6 V
VDDQ I/O Supply Voltage 3.3V −5%/+10% 3.135 3.6 V
VOH Output HIGH Vol tage VDD = Min., IOH = −4.0 mA 2.4 V
VOL Output LOW Voltage VDD = Min., IOL = 8.0 mA 0.4 V
VIH Input HIGH Voltage 2.0 VDDQ + 0.3V V
VIL Input LOW Voltage[7] –0.3 0.8 V
IXInput Load Current
Except ZZ and MODE GND ≤ VI ≤ VDDQ −5 5 µA
Input Current of MODE Input = VSS –30 µA
Input = VDDQ 5µA
Input Current of ZZ Input = VSS –5µA
Input = VDDQ 30 µA
IOZ Output Leakage
Current GND ≤ VI ≤ VDDQ, Output Disabled −5 5 µA
IDD VDD Operating Supply
Current VDD = Max., IOUT = 0 mA,
f = fMAX = 1/tCYC 7.5-ns cycle, 133 MHz 325 mA
10-ns cycle, 100 MHz 260 mA
ISB1 Automatic CS
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz 60 mA
10-ns cycle, 100 MHz 50 mA
ISB2 Automatic CS
Power-down
Current—CMOS Inputs
Max. VDD, Device Deselected,
VIN ≤ 0.3V or VIN > VDDQ – 0.3V,
f = 0
All speeds 5mA
ISB3 Automatic CS
Power-down
Current—CMOS Inputs
Max. VDD, Device Deselected, or
VIN ≤ 0.3V or VIN > VDDQ – 0.3V
f = fMAX = 1/tCYC
7.5-ns cycle, 133 MHz 40 mA
10-ns cycle, 100 MHz 30 mA
ISB4 Automatic CS
Power-down
Current—TTL Inputs
Max. VDD, Device Deselected,
VIN ≥ VIH or VIN ≤ VIL, f = 0 25 mA
Capacitance[9]
Parameter Description Test Conditions Max. Unit
CIN Input Capacitance TA = 25°C, f = 1 MHz,
VDD = 3.3V,
VDDQ = 3.3V
4pF
CCLK Clock Input Capacitance 4pF
CI/O Input/Output Capacitance 4pF
Note:
9. Tested initially and after any design or process changes that may affect these parameters.
CY7C1329
Document #: 38-05279 Rev. *A Page 8 of 15
AC Test Loads and Waveforms
Switching Characteristics Over the Op erating Range [11,12,13]
Parameter Description -133 -100 -75 UnitMin. Max. Min. Max. Min. Max.
tCYC Clock Cycle Time 7.5 10 13.3 ns
tCH Clock HIGH 1.9 3.2 5.0 ns
tCL Clock LOW 1.9 3.2 5.0 ns
tAS Address Set-up Before CLK Rise 1.5 2.5 2.5 ns
tAH Address Hold After CLK Rise 0.5 0.5 0.5 ns
tCO Data Output Valid After CLK Rise 4.2 5.0 7.0 ns
tDOH Data Output Hold After CLK Rise 1.5 2.0 2.5 ns
tADS ADSP, ADSC Set-u p Before CLK Rise 1.5 2.5 2.5 ns
tADH ADSP, ADSC Hold After CLK Rise 0.5 0.5 0.5 ns
tWES BWE, GW, BW[3:0] Set-up Before CLK Rise 1.5 2.5 2.5 ns
tWEH BWE, GW, BW[3:0] Hold After CLK Rise 0.5 0.5 0.5 ns
tADVS ADV Set-up Before CLK Rise 1.5 2.5 2.5 ns
tADVH ADV Hold After CLK Rise 0.5 0.5 0.5 ns
tDS Data Input Set-up Before CLK Rise 1.5 2.5 2.5 ns
tDH Data Input Hold After CLK Rise 0.5 0.5 0.5 ns
tCES Chip Sele ct Set-u p 1.5 2.5 2.5 ns
tCEH Chip Select Hold After CLK Rise 0.5 0.5 0.5 ns
tCHZ Clock to High-Z[12] 1.5 3.5 1.5 5 2 6 ns
tCLZ Clock to Low-Z[12] 0 0 0 ns
tEOHZ OE HIGH to Output High-Z[12, 13] 3.5 5.5 6ns
tEOLZ OE LOW to Output Low-Z[12, 13] 0 0 0 ns
tEOV OE LOW to Output Valid[12] 4.2 5.0 6ns
Notes:
10. Input waveform should have a slew rate of 1V/ns.
1 1. Unless otherwise noted, test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V , input p ulse l evels of 0 to 3. 0V, an d out put
loading of the specified IOL/IOH and load capacitance. Shown in (a) and (b) of AC Test Loads.
12. tCHZ, tCLZ, tEOV, tEOLZ, and tEOHZ are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ± 200 mV from
steady-state voltage.
13. At any given voltage and temperature, tEOHZ is less than tEOLZ and tCHZ is less than tCLZ.
OUTPUT
R = 317Ω
R = 351Ω
5pF
INCLUDING
JIG AND
SCOPE
(a) (b)
OUTPUT
RL= 50Ω
Z0= 50Ω
VL= 1.5V
3.3V ALL INPUT PULSES[10]
3.3V
GND
90%
10% 90%
10%
<3.3 ns <3.3 ns
(c)
CY7C1329
Document #: 38-05279 Rev. *A Page 9 of 15
Switching Waveforms
Write Cycle Timing[14, 15]
Notes:
14. WE is the combination of BWE, BW [3:0] and GW to define a Write cycle (see Write Cycle Descriptions table).
15. WDx stands for Write Data to Address X.
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
1a
Data-
In
tCYC
tCH
tCL
tADS
tADH
tADS tADH
tADVS tADVH
WD1 WD2 WD3
tAH
tAS
tWS tWH tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
2b 3a
1a
Single Write Burst Write Unselected
ADSP ignored with CE1 inactive
CE1 masks ADSP
= DON’T CARE
= UNDEFINED
Pipelined Write
2a 2c 2d
tDH
tDS
High-Z
High-Z
Unsel ected with CE2
ADV Must Be Inactive for ADSP Write
ADSC initiated Write
CY7C1329
Document #: 38-05279 Rev. *A Page 10 of 15
Read Cycle Ti ming [14, 16]
Note:
16. RDx stands for Read Data from Address X.
Switching Waveforms (continued)
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
2a 2c
1a
Data-
Out
tCYC tCH
tCL
tADS tADH
tADS
tADH
tADVS
tADVH
RD1 RD2 RD3
tAH
tAS
tWS tWH
tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
tCO
tDOE
2b 2c 2d 3a
1a
tOEHZ tDOH
tCLZ tCHZ
Single Read Burst Read Unselected
ADSP igno red with CE1 inactive
Suspend Burst
CE1 masks ADSP
= DON’T CARE = UNDEFINED
Pipelined Read
ADSC initiated Read
Unselected with CE2
CY7C1329
Document #: 38-05279 Rev. *A Page 11 of 15
Read/Write Cycle Timing[14,15,16 , 17]
Note:
17. Data bus is driven by SRAM, but data is not guaranteed.
Switching Waveforms (continued)
ADSP
CLK
ADSC
ADV
ADD
CE1
OE
GW
WE
CE2
CE3
1a
Data-
In/Out
tCYC tCH
tCL
tADS tADH
tADS
tADH
tADVS
tADVH
RD1 WD2 RD3
tAH
tAS
tWS tWH
tWH
tWS
tCES tCEH
tCES tCEH
tCES tCEH
tOELZ
tCO
tDOE
3a 3c 3d
1a
tOEHZ tDOH
TCHZ
Single Read Burst Read Unselected
ADSP ignored with CE1 inactive
CE1 masks ADSP
= DON’T CARE = UNDEFINED
Pipelined Read
Out 2a
In 3b
Out
Out Out Out
Single Write
tDS tDH
2a
Out
See Note 17
CY7C1329
Document #: 38-05279 Rev. *A Page 12 of 15
Pipeline Timing[18,19]
Notes:
18. Device originally deselected.
19. CE is the combination of CE2 and CE3. All chip selects need to be active in order to select the device.
Switching Waveforms (continued)
tAS
= DON’T CARE = UNDEFINED
tCLZ
tCHZ
tDOH
CLK
ADD
WE
CE1
Data In/Out
ADSC
ADSP
ADV
CE
OE
D(C)
tCYC
tCH tCL
tADS tADH
tCEH
tCES
tWEH
tWES
tCO
ADSP ignored
with CE1 HIGH
RD1 RD2 RD3 RD4 WD1 WD2 WD3 WD4
1a
Out 2a
Out 3a
Out 4a
Out 1a
In 2a
In 3a
In 4a
In
Back to Back Reads
ADSP initiated Reads
ADSC initiated Reads
CY7C1329
Document #: 38-05279 Rev. *A Page 13 of 15
ZZ Mode Timing[20, 21]
Notes:
20. Device must be deselected when entering ZZ mode. See Cycle Description table for all possible signal conditions to deselect the device .
21. I/Os are in three-state when exiting ZZ sleep mode.
Switching Waveforms (continued)
ADSP
CLK
ADSC
CE1
CE3
LOW
HIGH
ZZ tZZS
tZZREC
IDD IDD(active)
Three-state
I/Os
CE2
IDDZZ
HIGH
CY7C1329
Document #: 38-05279 Rev. *A Page 14 of 15
© Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry emb odied in a Cypress Semiconductor product. Nor does it convey or imply any license under paten t or other rights. Cypress Se miconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconducto r products in life-support systems application implies that the manu factur er assume s all risk of such use and in doi
ng so indemnifies Cypress Semiconductor against all charges.
Package Diagram
i486 is a trademark of Intel Corporation. Intel and Pentium are registered trademarks of Intel Corporation. PowerPC is a trademark
of I BM C orpo rati on. All prod uct and com pan y names men tioned i n thi s doc ument are the tra de mar ks of thei r re sp ect iv e h ol ders .
Ordering Information
Speed
(MHz) Ordering Code Package
Name Package Type Operating
Range
133 CY7C1329-133AC A101 100-lead Thin Quad Flat Pack Commercial
100 CY7C1329-100AC A101 100-lead Thin Quad Flat Pack
100-lead Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
CY7C1329
Document #: 38-05279 Rev. *A Page 15 of 15
Document Title: CY7C1329 64K x 32 Synchronous-Pipelined Cache RAM
Document Number:38-05279
REV. ECN NO Issue
Date Orig. of
Change Description of changes
** 114388 03/25/02 DSG Change from Spec number: 38-00561 to 38-05279
*A 114499 04/11/02 GLC Changed to 1.5 set-up
