4715FS23TB50D00 - NMB TECHNOLOGIES

®ISL54105A

TMDS Regenerator

The ISL54105A is a high-performance TMDS timing

regenerator containing a programmable equalizer and a

clock data recovery (CDR) func tion fo r each of the 3 TMDS

pairs in an HDMI or DVI signal. The TMDS data outputs of

the ISL54105A are regenerated and perfectly aligned to the

regenerated TMDS clock signal, creating an extremely

clean, low-jitter DVI/HDMI signal that can be easily

decoded by any TMDS receiver.

The ISL54105A can be used as a cable extender, to clean

up a noisy/jittery TMDS source, or to provide a very stable

TMDS signal to a finicky DVI or HDMI receiver.

Features

• Clock Data Recovery and Retiming

• Programmable pre-emphasis on output driver

• Programmable internal 50Ω, 100Ω, or high-Z termination

• Stand-alone or I2C software-contro lled operation

• 72 lead, 10mm x 10mm QFN package

• Pb-free (RoHS compliant)

Applications

• DVI/HDMI extenders

• Televisions/PC monitors/projectors

Block Diagram

2TX1

2TX0

2TXC

2TX2

CONFIGURATION AND CONTRO L

RES_BIAS

SCL

RESET

ACTIVITY

DETECT

ADDR

SDA

RX0

RX1

RX2

CDR

CH0

CDR

CH1

CDR

PLL

RES_TERM

BIAS GENERATION

TERMINATION AND

EQUALIZATION

TERMINATION

RXC 2

FIFO

CH2

Ordering Information

PART NUMBER TEMP. RANGE (°C) PACKAGE PKG. DWG. #

ISL54105ACRZ 0 to +70 72 Ld QFN (Pb-Free) L72.10x10B

NOTE : These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100%

matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil

Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

Key Features

Data Sheet June 4, 2008

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

FN6716.0

2FN6716.0

June 4, 2008

Absolute Maximum Ratings Thermal Information

Voltage on VD (referenced to GND). . . . . . . . . . . . . . . . . . . . . . 4.0V

Voltage on any Input Pin (referenced to GND) . . . -0.3V to VD+0.3V

Voltage on any “5V Tolerant” Input Pin

(referenced to GND). . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V

Current into any Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . ±20mA

ESD Classification

Human Body Model . . . >4 0 00V, hi g her v o l tage t es t ing i n p r ogres s

Machine Model. . . . . . . .>200V, higher voltage testing in progress

Thermal Resistance (Typical, Note 1) θJA (°C/W)

QFN Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

Maximum Biased Junction Temperature . . . . . . . . . . . . . . . . +125°C

Storage Temperature. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C

Pb-Free Reflow Profile. . . . . . . . . . . . . . . . . . . . . . . . .see link below

http://www.intersil.com/pbfree/Pb-FreeReflow.asp

Recommended Operating Conditions

Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to +70°C

Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .VD = 3.3V

CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and

result in failures not covered by warranty.

NOTE:

1. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech

Brief TB379.

Electrical Specifications S pecifications apply for VD = 3.3V, pixel rate = 165MHz, T A = +25°C, RES_TERM = 1kΩ, RES_BIAS = 3.16kΩ,

TMDS output load = 50Ω, TMDS output termination voltage VTERM = 3.3V unless otherwise noted.

SYMBOL PARAMETER COMMENT MIN

(Note 2) TYP MAX

(Note 2) UNIT

FULL CHANNEL CHARACTERISTICS

fDATA_MAX Maximum Rx Clock Frequency/Pixel Rate (Note 3) 165 225 MHz

fDATA_MIN Minimum Rx Clock Frequency/Pixel Rate 25 MHz

TMDS RECEIVER CHARACTERISTICS

VSENS Minimum Differential Input Sensitivity 50 150 mVP-P

R50 50Ω Termination Resistance 45 50 55 Ω

R100 100Ω Termination Resistance 90 97 110 Ω

CLKDUTY Rx Clock Duty Cycle 20 80 %

TMDS TRANSMITTER CHARACTERISTICS

jTX_CLOCK Total Jitter on Clock Outputs Independent of incoming jitter 32 ps

jTX_DATA Total Jitter on Data Outputs Independent of incoming jitter 52 ps

SKEWINTRA Intra-Pair (+ to -) Differential Skew ±4 ps

SKEWINTER Inter-Pair (channel-to-channel) Skew Added with respect to incoming

inter-pair skew 2UI

tRISE Rise Time into 50Ω Load to 3.3V 20% to 80% 80 240 ps

tFALL F all Time into 50Ω Load to 3.3V 20% to 80% 80 240 ps

TX VOH Single-Ended High Level Output Voltage VTERM - 10 VTERM + 10 mV

TX VOL Single-Ended Low Level Output Voltage VTERM - 600 VTERM - 400 mV

DIGITAL SCHMITT INPUT CHARACTERISTICS

VIH High Threshold Voltage 2.0 V

VIL High to Low Threshold Voltage 0.8 V

I Input Leakage Current ±10 nA

RPU Internal Pull-Up Resistance SDA and SCL pins 65 kΩ

RPD Internal Pull-Down Resistance AUTO_CH_SEL, CH_SEL_x,

RESET, ADDRx, PD pins 60 kΩ

CIN Input Capacitance 5pF

ISL54105AISL54105A

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DIGITAL OUTPUT CHARACTERISTICS

VOH Output HIGH Voltage, IO = 8mA 2.4 V

VOL Output LOW Voltage, IO = -8mA 0.4 V

POWER SUPPLY REQUIREMENTS

VDSupply Voltage 3 3.3 3.6 V

IDSupply Current Inputs driven by 165Mpixel/s

TMDS signals.

Default register settings

357 405 mA

IDSupply Current in Power-down Mode All available inputs driven by

165Mpixel/s TMDS signals. 20 26 mA

AC TIMING CHARACTERISTICS (2-WIRE INTERFACE)

fSCL SCL Clock Frequency 0 400 kHz

tAA SCL LOW to SDA Data Out Valid 200 470 ns

tBUF Time the Bus Must be Free Before a New

Transmission Can Start 1.3 µs

tLOW Clock LOW Time 1.3 0.1 µs

tHIGH Clock HIGH Time 0.6 0.2 µs

tSU:STA Start Condition Setup Time 0.6 0.03 µs

tHD:STA Start Condition Hold Time 0.6 0.07 µs

tSU:DAT Data In Setup Time 100 0.03 ns

tHD:DAT Data In Hold Time 0 ns

tSU:STO Stop Condition Setup Time 0.6 µs

tDH Data Output Hold Time 160 ns

NOTE:

2. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. T emperature limits established by characterization

and are not production tested.

3. Operation up to 165MHz is guaranteed. While many parts will typically operate up to 225MHz, operation above 165MHz is not guaranteed.

Electrical Specifications S pecifications apply for VD = 3.3V, pixel rate = 165MHz, T A = +25°C, RES_TERM = 1kΩ, RES_BIAS = 3.16kΩ,

TMDS output load = 50Ω, TMDS output termination voltage VTERM = 3.3V unless otherwise noted.

SYMBOL PARAMETER COMMENT MIN

(Note 2) TYP MAX

(Note 2) UNIT

tSU:STO

tDH

tHIGH

tSU:STA tHD:STA tHD:DAT

tSU:DAT

SCL

SDA IN

SDA OUT

tFtLOW

tBUF

tAA

FIGURE 1. 2-WIRE INTERFACE TIMING

ISL54105AISL54105A

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ISL54105A Pin Configuration

ADDR2

72 71 70 69 68 67 66 65 64 63 62 61

ADDR1

60 59

VD_ESD

TXC+

TXC-

TX2+

TX2-

TX1+

TX1-

TX0+

TX0-

VD_ESD

RES_TERM

RES_BIAS

RXC-

RXC+

19 20 21 22 23 24 25 26 27 28 29 30 31 32

ADDR3

ADDR4

RX1-

RX1+

RX2-

RX2+

ADDR5

RX0-

RX0+

RESET

33 34 35 36

ADDR6

TEST

SCL

SDA

58 57

ADDR0

56 55

ISL54105A

5FN6716.0

June 4, 2008

Pin Desc riptions

SYMBOL DESCRIPTION

RX0-, RX0+, RX1-, RX1+, RX2-, RX2+ TMDS Inputs. Incoming TMDS data signals.

RXC-, RXC+ TMDS Inputs. Incoming TMDS clock signals.

TX0-, TX0+, TX1-, TX1+, TX1-, TX1+ TMDS Outputs. TMDS output data for selected channel.

TXC-, TXC+ TMDS Outputs. TMDS output clock for selected channel.

SCL Digital input, 5V tolerant, 500mV hysteresis. Serial data clock for 2-wire interface.

Note: Internal 65kΩ pull-up to VD.

SDA Bidirectional Digital I/O, open drain, 5V tolerant. Serial data I/O for 2-wire interface.

Note: Internal 65kΩ pull-up to VD.

ADDR[6:0] Digital inputs, 5V tolerant. 7-Bit address for serial interface.

Note: Internal 60kΩ pull-down to GND.

AD Digital Output, 3.3V. AD = Activity Detect. Output goes high when an active TMDS clock is detected on

RXC.

RES_BIAS Tie to GND through a 3.16k external resistor. Sets up internal bias currents.

RES_TERM T ie to VD through a 1.0k 1% external resistor. During calibration, the termination resistor closest in value

to RES_TERM/20 (= 50Ω) is selected.

PD Digital Input, 3.3V. PD = Power-down. Pull high to put the ISL54105A in a minimum power consumption

mode.

Note: To ensure proper operation, this pin must be held low during power-up. It may be taken high 100ms

after the power supplies have settled to 3.3V ±10%.

When exiting Power-down, a termination resistor Recalibration cycle must be run to re-trim the

termination resistors (see register 0x03[7]).

Note: Internal 60kΩ pull-down to GND.

RESET Digital Input, 3.3V. Pull high then low to reset the mux. Tie to GND in final application.

Note: Internal 60kΩ pull-down to GND.

TEST Digital Input. Used for production testing only. Tie to GND in final application. This pin has an internal

pulldown to GND, so it is also acceptable to leave this pin floating.

VDPower supply. Connect to a 3.3V supply and bypass each pin to GND with 0.1µF.

VD_ESD Power supply for ESD protection diodes. Connect one of these pins (pin 41 or 53) to the 3.3V VD supply

rail with a low VF (0.4V or lower) Schottky diode, with the cathode connected to VD_ESD and the anode

connected to VD. Bypass each pin to GND with 0.1µF.

THERMAL PAD (GND) Ground return for the entire chip. The thermal pad must have a low impedance connection to GND for

the ISL54105A to function at all. The lower electrical impedance, the better the ground, and the better the

performance. A low thermal impedance between the thermal pad and the GND plane of the PCB will

dissipate the heat from the package more efficiently as well and is recommended.

ISL54105A

6FN6716.0

June 4, 2008

ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME DESCRIPTION

0x00 Device ID (read only) 3:0 Device Revision 1 = initial silicon, 2 = second revision, etc.

7:4 Device ID 3 = ISL54105A

0x01 Channel Activity Detect (read only) 1:0 Reserved Reserved

2 Activity Detect 0: TMDS clock not present on RXC

1: TMDS clock detected on RXC

0x02 Channel Selection (0x0C) 3:0 Reserved This nibble should always be set to 0xC.

4 Reset Full chip reset. Write a 1 to reset. Will set itself to 0 when

reset is complete.

5 Power-down 0: Normal Operation

1: Puts the chip in a minimal power consumption mode,

turning off all TMDS outputs and open-circuiting all TMDS

inputs.

This bit is OR'ed with the Power-down input pin. If either is

set, the chip will enter power-down. Serial

I/O stays operational in PD mode.

Note: When exiting Power-down, a termination resistor

Recalibration cycle must be run to re-trim the termination

resistors (see register 0x03[7]).

0x03 Input Control (0x12)

Recommended default: 0x63 0 Reserved Set to 1. Default value of 0 is OK, set to 1 to slightly reduce

power consumption.

1 Reserved Set to 1.

2 Tri-state Clock

Inputs 0: Clock inputs are terminated into 50Ω/100Ω.

1: Clock inputs are tri-stated (to allow chip to operate in

parallel with another TMDS receiver with fixed 50Ω

termination)

3 Tri-state Data Inputs 0: Data inputs are terminated into 50Ω/100Ω.

1: Data inputs are tri-stated (to allow chip to operate in

parallel with another TMDS receiver with fixed 50Ω

termination)

4 Activity Detect Mode 0: AC Activity . Activity detection is based on the presence of

AC activity on TMDS clock inputs. This setting (along with a

hysteresis of 20mV enabled) provides reliable activity

detection. (recommended setting)

1: Common Mode Voltage. If the common mode voltage is

above ~3.05V , the input is considered in active. This method

has been found to be unreliable with small signal swings and

should not be used. This setting is the silicon default but

should be changed in software for more reliable activity

detection.

5 Clock Rx Hysteresis Enables hysteresis for the clock inputs to prevent false clock

detection when both inputs are high. Data inputs do not get

hysteresis.

0: TMDS input hysteresis disabled

1: TMDS input hysteresis enabled. Eliminates false activity

detects on unconnected channels. (recommended setting)

6 Clock Rx Hysteresis

Magnitude Controls the amount of hysteresis in the clock inputs.

0: 10mV

1: 20mV (recommended setting)

7 Recalibrate 0: Normal Operation

1: Recalibrates termination resistance. To recalibrate, take

this bit high, wait at least 1ms, then take this bit low.

Calibration is automatically done after power-on, but

performing a recalibration after the supply voltage and

temperature have stabilized may result in termination

resistances closer to the desired 50Ω.

ISL54105A

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0x04 Termination Control (0x00) 1:0 Reserved Set to 00.

2 Data Termination 0: TMDS Data inputs terminated into 50Ω (normal

operation)

1: TMDS Data inputs terminated into 100Ω (for paralleled

inputs)

5:3 Reserved Set to 000.

6 Clk Termination 0: TMDS Clock inputs terminated into 50Ω (normal

operation)

1: TMDS Clock inputs terminated into 100Ω (f or paralleled

inputs)

7 Reserved Set to 0.

0x05 Output Options (0x00) 0 Tri-state Clock

Outputs 0: Normal Operation

1: Clock outputs tri-stated (allows another chip to drive the

output clock pins)

1 Tri-state Data

Outputs 0: Normal Operation

1: Data outputs tri-stated (allows another chip to drive the

output data pins)

2 Invert Output

Polarity 0: Normal Operation

1: The polarity of the TMDS data outputs is inverted

(+ becomes -, - becomes +). TMDS clock unchanged.

3 Reverse Output

Order 0: Normal Operation

1: CH0 data is output on CH2 and CH2 data is output on

CH0. No change to CH1.

0x06 Data Output Drive (0x00) 3:0 Transmit Current Transmit Drive Current for data signals, adjustable in

0.125mA steps. Clock current is fixed at 10mA.

0x0: 10mA

0x8: 11mA

0xF: 11.875mA

7:4 Transmit

Pre-emphasis Drive boost (in 0.125mA steps) added during first half of

each bit period for data signals. Clock signals do not have

pre-emphasis.

0x0: 0mA

0x8: 1mA

0xF: 1.875mA

0x07 Reserved (0xCC) 7:0 Reserved Default value of 0xCC is OK, can also be set to 0x00.

0x08 Equalization (0xCC) 3:0 Equalizer Gain Boost (dB) = 1dB + <gain value> * 0.8dB

0x0: 1dB boost at 800MHz

0xC: 10.6dB boost at 800MHz (default)

0xF: 13dB boost at 800MHz

7:4 Reserved Default value of 0xC is OK, can also be set to 0x0.

0x09 Test Pattern Generator (0x00) 1:0 Generator Mode When a 25MHz to 165MHz clock is applied to the clock

input, this function will output a PRBS7 pattern on the TX

pins.

0: Normal operation (test patterns disabled)

1: PRBS7 pattern

2: Low frequency toggle (0000011111…)

3: High frequency toggle (1010101010…)

Note: When switching from the high frequency toggle

pattern to the low frequency toggle pattern, you must first

select normal operation.

2 Enable PRBS7 Error

Counter Enables PRBS7 error counter in registers 0x0A to 0x0C.

0: Disable PRBS7 Error Counter

1: Enable PRBS7 Error Counter

ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME DESCRIPTION

ISL54105A

8FN6716.0

June 4, 2008

0x0A PRBS7 Error Counter Link 0 (read only) 7:0 PRBS7 Error

Counter Link 0 PRBS7 Error Counter of Link 0. Saturates at 0xFF. Reading

this register clears this register at end of read

0x0B PRBS7 Error Counter Link 1 (read only) 7:0 PRBS7 Error

Counter Link 1 PRBS7 Error Counter of Link 1. Saturates at 0xFF. Reading

this register clears this register at end of read

0x0C PRBS7 Error Counter Link 2 (read only) 7:0 PRBS7 Error

Counter Link 2 PRBS7 Error Counter of Link 2. Saturates at 0xFF. Reading

this register clears this register at end of read

0x10 PLL Bandwidth (0x10)

Recommended default: 0x12 1:0 PLL Bandwidth Selects between 4 PLL bandwidth settings

0: 4MHz (silicon default)

1: 2MHz

2: 1MHz (recommended default)

3: 500kHz

1MHz provides slightly better performance with high jitter/

high noise signals.

7:2 Reserved Keep set to 000100 binary.

ADDRESS REGISTER (DEFAULT VALUE) BIT(S) FUNCTION NAME DESCRIPTION

ISL54105A

9FN6716.0

June 4, 2008

Application Information

The ISL54105A is a TMDS regenerator , locking to the incoming

DVI or HDMI signal with triple Clock Data Recovery units

(CDRs) and a Phase Locked Loop (PLL). The PLL generates a

low jitter pixel clock from the incoming TMDS clock. The TMDS

data signals are equalized, sliced by the CDR, re-aligned to the

PLL clock, and sent out the TMDS outputs.

Activity Detection

The TMDS input is considered active using one of two

methods. The original default activity detect method (registe r

0x03b4 = 1) is to measure the co mmon mode of the TMDS

clock input for each channel. If the common mode is 3.3V, it

indicates that there is nothing connected to tha t input, or that

whatever is connected is turned off (in active). This has been

found to be relatively unreliabl e, particularly with weak sign als.

The preferred method of activity detection is lookin g for an

active AC signal on the TMDS clock input for that channel

(register 0x03b4 = 1). This is more robust, however

disconnected inputs will cause both inputs to the differential

receiver to be the same level - 3.3V. If the offset error of the

differential TMDS receiver is very small, the receiver can not

resolve a 1 or a 0 and will randomly switch between states,

which may be detected as an active clock. Register 0x03 bit s

5 and 6 allow a 10mV or 20mV offset to be added to the input

stage of the clock inputs, eliminating this problem. This offset

will slightly reduce the sensitivity of TMDS receiver for the

clock lines, but since the clock signals are much lower

frequency than the data, they will not be nearly as

attenuated, so this is not a problem in practice.

Again, using the AC activity detection method (register

0x03b4 = 0) is recommended.

Rx Equalization

applied to the TMDS inputs, providing 4 bits of control. The

equalization range available is from a minimum of 1dB boost

to a maximum of 13dB at 800MHz, in 0.8dB increments.

Ideally, the equalization is adjusted in the final application to

provide optimal performance with the specific DVI/HDMI

transmitter and cable used. In general, the amount of

equalization required is propo rtional to the cable length. If

the equalization must be fixed (can not be adjusted in the

final application), an equalization setting of 0xA works well

with short cables as well as medium to longer cables.

Tx Pre-emphasis

The transmit pre-emphasis function sinks additional current

during the first bit after every transition, increasing the slew

rate for a given capacitance, and helping to maintain the

slew rate when using longer/higher capacitance cables.

Pre-emphasis is controlled by register 0x06 bits 7:4, and

ranges from a minimum of 0mA (no pre-emphasis) to

1.875mA (max pre-emphasis).

PLL Bandwidth

The 2-bit PLL Bandwidth register controls the loop

bandwidth of the PLL used to recover the incoming clock

signal. The default 4MHz setting works well in most

applications, however a lower bandwidth of 1MHz has

proven to work just as well with good TMDS sources and

slightly better with marginal sources.

Power-down

The chip can be placed in a Power-down mode when not in

use to conserve power. Setting the Power-down bit (register

0x02 bit 5) to a 1 or pulling the PD input pin high pl aces the

chip in a minimal power consumption mode, turning off all

TMDS outputs and disconnecting all TMDS inputs. Serial I/O

stays operational in PD mode. Note that the PD pin must be

low during power-on in order to initialize the I2C in terface.

Note: When exiting Power-down, a termination resistor

Recalibration cycle mu st be run to re-trim the termination

resistors (see register 0x03[7]).

Typical Performance

Setup A (Figure 2) was used to capture the TMDS eye

diagrams shown in Figure 3 and Figure 4:

The 162.5Mpixel/s (UXGA 60Hz) DVI outp ut of the Chroma

2326 was terminated into a T PA2 Plug adapter and

measured with a LeCroy differential probe and 6MHz SDA

using the LeCroy’s software clock recovery. As Figure 3

shows, the amplitude of the TMDS signal is slightly low, but

the eye is otherwise acceptable.

CHROMA 2326

VIDEO PATTERN

GENERATOR @

UXGA 60Hz

DELL 2000FP

UXGA MONITOR

15m DUAL-LINK

DVI CABLE

FIGURE 2. TEST SETUP A

FIGURE 3 FIGURE 4

FIGURE 3. EYE DIAGRAM AT OUTPUT OF CHROMA

GENERATOR

ISL54105A

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June 4, 2008

Next, a 15m DualLink DVI cable was attached and

terminated into a female TPA2 adapter and the eye captured

in Figure 4.

The eye is not meeting the minimum requirements of either

the HDMI or DVI standards and the Dell Monitor is unable to

recover the data and display an image.

Setup B inserts an ISL54105A and an additional 15m cable

between the pattern generator and the monitor:

Given the input signal shown in Figure 4, the ISL54105A’s

TMDS output signal (Figure 6) is extremely clean. The

output is an improvement over the original signal coming

from the pattern generator in both amplitude and jitter.

The cleaner signal generated at the output of the ISL54105A

results in an improved eye at the end of another 15m cable

(Figure 7). The eye is open enough that the Dell 2000FP can

now display a UXGA image with no visible sparkle or other

artifacts.

Tx Loading Considerations

When the ISL54105A is powered-up and its Tx outputs are

disabled, via either the PD (power down) pin, the

power-down reg i ster bit (register 0x 02[5]), or the tri-state

outputs bits (register 0x05[1:0]), the Tx pins are high

impedance. In this state they will draw no current from the

Rx pins of any TMDS receiver they may be connected to.

However, if power to the ISL54105A is removed, the Tx pins

are no longer high-impedance. Figure 8 shows the relevant

equivalent circuit, including the internal ESD protection

diodes. For simplicity’s sake, only one of the eight Tx

outputs, ESD protection diodes, and Rx termination resistors

are shown.

When VD to the ISL54105A drops below ~2.7V and power is

applied to the external TMDS receiver, ESD protection

diodes inside the ISL54105A can become forward-biased,

FIGURE 4. CHROMA EYE DIAGRAM AFTER 15m CABLE

CHROMA 2326

VIDEO PATTERN

GENERATOR

15m DUAL-LINK

DVI CABLE

DELL 2000FP

UXGA MONITOR

ISL54105A 15m DUAL-LINK

DVI CABLE

FIGURE 5. TEST SETUP B

FIGURE 6

FIGURE 3

FIGURE 4 FIGURE 7

FIGURE 6. EYE DIAGRAM AT OUTPUT OF ISL54105A

FIGURE 7. ISL54105A EYE DIAGRAM AFTER 15m CABLE

ISL54105A

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drawing current from the external TMDS receiver it is

attached to.

This is non-ideal and can cause the ISL54105A to fail HDMI

Compliance Test 7-3 (“VOFF”). VOFF is the voltage across

each 50Ω RxN resistor when the power is removed from the

device containing the ISL54105A.

To prevent this leakage current, insert a Schottky diode

between the VD power net and the VD_ESD pins as shown

in Figure 9. With the addition of this diode the system will

pass compliance test 7-3.

Inter-Pair (Channel-to-Channel) Skew

The read pointers for Channel 0, 1, and 2 of the FIFO that

follows the CDR all have the same clock, so all 3 channels

transition within a few picoseconds of each other - there is

essentially no skew between the transitions of the three

channels.

However the FIFO read pointers may be positioned up to 2

bits apart relative to each other, introducing a random, fixed

channel-to-channel skew of skew of 1 or (much less

frequently) 2 bits. The random skew is introduced whenever

there is a discontinuity in the input signal (typically a video

mode change or a new mux channel selection). After the

CDRs and PLL lock, the skew is fixed until the next

discontinuity . This adds up to 2 bits of skew in addition to any

incoming skew, as shown in the following examples.

Figure 10 shows an input (the top three sign als) with

essentially no skew. After the ISL54105A locks on to the

signal, there may be 1 bit of skew on the output, as shown in

Figure 10.

When there is pre-existing skew on the input, the ISL54105A

can add up to 2 bits to the channel-to-channel skew. In the

example in Figure 11, the incoming red channel has 2.3 bits

of skew relative to the incoming green and blue. The FIFO’s

quantization (worst case) increases the total skew to 4.0 bits.

While increasing skew is not desirable, DVI and HDMI

receivers are re qu i red to have a minimum of 6 bi ts of inter-

pair skew tolerance, so the addition of 2 bits of skew is only a

problem with the most pathological cables and transmitters.

It does, however, limit the number of ISL54105As that can

be put in series (although statistically it is unlikely that all the

skews would line up in a worst-case configuration).

FIGURE 8. ISL54105A ESD PROTECTION DIODES

ISL54105A

VD_ESD (41 , 5 3)

3.3VTX

TxN

3.3VRX

50RxN

FIGURE 9. SCHOTTKY DIODE MODIFICATION

ISL54105A

VD_ESD (41 , 5 3)

3.3VTX

TxN

3.3VRX

50RxN

0.1μF

FIGURE 10. MAXIMUM ADDITIONAL INTERCHANNEL SKEW

FOR INPUTS WITH NO OR LITTLE SKEW