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Zarlink Semiconductor Inc.
Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.
Copyright 2007, Zarlink Semiconductor Inc. All Rights Reserved.
A full Design Manual is available to qualified
customers. To register, please send an email to
VoiceProcessing@Zarlink.com.
Features
• 100 MHz (200 MIPs) Zarlink voice processor with
Butterfly hardware accelerator and
breakpoint/interrupt controller
• On-board Data (26 Kbytes), Instruction (24
Kbytes RAM and Boot (3 Kbytes) ROM
• 2048 tap Filter co-processor shared across up to
16 separate functions in 128 tap increments
• Primary PCM port supports TDM (ST BUS, GCI or
McBSP framing) or SSI modes at bit rates of 128,
256, 512, 1024, 2048, 4096, 8192 or 16384 Kb/sec
• Separate slave (microcontroller) and master
(Flash) SPI ports, maximum clock rate = 25 MHz
• Watchdog and 2 auxiliary timers
• 11 General Purpose Input/Output (GPIO) pins
• General purpose UART port
• Bootloadable for future Zarlink software upgrades
• External oscillator or crystal/ceramic resonator
• 1.2 V Core; 3.3 V IO with 5 V-tolerant inputs
• IEEE-1149.1 compatible JTAG port
Applications
• Wireless Local Loop base stations and controllers
• Voice telephony gateways
• Digital, VoIP based and wireless PBX systems
• Echo Canceller pools
• Customer Premise equipment
• Integrated access devices
• SOHO gateways
June 2007
Ordering Information
ZL38015QCG1 100 Pin LQFP Trays, Bake &
Drypack
*Pb Free Matte Tin
-40°C to +85°C
ZL38015
Voice Processor
Data Sheet
Figure 1 - Functional Block Diagram
Data RAM
DSP
Boot
ROM
Instruction
RAM
27 K
Bytes
24 K
Bytes
3K
Bytes
Interrupt
Controller
ButterFly
Hardware
Accelerator
IRQ[15:0]
Filter
Co-processor
Watchdog
Master
SPI
Slave
SPI
UART
GPIO
AUX Timer1
AUX Timer2
IRQ
IRQ
APLL
MCLK
OSC
JTAG
IRQ
APLL
Timing
Generator
100 MHz MCLK
IRQ
IRQ
IRQ
IRQ
IRQ
Device Clocks
Chain
OSCi
OSCo
PCM_CLKi
PCM_LBCi
5
/
5
/
4
/
2
/
11
/
Core
PCM P1
PCM P0
Clock
IRQ
5
/
PCM P0
IRQ
5
/