Power Management & Multimarket
SiC- JFET
Silicon Carbide- Junction Field Effect Transistor
Final Datasheet
Rev. 2.0, <2013-09-11>
CoolSiC™
1200 V CoolSiC™ Power Transistor
IJW120R070T1
1) J-STD20 and JESD22
Final Datasheet 2 Rev. 2.0, <2013-09-11>
Description
Features
Ultra fast switching
Internal fast body diode
Low intrinsic capacitance
Low gate charge
175 °C maximum operating temperature
Benefits
Enabling higher system efficiency and/ or higher output power in same housing
Enabling higher frequency / increased power density solutions
System cost / space savings due to reduced cooling requirements
Higher system reliability due to enlarged junction temperatures rates
Reduced EMI
Applications
Solar Inverters
High voltage DC/ DC or AC/ DC conversion
Bidirectional Inverter
Compliant for applications according to climate class IEC 60721-3-4 (4K4H)
Table 1 Key Performance Parameters
Parameter
Value
Unit
VDS
1200
V
RDS(on) max
70
mΩ
QG, typ
92
nC
ID, pulse
114
A
Eoss @ 800 V
38
µJ
Table 2 Pin Definition
Pin 1
Pin 2
Pin 3
Gate
Drain
Source
Type / ordering Code
Package
Marking
Related links
IJW120R070T1 1)
PG-TO247-3
120R070T1
www.infineon.com/CoolSiC
CoolSiC™ is Infineon’s new family of active power switches based on
silicon carbide. Combining the excellent material properties of silicon
carbide with our normally-on JFET concept allows the next steps towards
higher performance paired with very high ruggedness. The extremely low
switching and conduction losses make applications even more efficient,
compact, lighter and cooler.
Gate
Pin 1
Drain
Pin 2
Source
Pin 3
IJW120R070T1
1200 V Silicon Carbide JFET
Gate
Drain
Source
Silicon Carbide JFET
IJW120R070T1
Description
Final Datasheet 3 Rev. 2.0, <2013-09-11>
Table of Contents
Description ............................................................................................................................................................. 2
1 Application considerations ............................................................................................................... 4
1.1 Introduction ........................................................................................................................................... 4
1.2 Driver circuit ......................................................................................................................................... 4
1.3 Device characteristics .......................................................................................................................... 5
1.3.1 Gate voltage window ............................................................................................................................ 5
1.3.2 Controllability ........................................................................................................................................ 5
1.3.3 Reverse biased behavior ..................................................................................................................... 6
1.3.4 Short circuit ruggedness ...................................................................................................................... 6
1.3.5 Switching and conduction losses ......................................................................................................... 6
1.4 Environmental Conditions .................................................................................................................... 6
2 Maximum ratings ................................................................................................................................ 7
3 Thermal characteristics ..................................................................................................................... 8
4 Electrical characteristics ................................................................................................................... 8
5 Electrical characteristics diagrams ................................................................................................ 10
6 Test circuits ...................................................................................................................................... 17
7 Package outlines .............................................................................................................................. 18
8 Revision History ............................................................................................................................... 19
Silicon Carbide JFET
IJW120R070T1
Application considerations
Final Datasheet 4 Rev. 2.0, <2013-09-11>
1 Application considerations
1.1 Introduction
Wide bandgap semiconductors are very attractive as a basematerial for power devices due to low losses,
improved temperature capability and high thermal conductivity. Infineon’s silicon carbide schottky diodes have
been commercially available on the market for many years. The material and technology knowhow has been
used to create new active switches based on silicon carbide providing significant improvement in the value
proposition in comparison to known devices such as:
• Resistive forward characteristic in first and third quadrant
• Monolithic integrated body diode, in switching performance very close to SiC schottky barrier diodes
• Very fast and controllable switching transients
• Very low capacitances and gate charge
These benefits result in higher system efficiency, allow higher switching frequencies, increased power density
and reduced cooling efforts. Due to the normally-on JFET concept any reliability-relevant issues from gate
oxides on SiC are completely avoided. To allow the use of this normally-on concept in voltage-source-inverter
configurations we propose the following driver circuit.
1.2 Driver circuit
Being a normally-on device, the JFET is in its on-state at zero gate voltage and will go into the off-state at
negative gate voltage. The normally off behavior can be easily realized by implementing a cascode
configuration with a low voltage MOSFET as shown in Figure 1 (state of the art cascode). At e.g. startup, the LV
MOSFET is in the off-state pushing the source of the JFET to positive potential relative to its gate and keeping
the JFET hence in the off-state.
In this conventional cascode, the LV MOSFET will be switched on and off together with the JFET in each
switching cycle. This approach has two major drawbacks: firstly, at turn-on additional switching losses will occur
as the output capacitance of the LV MOSFET needs to be charged from the positive rail voltage, secondly the
combination allows no direct control of the JFET due to the absence of a (JFET) - Drain- to- (LV MOS) - Gate
capacitance. These drawbacks can be avoided with the proposed “direct drive” approach. Here, the JFET is
directly switched on and off by applying a negative gate voltage and 0V respectively, whereas the series
connected LV MOSFET is always in its on- state. The LV MOSFET is turned off only during start- up and e.g.
emergency cases such as loss of auxiliary power supply. This solution represents the best match between
performance and safety requirements. The driving scheme with a dedicated driver is shown in Fig. 2 (direct
drive technology with 1EDI30J12Cx).
Figure 1: state of the art cascode Figure 2: direct drive technology with 1EDI30J12Cx
Silicon Carbide JFET
IJW120R070T1
Application considerations
Final Datasheet 5 Rev. 2.0, <2013-09-11>
1.3 Device characteristics
1.3.1 Gate voltage window
The gate electrode of the JFET shows, in contrary to isolated MOSFET concepts, a bipolar pn-junction like
characteristic: it get’s forward biased at around +2.5 V, hence a bipolar current will flow into the gate once the
gate- to- source voltage exceeds 2.5 V. This is uncritical and may be used to turn-on the device faster than with
the recommended 0 V turn-on. At 25 °C the threshold voltage of the channel can vary between -12 V and -15 V
(Figure 3: VGS(th)=f(Tj ) parameter: IGSS). The products will be delivered within three groups (bin1, bin2, bin3) of
1 V range each. For paralleling, it is only allowed to parallel devices from the same bin. The use of devices from
different bins for paralleling leads to different thermal device behavior. At a voltage of around -23 V the gate- to-
source junction enters reverse breakdown, which leads to a temperature dependend bipolar current flow across
the junction. In pure voltage driven turn-on and turn-off the lower gate voltage should stay within the window
between the pinch-off (threshold) and the punch-through (increased leakage) voltage. For fast and safe turn-off
it is strongly recommended to move the lower gate voltage level as close as possible to the punch-through
threshold.
Figure 3: VGS(th)=f(Tj ) parameter: IDSS=14 µA
1.3.2 Controllability
The JFET can be well controlled through its miller plateau with an external gate resistor (Figure 4: dVoff/ dt=
f(IDS), dVon/ dt= f(IDS), dIoff/ dt= f(IDS), dIon/ dt= f(IDS) parameter: Tj=25 °C, RG, external). Especially dI/ dt is saturating
at high current levels. This helps to avoid voltage overshoots in peak current conditions. It is strongly
recommended to use very low turn-off gate resistors (down to zero Ohm external gate resistor) to achive
maximum performance from the device as well as to avoid any parasitic dV/dt or dI/dt coupled turn-on effects.
As shown in the maximum rating division of the datasheet the external gate loop resistance should be lower
than 5.1 Ω.
Figure 4: dVoff/ dt= f(IDS), dVon/ dt= f(IDS), dIoff/ dt= f(IDS), dIon/ dt= f(IDS) parameter: Tj=25 °C, RG, external
-20
-19
-18
-17
-16
-15
-14
-13
-12
-11
-50 25 100 175
VGS(th) [V]
Tj [°C]
bin 3
gate off window
bin 1
bin 2
Silicon Carbide JFET
IJW120R070T1
Application considerations
Final Datasheet 6 Rev. 2.0, <2013-09-11>
1.3.3 Reverse biased behavior
The monolithically integrated body diode shows a switching performance close to that of an external SiC
schottky barrier diodes, renowned for their zero reverse recovery characteristic. Figure 5 (reverse recovery
characteristic ISD= 2 A left and ISD= 10 A; Tj= 150 °C; Vbulk=400 V; RG, external = (T1) 3.3 Ω, (T2) 10 Ω) shows the
reverse recovery characteristic of the monolithic integrated body diode of the JFET. The reverse recovery
charge is load current independent. To avoid any additional losses during hard commutation of the body diode,
it is recommended to couple the gate of the switch (acting as diode) with a very low external gate resistor to the
gate driver.
Figure 5:
reverse recovery characteristic ISD= 2 A left and ISD= 10 A; Tj= 150 °C; Vbulk=400 V; RG, external = (T1) 3.3 Ω,
(T2) 10 Ω
Due to the material properties of SiC the forward voltage drop Vf of the internal body diode is significantly higher
compared to a SiC schottky barrier diode. Therefore, active turn-on of the channel of the JFET during reverse
operation (synchronous rectification) is the preferred way of operation.
1.3.4 Short circuit ruggedness
Due to excellent material properties and a very high temperature level for intrinsic carrier generation the device
shows extremely good short circuit ruggedness.
1.3.5 Switching and conduction losses
The switching energies are typically one order of magnitude lower than the losses of IGBTs. It is noteworthy to
consider that the JFET, as pure majority carrier device, has no forward knee voltage and can be used on its
ohmic characteristic both in forward and reverse direction.
Nevertheless, the JFET shows a strong dependency of the switching energies as function of the used gate
resistor. A low resistive value of the gate resistor is recommended to operate the JFET at optimal conditions.
The conduction losses in comparison to Super Junction MOSFET’s are less temperature dependent. A factor of
only 1.6 between 25 °C and 100 °C is measurable.
1.4 Environmental Conditions
The parts are proofed according to IEC 60721-3-4 (4K4H). (Low air temperature -20 °C; High air temperature
+55 °C; Low relative humitidy 4 %; High relative humitidy 100 %; Low absolute humitidy 0.9 g/ m³; High absolute
humitidy 36 g/ m³…)
10mΩ
RG external
RG external
T2
T1
LLoad
VDS
VDS
VDS
IDS
IDS
IDS
VGS
VGS
VGS
Silicon Carbide JFET
IJW120R070T1
Maximum ratings
Final Datasheet 7 Rev. 2.0, <2013-09-11>
2 Maximum ratings
Table 3 Maximum ratings
Parameter
Symbol
Values
Unit
Note/Test Condition
Min.
Typ.
Max.
Continuous current, drain source 1)
IDS
–
–
35
A
VGS = 0 V; TC = 25 °C;
RthJC = RthJC, max
–
–
25 5)
VGS = 0 V; TC = 100 °C;
RthJC = RthJC, max
–
–
14 5)
VGS = 0 V; TC = 150 °C;
RthJC = RthJC, max
Pulsed current, drain source 1)
IDS, pulse
–
–
114
VGS = 0 V; TC = 25 °C;
RthJC = RthJC, max
–
–
98 5)
VGS = 0 V; TC = 100 °C;
RthJC = RthJC, max
–
–
88 5)
VGS = 0 V; TC = 150 °C;
RthJC = RthJC, max
Gate source voltage 2)
VGS
-19.5
–
2
V
Power dissipation
Ptot
–
–
238
W
TC = 25 °C
dV/ dt ruggedness, drain source
dVDS/ dt
–
–
80
V/ ns
IDS ≤ IDS, pulse
Pulsed current, source drain 1)
ISD, pulsed
–
–
114
A
VGS = -19 V; TC = 25 °C;
RthJC = RthJC, max
–
–
88 5)
VGS = -19 V; TC = 150 °C;
RthJC = RthJC, max
dV/ dt ruggedness, source drain
dVSD/ dt
–
–
80
V/ ns
ISD ≤ IDS, pulse
Gate loop resistance, turn off 3)
RG, off
–
–
5.1
Ω
Operating and storage temp. 4)
Tj;Tstg
-55
–
175
°C
Mounting torque
–
–
60
Ncm
M 2.5 screws
1) Limited by Tj, max
2) The device is proofed against VGS peaks. That allows to drive the parts shortly outside of the given maximum ratings
(VGS, max= 20 V, VGS, min= -50 V @ tp, max= 20 ns). This will result in a temporary gate leakage peak only.
3) See application information
4) Prolonged storage at high temperatures reduces the lifetime of the product. Tested according to EIA/JESD22-A103D
5) Limits derived from product characterization, parameter not measured during production
Silicon Carbide JFET
IJW120R070T1
Thermal characteristics
Final Datasheet 8 Rev. 2.0, <2013-09-11>
3 Thermal characteristics
Table 4 Thermal characteristics TO-247-3
Parameter
Symbol
Values
Unit
Note/Test Condition
Min.
Typ.
Max.
Thermal resistance, junction-case
RthJC
–
–
0.63
K/W
Thermal resistance, junction-
ambient
RthJA
–
–
62
leaded
Soldering temperature,
wavesoldering only allowed at leads
Tsold
–
–
260
°C
1.6 mm (0.063 in.) from case for
10 s
4 Electrical characteristics
Table 5 Static characteristics
Parameter
Symbol
Values
Unit
Note/Test Condition
Min.
Typ.
Max.
Breakdown voltage, drain source
V(BR)DSS
1200
–
–
V
VGS= -19.5 V; IDS= 1 mA;
TC= -50 °C
Gate threshold voltage 2)
VGS(th)
-13.1bin1
–
-12.0bin1
IDS= 14 µA; VDS= 40 V;
Tj= 25 °C
-14.1bin2
–
-12.9bin2
-15.0bin3
–
-13.9bin3
-13.5bin1
–
-12.3bin1
IDS= 14 µA; VDS= 40 V;
Tj= 100 °C; 1)
-14.5bin2
–
-13.2bin2
-15.4bin3
–
-14.2bin3
-13.8bin1
–
-12.4bin1
IDS= 14 µA; VDS= 40 V;
Tj= 150 °C; 1)
-14.8bin2
–
-13.3bin2
-15.7bin3
–
-14.3bin3
Drain- source leakage current
IDSS
–
3.3
42
µA
VDS= 1200 V; VGS= -19.5 V;
TC= 25 °C
–
6.6
84 1)
VDS= 1200 V; VGS= -19.5 V;
TC= 100 °C
–
13.2
168 1)
VDS= 1200 V; VGS= -19.5 V;
Tj= 150 °C
Gate- source leakage current
IGSS
–
–
125
VDS= 0 V; VGS=-19.5 V;
TC= 25 °C
–
–
500 1)
VDS= 0 V; VGS= -19.5 V;
TC= 100 °C
–
–
1000 1)
VDS= 0 V; VGS= -19.5 V;
TC= 150 °C
Drain- source on- state resistance
RDS(on)
–
0.055
0.070
Ω
VGS= 0 V; IDS=12.5 A;
TC= 25 °C
–
0.100
–
VGS= 0 V; IDS=12.5 A;
TC= 100 °C
–
0.130
–
VGS= 0 V; IDS=12.5 A;
TC= 150 °C
Gate resistance
RG
–
1.4
–
f= 1 MHz, open drain;
TC = 25 °C
1) Limits derived from product characterization, parameter not measured during production
2) For paralleling see application note
Silicon Carbide JFET
IJW120R070T1
Electrical characteristics
Final Datasheet 9 Rev. 2.0, <2013-09-11>
Table 6 Dynamic characteristics
Parameter
Symbol
Values
Unit
Note/Test Condition
Min.
Typ.
Max.
Input capacitance
Ciss
–
2000
–
pF
VGS= -19.5 V; VDS= 0 V;
f= 1 MHz
–
1600
–
VGS= -19.5 V; VDS= 800 V;
f= 1 MHz
Output capacitance
Coss
–
1350
–
VGS= -19.5 V; VDS= 0 V;
f= 1 MHz
–
102
–
VGS= -19.5 V; VDS= 800 V;
f= 1 MHz
Effective output capacitance,
energy related 1)
Co(er)
–
120
–
VGS= -19.5 V; VDS= 0 V/ 800 V;
TC=25 °C
Effective output capacitance,
time related 2)
Co(tr)
–
152
–
VGS= -19.5 V; VDS= 0 V/ 800 V;
TC=25 °C
Turn- on delay time
td(on)
–
51
–
ns
VDS= 800 V;
VGS= -19.5 V/ 0 V; ID= 26 A;
TC= 25 °C; RG(on),tot= 2 Ω
Turn- off delay time
td(off)
–
27
–
Rise time
tr
–
32
–
Fall time
tf
–
19
–
1) Co(er) is a fixed capacitance that gives the same stored energy as Coss while VDS is rising from 0 V to 800 V
2) Co(tr) is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 V to 800 V
Table 7 Gate charge characteristics
Parameter
Symbol
Values
Unit
Note/Test Condition
Min.
Typ.
Max.
Gate charge, gate to source
QGS
–
21
–
nC
VDS= 800 V to 0 V; IDS= 25 A;
VGS= -19.5 V to 0 V
Gate charge, gate to drain
QGD
–
51
–
Gate charge, total
QG
–
92
–
Gate plateau voltage
Vplateau
–
-8
–
V
Table 8 Reverse diode characteristics
Parameter
Symbol
Values
Unit
Note/Test Condition
Min.
Typ.
Max.
Diode forward voltage
VSD
–
7.2
–
V
ISD = 25 A; VGS= -19.5 V;
TC = 25 °C
–
8
–
ISD = 25 A; VGS= -19.5 V;
TC = 100 °C
–
8.1
–
ISD = 25 A; VGS= -19.5 V;
TC = 150 °C
Reverse recovery time
trr
–
14
–
ns
ISD = 25 A, VDS = 800 V,
RG= 0 Ω, Tj = 25 °C
Reverse recovery charge
Qrr
–
120
–
nC
Peak reverse recovery current
Irrm
–
15
–
A
Current slope forward
dIF/ dt
–
3
–
A/ns
Current slope reverse
dIrr/ dt
–
2.5
–
Silicon Carbide JFET
IJW120R070T1
Electrical characteristics diagrams
Final Datasheet 10 Rev. 2.0, <2013-09-11>
5 Electrical characteristics diagrams
Table 9
Typical output characteristic
Typical output characteristic
IDS= ƒ(VDS ); Tj= 25°C; parameter: VGS; Vpi 25°C
IDS= ƒ(VDS ); Tj= 100°C; parameter: VGS; Vpi 25°C
Table 10
Typical output characteristic
Typical drain- source on- state resistance
IDS= ƒ(VDS ); Tj= 150 °C; parameter: VGS; Vpi 25 °C
RDS(on)= ƒ(Tj ); VGS= 0 V; Tj= 25 °C; parameter: IDS
0
0.02
0.04
0.06
0.08
0.1
0.12
0.14
0.16
-50 -25 025 50 75 100 125 150 175
RDS(on) [Ω]
Tj [°C]
ID=25A
ID=13A
Silicon Carbide JFET
IJW120R070T1
Electrical characteristics diagrams
Final Datasheet 11 Rev. 2.0, <2013-09-11>
Table 11
Typical transfer characteristic- linear scale
Typical transfer characteristic- logarithmic scale
IDS= ƒ(VGS ); VDS= 30 V; parameter: Tj; Vpi 25 °C
IDS= ƒ(VGS ); VDS= 30 V; parameter: Tj; Vpi 25 °C
Table 12
Gate voltage window
Body diode characteristics
VGS(th) = ƒ(Tj ), VDS=40 V; parameter: IDSS=14 µA
1) lower gate voltage leads to increased leakage current
ISD= ƒ(VDS ); Tj= 25 °C parameter: VGS
0
20
40
60
80
100
120
140
160
180
200
-14 -12 -10 -8 -6 -4 -2 0 2
IDS [A]
VGS [V]
25°C
175 °C
1
10
100
1 000
-14 -12 -10 -8 -6 -4 -2 0 2
IDS [A]
VGS [V]
T = 25°C
-20
-19
-18
-17
-16
-15
-14
-13
-12
-11
-50 25 100 175
VGS(th) [V]
Tj [°C]
bin 3
gate off window 1)
bin 1
bin 2
0
10
20
30
40
50
0 2 4 6 8 10
ISD [A]
VDS (V)
-10 V
-5 V
0 V
-15 V
-20 V
Silicon Carbide JFET
IJW120R070T1
Electrical characteristics diagrams
Final Datasheet 12 Rev. 2.0, <2013-09-11>
Table 13
Typical gate charge
Typical breakdown voltage
VGS= ƒ(QG ); VDS= 800 V; parameter: IDS
VBR(dss)= ƒ(Tj ); IDS= 1 mA
Table 14
Typical capacitances
Typical stored energy in Coss
Ciss= ƒ(VDS ); VGS= -19 V; f= 1 MHz
Coss= ƒ(VDS ); VGS= -19 V; f= 1 MHz
Crss= ƒ(VDS ); VGS= -19 V; f= 1 MHz
Eoss= ƒ(VDS )
-20
-15
-10
-5
0
5
-100 -80 -60 -40 -20 020
VGS [V]
QG [nC]
ID = 2A
ID = 25A
1 540
1 550
1 560
1 570
1 580
1 590
1 600
1 610
1 620
-50 050 100 150 200
VBR(dss) [V]
Tj [°C]
10
100
1 000
10 000
0250 500 750 1000
C [pF]
VDS [V]
Crss
Ciss
Coss
0
10
20
30
40
50
60
0250 500 750 1000
Eoss [µJ]
VDS [V]
Silicon Carbide JFET
IJW120R070T1
Electrical characteristics diagrams
Final Datasheet 13 Rev. 2.0, <2013-09-11>
Table 15
Typical stored charge Coss
Maximum gate leakage current IGSS
Qoss= ƒ(VDS )
IGss= ƒ(Tj); parameter VGS= -19.5 V
Table 16
Typical switching losses- JFET vs. IDH15S120
Typical switching losses- JFET vs. JFET
Eoff= ƒ(RG); Vbulk= 800 V; Tj = 25 °C;
Vpi = -13.5 V; parameter: IDS
Eoff= ƒ(RG); Vbulk= 800 V; Tj = 25 °C;
Vpi = -13.5 V; parameter: IDS
0
20
40
60
80
100
120
140
160
0200 400 600 800 1000
Qoss [nC]
VDS [V]
1.E-04
1.E-03
1.E-02
-50 050 100 150 200
IGSS [A]
Tj [°C]
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 2 4 6 8 10
Eoff [mJ]
Rg off [Ω]
Ids= 1A
Ids= 10A
Ids= 20A
0.0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0 2 4 6 8 10
Eoff [mJ]
Rg off [Ω]
Ids= 1A
Ids= 10A
Ids= 20A
Silicon Carbide JFET
IJW120R070T1
Electrical characteristics diagrams
Final Datasheet 14 Rev. 2.0, <2013-09-11>
Table 17
Typical switching losses- JFET vs. IDH15S1201)
Typical switching losses- JFET vs. JFET 1)
Eon= ƒ(IDS); Vbulk= 800 V; Tj = 25 °C; RG on= 3.3 Ω;
Vpi = -13.5 V; parameter: Vbulk
Eon= ƒ(IDS); Vbulk= 800 V; Tj = 25 °C; RG on= 3.3 Ω;
Vpi = -13.5 V; parameter: Vbulk
Table 18
Typical switching losses- JFET vs. IDH15S1201)
Typical switching losses- JFET vs. JFET 1)
Eoff= ƒ(IDS); Vbulk= 800 V; Tj = 25 °C; RG off= 3.3 Ω;
Vpi = -13.5 V; parameter: Vbulk
Eoff= ƒ(IDS); Vbulk= 800 V; Tj = 25 °C; RG off= 3.3 Ω;
Vpi = -13.5 V; parameter: Vbulk
1) Measured with Push Pull stage close to the gate ; Rg on =0 Ω
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0 5 10 15 20 25 30
Eon [mJ]
IDS [A]
400V
800V
0.0
0.2
0.4
0.6
0.8
1.0
1.2
0 5 10 15 20 25 30
Eon [mJ]
IDS [A]
400V
800V
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0 5 10 15 20 25 30
Eoff [mJ]
IDS [A]
400V
800V
0.00
0.05
0.10
0.15
0.20
0.25
0.30
0 5 10 15 20 25 30
Eoff [mJ]
IDS [A]
400V
800V
Silicon Carbide JFET
IJW120R070T1
Electrical characteristics diagrams
Final Datasheet 15 Rev. 2.0, <2013-09-11>
Table 19
Power dissipation
Safe operating area
Ptot= ƒ(TC )
IDS= ƒ(VDS ); Tc= 25 °C; D= 0 parameter: tp
Table 20
Safe operating area
Safe operating area
IDS= ƒ(VDS ); Tc= 100 °C; D= 0 parameter: tp
IDS= ƒ(VDS ); Tc= 150 °C; D= 0 parameter: tp
0
20
40
60
80
100
120
140
160
180
200
050 100 150 200
Ptot [W]
Tc [°C]
0.1
1
10
100
110 100 1000
IDS [A]
VDS [V]
1µs
10µs
100µs
1ms
10ms
DC
0.1
1
10
100
110 100 1000
IDS [A]
VDS [V]
1 µs
10 µs
100 µs
1 ms
10 ms
DC
0.1
1
10
100
110 100 1000
IDS [A]
VDS [V]
1 µs
10 µs
100 µs
1 ms
10 ms
DC
Silicon Carbide JFET
IJW120R070T1
Electrical characteristics diagrams
Final Datasheet 16 Rev. 2.0, <2013-09-11>
Table 21
Safe operating area diode
Maximum transient thermal impedance
ISD max= ƒ(D= tp / T); Tc= 25 °C; parameter: tp
ZTHjc= ƒ(tp ); parameter: D= tp / T
1
10
100
1000
1E-04 1E-03 1E-02 1E-01 1E+00
ID max [A]
D
1E-06
1E-05
1E-04
1E-03
Pulse Width [s]
1E-3
1E-2
1E-1
1E0
1E-6 1E-4 1E-2 1E0
ZTHjc [K/W]
tp [s]
0.5
0.2
0.1
0.05
0.02
0.01
0
Silicon Carbide JFET
IJW120R070T1
Test circuits
Final Datasheet 17 Rev. 2.0, <2013-09-11>
6 Test circuits
Table 22
Switching times test circuit for inductive load
Switching time waveform
10mΩ
RG external
T2
LLoad
ton toff
tftr
td(on) td(off)
VDS
VGS
90%
10%
t
V
Table 23
Unclamped inductive load test circuit
Unclamped inductive waveform
10mΩ
RG external
T2
LLoad
VDS
IDS
V(BR)DS
t
V, I
Table 24
Test circuit for diode characteristics
Diode recovery waveform
10mΩ
RG external
T2
RG external
T1
LLoad
t
V, I
Irrm
IF
VDS
10% Irrm
trr
tFtS
QFQS
dIF/ dt
dIrr/ dt
VDS(peak)
Qrr = QF + QS
trr = tF + tS
VDS
IDS
Silicon Carbide JFET
IJW120R070T1
Package outlines
Final Datasheet 18 Rev. 2.0, <2013-09-11>
7 Package outlines
Figure 1 Outlines PG-TO247-3, dimensions in mm/inches
Silicon Carbide JFET
IJW120R070T1
Revision History
Final Datasheet 19 Rev. 2.0, <2013-09-11>
8 Revision History
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Edition 2011-12-09
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2011 Infineon Technologies AG
All Rights Reserved.
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IJW120R070T1, 1200 V CoolSiC™ Power Transistor
Revision History: Rev. 2.0, <2013-09-11>
Previous Revision:
Revision
Subjects (major changes since last version)
0.9
Target datasheet
1.0
Preliminary Datasheet
2.0
Final Datasheet
Published by Infineon Technologies AG
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