MC74VHC393DTR2G - ON SEMICONDUCTOR

April 1994

Revised October 2003

74VHC4046 CMOS Phase Lock Loop

74VHC4046

CMOS Phase Lock Loop

General Description

The VHC4046 is a low power phase lock loop utilizing

advanced silicon-gate CMOS technology to obtain high fre-

quency ope ration both in the phase comparator and VCO

sections. This device contains a low power linear voltage

controlled oscillator (VCO), a source follower, and three

phase comparators. The three phase comparators have a

common signal input and a common comparator input. The

signal input has a self biasing amplif ier all owing signals to

be either capacitively coupled to the phase comparators

with a small signal or directly coupled with standard input

logic levels. This device is similar to the CD4046 except

that the Zener diode of the metal gate CMOS device has

been replaced with a third phase comparator.

Phase Comparator I is an exclusive OR (XOR) gate. It pro-

vides a digital error signal that maintains a 90 pha se shift

between the VCO’s center frequency and the input signal

(50% duty cycle input waveforms). This phase detector is

more susceptible to locking onto harmonics of the input fre-

quency than ph ase comp arator I, but provide s bet ter noise

rejection.

Phase com par ato r III is an S R fl ip -flop gate. It can b e us ed

to provid e t he p ha se co mp arator fun cti on s an d is similar to

the first comparator in performance.

Phase com parator II is an edge se nsitive digital seque ntial

network. Two signal outputs are provided, a comparator

output and a phase pulse output. The comparator output is

a 3-ST ATE output that provides a signal that locks the VCO

output sign al to th e i n pu t sign al w ith 0 ph ase sh if t b etwe en

them. This comparator is more susceptible to noise throw-

ing the loop out of lock, but is less likely to lock onto har-

monics than the other two comparators.

In a typical application any one of the three comparators

feed an extern al fi lt er network whic h in tur n f eed s the VCO

input. This input is a very high impedance CMOS input

which also drives the source follower. The VCO’s operating

frequency is set by three external components connected

to the C1 A, C1B, R1 and R2 pins. A n inh ibit pin is pro vided

to disable the VCO and the source follower, providing a

method of putti ng the IC in a low pow er state.

The source follower is a MOS transistor whose gate is con-

nected to the VCO input and whose drain connects the

Demod ulator output. This output normally i s used by tying

a resi stor from pin 10 to grou nd, and provides a means of

looking at the VCO input without loading down modifying

the characteristics of the PLL filter.

Features

■Low dynamic pow er c onsu mp tion : (VCC = 4.5V)

■Maximu m VCO ope ra ting fre que ncy: 12 MHz

(VCC = 4.5V)

■Fast comparator response time (VCC = 4.5V)

Comparator I: 25 ns

Comparator II: 30 ns

Comparator III: 25 ns

■VCO has high linearity and high temperature stability

■Pin and function compatible with the 74HC4046

Ordering Code:

Surface m ount pa c k ages are als o available on Ta pe and Reel. Specify by appending the s uffix let te r “X” to th e ordering co de.

Order Number Package Number Package Description

74VHC4046M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

74VHC4046MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

74VHC4046N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

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74VHC4046

Connection Diagram

Block Diagram

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74VHC4046

Absolute Maximum Ratings(Note 1)

(Note 2) Recommended Operating

Conditions

Note 1: Maxim um R at ings are th ose value s be yond which da mag e to the

device may occur.

Note 2: U nless otherwise s pecified all v olt ages are referenc ed to ground.

Note 3: Pow er D iss ipat ion temp er atur e derat ing — plas tic “N” package: −

12 mW/°C from 65°C to 85°C.

DC Electrical Characteristics (Note 4)

Note 4: For a power su pply of 5 V ±10% the w orst cas e output v oltages (VOH, and VOL) occur for VHC at 4.5V. Thus the 4.5V values should be used when

designi ng with t his s upply. Wors t c as e VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage cur-

rent (IIN, ICC, and IOZ) occur for CMOS at the h igher volta ge and so th e 6. 0V values s hould be used.

Supply Voltage (VCC)−0.5 to + 7.0V

DC Input Voltage (VIN)−1.5 to VCC +1.5V

DC Output Voltage (VOUT)−0.5 to VCC + 0.5V

Clamp Diode Current (IIK, IOK)±20 mA

DC Output Current per pin (IOUT)±25 mA

DC VCC or GND Current,

per pin (ICC)±50 mA

Storage Temperature Range (TSTG)−65°C +150°C

Power Dissipation (PD)

(Note 3) 600 mW

S.O. Package onl y 500 mW

Lead Temperature (TL)

(Solder i ng 10 seco nds) 260°C

Min Max Units

Supply Voltage (VCC)26V

DC Input or Output Voltage 0 VCC V

(VIN, VOUT)

Operating Temperature Range (TA)−40 +85 °C

Input Rise or Fal l Times

(tr, t f)V

CC = 2.0V 1000 ns

VCC = 4.5V 500 ns

VCC = 6.0V 400 ns

Symbol Parameter Conditions VCC TA=25°CT

A=−40 t o 85°CUnits

Typ Guar ant eed Lim its

VIH Minimum HIGH Level 2.0V 1.5 1.5 V

Input Voltage 4.5V 3.15 3.15 V

6.0V 4.2 4.2 V

VIL Maximum LOW Level 2.0V 0.5 0.5 V

Input Voltage 4.5V 1.35 1.35 V

6.0V 1.8 1.8 V

VOH Minimum HIGH Level VIN = VIH or VIL 2.0V 2.0 1.9 1.9 V

Output Voltage |IOUT| ≤ 20 µA 4.5V 4.5 4.4 4.4 V

6.0V 6.0 5.9 5.9 V

VIN = VIH or VIL

|IOUT| ≤ 4.0 mA 4.5V 4.2 3.98 3.84 V

|IOUT| ≤ 5.2 mA 6.0V 5.7 5.48 5.34 V

VOL Maximum LOW Level VIN = VIH or VIL 2.0V 0 0.1 0.1 V

Output Voltage |IOUT| ≤ 20 µA4.5V00.10.1V

6.0V 0 0.1 0.1 V

VIN = VIH or VIL

|IOUT| ≤ 4.0 mA 4.5V 0.2 0.26 0.33 V

|IOUT| ≤ 5.2 mA 6.0V 0.2 0.26 0.33 V

IIN Maximum Input Current (Pins 3,5,9) VIN = VCC or GND 6.0V ±0.1 ±1.0 µA

IIN Maximum Input Current (Pin 14) VIN = VCC or GND 6.0V 20 50 80 µA

IOZ Maximum 3-STATE Outpu t VOUT = VCC or GND 6.0V ±0.25 ±2.5 µA

Leakage Current (Pin 13)

ICC Maximum Quiescent Supply VIN = VCC or GND 6.0V 30 40 65 µA

Current IOUT = 0 µA

VIN = VCC or GND 6.0V 600 750 1200 µA

Pin 14 Open

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74VHC4046

AC Electrical Characteristics VCC = 2.0 to 6.0V, CL = 50 pF, tr = tf = 6 ns (unless otherwise specified.)

Symbol Parameters Conditions VCC TA=25C TA=−40 to 85°CUnits

Typ Guaranteed Limits

AC Coupled C (series) = 100 pF 2.0V 25 100 150 mV

Input Sensitivity, fIN = 500 kHz 4.5V 50 150 200 mV

Signal In 6.0V 135 250 300 mV

tr, tfMaximum Output 2.0V 30 75 95 ns

Rise and Fall Time 4.5V 9 15 19 ns

6.0V 8 12 15 ns

CIN Maximum Input 7 pF

Capacitance

Phase Comparator I

tPHL, tPLH Maximum Propagation 3.3V 65 117 146 ns

Delay 4.5V 25 40 50 ns

6.0V 20 34 43 ns

Phase Comparator II

tPZL Maximum 3-STATE 3.3V 75 130 160 ns

Enable Time 4.5V 25 45 56 ns

6.0V 22 38 48 ns

tPZH, tPHZ Maximum 3-STATE 3.3V 88 140 175 ns

Enable Time 4.5V 30 48 60 ns

6.0V 25 41 51 ns

tPLZ Maximum 3-STATE 3.3V 90 140 175 ns

Disable Time 4.5V 32 48 60 ns

6.0V 28 41 51 ns

tPHL, tPLH Maximum Propagation 3.3V 100 146 180 ns

Delay HIGH-to-LOW 4.5V 34 50 63 ns

to Phase Pulses 6.0V 27 43 53 ns

Phase Comparator III

tPHL, tPLH Maximum Propagation 3.3V 75 117 146 ns

Delay 4.5V 25 40 50 ns

6.0V 22 34 43 ns

CPD Maximum Power All Comparators 130 pF

Dissipation VIN = VCC and GND

Capacitance

Voltage Controlled Oscillator (Specified to operate from VCC = 3.0V to 6.0V)

fMAX Maximum C1 = 50 pF

Operating R1 = 100Ω4.5V 7 4.5 MHz

Frequency R2 = ∞6.0V 11 7 MHz

VCOin = VCC

C1 = 0 pF 4.5V 12 MHz

R1 = 100Ω6.0 14 MHz

VCOin = VCC

Duty Cycle 50 %

Demodulator Output

Offset Voltage Rs = 20 kΩ4.5V 0.75 1.3 1.5 V

VCOin–Vdem

Offset Rs = 20 kΩ4.5V

Variation VCOin = 1.75V 0.65 V

2.25V 0.1

2.75V 0.75

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74VHC4046

Typical Performance Characteristics

Ty pi cal C en ter Fr eq uen cy

vs R1, C1VCC = 4.5V Typical Center Frequency

vs R1, C1VCC = 6V

Typica l Offset Frequency

vs R2, C1VCC = 4.5V Typical Offset Frequency

vs R2, C1VCC = 6V

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74VHC4046

Typical Performance Characteristics (Continued)

VHC4046 Typical VCO Power Dissipation

@ Center Frequency vs R1

VHC4046 Typical VCO Powe r

Dissipation @ fMIN vs R2

VHC4046 VCOIN vs fOUT VCC = 4.5V VHC4046 VCOIN vs fOUT VCC = 4.5V

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74VHC4046

Typical Performance Characteristics (Continued)

VHC4046 VCOOUT vs

Temperature VCC = 4.5V VHC4046 VCOOUT vs

Temperature VCC = 6V

VHC4046 Typical Source Follower

Power Dissi pa tio n vs RS Typical fMAX/fMIN vs R2/R1

VCC = 4.5V & 6V fMAX/fMIN

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74VHC4046

Typical Performance Characteristics (Continued)

VHC4046 Typical VCO Linearity vs R1 & C1VHC4046 Typical VCO Linearity vs R1 & C1

VCO WITH OUT OFFSET

R2 = ∞ VCO WITH OFFSET

Comparator I Comparator II & III

R2=∞ R2≠∞ R2=∞ R2≠∞

–Given: fO–Given: fO and fL–Given: fMAX –Given: fMIN and f MAX

–Use fO with curve titled –Calculate fMIN from the –Calculate fO from the –Use fMIN with curve titled

center freque ncy vs R 1, C equation fMIN = fO − fLeq uat ion fO = fMAX/2 offset frequency vs R2,

to determine R1 and C1–Use fMIN with curve titled –Use fO with curve titled C to determine R2 and C1

offset frequency vs R2, C center frequency vs R1, C –Calculate fMAX/fMIN

to determine R2 and C1to determine R1 and C1–Use fMAX/fMIN with curve

–Calculate fMAX/fMIN from titled fMAX/fMIN vs R2/R1

the equation fMAX/fMIN =to determine ratio R2/R1

fO + fL/fO − fLto obtain R1

–Use fMAX/fMIN with curve

titled fMAX/fMIN vs R2/R1

to determine ratio R2/R1

to obtain R1

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74VHC4046

Detailed Circuit Description

VOLTAGE CONTROLLED OSCILLATOR/SOURCE

FOLLOWER

The VCO requires two or three external components to

operate. These are R1, R2, C1. Resistor R1 and capacit or

C1 are selected to determine the center frequency of the

VCO. R1 controls the lock range. As R1’s resistance

decreases the range of fMIN to fMAX increases. Thus the

VCO’s gain increases. As C1 is changed the offset (if used)

of R2, and the center frequency is changed. (See typical

performance curves) R2 can be used to set the offset f re-

quency with 0V at VCO input. If R2 is omitted the VCO

range is from 0Hz. As R2 is decreased the offset frequency

is increas ed. The effect of R2 is shown in the des ign inf or-

mation table and typical performance curves. By increasing

the value of R2 the lock range of the PLL is offset above

0Hz and the gain (Hz/Volt) does not change. In general,

when offset is desired, R2 and C1 should be chosen first,

and then R 1 shoul d be chosen to obtain t he prop er center

frequency.

FIGURE 1. Logic Diagram for VCO

Internally the resistors set a current in a current mirror as

shown in Fig ure 1. T he mir rored curre nt drive s one side of

the capacito r once the capacitor charges up to the th resh-

old of the Schmitt Trigger the oscillator logic flips the

capacitor over and causes the mirror to charge the oppo-

site side of the capa citor. The output fr om the inter na l logic

is then taken to pin 4.

The input to the VCO is a very high impedance CMOS

input and so it will not load down the loop filter, easing the

filters design. In order to make signals at the VCO input

accessible without degrading the loop performance a

source follower transistor is provided. This transistor can

be used by connecting a resistor to ground and its drain

output will follow the VCO input signal.

An inhibit signal is provided to allow disabling of the VCO

and the source follower. This is useful if the internal VCO is

not being used. A logic high on inhibit disables the VCO

and source follower.

The output of the VCO is a standard high speed CMOS

output with an equivalent LSTTL fanout of 10. The VCO

output is approximately a square wave. This output can

either dire ctly f eed the com pa rat or i n pu t of t he pha se co m-

parators or feed external prescalers (counters) to enable

frequency synthesis.

PHASE COMPARATORS

All three phase comparators share two inputs, Signal In

and Comparator In. The Signal In has a special DC bias

network that enables AC coupling of input signals. If the

signals are not AC coupled then this input requires logic

levels the same as standard 74VHC. The Comparator input

is a standar d digital input . Both input stru ctures are s hown

in Figure 2.

The out puts of the se com parato rs are essent ially sta ndard

74VHC voltage outputs. (Comparator II is 3-STATE.)

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74VHC4046

Detailed Circuit Description (Continued)

FIGURE 2. Logic Diagram for Phase Comparator I and the Common Inp ut Circuit for All Three Comparators

FIGURE 3. Typical Phase Comparator I. Waveforms

Thus in normal operation VCC and ground voltage levels

are fed to the loop filter. This differs from some phase

detectors which supply a current output to the loop filter

and this should be considered in the design. (The CD4046

also provides a voltage.)

Figure 4 shows the state tables for all three comparators.

PHASE COMPARATOR I

This comparator is a simple XOR gate similar to the

74HC86, and its operation is similar to an overdriven bal-

anced modulator. To maximize lock range the input fre-

quencies must have a 50% duty cycle. Typical input and

output waveform s ar e sh own i n Fig u re 3. T he out put of th e

phase detector feeds the loop filter which averages the out-

put voltage. The frequency range upon which the PLL will

lock onto if initially out of lock is defined as the capture

range. The capture range for phase detector I is dependent

on the loop filter employed. The capture range can be as

large as the lock range which is equal to the VCO fre-

quency range.

To see how the detecto r operates r efer to Figure 3. When

two sq uare wave inputs are applied to this com parator, an

output waveform whose duty cycle is dependent on the

phase difference between the two signals results. As the

phase d ifference i ncr eas es th e o utpu t du ty cyc l e incr ea ses

and the voltage after the loop filter increases. Thus in order

to achieve lock, when the PLL input frequency increases

the V CO in put volta ge mu st incre ase and th e phas e differ-

ence between co mparator in and signal in will increase. At

an input frequency equal fMIN, the VCO input is at 0V an d

this re quir es the pha se de tector outpu t to be gro und hen ce

the two input signals must be in phase. When the input fre-

quency is fMAX then the VCO input must be VCC and the

phase detector inputs must be 180° out of phase.

The XO R is m ore sus cept ible to l ocking onto h armon ics of

the sign al input than th e digital p hase detecto r II. Thi s can

be seen by noticing that a signal 2 times the VCO fre-

quency results in the same output duty cycle as a signal

equal t he VCO freque ncy. The di fference is t hat the out put

frequency of the 2f example is twice that of the other exam-

ple. The lo op filte r and the VCO range shou ld be designed

to prevent locking on to harmonics.

PHASE COMPARATOR II

This detector is a digital memory network. It consists of four

flip-flop s and s ome gating logi c, a th ree sta te outp ut an d a

phase pul se ou tput a s shown i n Fig ur e 5. This comparator

acts on ly on the po sitive edges of the inpu t signals an d is

thus independent of signal duty cycle.

Phase comparator II operates in such a way as to force the

PLL into lock with 0 phase difference between the VCO

output and the signal input positive waveform edges. Fig-

ure 6 shows some typical loop waveforms. First assume

that the si g nal i n put pha se is lead i ng t he c om par ato r i np ut.

This me an s th at th e VCO’s frequency must be increased to

bring its leading edge into proper phase alignment. Thus

the phase detector II output is set HIGH. This will cause the

loop filter to charge up th e VCO input increa sing the VCO

frequency. Once the lea ding edge of t he comparato r input

is detected the output goes 3-STATE holding the VCO

input at the loop filter voltage. If th e VCO still lags the sig-

nal then the phase detector will again charge up to VCO

input for the ti m e be twee n the le adin g edg es of both wa ve-

forms.

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74VHC4046

Detailed Circuit Description (Continued)

Phase Comparator State Diagrams

FIGURE 4. PLL State T ables

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74VHC4046

Detailed Circuit Description (Continued)

FIGURE 5. Logic Diagram for Phase Comparator II

FIGURE 6. Typical Phase Comparator II Output Waveforms

If the VCO l eads the signa l then when the l eading edg e of

the VCO is seen the output o f the phase c omparato r goes

LOW. This discharg es the loop filte r until the leading edge

of the signal is detected at which time the output 3-STATEs

itself again. This has the effect of slowing down the VCO to

again make the rising edges of both waveform coincident.

When the PLL is out of lock the VCO will be running either

slower or faster than the signal input. If it is runnin g slowe r

the phase detector will see more signal rising edges and so

the outp ut of the phase co mparator w ill be high a majo rity

of the time , raising t he VCO ’s frequency. Conver sely, if the

VCO is running faster than the signal the output of the

detector will b e low most of t he time an d the VCO’s output

frequency will be decreased.

As one can see when the PLL is locked the output of phase

comparator II will be almost always 3-STATE except for

minor corrections at the leading edge of the waveforms.

When the detector is 3-STATE the phase pulse output is

HIGH. This ou tpu t can b e used to de ter mine when the P LL

is in the locked condition.

This detector has several interesting characteristics. Over

the entire VCO frequency range there is no phase differ-

ence between the comparator input and the signal input.

The lock range of the PLL is the same as the capture

range. Minimal power is consumed in the loop filter since in

lock the detector output is a high impedance. Also when no

signal is present the detector will see only VCO leading

edges, and so the comparator output will stay low forcing

the VCO to fMIN operating frequency.

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74VHC4046

Detailed Circuit Description (Continued)

Phase comparator II is more susceptible to noise causing

the phase lock loop to unlock. If a n oise pulse is seen on

the signal input, the comparator treats it as another positive

edge of the signal and will cause the output to go HIGH

until the VC O leading ed ge is seen, potent ially for a wh ole

signal input period. This would cause the VCO to speed up

during that time. When using the phase comparator I the

output of that phase detector would be disturbed for only

the short duratio n of th e noi se spik e and would cause less

upset.

PHASE COMPARATOR III

This comparator is a simple S-R Flip-Flop which can func-

tion as a phase comparator Figure 7. It has some similar

characteristics to the edge sensitive comparator. To see

how this detector works assume input pulses are applied to

the signal and comparator inputs as shown in Figure 8.

When the signal input leads the comparator input the flop is

set. This will charge up the loop filter and cause the VCO to

speed up , bri nging th e comp arato r into p hase w ith the sig-

nal input. When using short pulses as input this comparator

behaves very similar to the second comparator. But one

can see that if the signal input is a long pulse, the output of

the comparator will be forced to a one no matter how many

comparator input pulses are received. Also if the VCO input

is a square wave (as it is) and the signal input is pulse then

the VCO will force the comparator output LOW much of the

time. The refore it i s ideal to condi tion the signa l and com-

parator input to short pulses. This is most easily done by

using a series capacitor.

FIGURE 7. Phase Comparator III Logic Diagram

FIGURE 8. Typical Waveforms for Phase C omparator III

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74VHC4046

Physical Dimensions inches (millimeters) unless otherwise noted

16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow

Package Number M16A

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74VHC4046

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lea d Th in S hri n k Small Ou tlin e Pack age (TSSOP ), JED EC MO-1 53, 4.4mm Wide

Package Number MTC16

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74VHC4046 CMOS Phase Lock Loop

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

Package Number N16E

Fairchild does not assu me any responsibility for use of any circuitry de scribed, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

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