MC68HC912DG128CPV8 - Motorola / Freescale Semiconductor

MC68HC912DG128/D

MC68HC912DG128

Advance Information

April 27, 1999

MC68HC912DG128

MOTOROLA List of Sections 3

List of Sections

List of Sections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

Central Processing Unit. . . . . . . . . . . . . . . . . . . . . . . . . . 17

Pinout and Signal Descriptions. . . . . . . . . . . . . . . . . . . . 23

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

Resource Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Bus Control and Input/Output . . . . . . . . . . . . . . . . . . . . 75

Flash EEPROM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Resets and Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . 109

I/O Ports With Key Wake-Up. . . . . . . . . . . . . . . . . . . . . 119

Clock Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

Pulse-Width Modulator . . . . . . . . . . . . . . . . . . . . . . . . . 153

List of Sections

MC68HC912DG128

4 List of Sections MOTOROLA

Enhanced Capture Timer . . . . . . . . . . . . . . . . . . . . . . . 169

Multiple Serial Interface . . . . . . . . . . . . . . . . . . . . . . . . 205

Inter-IC Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229

MSCAN Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Analog-To-Digital Converter (ATD) . . . . . . . . . . . . . . . 293

Development Support. . . . . . . . . . . . . . . . . . . . . . . . . . 305

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . 329

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363

Literature Updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365

MC68HC912DG128

MOTOROLA Table of Contents 5

Table of Contents

List of Sections

Table of Contents

General Description Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

HC912DG128 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Central Processing

Unit Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Indexed Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Pinout and Signal

Descriptions Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23

MC68HC912DG128 Pin Assignments in 112-pin QFP . . . . . . . . . . .23

Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Port Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

Registers Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45

Operating Modes Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Resource Mapping Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

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MC68HC912DG128

6 Table of Contents MOTOROLA

Internal Resource Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

Flash EEPROM mapping through internal Memory Expansion . . . . 64

Miscellaneous System Control Register . . . . . . . . . . . . . . . . . . . . . . 69

Mapping test registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

Bus Control and In-

put/Output Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . 75

Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

Flash EEPROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Flash EEPROM Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

Flash EEPROM Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . 94

Erasing the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

Program/Erase Protection Interlocks . . . . . . . . . . . . . . . . . . . . . . . . 99

Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

Test Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

EEPROM Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

Resets and Inter-

rupts Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Maskable interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

Interrupt Control and Priority Registers . . . . . . . . . . . . . . . . . . . . . . 112

Interrupt test registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Effects of Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

Table of Contents

MC68HC912DG128

MOTOROLA Table of Contents 7

I/O Ports With Key

Wake-Up Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Key Wake-up and port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .120

Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

Clock Functions Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Clock Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Acquisition and Tracking Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Limp-Home and Fast STOP Recovery modes . . . . . . . . . . . . . . . . .130

System Clock Frequency formulas . . . . . . . . . . . . . . . . . . . . . . . . . .141

Clock Divider Chains . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . .146

Real-Time Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Clock Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

Pulse-Width Modu-

lator Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

PWM Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

PWM Boundary Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Enhanced Capture

Timer Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . . . . . .176

Timer Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

Timer and Modulus Counter Operation in Different Modes . . . . . . .204

Multiple Serial Inter-

face Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Serial Communication Interface (SCI) . . . . . . . . . . . . . . . . . . . . . . .206

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

Port S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

Inter-IC Bus Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

IIC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

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MC68HC912DG128

8 Table of Contents MOTOROLA

IIC System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

IIC Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232

IIC Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236

IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245

MSCAN Controller Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251

External Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252

Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253

Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258

Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261

Protocol Violation Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263

Low Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264

Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267

Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268

Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270

Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . 271

Programmer’s Model of Control Registers . . . . . . . . . . . . . . . . . . . 276

Analog-To-Digital

Converter (ATD) Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293

Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294

ATD Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295

ATD Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304

Development Sup-

port Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305

Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307

Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321

Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328

Electrical Character-

istics Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Important Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329

Tables of Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331

Glossary

Revision History Major HC912DG128 specification changes – April 1999 . . . . . . . . 363

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MC68HC912DG128

MOTOROLA Table of Contents 9

Literature Updates Literature Distribution Centers . . . . . . . . . . . . . . . . . . . . . . . . . . . . .365

Customer Focus Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366

Mfax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .366

Motorola SPS World Marketing World Wide Web Server . . . . . . . . .366

Microcontroller Division’s Web Site . . . . . . . . . . . . . . . . . . . . . . . . .366

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MC68HC912DG128

MOTOROLA Table of Contents 10

MC68HC912DG128

MOTOROLA General Description 11

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11

Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12

HC912DG128 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15

Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16

Introduction

The MC68HC912DG128 microcontroller unit (MCU) is a 16-bit device

composed of standard on-chip peripherals including a 16-bit central

processing unit (CPU12), 128K bytes of flash EEPROM, 8K bytes of

RAM, 2K bytes of EEPROM, two asynchronous serial communications

interfaces (SCI), a serial peripheral interface (SPI), an inter-IC interface

C), an enhanced capture timer (ECT), two 8-channel, 10-bit

analog-to-digital converters (ADC), a four-channel pulse-width

modulator (PWM), and two CAN 2.0 A, B software compatible modules

(MSCAN12). System resource mapping, clock generation, interrupt

control and bus interfacing are managed by the lite integration module

(LIM). The MC68HC912DG128 has full 16-bit data paths throughout,

however, the external bus can operate in an 8-bit narrow mode so single

8-bit wide memory can be interfaced for lower cost systems. The

inclusion of a PLL circuit allows power consumption and performance to

be adjusted to suit operational requirements. In addition to the I/O ports

available in each module, 16 I/O ports are available with Key-Wake-Up

capability from STOP or WAIT mode.

1-gen

General Description

MC68HC912DG128

12 General Description MOTOROLA

Features

• 16-bit CPU12

– Upward compatible with M68HC11 instruction set

– Interrupt stacking and programmer’s model identical to

M68HC11

– 20-bit ALU

– Instruction queue

– Enhanced indexed addressing

• Multiplexed bus

– Single chip or expanded

– 16 address/16 data wide or 16 address/8 data narrow modes

• Memory

– 128K byte flash EEPROM, made of four 32K byte modules

with 8K bytes protected BOOT section in each module

– 2K byte EEPROM

– 8K byte RAM, made of two 4K byte modules with Vstby in each

module.

• Two Analog-to-digital converters

– 2 times 8-channels, 10-bit resolution

• Two 1M bit per second, CAN 2.0 A, B software compatible

modules

– Two receive and three transmit buffers per CAN

– Flexible identifier filter programmable as 2 x 32 bit, 4 x 16 bit or

8 x 8 bit

– Four separate interrupt channels for Rx, Tx, error and wake-up

per CAN

– Low-pass filter wake-up function

– Loop-back for self test operation

2--gen

General Description

Features

MC68HC912DG128

MOTOROLA General Description 13

– Programmable link to a timer input capture channel, for

time-stamping and network synchronization.

• Enhanced capture timer (ECT)

– 16-bit main counter with 7-bit prescaler

– 8 programmable input capture or output compare channels; 4

of the 8 input captures with buffer

– Input capture filters and buffers, three successive captures on

four channels, or two captures on four channels with a

capture/compare selectable on the remaining four

– Four 8-bit or two 16-bit pulse accumulators

– 16-bit modulus down-counter with 4-bit prescaler

– Four user-selectable delay counters for signal filtering

• 4 PWM channels with programmable period and duty cycle

– 8-bit 4-channel or 16-bit 2-channel

– Separate control for each pulse width and duty cycle

– Center- or left-aligned outputs

– Programmable clock select logic with a wide range of

frequencies

• Serial interfaces

– Two asynchronous serial communications interfaces (SCI)

– Inter IC bus interface (I

– Synchronous serial peripheral interface (SPI)

• LIM (lite integration module)

– WCR (windowed COP watchdog, real time interrupt, clock

monitor)

– ROC (reset and clocks)

– MEBI (multiplexed external bus interface)

– MMI (memory map and interface)

– INT (interrupt control)

3-gen

General Description

MC68HC912DG128

14 General Description MOTOROLA

– BKP (breakpoints)

– BDM (background debug mode)

• Two 8-bit ports with key wake-up interrupt

• Clock generation

– Phase-locked loop clock frequency multiplier

– Limp home mode in absence of external clock

– Slow mode divider

– Low power 0.5 to 16 MHz crystal oscillator reference clock

• 112-Pin TQFP package

– Up to 67 general-purpose I/O lines, plus up to 18 input-only

lines

– 5.0V operation at 8 MHz

• Development support

– Single-wire background debug™ mode (BDM)

– On-chip hardware breakpoints

4-gen

General Description

HC912DG128 Block Diagram

MC68HC912DG128

MOTOROLA General Description 15

HC912DG128 Block Diagram

Figure 1 HC912DG128 Block Diagram

TxCAN0

DDRH

PORTH

KWH4

KWH3

KWH2

KWH1

KWH0

KWH7

KWH6

KWH5 PH4

PH3

PH2

PH1

PH0

PH7

PH6

PH5

DDRJ

PORTJ

PJ4

PJ3

PJ2

PJ1

PJ0

PJ7

PJ6

PJ5

KWJ4

KWJ3

KWJ2

KWJ1

KWJ0

KWJ7

KWJ6

KWJ5

IOC0

IOC1

IOC2

IOC3

IOC4

IOC5

IOC6

IOC7

DDRT

PORT T

128K byte flash EEPROM

8K byte RAM

PORT E

Enhanced

PT0

PT1

PT2

PT3

PT4

PT5

PT6

PT7

SPI

DDRS

PORT S

PORT AD1

PE1

PE2

PE4

PE5

PE6

PE3

PAD13

PAD14

PAD15

PAD16

PAD17

VDDA

VSSA

VRH1

VRL1

PAD10

PAD11

PAD12

RESET

EXTAL

XTAL

PW0

PW1

PW2

PW3

PWM

DDRP

PORT P

PP0

PP1

PP2

PP3

VDD ×2

VSS ×2

SCI0 RxD0

TxD0

RxD1

TxD1

SDI/MISO

SDO/MOSI

SCK

PS0

PS1

PS2

PS3

PS4

PS5

PS6

PS7

2K byte EEPROM

PE0

PE7

AN13

AN14

AN15

AN16

AN17

VDDA

VSSA

VRH1

VRL1

AN10

AN11

AN12

BKGD

ECLK

R/W

LSTRB

MODA

MODB

XIRQ

DBE/CAL

capture

timer

Lite

IRQ

PIB5

PIB4

SCI1

integration

module

(LIM)

VFP

CPU12

Periodic interrupt

COP watchdog

Clock monitor

Single-wire

background

debug module Breakpoints

PLL

VSSPLL

XFC

VDDPLL

CAN0 RxCAN0

DDRA

PORT A

DDRB

PORT B

PA4

PA3

PA2

PA1

PA0

PA7

PA6

PA5

PB4

PB3

PB2

PB1

PB0

PB7

PB6

PB5

DATA15

Multiplexed Address/Data Bus

ADDR15

ADDR14

ADDR13

ADDR12

ADDR11

ADDR10

ADDR9

ADDR8

DATA14

DATA13

DATA12

DATA11

DATA10

DATA9

DATA8

ADDR7

ADDR6

ADDR5

ADDR4

ADDR3

ADDR2

ADDR1

ADDR0

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

ATD1

PORT AD0

PAD03

PAD04

PAD05

PAD06

PAD07

VRH0

VRL0

PAD00

PAD01

PAD02

AN03

AN04

AN05

AN06

AN07

VDDA

VSSA

VRH0

VRL0

AN00

AN01

AN02

ATD0

PPAGE

DATA7

DATA6

DATA5

DATA4

DATA3

DATA2

DATA1

DATA0

Wide

bus

Narrow bus

VDDX ×2

VSSX ×2

Power for internal circuitry

Power for I/O drivers

PK0

PK1

PK2

PK3

VSTBY

IIC SCL

SDA PIB7

PIB6

DDRK

PORT K

PIX0

PIX1

PIX2

ECS

DDRIB

PORTIB

KWU

Clock

Generation

module

I/O

PK7

I/O

TxCAN1

CAN1 RxCAN1

5-gen

General Description

MC68HC912DG128

16 General Description MOTOROLA

Ordering Information

NOTE:

Because the SDIL12 is not available until the end of May/begining of

June, the M68EVB912DG128 kit was put together as a short term

solution. The M68KIT912DG128 kit will include the cable as mentioned

above. If necessary, an SDIL cable can be obtained directly from Noral

Micrologics Ltd (http://www.noral.com).

Table 1 MC68HC912DG128 Device Ordering Information

Package Temperature Voltage Frequency Order Number

Range Designator

112-Pin TQFP –40 to +85

C C XC912DG128CPV8

Table 2 MC68HC912DG128 Development Tools Ordering Information

Description Details Order Number

Evaluation board kit EVB and user's manual only, available now M68EVB912DG128

Serial Debug Interface Low voltage serial debug interface cable orderable

seperately M68SDIL12

Complete evaluation

board kit EVB, MCUez deb ug softw are, SDIL lo w v oltage serial

debug interface cable M68KIT912DG128

Adapter 112 pin TQFP adapter is also available. M68ADP912DG128PV

6-gen

MC68HC912DG128

MOTOROLA Central Processing Unit 17

Central Processing Unit

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17

Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18

Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19

Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20

Indexed Addressing Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21

Opcodes and Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22

Introduction

The CPU12 is a high-speed, 16-bit processing unit. It has full 16-bit data

paths and wider internal registers (up to 20 bits) for high-speed extended

math instructions. The instruction set is a proper superset of the

M68HC11instruction set. The CPU12 allows instructions with odd byte

counts, including many single-byte instructions. This provides efficient

use of ROM space. An instruction queue buffers program information so

the CPU always has immediate access to at least three bytes of machine

code at the start of every instruction. The CPU12 also offers an

extensive set of indexed addressing capabilities.

1-cpu12

Central Processing Unit

MC68HC912DG128

18 Central Processing Unit MOTOROLA

Programming Model

CPU12 registers are an integral part of the CPU and are not addressed

as if they were memory locations.

Figure 2 Programming Model

Accumulators

A and B are general-purpose 8-bit accumulators used to

hold operands and results of arithmetic calculations or data

manipulations. Some instructions treat the combination of these two

8-bit accumulators as a 16-bit double accumulator (accumulator D).

Index registers

X and Y are used for indexed addressing mode. In the

indexed addressing mode, the contents of a 16-bit index register are

added to 5-bit, 9-bit, or 16-bit constants or the content of an accumulator

to form the effective address of the operand to be used in the instruction.

NSXHI ZVC

CONDITION CODE REGISTER

8-BIT ACCUMULATORS A & B

16-BIT DOUBLE ACCUMULATOR D

INDEX REGISTER X

INDEX REGISTER Y

STACK POINTER

PROGRAM COUNTER

2--cpu12

Central Processing Unit

Data Types

MC68HC912DG128

MOTOROLA Central Processing Unit 19

Stack pointer

(SP) points to the last stack location used. The CPU12

supports an automatic program stack that is used to save system

context during subroutine calls and interrupts, and can also be used for

temporary storage of data. The stack pointer can also be used in all

indexed addressing modes.

Program counter

is a 16-bit register that holds the address of the next

instruction to be executed. The program counter can be used in all

indexed addressing modes except autoincrement/decrement.

Condition Code Register

(CCR) contains five status indicators, two

interrupt masking bits, and a STOP disable bit. The five flags are half

carry (H), negative (N), zero (Z), overflow (V), and carry/borrow (C). The

half-carry flag is used only for BCD arithmetic operations. The N, Z, V,

and C status bits allow for branching based on the results of a previous

operation.

Data Types

The CPU12 supports the following data types:

• Bit data

• 8-bit and 16-bit signed and unsigned integers

• 16-bit unsigned fractions

• 16-bit addresses

A byte is eight bits wide and can be accessed at any byte location. A

word is composed of two consecutive bytes with the most significant

byte at the lower value address. There are no special requirements for

alignment of instructions or operands.

3-cpu12

Central Processing Unit

MC68HC912DG128

20 Central Processing Unit MOTOROLA

Addressing Modes

Addressing modes determine how the CPU accesses memory locations

to be operated upon. The CPU12 includes all of the addressing modes

of the M68HC11 CPU as well as several new forms of indexed

addressing. Table 3 is a summary of the available addressing modes.

Table 3 M68HC12 Addressing Mode Summary

Addressing Mode Source Format Abbreviation Description

Inherent

INST

(no externally supplied

operands) INH Operands (if any) are in CPU registers

Immediate

INST #

opr8i

INST #

opr16i

IMM Operand is included in instruction stream

8- or 16-bit size implied by context

Direct

INST

opr8a

DIR Operand is the lo w er 8-bits of an address in the

range $0000 – $00FF

Extended

INST

opr16a

EXT Operand is a 16-bit address

Relative

INST

rel8

INST

rel16

REL An 8-bit or 16-bit relative offset from the current

pc is supplied in the instruction

Indexed

(5-bit offset)

INST

oprx5

xysp

IDX 5-bit signed constant offset from x, y, sp, or pc

Indexed

(auto pre-decrement)

INST

oprx3

–

xys

IDX Auto pre-decrement x, y, or sp by 1 ~ 8

Indexed

(auto pre-increment)

INST

oprx3

,+xys

IDX Auto pre-increment x, y, or sp by 1 ~ 8

Indexed

(auto post-

decrement) INST

oprx3

xys–

IDX Auto post-decrement x, y, or sp by 1 ~ 8

Indexed

(auto

post-increment) INST

oprx3

xys+

IDX Auto post-increment x, y, or sp by 1 ~ 8

Indexed

(accumulator offset) INST

abd

xysp

IDX Indexed with 8-bit (A or B) or 16-bit (D)

accumulator offset from x, y, sp, or pc

Indexed

(9-bit offset) INST

oprx9

xysp

IDX1 9-bit signed constant offset from x, y, sp, or pc

(lower 8-bits of offset in one extension byte)

Indexed

(16-bit offset) INST

oprx16

xysp

IDX2 16-bit constant offset from x, y, sp, or pc

(16-bit offset in two extension bytes)

Indexed-Indirect

(16-bit offset) INST [

oprx16

xysp

][IDX2] Pointer to operand is found at...

16-bit constant offset from x, y, sp, or pc

(16-bit offset in two extension bytes)

Indexed-Indirect

(D accumulator

offset) INST [D,

xysp

][D,IDX] Pointer to operand is found at...

x, y, sp, or pc plus the value in D

4-cpu12

Central Processing Unit

Indexed Addressing Modes

MC68HC912DG128

MOTOROLA Central Processing Unit 21

Indexed Addressing Modes

The CPU12 indexed modes reduce execution time and eliminate code

size penalties for using the Y index register. CPU12 indexed addressing

uses a postbyte plus zero, one, or two extension bytes after the

instruction opcode. The postbyte and extensions do the following tasks:

• Specify which index register is used.

• Determine whether a value in an accumulator is used as an offset.

• Enable automatic pre- or post-increment or decrement

• Specify use of 5-bit, 9-bit, or 16-bit signed offsets.

Table 4 Summary of Indexed Operations

Postbyte

Code (xb) Source Code

Syntax Comments

rr0nnnnn ,r

n,r

–n,r

5-bit constant offset n = –16 to +15

rr can specify X, Y, SP, or PC

111rr0zs n,r

–n,r

Constant offset (9- or 16-bit signed)

z-0 = 9-bit with sign in LSB of postbyte(s)

1 = 16-bit

if z = s = 1, 16-bit offset indexed-indirect (see below)

rr can specify X, Y, SP, or PC

111rr011 [n,r] 16-bit offset indexed-indirect

rr can specify X, Y, SP, or PC

rr1pnnnn n,–r n,+r

n,r– n,r+

Auto pre-decrement/increment or Auto post-decrement/increment;

p = pre-(0) or post-(1), n = –8 to –1, +1 to +8

rr can specify X, Y, or SP (PC not a valid choice)

111rr1aa A,r

B,r

D,r

Accumulator offset (unsigned 8-bit or 16-bit)

aa-00 = A

01 = B

10 = D (16-bit)

11 = see accumulator D offset indexed-indirect

rr can specify X, Y, SP, or PC

111rr111 [D,r] Accumulator D offset indexed-indirect

rr can specify X, Y, SP, or PC

5-cpu12

Central Processing Unit

MC68HC912DG128

22 Central Processing Unit MOTOROLA

Opcodes and Operands

The CPU12 uses 8-bit opcodes. Each opcode identifies a particular

instruction and associated addressing mode to the CPU. Several

opcodes are required to provide each instruction with a range of

addressing capabilities.

Only 256 opcodes would be available if the range of values were

restricted to the number that can be represented by 8-bit binary

numbers. To expand the number of opcodes, a second page is added to

the opcode map. Opcodes on the second page are preceded by an

additional byte with the value $18.

To provide additional addressing flexibility, opcodes can also be

followed by a postbyte or extension bytes. Postbytes implement certain

forms of indexed addressing, transfers, exchanges, and loop primitives.

Extension bytes contain additional program information such as

addresses, offsets, and immediate data.

6-cpu12

MC68HC912DG128

MOTOROLA Pinout and Signal Descriptions 23

Pinout and Signal Descriptions

General Description

Contents

MC68HC912DG128 Pin Assignments in 112-pin QFP. . . . . . . . . . . .23

Power Supply Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26

Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28

Port Signals. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35

MC68HC912DG128 Pin Assignments in 112-pin QFP

The HC912DG128 is available in a 112-pin thin quad flat pack (TQFP).

Most pins perform two or more functions, as described in the Signal

Descriptions. Figure 3 shows pin assignments.In expanded narrow

modes the lower byte data is multiplexed with higher byte data through

pins 57-64.

1-pins

Pinout and Signal Descriptions

MC68HC912DG128

24 Pinout and Signal Descriptions MOTOROLA

Figure 3 Pin Assignments in 112-pin QFP for HC912DG128

112

111

110

109

108

107

106

105

104

103

102

101

100

HC912DG128

112TQFP

PAD17/AN17

PAD07/AN07

PAD16/AN16

PAD06/AN06

PAD15/AN15

PAD05/AN05

PAD14/AN14

PAD04/AN04

PAD13/AN13

PAD03/AN03

PAD12/AN12

PAD02/AN02

PAD11/AN11

PAD01/AN01

PAD10/AN10

PAD00/AN00

VRL0

VRH0

VSS

VDD

PA7/ADDR15/DATA15/DATA7

PA6/ADDR14/DATA14/DATA6

PA5/ADDR13/DATA13/DATA5

PA4/ADDR12/DATA12/DATA4

PA3/ADDR11/DATA11/DATA3

PA2/ADDR10/DATA10/DATA2

PA1/ADDR9/DATA9/DATA1

PA0/ADDR8/DATA8/DATA0

PP3/PW3

PK0/PIX0

PK1/PIX1

PK2/PIX2

PK7/ECS

VDDX

VSSX

RxCAN0

TxCAN0

RxCAN1

TxCAN1

PIB4

PIB5

PIB6/SDA

PIB7/SCL

VFP

PS7/SS

PS6/SCK

PS5/SDO/MOSI

PS4/SDI/MISO

PS3/TxD1

PS2/RxD1

PS1/TxD0

PS0/RxD0

VSSA

VRL1

VRH1

VDDA

PW2/PP2

PW1/PP1

PW0/PP0

IOC0/PT0

IOC1/PT1

IOC2/PT2

IOC3/PT3

KWJ7/PJ7

KWJ6/PJ6

KWJ5/PJ5

KWJ4/PJ4

VDD

PK3

VSS

IOC4/PT4

IOC5/PT5

IOC6/PT6

IOC7/PT7

KWJ3/PJ3

KWJ2/PJ2

KWJ1/PJ1

KWJ0/PJ0

SMODN/TAGHI/BKGD

ADDR0/DATA0/PB0

ADDR1/DATA1/PB1

ADDR2/DATA2/PB2

ADDR3/DATA3/PB3

ADDR4/DATA4/PB4

ADDR5/DATA5/PB5

ADDR6/DATA6/PB6

ADDR7/DATA7/PB7

KWH7/PH7

KWH6/PH6

KWH5/PH5

KWH4/PH4

DBE/CAL/PE7

MODB/IPIPE1/PE6

MODA/IPIPE0/PE5

ECLK/PE4

VSSX

VSTBY

VDDX

VDDPLL

XFC

VSSPLL

RESET

EXTAL

XTAL

KWH3/PH3

KWH2/PH2

KWH1/PH1

KWH0/PH0

LSTRB/TAGLO/PE3

R/W/PE2

IRQ/PE1

XIRQ/PE0

2-pins

Pinout and Signal Descriptions

MC68HC912DG128 Pin Assignments in 112-pin QFP

MC68HC912DG128

MOTOROLA Pinout and Signal Descriptions 25

Figure 4 112-pin QFP Mechanical Dimensions (case no. 987)

3-pins

Pinout and Signal Descriptions

MC68HC912DG128

26 Pinout and Signal Descriptions MOTOROLA

Power Supply Pins

MC68HC912DG128 power and ground pins are described below and

summarized in Table 5.

Internal Power

(VDD) and Ground

(VSS)

Power is supplied to the MCU through VDD and VSS. Because fast signal

transitions place high, short-duration current demands on the power

supply, use bypass capacitors with high-frequency characteristics and

place them as close to the MCU as possible.

External Power

(VDDX) and

Ground (VSSX)

External power and ground for I/O drivers. Because fast signal

transitions place high, short-duration current demands on the power

supply, use bypass capacitors with high-frequency characteristics and

place them as close to the MCU as possible. Bypass requirements

depend on how heavily the MCU pins are loaded.

VDDA, VSSA Provides operating voltage and ground for the analog-to-digital

converter. This allows the supply voltage to the A/D to be bypassed

independently.

Analog to Digital

Reference

Voltages (VRH, VRL)

VDDPLL, VSSPLL Provides operating voltage and ground for the Phased-Locked Loop.

This allows the supply voltage to the PLL to be bypassed independently.

NOTE:

The VSSPLL pin should always be grounded even if the PLL is not used.

The VDDPLL pin should not be left floating. It is recommended to

connect the VDDPLL pin to ground if the PLL is not used.

4-pins

Pinout and Signal Descriptions

Power Supply Pins

MC68HC912DG128

MOTOROLA Pinout and Signal Descriptions 27

XFC PLL loop filter. Please ask your Motorola representative for the

interactive application note to compute PLL loop filter elements. Any

current leakage on this pin must be avoided.

Figure 5 PLL Loop FIlter Connections

VFP Flash EEPROM program/erase voltage and supply voltage during

normal operation.

VSTBY Stand-by voltage supply to static RAM. Used to maintain the contents of

RAM with minimal power when the rest of the chip is powered down.

MCU

XFC

VDDPLLVDDPLL

Table 5 MC68HC912DG128 Power and Ground Connection Summary

Mnemonic Pin Number Description

112-pin QFP

VDD 12, 65 Internal power and ground.

VSS 14, 66

VDDX 42, 107 External power and ground, supply to pin drivers.

VSSX 40, 106

VDDA 85 Operating voltage and ground for the analog-to-digital converter, allows the

supply voltage to the A/D to be bypassed independently.

VSSA 88

VRH1 86 Reference voltages for the analog-to-digital converter 1

VRL1 87

VRH0 67 Reference voltages for the analog-to-digital converter 0.

VRL0 68

VDDPLL 43 Provides operating v oltage and ground f or the Phased-Loc ked Loop . This allows

the supply voltage to the PLL to be bypassed independently.

VSSPLL 45

5-pins

Pinout and Signal Descriptions

MC68HC912DG128

28 Pinout and Signal Descriptions MOTOROLA

Signal Descriptions

Crystal Driver and

External Clock

Input (XTAL, EXTAL)

These pins provide the interface for either a crystal or a CMOS

compatible clock to control the internal clock generator circuitry. Out of

reset the frequency applied to EXTAL is twice the desired E–clock rate.

All the device clocks are derived from the EXTAL input frequency.

NOTE:

CRYSTAL CIRCUIT IS CHANGED FROM STANDARD.

NOTE:

The internal return path for the oscillator is the VSSPLL pin. Therefore it

is recommended to connect the common node of the resonator and the

capacitor directly to the VSSPLL pin.

Figure 6 Common Crystal Connections

VFP 97 Program/erase voltage for the Flash EEPROM and required supply for normal

operation.

VSTBY 41 Stand-by voltage supply to maintain the contents of RAM with minimal power

when the rest of the chip is powered down.

Table 5 MC68HC912DG128 Power and Ground Connection Summary

Mnemonic Pin Number Description

112-pin QFP

MCU

EXTAL

XTAL

2 x E crystal or ceramic resonator

6-pins

Pinout and Signal Descriptions

Signal Descriptions

MC68HC912DG128

MOTOROLA Pinout and Signal Descriptions 29

7-pins

Figure 7 External Oscillator Connections

XTAL is the crystal output.The XTAL pin must be left without terminal

when an external CMOS compatible clock input is connected to the

EXTAL pin. The XTAL output is normally intended to drive only a crystal.

The XTAL output can be buffered with a high-impedance buffer to drive

the EXTAL input of another device.

In all cases take extra care in the circuit board layout around the

oscillator pins. Load capacitances in the oscillator circuits include all

stray layout capacitances. Refer to Figure 6 and Figure 7 for diagrams

of oscillator circuits.

E-Clock Output

(ECLK)

ECLK is the output connection for the internal bus clock. It is used to

demultiplex the address and data in expanded modes and is used as a

timing reference. ECLK frequency is equal to 1/2 the crystal frequency

out of reset. The E-clock output is turned off in single chip user mode to

reduce the effects of RFI. It can be turned on if necessary. In special

single-chip mode, the E-clock is turned ON at reset and can be turned

OFF. In special peripheral mode the E-clock is an input to the MCU. All

clocks, including the E clock, are halted when the MCU is in STOP

mode. It is possible to configure the MCU to interface to slow external

memory. ECLK can be stretched for such accesses.

Reset (RESET)An active low bidirectional control signal, RESET, acts as an input to

initialize the MCU to a known start-up state. It also acts as an open-drain

output to indicate that an internal failure has been detected in either the

clock monitor or COP watchdog circuit. The MCU goes into reset

asynchronously and comes out of reset synchronously. This allows the

MCU

EXTAL

XTAL

2 x E

CMOS-COMPATIBLE

EXTERNAL OSCILLATOR

Pinout and Signal Descriptions

MC68HC912DG128

30 Pinout and Signal Descriptions MOTOROLA

part to reach a proper reset state even if the clocks have failed, while

allowing synchronized operation when starting out of reset.

It is important to use an external low-voltage reset circuit (such as

MC34064 or MC34164) to prevent corruption of RAM or EEPROM due

to power transitions.

The reset sequence is initiated by any of the following events:

• Power-on-reset (POR)

• COP watchdog enabled and watchdog timer times out

• Clock monitor enabled and Clock monitor detects slow or stopped

clock

• User applies a low level to the reset pin

External circuitry connected to the reset pin should not include a large

capacitance that would interfere with the ability of this signal to rise to a

valid logic one within nine bus cycles after the low drive is released.

Upon detection of any reset, an internal circuit drives the reset pin low

and a clocked reset sequence controls when the MCU can begin normal

processing. In the case of POR or a clock monitor error, a 4096 cycle

oscillator startup delay is imposed before the reset recovery sequence

starts (reset is driven low throughout this 4096 cycle delay). The internal

reset recovery sequence then drives reset low for 16 to 17 cycles and

releases the drive to allow reset to rise. Nine cycles later this circuit

samples the reset pin to see if it has risen to a logic one level. If reset is

low at this point, the reset is assumed to be coming from an external

request and the internally latched states of the COP timeout and clock

monitor failure are cleared so the normal reset vector ($FFFE:FFFF) is

taken when reset is finally released. If reset is high after this nine cycle

delay, the reset source is tentatively assumed to be either a COP failure

or a clock monitor fail. If the internally latched state of the clock monitor

fail circuit is true, processing begins by fetching the clock monitor vector

($FFFC:FFFD). If no clock monitor failure is indicated, and the latched

state of the COP timeout is true, processing begins by fetching the COP

vector ($FFFA:FFFB). If neither clock monitor fail nor COP timeout are

pending, processing begins by fetching the normal reset vector

($FFFE:FFFF).

8-pins

Pinout and Signal Descriptions

Signal Descriptions

MC68HC912DG128

MOTOROLA Pinout and Signal Descriptions 31

9-pins

Maskable

Interrupt Request

(IRQ)

The IRQ input provides a means of applying asynchronous interrupt

requests to the MCU. Either falling edge-sensitive triggering or

level-sensitive triggering is program selectable (INTCR register). IRQ is

always enabled and configured to level-sensitive triggering at reset. It

can be disabled by clearing IRQEN bit (INTCR register). When the MCU

is reset the IRQ function is masked in the condition code register. This

pin is always an input and can always be read. There is an active pull-up

on this pin while in reset and immediately out of reset. The pullup can be

turned off by clearing PUPE in the PUCR register.

Nonmaskable

Interrupt (XIRQ)

The XIRQ input provides a means of requesting a nonmaskable interrupt

after reset initialization. During reset, the X bit in the condition code

enables it. Because the XIRQ input is level sensitive, it can be connected

to a multiple-source wired-OR network. This pin is always an input and

can always be read. There is an active pull-up on this pin while in reset

and immediately out of reset. The pullup can be turned off by clearing

PUPE in the PUCR register. XIRQ is often used as a power loss detect

interrupt.

Whenever XIRQ or IRQ are used with multiple interrupt sources (IRQ

must be configured for level-sensitive operation if there is more than one

source of IRQ interrupt), each source must drive the interrupt input with

an open-drain type of driver to avoid contention between outputs. There

must also be an interlock mechanism at each interrupt source so that the

source holds the interrupt line low until the MCU recognizes and

acknowledges the interrupt request. If the interrupt line is held low, the

MCU will recognize another interrupt as soon as the interrupt mask bit in

the MCU is cleared (normally upon return from an interrupt).

Mode Select

(SMODN, MODA,

and MODB)

The state of these pins during reset determine the MCU operating mode.

After reset, MODA and MODB can be configured as instruction queue

tracking signals IPIPE0 and IPIPE1 in expanded modes. MODA and

MODB have active pulldowns during reset.

The SMODN pin has an active pullup when configured as an input. The

pin can be used as BKGD or TAGHI after reset.

Pinout and Signal Descriptions

MC68HC912DG128

32 Pinout and Signal Descriptions MOTOROLA

Single-Wire

Background Mode

Pin (BKGD)

The BKGD pin receives and transmits serial background debugging

commands. A special self-timing protocol is used. The BKGD pin has an

active pullup when configured as an input; BKGD has no pullup control.

Refer to Development Support.

External Address

and Data Buses

(ADDR[15:0] and

DATA[15:0])

External bus pins share functions with general-purpose I/O ports A and

B. In single-chip operating modes, the pins can be used for I/O; in

expanded modes, the pins are used for the external buses.

In expanded wide mode, ports A and B are used for multiplexed 16-bit

data and address buses. PA[7:0] correspond to

ADDR[15:8]/DATA[15:8]; PB[7:0] correspond to ADDR[7:0]/DATA[7:0].

In expanded narrow mode, ports A and B are used for the16-bit address

bus, and an 8-bit data bus is multiplexed with the most significant half of

the address bus on port A. In this mode, 16-bit data is handled as two

back-to-back bus cycles, one for the high byte followed by one for the

low byte. PA[7:0] correspond to ADDR[15:8] and to DATA[15:8] or

DATA[7:0], depending on the bus cycle. The state of the address pins

should be latched at the rising edge of E. To allow for maximum address

setup time at external devices, a transparent latch should be used.

Read/Write (R/W)In all modes this pin can be used as a general-purpose I/O and is an

input with an active pull-up out of reset. If the read/write function is

required it should be enabled by setting the RDWE bit in the PEAR

Low-Byte Strobe

(LSTRB)

In all modes this pin can be used as a general-purpose I/O and is an

input with an active pull-up out of reset. If the strobe function is required,

it should be enabled by setting the LSTRE bit in the PEAR register. This

signal is used in write operations. Therefore external low byte writes will

not be possible until this function is enabled. This pin is also used as

TAGLO in Special Expanded modes and is multiplexed with the LSTRB

function.

10-pins

Pinout and Signal Descriptions

Signal Descriptions

MC68HC912DG128

MOTOROLA Pinout and Signal Descriptions 33

11-pins

Instruction Queue

Tracking Signals

(IPIPE1 and IPIPE0)

IPIPE1 (PE6) and IPIPE0 (PE5) signals are used to track the state of the

internal instruction queue. Data movement and execution state

information is time-multiplexed on the two signals. Refer to

Development Support.

Data Bus Enable

(DBE)

The DBE pin (PE7) is an active low signal that will be asserted low during

E-clock high time. DBE provides separation between output of a

multiplexed address and the input of data. When an external address is

stretched, DBE is asserted during what would be the last quarter cycle

of the last E-clock cycle of stretch. In expanded modes this pin is used

to enable the drive control of external buses during external reads. Use

of the DBE is controlled by the NDBE bit in the PEAR register. DBE is

enabled out of reset in expanded modes.

Inverted E clock

(ECLK)

The ECLK pin (PE7) can be used to latch the address for

de-multiplexing. It has the same behavior as the ECLK, except is

inverted. In expanded modes this pin is used to enable the drive control

of external buses during external reads. Use of the ECLK is controlled

by the NDBE and DBENE bits in the PEAR register.

Calibration

reference (CAL)

The CAL pin (PE7) is the output of the Slow Mode programmable clock

divider, SLWCLK, and is used as a calibration reference. The SLWCLK

frequency is equal to the crystal frequency out of reset and always has

a 50% duty. If the DBE function is enabled it will override the enabled

CAL output. The CAL pin output is disabled by clearing CALE bit in the

PEAR register.

Clock generation

module

test(CGMTST)

The CGMTST pin (PE6) is the output of the clocks tested when CGMTE

bit is set in PEAR register. The PIPOE bit must be cleared for the clocks

to be tested.

Pinout and Signal Descriptions

MC68HC912DG128

34 Pinout and Signal Descriptions MOTOROLA

Table 6 MC68HC912DG128 Signal Description Summary

Pin Name Shared

port

Number Description

112-pin

EXTAL - 47 Crystal driver and external clock input pins. On reset all the device clocks

are derived from the EXTAL input frequency. XTAL is the crystal output.

XTAL - 48

RESET - 46 An active low bidirectional control signal, RESET acts as an input to

initialize the MCU to a known start-up state, and an output when COP or

clock monitor causes a reset.

ADDR[7:0]

DATA[7:0] PB[7:0] 31–24 External bus pins share function with gener al-purpose I/O ports A and B. In

single chip modes, the pins can be used for I/O. In expanded modes, the

pins are used for the external buses.

ADDR[15:8]

DATA[15:8] PA[7:0] 64–57

DBE PE7 36 Data bus control and, in expanded mode, enables the drive control of

external buses during external reads.

ECLK PE7 36 Inverted E clock used to latch the address.

CAL PE7 36 CAL is the output of the Slo w Mode progr ammable cloc k divider, SLWCLK,

and is used as a calibration ref erence f or functions such as time of da y. It is

overridden when DBE function is enabled. It always has a 50% duty.

CGMTST PE6 37 Clock generation module test output.

MODB/IPIPE1,

MODA/IPIPE0 PE6, PE5 37, 38

State of mode select pins during reset determine the initial operating mode

of the MCU. After reset, MODB and MODA can be conﬁgured as

instruction queue tracking signals IPIPE1 and IPIPE0 or as

general-purpose I/O pins.

ECLK PE4 39 E Clock is the output connection for the external bus clock. ECLK is used

as a timing reference and for address demultiplexing.

LSTRB/TAGLO PE3 53

Low byte strobe (0 = low byte valid), in all modes this pin can be used as

I/O. The low strobe function is the exclusive-NOR of A0 and the internal

SZ8 signal. (The SZ8 internal signal indicates the size 16/8 access.) Pin

function TAGLO used in instruction tagging. See Development Support.

R/W PE2 54 Indicates direction of data on expansion bus. Shares function with

general-purpose I/O. Read/write in expanded modes.

IRQ PE1 55

Maskable interrupt request input provides a means of applying

asynchronous interrupt requests to the MCU. Either falling edge-sensitive

triggering or level-sensitive triggering is program selectable (INTCR

XIRQ PE0 56 Provides a means of requesting asynchronous nonmaskable interrupt

requests after reset initialization

SMODN/BKGD/

TAGHI -23

During reset, this pin determines special or normal operating mode. After

reset, single-wire background interface pin is dedicated to the background

debug function. Pin function TAGHI used in instruction tagging. See

Development Support.

IX[2:0] PK[2:0] 109-111 Page Index register emulation outputs.

ECS PK7 108 Emulation Chip select.

12-pins

Pinout and Signal Descriptions

Port Signals

MC68HC912DG128

MOTOROLA Pinout and Signal Descriptions 35

13-pins

Port Signals

The MC68HC912DG128 incorporates eleven ports which are used to

control and access the various device subsystems. When not used for

these purposes, port pins may be used for general-purpose I/O. In

addition to the pins described below, each port consists of a data register

PW[3:0] PP[3:0] 112, 1–3 Pulse Width Modulator channel outputs.

SS PS7 96 Slave select output for SPI master mode, input for slave mode or master

mode.

SCK PS6 95 Serial clock for SPI system.

SDO/MOSI PS5 94 Master out/slave in pin for serial peripheral interface

SDI/MISO PS4 93 Master in/slave out pin for serial peripheral interface

TxD1 PS3 92 SCI1 transmit pin

RxD1 PS2 91 SCI1 receive pin

TxD0 PS1 90 SCI0 transmit pin

RxD0 PS0 89 SCI0 receive pin

IOC[7:0] PT[7:0] 18–15,

7–4 Pins used for input capture and output compare in the timer and pulse

accumulator subsystem.

AN1[7:0] PAD1[7:0] 84/82/80

/78/76/7

4/72/70 Analog inputs for the analog-to-digital conversion module 1

AN0[7:0] PAD0[7:0] 83/81/79

/77/75/7

3/71/69 Analog inputs for the analog-to-digital conversion module 0

TxCAN1 - 102 MSCAN1 transmit pin

RxCAN1 - 103 MSCAN1 receive pin

TxCAN0 - 104 MSCAN0 transmit pin

RxCAN0 - 105 MSCAN0 receive pin

SCL PIB7 98 I2C bus serial clock line pin

SDA PIB6 99 I2C bus serial data line pin

KWJ[7:0] PJ[7:0] 8–11,

19–22 Key wake-up and general purpose I/O; can cause an interrupt when an

input transitions from high to low or from low to high (KWPJ).

KWH[7:0] PH[7:0] 32–35,

49–52 Key wake-up and general purpose I/O; can cause an interrupt when an

input transitions from high to low or from low to high (KWPH).

Table 6 MC68HC912DG128 Signal Description Summary

Pin Name Shared

port

Number Description

112-pin

Pinout and Signal Descriptions

MC68HC912DG128

36 Pinout and Signal Descriptions MOTOROLA

which can be read and written at any time, and, with the exception of port

AD0, port AD1, PE[1:0], RxCAN and TxCAN, a data direction register

which controls the direction of each pin. After reset all general purpose

I/O pins are configured as input.

Port A Port A pins are used for address and data in expanded modes. When

this port is not used for external access such as in single-chip mode,

these pins can be used as general purpose I/O. The port data register is

not in the address map during expanded and peripheral mode operation.

When it is in the map, port A can be read or written at anytime.

DDRA is not in the address map during expanded and peripheral mode

operation. Setting a bit in DDRA makes the corresponding bit in port A

an output; clearing a bit in DDRA makes the corresponding bit in port A

an input. The default reset state of DDRA is all zeroes.

When the PUPA bit in the PUCR register is set, all port A input pins are

pulled-up internally by an active pull-up device. PUCR is not in the

address map in peripheral mode.

Setting the RDPA bit in register RDRIV causes all port A outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

Port B Port B pins are used for address and data in expanded modes. When

this port is not used for external access such as in single-chip mode,

these pins can be used as general purpose I/O. The port data register is

not in the address map during expanded and peripheral mode operation.

When it is in the map, port B can be read or written at anytime.

DDRB is not in the address map during expanded and peripheral mode

operation. Setting a bit in DDRB makes the corresponding bit in port B

an output; clearing a bit in DDRB makes the corresponding bit in port B

an input. The default reset state of DDRB is all zeroes.

14-pins

Pinout and Signal Descriptions

Port Signals

MC68HC912DG128

MOTOROLA Pinout and Signal Descriptions 37

15-pins

When the PUPB bit in the PUCR register is set, all port B input pins are

pulled-up internally by an active pull-up device. PUCR is not in the

address map in peripheral mode.

Setting the RDPB bit in register RDRIV causes all port B outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

Port E Port E pins operate differently from port A and B pins. Port E pins are

used for bus control signals and interrupt service request signals. When

a pin is not used for one of these specific functions, it can be used as

general-purpose I/O. However, two of the pins (PE[1:0]) can only be

used for input, and the states of these pins can be read in the port data

The PEAR register determines pin function, and register DDRE

determines whether each pin is an input or output when it is used for

general-purpose I/O. PEAR settings override DDRE settings. Because

PE[1:0] are input-only pins, only DDRE[7:2] have effect. Setting a bit in

the DDRE register makes the corresponding bit in port E an output;

clearing a bit in the DDRE register makes the corresponding bit in port E

an input. The default reset state of DDRE is all zeroes.

When the PUPE bit in the PUCR register is set, PE[7,3,2,1,0] are pulled

up. PE[7,3,2,0] are active pull-up devices. PUPCR is not in the address

map in peripheral mode.

Neither port E nor DDRE is in the map in peripheral mode or in the

internal map in expanded modes with EME set.

Setting the RDPE bit in register RDRIV causes all port E outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

Port H Port H pins are used for key wake-ups that can be used with the pins

configured as inputs or outputs. The key wake-ups are triggered with

Pinout and Signal Descriptions

MC68HC912DG128

38 Pinout and Signal Descriptions MOTOROLA

either a rising or falling edge signal (KWPH). An interrupt is generated if

the corresponding bit is enabled (KWIEH). If any of the interrupts is not

enabled, the corresponding pin can be used as a general purpose I/O

pin. Refer to I/O Ports With Key Wake-Up.

output. Setting a bit in DDRH makes the corresponding bit in port H an

output; clearing a bit in DDRH makes the corresponding bit in port H an

input. The default reset state of DDRH is all zeroes.

are triggered, but it also determines what type of resistive load is used

for port H input pins when PUPH bit is set in the PUCR register. Setting

a bit in KWPH makes the corresponding key wake up input pin trigger at

rising edges and loads a pull down in the corresponding port H input pin.

Clearing a bit in KWPH makes the corresponding key wake up input pin

trigger at falling edges and loads a pull up in the corresponding port H

input pin. The default state of KWPH is all zeroes.

Setting the RDPH bit in register RDRIV causes all port H outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

Port J Port J pins are used for key wake-ups that can be used with the pins

configured as inputs or outputs. The key wake-ups are triggered with

either a rising or falling edge signal (KWPJ). An interrupt is generated if

the corresponding bit is enabled (KWIEJ). If any of the interrupts is not

enabled, the corresponding pin can be used as a general purpose I/O

pin. Refer to I/O Ports With Key Wake-Up.

Setting a bit in DDRJ makes the corresponding bit in port J an output;

clearing a bit in DDRJ makes the corresponding bit in port J an input. The

default reset state of DDRJ is all zeroes.

are triggered, but it also determines what type of resistive load is used

for port J input pins when PUPJ bit is set in the PUCR register. Setting a

16-pins

Pinout and Signal Descriptions

Port Signals

MC68HC912DG128

MOTOROLA Pinout and Signal Descriptions 39

17-pins

bit in KWPJ makes the corresponding key wake up input pin trigger at

rising edges and loads a pull down in the corresponding port J input pin.

Clearing a bit in KWPJ makes the corresponding key wake up input pin

trigger at falling edges and loads a pull up in the corresponding port J

input pin. The default state of KWPJ is all zeroes.

Setting the RDPJ bit in register RDRIV causes all port J outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

Port K Port K pins are used for page index emulation in expanded or peripheral

modes. When page index emulation is not enabled, EMK is not set in

MODE register, or the part is in single chip mode, these pins can be used

for general purpose I/O. Port K bit 3 is used as a general purpose I/O pin

only. The port data register is not in the address map during expanded

and peripheral mode operation with EMK set. When it is in the map, port

K can be read or written at anytime.

DDRK is not in the address map during expanded and peripheral mode

operation with EMK set. Setting a bit in DDRK makes the corresponding

bit in port K an output; clearing a bit in DDRK makes the corresponding

bit in port K an input. The default reset state of DDRK is all zeroes.

When the PUPK bit in the PUCR register is set, all port K input pins are

pulled-up internally by an active pull-up device. PUCR is not in the

address map in peripheral mode.

Setting the RDPK bit in register RDRIV causes all port K outputs to have

reduced drive level. RDRIV can be written once after reset. RDRIV is not

in the address map in peripheral mode. Refer to Bus Control and

Input/Output.

Port CAN1 The MSCAN1 uses two external pins, one input (RxCAN1) and one

output (TxCAN1). The TxCAN1 output pin represents the logic level on

the CAN: ‘0’ is for a dominant state, and ‘1’ is for a recessive state.

RxCAN1 is on bit 0 of Port CAN1, TxCAN1 is on bit 1.

Pinout and Signal Descriptions

MC68HC912DG128

40 Pinout and Signal Descriptions MOTOROLA

Port CAN0 The MSCAN0 uses two external pins, one input (RxCAN0) and one

output (TxCAN0). The TxCAN0 output pin represents the logic level on

the CAN: ‘0’ is for a dominant state, and ‘1’ is for a recessive state.

RxCAN0 is on bit 0 of Port CAN0, TxCAN0 is on bit 1.

Port IB Bidirectional pins to IIC bus interface subsystem. The IIC bus interface

uses a Serial Data line (SDA) and Serial Clock line (SCL) for data

transfer. The pins are connected to a positive voltage supply via a pull

up resistor. The pull ups can be enabled internally or connected

externally. The output stages have open drain outputs in order to

perform the wired-AND function. When the IIC is disabled the pins can

be used as general purpose I/O pins. SCL is on bit 7 of Port IB and SDA

is on bit 6. The remaining two pins of Port IB are controlled by registers

in the IIC address space.

general-purpose I/O. When DDRIB bits are set, the corresponding pin is

configured for output. On reset the DDRIB bits are cleared and the

corresponding pin is configured for input.

When the PUPIB bit in the IBPURD register is set, all input pins are

pulled up internally by an active pull-up device. Pullups are disabled after

reset, except for input ports 0 through 3, which are always on regardless

of PUPIB bit.

Setting the RDPIB bit in the IBPURD register configures all port IB

outputs to have reduced drive levels. Levels are at normal drive

capability after reset. The IBPURD register can be read or written

anytime after reset. Refer to section Inter-IC Bus.

Port AD1 This port is an analog input interface to the analog-to-digital subsystem

and used for general-purpose input. When analog-to-digital functions

are not enabled, the port has eight general-purpose input pins,

PAD1[7:0]. The ADPU bit in the ATD1CTL2 register enables the A/D

function.

18-pins

Pinout and Signal Descriptions

Port Signals

MC68HC912DG128

MOTOROLA Pinout and Signal Descriptions 41

19-pins

Port AD1 pins are inputs; no data direction register is associated with

this port. The port has no resistive input loads and no reduced drive

controls. Refer to Analog-To-Digital Converter (ATD).

Port AD0 This port is an analog input interface to the analog-to-digital subsystem

and used for general-purpose input. When analog-to-digital functions

are not enabled, the port has eight general-purpose input pins,

PAD0[7:0]. The ADPU bit in the ATD0CTL2 register enables the A/D

function.

Port AD0 pins are inputs; no data direction register is associated with

this port. The port has no resistive input loads and no reduced drive

controls. Refer to Analog-To-Digital Converter (ATD).

Port P The four pulse-width modulation channel outputs share general-purpose

port P pins. The PWM function is enabled with the PWEN register.

Enabling PWM pins takes precedence over the general-purpose port.

When pulse-width modulation is not in use, the port pins may be used

for general-purpose I/O.

general-purpose I/O. When DDRP bits are set, the corresponding pin is

configured for output. On reset the DDRP bits are cleared and the

corresponding pin is configured for input.

When the PUPP bit in the PWCTL register is set, all input pins are pulled

up internally by an active pull-up device. Pullups are disabled after reset.

Setting the RDPP bit in the PWCTL register configures all port P outputs

to have reduced drive levels. Levels are at normal drive capability after

reset. The PWCTL register can be read or written anytime after reset.

Refer to Pulse-Width Modulator.

Port S Port S is the 8-bit interface to the standard serial interface consisting of

the two serial communications interfaces (SCI1 and SCI0) and the serial

peripheral interface (SPI) subsystems. Port S pins are available for

general-purpose I/O when standard serial functions are not enabled.

Pinout and Signal Descriptions

MC68HC912DG128

42 Pinout and Signal Descriptions MOTOROLA

Port S pins serve several functions depending on the various internal

control registers. If WOMS bit in the SC0CR1register is set, the

P-channel drivers of the output buffers are disabled (wire-or mode) for

pins 0 through 3. If SWOM bit in the SP0CR1 register is set, the

P-channel drivers of the output buffers are disabled (wire-or mode) for

pins 4 through 7. The open drain control affects both the serial and the

general-purpose outputs. If the RDPS bit in the SP0CR2 register is set,

Port S pin drive capabilities are reduced. If PUPS bit in the SP0CR2

programmed as a general purpose input. If the pin is programmed as a

general-purpose output, the pull-up is disconnected from the pin

regardless of the state of PUPS bit. See Multiple Serial Interface.

Port T This port provides eight general-purpose I/O pins when not enabled for

input capture and output compare in the timer and pulse accumulator

subsystem. The TEN bit in the TSCR register enab les the timer function.

The pulse accumulator subsystem is enabled with the PAEN bit in the

PACTL register.

general-purpose I/O. When DDRT bits are set, the corresponding pin is

configured for output. On reset the DDRT bits are cleared and the

corresponding pin is configured for input.

When the PUPT bit in the TMSK2 register is set, all input pins are pulled

up internally by an active pull-up device. Pullups are disabled after reset.

Setting the RDPT bit in the TMSK2 register configures all port T outputs

to have reduced drive levels. Levels are at normal drive capability after

reset. The TMSK2 register can be read or written anytime after reset.

Refer to Enhanced Capture Timer.

20-pins

Pinout and Signal Descriptions

Port Signals

MC68HC912DG128

MOTOROLA Pinout and Signal Descriptions 43

21-pins

Port Pull-Up

Pull-Down and

Reduced Drive

MCU ports can be configured for internal pull-up. To reduce power

consumption and RFI, the pin output drivers can be configured to

operate at a reduced drive level. Reduced drive causes a slight increase

in transition time depending on loading and should be used only for ports

which have a light loading. Table 1 summarizes the port pull-up default

status and controls.

Table 7 MC68HC912DG128 Port Description Summary

Port Name Pin

Numbers Data Direction

112-pin

Port A

PA[7:0] 64-57 In/Out

DDRA ($0002) Port A and port B pins are used for address and data in

e xpanded modes. The port data registers are not in the address

map during expanded and peripheral mode operation. When in

the map, port A and port B can be read or written any time.

DDRA and DDRB are not in the address map in expanded or

peripheral modes.

Port B

PB[7:0] 31–24 In/Out

DDRB ($0003)

Port AD1

PAD1[7:0]

84/82/80/

78/76/74/

72/70 In Analog-to-digital converter 1 and general-purpose I/O.

Port AD0

PAD0[7:0]

83/81/79/

77/75/73/

71/69 In Analog-to-digital converter 0 and general-purpose I/O.

Port CAN1

PCAN1[1:0] 102–103 PCAN1[1] Out

PCAN1[0] In PCAN1[1:0] are used with the MSCAN1 module and cannot be

used as general purpose I/O.

Port CAN0

PCAN0[1:0] 104–105 PCAN0[1] Out

PCAN0[0] In PCAN0[1:0] are used with the MSCAN0 module and cannot be

used as general purpose I/O.

Port IB

PIB[7:4] 98–101 In/Out

DDRIB ($00E7) General purpose I/O. PIB[7:6] are used with the I-Bus module

when enabled.

Port E

PE[7:0] 36–39,

53–56

PE[1:0] In

PE[7:2] In/Out

DDRE ($0009)

Mode selection, bus control signals and interrupt service

request signals; or general-purpose I/O.

Port K

PK[7,3:0] 13,

108-111 In/Out

DDRK ($00FD) Page index emulation signals in expanded or peripheral mode

or general-purpose I/O.

Port P

PP[3:0] 112,

1–3 In/Out

DDRP ($0057) General-purpose I/O. PP[3:0] are used with the pulse-width

modulator when enabled.

Port S

PS[7:0] 96–89 In/Out

DDRS ($00D7) Serial communications interfaces 1 and 0 and serial peripheral

interface subsystems; or general-purpose I/O.

Port T

PT[7:0] 18–15,

7–4 In/Out

DDRT ($00AF) General-purpose I/O when not enabled for input capture and

output compare in the timer and pulse accumulator subsystem.

Pinout and Signal Descriptions

MC68HC912DG128

44 Pinout and Signal Descriptions MOTOROLA

Table 1 Port Pull-Up, Pull-Down and Reduced Drive Summary

Enable Bit Reduced Drive Control Bit

Port

Name Resistive

Input Loads Register

(Address) Bit Name Reset

State Register

(Address) Bit Name Reset

State

Port A Pull-up PUCR ($000C) PUPA Disabled RDRIV ($000D) RDPA Full drive

Port B Pull-up PUCR ($000C) PUPB Disabled RDRIV ($000D) RDPB Full drive

Port E:

PE7, PE[3:2] Pull-up PUCR ($000C) PUPE Enabled RDRIV ($000D) RDPE Full drive

PE[1:0] Pull-up PUCR ($000C) PUPE Enabled —

PE[6:4] None — RDRIV ($000D) RDPE Full drive

Port H Pull-up or

Pull-down PUCR ($000C) PUPH Disabled RDRIV ($000D) RDPH Full drive

Port J Pull-up or

Pull-down PUCR ($000C) PUPJ Disabled RDRIV ($000D) RDPJ Full drive

Port K Pull-up PUCR ($000C) PUPK Disabled RDRIV ($000D) RDPK Full drive

Port P Pull-up PWCTL ($0054) PUPP Disabled PWCTL ($0054) RDPP Full drive

Port S Pull-up SP0CR2 ($00D1) PUPS Enabled SP0CR2

($00D1) RDPS Full drive

Port T Pull-up TMSK2 ($008D) TPU Disabled TMSK2 ($008D) TDRB Full drive

Port IB[7:4] Pull-up IBPURD ($00E5) PUPIB Disabled IBPURD ($00E5) RDPIB Full drive

Port AD0 None — —

Port AD1 None — —

Port CAN1[1] None — —

Port CAN1[0] Pull-up Always enabled —

Port CAN0[1] None — —

Port CAN0[0] Pull-up Always enabled —

22-pins

MC68HC912DG128

MOTOROLA Registers 45

Registers

General Description

Contents

The register block can be mapped to any 2K byte boundary within the

standard 64K byte address space by manipulating bits REG[15:11] in

the INITRG register. INITRG establishes the upper five bits of the

byte of the 2K byte block. Default addressing (after reset) is indicated in

the table below. For additional information refer to Operating Modes.

Table 8 MC68HC912DG128 Register Map (Sheet 1 of 10)

Address Bit 7 654321Bit 0 Name

$0000 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 PORTA(1)

$0001 PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 PORTB(1)

$0002 DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 DDRA(1)

$0003 DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 DDRB(1)

$0004-$

0007 00000000Reserved(3)

$0008 PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 PORTE(2)

$0009 DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 0 0 DDRE(2)

$000A NDBE CGMTE PIPOE NECLK LSTRE RDWE CALE DBENE PEAR(3)

$000B SMODN MODB MODA ESTR IVIS EBSWAI EMK EME MODE(3)

$000C PUPK PUPJ PUPH PUPE 0 0 PUPB PUPA PUCR(3)

$000D RDPK RDPJ RDPH RDPE 0 0 RDPB RDPA RDRIV(3)

$000E 00000000Reserved(3)

$000F 00000000Reserved(3)

$0010 RAM15 RAM14 RAM13 00000INITRM

$0011 REG15 REG14 REG13 REG12 REG11 0 0 MMSWAI INITRG

1-reg

Registers

MC68HC912DG128

46 Registers MOTOROLA

$0012 EE15 EE14 EE13 EE12 0 0 0 EEON INITEE

$0013 ROMTST NDRF RFSTR1 RFSTR0 EXSTR1 EXSTR0 ROMHM ROMON MISC

$0014 RTIE RSWAI RSBCK Reserved RTBYP RTR2 RTR1 RTR0 RTICTL

$0015 RTIF 0000000RTIFLG

$0016 CME FCME FCMCOP WCOP DISR CR2 CR1 CR0 COPCTL

$0017 Bit 7 654321Bit 0 COPRST

$0018 ITE6 ITE8 ITEA ITEC ITEE ITF0 ITF2 ITF4 ITST0

$0019 ITD6 ITD8 ITDA ITDC ITDE ITE0 ITE2 ITE4 ITST1

$001A ITC6 ITC8 ITCA ITCC ITCE ITD0 ITD2 ITD4 ITST2

$001B ITB6 ITB8 ITBA ITBC ITBE ITC0 ITC2 ITC4 ITST3

$001C 00000000Reserved

$001D 00000000Reserved

$001E IRQE IRQEN DLY 00000INTCR

$001F 1 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0 HPRIO

$0020 BKEN1 BKEN0 BKPM 0 BK1ALE BK0ALE 0 0 BRKCT0

$0021 0 BKDBE BKMBH BKMBL BK1RWE BK1RW BK0RWE BK0RW BRKCT1

$0022 Bit 15 14 13 12 11 10 9 Bit 8 BRKAH

$0023 Bit 7 654321Bit 0 BRKAL

$0024 Bit 15 14 13 12 11 10 9 Bit 8 BRKDH

$0025 Bit 7 654321Bit 0 BRKDL

$0026 00000000Reserved

$0027 00000000Reserved

$0028 PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0 PORTJ

$0029 PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0 PORTH

$002A DDJ7 DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0 DDRJ

$002B DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0 DDRH

$002C KWIEJ7 KWIEJ6 KWIEJ5 KWIEJ4 KWIEJ3 KWIEJ2 KWIEJ1 KWIEJ0 KWIEJ

$002D KWIEH7 KWIEH6 KWIEH5 KWIEH4 KWIEH3 KWIEH2 KWIEH1 KWIEH0 KWIEH

$002E KWIFJ7 KWIFJ6 KWIFJ5 KWIFJ4 KWIFJ3 KWIFJ2 KWIFJ1 KWIFJ0 KWIFJ

$002F KWIFH7 KWIFH6 KWIFH5 KWIFH4 KWIFH3 KWIFH2 KWIFH1 KWIFH0 KWIFH

$0030 KWPJ7 KWPJ6 KWPJ5 KWPJ4 KWPJ3 KWPJ2 KWPJ1 KWPJ0 KWPJ

$0031 KWPH7 KWPH6 KWPH5 KWPH4 KWPH3 KWPH2 KWPH1 KWPH0 KWPH

$0032 00000000Reserved

$0033 00000000Reserved

$0034–

$0037 Unimplemented5Reserved

$0038 0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0 SYNR

$0039 00000REFDV2 REFDV1 REFDV0 REFDV

$003A TSTOUT7 TSTOUT6 TSTOUT5 TSTOUT4 TSTOUT3 TSTOUT2 TSTOUT1 TSTOUT0 CGTFLG

$003B LOCKIF LOCK 0000LHIF LHOME PLLFLG

$003C LOCKIE PLLON AUTO ACQ 0 PSTP LHIE NOLHM PLLCR

Table 8 MC68HC912DG128 Register Map (Sheet 2 of 10)

Address Bit 7 654321Bit 0 Name

2--reg

Registers

MC68HC912DG128

MOTOROLA Registers 47

$003D 0 BCSP BCSS 0 0 MCS 0 0 CLKSEL

$003E 0 0 SLDV5 SLDV4 SLDV3 SLDV2 SLDV1 SLDV0 SLOW

$003F OPNLE TRK TSTCLKE TST4 TST3 TST2 TST1 TST0 CGTCTL

$0040 CON23 CON01 PCKA2 PCKA1 PCKA0 PCKB2 PCKB1 PCKB0 PWCLK

$0041 PCLK3 PCLK2 PCLK1 PCLK0 PPOL3 PPOL2 PPOL1 PPOL0 PWPOL

$0042 0000PWEN3 PWEN2 PWEN1 PWEN0 PWEN

$0043 0 Bit 6 54321Bit 0 PWPRES

$0044 Bit 7 654321Bit 0 PWSCAL0

$0045 Bit 7 654321Bit 0 PWSCNT0

$0046 Bit 7 654321Bit 0 PWSCAL1

$0047 Bit 7 654321Bit 0 PWSCNT1

$0048 Bit 7 654321Bit 0 PWCNT0

$0049 Bit 7 654321Bit 0 PWCNT1

$004A Bit 7 654321Bit 0 PWCNT2

$004B Bit 7 654321Bit 0 PWCNT3

$004C Bit 7 654321Bit 0 PWPER0

$004D Bit 7 654321Bit 0 PWPER1

$004E Bit 7 654321Bit 0 PWPER2

$004F Bit 7 654321Bit 0 PWPER3

$0050 Bit 7 654321Bit 0 PWDTY0

$0051 Bit 7 654321Bit 0 PWDTY1

$0052 Bit 7 654321Bit 0 PWDTY2

$0053 Bit 7 654321Bit 0 PWDTY3

$0054 0 0 0 PSWAI CENTR RDPP PUPP PSBCK PWCTL

$0055 DISCR DISCP DISCAL 00000PWTST

$0056 PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0 PORTP

$0057 DDP7 DDP6 DDP5 DDP4 DDP3 DDP2 DDP1 DDP0 DDRP

$0058-$

005F 00000000Reserved

$0060 Reserved ATD0CTL0

$0061 Reserved ATD0CTL1

$0062 ADPU AFFC ASWAI 0 0 0 ASCIE ASCIF ATD0CTL2

$0063 000000FRZ1 FRZ0 ATD0CTL3

$0064 RES10 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 ATD0CTL4

$0065 0 S8CM SCAN MULT CD CC CB CA ATD0CTL5

$0066 SCF 0000CC2CC1CC0ATD0STAT0

$0067 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 ATD0STAT1

$0068 SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 ATD0TESTH

$0069 SAR1 SAR0 RST TSTOUT TST3 TST2 TST1 TST0 ATD0TESTL

$006A–$

006E 00000000Reserved

Table 8 MC68HC912DG128 Register Map (Sheet 3 of 10)

Address Bit 7 654321Bit 0 Name

3-reg

Registers

MC68HC912DG128

48 Registers MOTOROLA

$006F PAD07 PAD06 PAD05 PAD04 PAD03 PAD02 PAD01 PAD00 PORTAD0

$0070 Bit 15 14 13 12 11 10 9 Bit 8 ADR00H

$0071 Bit 7 Bit 6 000000ADR00L

$0072 Bit 15 14 13 12 11 10 9 Bit 8 ADR01H

$0073 Bit 7 Bit 6 000000ADR01L

$0074 Bit 15 14 13 12 11 10 9 Bit 8 ADR02H

$0075 Bit 7 Bit 6 000000ADR02L

$0076 Bit 15 14 13 12 11 10 9 Bit 8 ADR03H

$0077 Bit 7 Bit 6 000000ADR03L

$0078 Bit 15 14 13 12 11 10 9 Bit 8 ADR04H

$0079 Bit 7 Bit 6 000000ADR04L

$007A Bit 15 14 13 12 11 10 9 Bit 8 ADR05H

$007B Bit 7 Bit 6 000000ADR05L

$007C Bit 15 14 13 12 11 10 9 Bit 8 ADR06H

$007D Bit 7 Bit 6 000000ADR06L

$007E Bit 15 14 13 12 11 10 9 Bit 8 ADR07H

$007F Bit 7 Bit 6 000000ADR07L

$0080 IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0 TIOS

$0081 FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0 CFORC

$0082 OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0 OC7M

$0083 OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 OC7D

$0084 Bit 15 14 13 12 11 10 9 Bit 8 TCNT

$0085 Bit 7 654321Bit 0 TCNT

$0086 TEN TSWAI TSBCK TFFCA Reserved TSCR

$0087 Reserved TQCR

$0088 OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4 TCTL1

$0089 OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0 TCTL2

$008A EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A TCTL3

$008B EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A TCTL4

$008C C7I C6I C5I C4I C3I C2I C1I C0I TMSK1

$008D TOI 0 PUPT RDPT TCRE PR2 PR1 PR0 TMSK2

$008E C7F C6F C5F C4F C3F C2F C1F C0F TFLG1

$008F TOF 0000000TFLG2

$0090 Bit 15 14 13 12 11 10 9 Bit 8 TC0

$0091 Bit 7 654321Bit 0 TC0

$0092 Bit 15 14 13 12 11 10 9 Bit 8 TC1

$0093 Bit 7 654321Bit 0 TC1

$0094 Bit 15 14 13 12 11 10 9 Bit 8 TC2

$0095 Bit 7 654321Bit 0 TC2

$0096 Bit 15 14 13 12 11 10 9 Bit 8 TC3

$0097 Bit 7 654321Bit 0 TC3

Table 8 MC68HC912DG128 Register Map (Sheet 4 of 10)

Address Bit 7 654321Bit 0 Name

4-reg

Registers

MC68HC912DG128

MOTOROLA Registers 49

$0098 Bit 15 14 13 12 11 10 9 Bit 8 TC4

$0099 Bit 7 654321Bit 0 TC4

$009A Bit 15 14 13 12 11 10 9 Bit 8 TC5

$009B Bit 7 654321Bit 0 TC5

$009C Bit 15 14 13 12 11 10 9 Bit 8 TC6

$009D Bit 7 654321Bit 0 TC6

$009E Bit 15 14 13 12 11 10 9 Bit 8 TC7

$009F Bit 7 654321Bit 0 TC7

$00A0 0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI PACTL

$00A1 000000PAOVFPAIFPAFLG

$00A2 Bit 7 654321Bit 0 PACN3

$00A3 Bit 7 654321Bit 0 PACN2

$00A4 Bit 7 654321Bit 0 PACN1

$00A5 Bit 7 654321Bit 0 PACN0

$00A6 MCZI MODMC RDMCL ICLAT FLMC MCEN MCPR1 MCPR0 MCCTL

$00A7 MCZF 0 0 0 POLF3 POLF2 POLF1 POLF0 MCFLG

$00A8 0000PA3EN PA2EN PA1EN PA0EN ICPAR

$00A9 000000DLY1DLY0DLYCT

$00AA NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0 ICOVW

$00AB SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ ICSYS

$00AC 00000000Reserved

$00AD 000000TCBYP 0 TIMTST

$00AE PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0 PORTT

$00AF DDT7 DDT6 DDT5 DDT4 DDT3 DDT2 DDT1 DDT0 DDRT

$00B0 0 PBEN 0000PBOVI0PBCTL

$00B1 000000PBOVF0PBFLG

$00B2 Bit 7 654321Bit 0 PA3H

$00B3 Bit 7 654321Bit 0 PA2H

$00B4 Bit 7 654321Bit 0 PA1H

$00B5 Bit 7 654321Bit 0 PA0H

$00B6 Bit 15 14 13 12 11 10 9 Bit 8 MCCNTH

$00B7 Bit 7 654321Bit 0 MCCNTL

$00B8 Bit 15 14 13 12 11 10 9 Bit 8 TC0H

$00B9 Bit 7 654321Bit 0 TC0H

$00BA Bit 15 14 13 12 11 10 9 Bit 8 TC1H

$00BB Bit 7 654321Bit 0 TC1H

$00BC Bit 15 14 13 12 11 10 9 Bit 8 TC2H

$00BD Bit 7 654321Bit 0 TC2H

$00BE Bit 15 14 13 12 11 10 9 Bit 8 TC3H

$00BF Bit 7 654321Bit 0 TC3H

$00C0 BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 SC0BDH

Table 8 MC68HC912DG128 Register Map (Sheet 5 of 10)

Address Bit 7 654321Bit 0 Name

5-reg

Registers

MC68HC912DG128

50 Registers MOTOROLA

$00C1 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 SC0BDL

$00C2 LOOPS WOMS RSRC M WAKE ILT PE PT SC0CR1

$00C3 TIE TCIE RIE ILIE TE RE RWU SBK SC0CR2

$00C4 TDRE TC RDRF IDLE OR NF FE PF SC0SR1

$00C5 0000000RAFSC0SR2

$00C6 R8 T8 000000SC0DRH

$00C7 R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0 SC0DRL

$00C8 BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 SC1BDH

$00C9 SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 SC1BDL

$00CA LOOPS WOMS RSRC M WAKE ILT PE PT SC1CR1

$00CB TIE TCIE RIE ILIE TE RE RWU SBK SC1CR2

$00CC TDRE TC RDRF IDLE OR NF FE PF SC1SR1

$00CD 0000000RAFSC1SR2

$00CE R8 T8 000000SC1DRH

$00CF R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0 SC1DRL

$00D0 SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBF SP0CR1

$00D1 0000PUPS RDPS SSWAI SPC0 SP0CR2

$00D2 00000SPR2 SPR1 SPR0 SP0BR

$00D3 SPIF WCOL 0 MODF 0000SP0SR

$00D4 0 0 0 0 0 0 0 0 Reserved

$00D5 Bit 7 654321Bit 0 SP0DR

$00D6 PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0 PORTS

$00D7 DDS7 DDS6 DDS5 DDS4 DDS3 DDS2 DDS1 DDS0 DDRS

$00D8–$

00DF 0 0 0 0 0 0 0 0 Reserved

$00E0 ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0 IBAD

$00E1 0 0 IBC5 IBC4 IBC3 IBC2 IBC1 IBC0 IBFD

$00E2 IBEN IBIE MS/SL Tx/Rx TXAK RSTA 0 IBSWAI IBCR

$00E3 TCF IAAS IBB IBAL 0 SRW IBIF RXAK IBSR

$00E4 D7 D6 D5 D4 D3 D2 D1 D0 IBDR

$00E5 0 0 0 RDPIB 0 0 0 PUPIB IBPURD

$00E6 PIB7 PIB6 PIB5 PIB4 PIB3 PIB2 PIB1 PIB0 PORTIB

$00E7 DDRIB7 DDRIB6 DDRIB5 DDRIB4 DDRIB3 DDRIB2 DDRIB1 DDRIB0 DDRIB

$00E8–

$00EF Unimplemented5Reserved

$00F0 NOBDML NOSHB 1 Reserved EESWAI PROTLC

KEERC EEMCR

$00F1 SHPROT 1 BPROT5 BPROT4 BPROT3 BPROT2 BPROT1 BPROT0 EEPROT

$00F2 EEODD EEVEN MARG EECPD EECPRD 0 EECPM 0 EETST

$00F3 BULKP 0 0 BYTE ROW ERASE EELAT EEPGM EEPROG

$00F4 0000000LOCK FEELCK

Table 8 MC68HC912DG128 Register Map (Sheet 6 of 10)

Address Bit 7 654321Bit 0 Name

6-reg

Registers

MC68HC912DG128

MOTOROLA Registers 51

7-reg

$00F5 0000000BOOTPFEEMCR

$00F6 FSTE GADR HVT FENLV FDISVFP VTCK STRE MWPR FEETST

$00F7 0 0 0 FESWAI SVFP ERAS LAT ENPE FEECTL

$00F8 MT07 MT06 MT05 MT04 MT03 MT02 MT01 MT00 MTST0

$00F9 MT0F MT0E MT0D MT0C MT0B MT0A MT09 MT08 MTST1

$00FA MT17 MT16 MT15 MT14 MT13 MT12 MT11 MT10 MTST2

$00FB MT1F MT1E MT1D MT1C MT1B MT1A MT19 MT18 MTST3

$00FC PK7 0 0 0 PK3 PK2 PK1 PK0 PORTK4

$00FD DDK7 0 0 0 DDK3 DDK2 DDK1 DDK0 DDRK4

$00FE 00000000Reserved

$00FF 00000PIX2 PIX1 PIX0 PPAGE

$0100 0 0 CSWAI SYNCH TLNKEN SLPAK SLPRQ SFTRES C0MCR0

$0101 00000LOOPB WUPM CLKSRC C0MCR1

$0102 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 C0BTR0

$0103 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 C0BTR1

$0104 WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF C0RFLG

$0105 WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE C0RIER

$0106 0 ABTAK2 ABTAK1 ABTAK0 0 TXE2 TXE1 TXE0 C0TFLG

$0107 0 ABTRQ2 ABTRQ1 ABTRQ0 0 TXEIE2 TXEIE1 TXEIE0 C0TCR

$0108 0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0 C0IDAC

$0109–

$010D Unimplemented5Reserved

$010E RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 C0RXERR

$010F TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 C0TXERR

$0110 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR0

$0111 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR1

$0112 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR2

$0113 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR3

$0114 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C0IDMR0

$0115 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C0IDMR1

$0116 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C0IDMR2

$0117 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C0IDMR3

$0118 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR4

$0119 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR5

$011A AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR6

$011B AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C0IDAR7

$011C AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C0IDMR4

$011D AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C0IDMR5

$011E AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C0IDMR6

$011F AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C0IDMR7

Table 8 MC68HC912DG128 Register Map (Sheet 7 of 10)

Address Bit 7 654321Bit 0 Name

Registers

MC68HC912DG128

52 Registers MOTOROLA

$0120–

$013C Unimplemented5Reserved

$013D 000000PUPCAN RDPCAN PCTLCAN0

$013E PCAN7 PCAN6 PCAN5 PCAN4 PCAN3 PCAN2 TxCAN RxCAN PORTCAN0

$013F DDCAN7 DDCAN6 DDCAN5 DDCAN4 DDCAN3 DDCAN2 0 0 DDRCAN0

$0140–

$014F FOREGROUND RECEIVE BUFFER 0 RxFG0

$0150–

$015F TRANSMIT BUFFER 00 Tx00

$0160–

$016F TRANSMIT BUFFER 01 Tx01

$0170–

$017F TRANSMIT BUFFER 02 Tx02

$0180–

$01DF Unimplemented5Reserved

$01E0 Reserved ATD1CTL0

$01E1 Reserved ATD1CTL1

$01E2 ADPU AFFC ASWAI 0 0 0 ASCIE ASCIF ATD1CTL2

$01E3 000000FRZ1 FRZ0 ATD1CTL3

$01E4 RES10 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0 ATD1CTL4

$01E5 0 S8CM SCAN MULT CD CC CB CA ATD1CTL5

$01E6 SCF 0000CC2CC1CC0ATD1STAT0

$01E7 CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0 ATD1STAT1

$01E8 SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2 ATD1TESTH

$01E9 SAR1 SAR0 RST TSTOUT TST3 TST2 TST1 TST0 ATD1TESTL

$01EA–$

01EE 0 0 0 0 0 0 0 0 Reserved

$01EF PAD17 PAD16 PAD15 PAD14 PAD13 PAD12 PAD11 PAD10 PORTAD1

$01F0 Bit 15 14 13 12 11 10 9 Bit 8 ADR10H

$01F1 Bit 7 Bit 6 000000ADR10L

$01F2 Bit 15 14 13 12 11 10 9 Bit 8 ADR11H

$01F3 Bit 7 Bit 6 000000ADR11L

$01F4 Bit 15 14 13 12 11 10 9 Bit 8 ADR12H

$01F5 Bit 7 Bit 6 000000ADR12L

$01F6 Bit 15 14 13 12 11 10 9 Bit 8 ADR13H

$01F7 Bit 7 Bit 6 000000ADR13L

$01F8 Bit 15 14 13 12 11 10 9 Bit 8 ADR14H

$01F9 Bit 7 Bit 6 000000ADR14L

$01FA Bit 15 14 13 12 11 10 9 Bit 8 ADR15H

$01FB Bit 7 Bit 6 000000ADR15L

$01FC Bit 15 14 13 12 11 10 9 Bit 8 ADR16H

$01FD Bit 7 Bit 6 000000ADR16L

Table 8 MC68HC912DG128 Register Map (Sheet 8 of 10)

Address Bit 7 654321Bit 0 Name

8-reg

Registers

MC68HC912DG128

MOTOROLA Registers 53

9-reg

$01FE Bit 15 14 13 12 11 10 9 Bit 8 ADR17H

$01FF Bit 7 Bit 6 000000ADR17L

$0200-$

02FF Unimplemented5Reserved

$0300 0 0 CSWAI SYNCH TLNKEN SLPAK SLPRQ SFTRES C1MCR0

$0301 00000LOOPB WUPM CLKSRC C1MCR1

$0302 SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 C1BTR0

$0303 SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10 C1BTR1

$0304 WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF C1RFLG

$0305 WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE C1RIER

$0306 0 ABTAK2 ABTAK1 ABTAK0 0 TXE2 TXE1 TXE0 C1TFLG

$0307 0 ABTRQ2 ABTRQ1 ABTRQ0 0 TXEIE2 TXEIE1 TXEIE0 C1TCR

$0308 0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0 C1IDAC

$0309–

$030D Unimplemented5Reserved

$030E RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0 C1RXERR

$030F TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0 C1TXERR

$0310 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR0

$0311 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR1

$0312 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR2

$0313 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR3

$0314 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C1IDMR0

$0315 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C1IDMR1

$0316 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C1IDMR2

$0317 AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C1IDMR3

$0318 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR4

$0319 AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR5

$031A AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR6

$031B AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0 C1IDAR7

$031C AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C1IDMR4

$031D AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C1IDMR5

$031E AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C1IDMR6

$031F AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0 C1IDMR7

$0320–

$033C Unimplemented5Reserved

$033D 000000PUPCAN RDPCAN PCTLCAN1

$033E PCAN7 PCAN6 PCAN5 PCAN4 PCAN3 PCAN2 TxCAN RxCAN PORTCAN1

$033F DDCAN7 DDCAN6 DDCAN5 DDCAN4 DDCAN3 DDCAN2 0 0 DDRCAN1

$0340–

$034F FOREGROUND RECEIVE BUFFER 1 RxFG1

$0350–

$035F TRANSMIT BUFFER 10 Tx10

Table 8 MC68HC912DG128 Register Map (Sheet 9 of 10)

Address Bit 7 654321Bit 0 Name

Registers

MC68HC912DG128

54 Registers MOTOROLA

1. Port A, port B and data direction registers DDRA, DDRB are not in map in expanded and peripheral modes.

2. Port E and DDRE not in the map in peripheral and expanded modes with EME set.

3. Registers also not in map in peripheral mode.

4. Port K and DDRK not in the map in peripheral and expanded modes with EMK set.

5. Data read at these locations is undefined.

$0360–

$036F TRANSMIT BUFFER 11 Tx11

$0370–

$037F TRANSMIT BUFFER 12 Tx12

$0380-$

03FF Unimplemented5Reserved

= Reserved or unimplemented bits.

Table 8 MC68HC912DG128 Register Map (Sheet 10 of 10)

Address Bit 7 654321Bit 0 Name

10-reg

MC68HC912DG128

MOTOROLA Operating Modes 55

Operating Modes

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Operating Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55

Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60

Introduction

Eight possible operating modes determine the operating configuration of

the MC68HC912DG128. Each mode has an associated default memory

map and external bus configuration.

Operating Modes

The operating mode out of reset is determined by the states of the

BKGD, MODB, and MODA pins during reset.

The SMODN, MODB, and MODA bits in the MODE register show current

operating mode and provide limited mode switching during operation.

The states of the BKGD, MODB, and MODA pins are latched into these

bits on the rising edge of the reset signal.

Table 9 Mode Selection

BKGD MODB MODA Mode Port A Port B

1 0 0 Normal Single Chip G.P. I/O G.P. I/O

1 0 1 Normal Expanded Narrow ADDR/DATA ADDR

1 1 0 Reserved (Forced to Peripheral) — —

1 1 1 Normal Expanded Wide ADDR/DATA ADDR/DATA

0 0 0 Special Single Chip G.P. I/O G.P. I/O

0 0 1 Special Expanded Narrow ADDR/DATA ADDR

1-modes

Operating Modes

MC68HC912DG128

56 Operating Modes MOTOROLA

There are two basic types of operating modes:

Normal modes — some registers and bits are protected

against accidental changes.

Special modes — allow greater access to protected control

registers and bits for special purposes such as testing and

emulation.

A system development and debug feature, background debug mode

(BDM), is available in all modes. In special single-chip mode, BDM is

active immediately after reset.

Normal Operating

Modes

These modes provide three operating configurations. Background

debug is available in all three modes, but must first be enabled for some

operations by means of a BDM background command, then activated.

Normal Single-Chip Mode — There are no external address and

data buses in this mode. The MCU operates as a stand-alone

device and all program and data resources are on-chip. External

port pins normally associated with address and data buses can be

used for general-purpose I/O.

Normal Expanded Wide Mode — This is a normal mode of

operation in which the expanded bus is present with a 16-bit data

bus. Ports A and B are used for the 16-bit multiplexed

address/data bus.

Normal Expanded Narrow Mode — This is a normal mode of

operation in which the expanded bus is present with an 8-bit data

bus. Ports A and B are used for the16-bit address bus. Port A is

used as the data bus, multiplexed with addresses. In this mode,

16-bit data is presented one byte at a time, the high byte followed

by the low byte. The address is automatically incremented on the

second cycle.

0 1 0 Special Peripheral ADDR/DATA ADDR/DATA

0 1 1 Special Expanded Wide ADDR/DATA ADDR/DATA

Table 9 Mode Selection

BKGD MODB MODA Mode Port A Port B

2--modes

Operating Modes

MC68HC912DG128

MOTOROLA Operating Modes 57

Special Operating

Modes

There are three special operating modes that correspond to normal

operating modes. These operating modes are commonly used in factory

testing and system development. In addition, there is a special

peripheral mode, in which an external master, such as an I.C. tester, can

control the on-chip peripherals.

Special Single-Chip Mode — This mode can be used to force the

MCU to active BDM mode to allow system debug through the

BKGD pin. There are no external address and data buses in this

mode. The MCU operates as a stand-alone device and all

program and data space are on-chip. External port pins can be

used for general-purpose I/O.

Special Expanded Wide Mode — This mode can be used for

emulation of normal expanded wide mode and emulation of

normal single-chip mode. Ports A and B are used for the 16-bit

multiplexed address/data bus.

Special Expanded Narrow Mode — This mode can be used for

emulation of normal expanded narrow mode. Ports A and B are

used for the16-bit address bus. Port A is used as the data bus,

multiplexed with addresses. In this mode, 16-bit data is presented

one byte at a time, the high byte followed by the low byte. The

address is automatically incremented on the second cycle.

Special Peripheral Mode — The CPU is not active in this mode.

An external master can control on-chip peripherals for testing

purposes. It is not possible to change to or from this mode without

going through reset. Background debugging should not be used

while the MCU is in special peripheral mode as internal bus

conflicts between BDM and the external master can cause

improper operation of both functions.

MODE — Mode Register $000B

Bit 7 654321Bit 0

SMODN MODB MODA ESTR IVIS EBSWAI EMK EME

RESET: 00011011Special Single Chip

RESET: 00111011Special Exp Nar

RESET: 01011011Peripheral

3-modes

Operating Modes

MC68HC912DG128

58 Operating Modes MOTOROLA

The MODE register controls the MCU operating mode and various

configuration options. This register is not in the map in peripheral mode

SMODN, MODB, MODA — Mode Select Special, B and A

These bits show the current operating mode and reflect the status of

the BKGD, MODB and MODA input pins at the rising edge of reset.

Read anytime.

SMODN may only be written if SMODN = 0 (in special modes) but the

first write is ignored.

MODB, MODA may be written once if SMODN = 1; anytime if SMODN

= 0 but the first write is ignored and in special peripheral and reserved

modes cannot be selected.

ESTR — E Clock Stretch Enable

Determines if the E Clock behaves as a simple free-running clock or

as a bus control signal that is active only for external bus cycles.

ESTR is always one in expanded modes since it is required for

address and data de-multiplexing and must follow stretched cycles.

0 = E never stretches (always free running).

1 = E stretches high during external access cycles and low during

non-visible internal accesses (IVIS = 0).

Normal modes: write once; Special modes: write anytime, read

anytime.

IVIS — Internal Visibility

This bit determines whether internal ADDR, DATA, R/W and LSTRB

signals can be seen on the external bus during accesses to internal

locations. In Special Narrow Mode if this bit is set and an internal

access occurs the data will appear wide on Ports A and B. This serves

RESET: 01111011Special Exp Wide

RESET: 10010000Normal Single Chip

RESET: 10110000Normal Exp Nar

RESET: 11110000Normal Exp Wide

MODE — Mode Register $000B

4-modes

Operating Modes

MC68HC912DG128

MOTOROLA Operating Modes 59

the same function as the EMD bit of the non-multiplexed versions of

the HC12 and allows for emulation. Visibility is not available when the

part is operating in a single-chip mode.

0 = No visibility of internal bus operations on external bus.

1 = Internal bus operations are visible on external bus.

Normal modes: write once; Special modes: write anytime EXCEPT

the first time. Read anytime.

EBSWAI — Multiplexed External Bus Interface Module Stops in Wait

Mode

This bit controls access to the multiplexed external bus interface

module during wait mode. The module will delay before shutting down

in wait mode to allow for ﬁnal bus activity to complete.

0 = MEBI continues functioning during wait mode.

1 = MEBI is shut down during wait mode.

Normal modes: write anytime; special modes: write never. Read

anytime.

EMK — Emulate Port K

In single-chip mode PORTK and DDRK are always in the map

regardless of the state of this bit.

0 = Port K and DDRK registers are in the memory map. Memory

expansion emulation is disable and all pins are general

purpose I/O.

1 = In expanded or peripheral mode, PORTK and DDRK are

removed from the internal memory map. Removing the

registers from the map allows the user to emulate the function

of these registers externally.

Normal modes: write once; special modes: write anytime EXCEPT

the first time. Read anytime.

EME — Emulate Port E

In single-chip mode PORTE and DDRE are always in the map

regardless of the state of this bit.

0 = PORTE and DDRE are in the memory map.

5-modes

Operating Modes

MC68HC912DG128

60 Operating Modes MOTOROLA

1 = If in an expanded mode, PORTE and DDRE are removed from

the internal memory map. Removing the registers from the

map allows the user to emulate the function of these registers

externally.

Normal modes: write once; special modes: write anytime EXCEPT

the first time. Read anytime.

Background Debug Mode

Background debug mode (BDM) is an auxiliary operating mode that is

used for system development. BDM is implemented in on-chip hardware

and provides a full set of debug operations. Some BDM commands can

be executed while the CPU is operating normally. Other BDM

commands are firmware based, and require the BDM firmware to be

enabled and active for execution.

In special single-chip mode, BDM is enabled and active immediately out

of reset. BDM is available in all other operating modes, but must be

enabled before it can be activated. BDM should not be used in special

peripheral mode because of potential bus conflicts.

Once enabled, background mode can be made active by a serial

command sent via the BKGD pin or execution of a CPU12 BGND

instruction. While background mode is active, the CPU can interpret

special debugging commands, and read and write CPU registers,

peripheral registers, and locations in memory.

While BDM is active, the CPU executes code located in a small on-chip

ROM mapped to addresses $FF20 to $FFFF, and BDM control registers

are accessible at addresses $FF00 to $FF06. The BDM ROM replaces

the regular system vectors while BDM is active. While BDM is active, the

user memory from $FF00 to $FFFF is not in the map except through

serial BDM commands.

6-modes

MC68HC912DG128

MOTOROLA Resource Mapping 61

Resource Mapping

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Internal Resource Mapping. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61

Flash EEPROM mapping through internal Memory Expansion . . . . .64

Miscellaneous System Control Register . . . . . . . . . . . . . . . . . . . . . . .69

Mapping test registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71

Memory Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72

Introduction

After reset, most system resources can be mapped to other addresses

by writing to the appropriate control registers.

Internal Resource Mapping

The internal register block, RAM, and EEPROM have default locations

within the 64K byte standard address space but may be reassigned to

other locations during program execution by setting bits in mapping

registers INITRG, INITRM, and INITEE. During normal operating modes

these registers can be written once. It is advisable to explicitly establish

these resource locations during the initialization phase of program

execution, even if default values are chosen, in order to protect the

registers from inadvertent modification later.

Writes to the mapping registers go into effect between the cycle that

follows the write and the cycle after that. To assure that there are no

unintended operations, a write to one of these registers should be

followed with a NOP instruction.

1-mapping

Resource Mapping

MC68HC912DG128

62 Resource Mapping MOTOROLA

If conflicts occur when mapping resources, the register block will take

precedence over the other resources; RAM or EEPROM addresses

occupied by the register block will not be available for storage. When

active, BDM ROM takes precedence over other resources, although a

conflict between BDM ROM and register space is not possible. The

following table shows resource mapping precedence.

In expanded modes, all address space not used by internal resources is

by default external memory.

The MC68HC912DG128 contains 128K bytes of Flash EEPROM

nonvolatile memory which can be used to store program code or static

data. This physical memory is composed of four 32k byte array modules,

00FEE32K, 01FEE32K, 10FEE32K and 11FEE32K. The 32K byte array

11FEE32K has a fixed location from $4000 to $7FFF and $C000 to

$FFFF. The three 32K byte arrays 00FEE32K, 01FEE32K and

10FEE32K are accessible through a 16K byte program page window

mapped from $8000 to $BFFF. The fixed 32K byte array 11FEE32K can

also be accessed through the program page window.

Mapping

After reset the 1K byte register block resides at location $0000 but can

be reassigned to any 2K byte boundary within the standard 64K byte

address space. Mapping of internal registers is controlled by five bits in

the INITRG register. The register block occupies the first 1K byte of the

2K byte block.

Table 10 Mapping Precedence

Precedence Resource

1 BDM ROM (if active)

2 Register Space

3 RAM

4 EEPROM

5 On-Chip Flash EEPROM

6 External Memory

2--mapping

Resource Mapping

Internal Resource Mapping

MC68HC912DG128

MOTOROLA Resource Mapping 63

REG[15:11] — Internal register map position

These bits specify the upper five bits of the 16-bit registers address.

Normal modes: write once; special modes: write anytime. Read

anytime.

MMSWAI — Memory Mapping Interface Stop in Wait Control

This bit controls access to the memory mapping interface when in

Wait mode.

Normal modes: write anytime; special modes: write never. Read

anytime.

0 = Memory mapping interface continues to function during Wait

mode.

1 = Memory mapping interface access is shut down during Wait

mode.

RAM Mapping The MC68HC912DG128 has 8K bytes of fully static RAM that is used for

storing instructions, variables, and temporary data during program

execution. Since the RAM is actually implemented with two 4K RAM

arrays, any misaligned word access between last address of first 4K

RAM and first address of second 4K RAM will take two cycles instead of

one. After reset, RAM addressing begins at location $2000 but can be

assigned to any 8K byte boundary within the standard 64K byte address

space. Mapping of internal RAM is controlled by three bits in the INITRM

RAM[15:13] — Internal RAM map position

INITRG — Initialization of Internal Register Position Register $0011

Bit 7 654321Bit 0

REG15 REG14 REG13 REG12 REG11 0 0 MMSWAI

RESET: 00000000

INITRM — Initialization of Internal RAM Position Register $0010

Bit 7 654321Bit 0

RAM15 RAM14 RAM13 00000

RESET: 00100000

3-mapping

Resource Mapping

MC68HC912DG128

64 Resource Mapping MOTOROLA

These bits specify the upper three bits of the 16-bit RAM address.

Normal modes: write once; special modes: write anytime. Read

anytime.

EEPROM Mapping The MC68HC912DG128 has 2K bytes of EEPROM which is activated by

the EEON bit in the INITEE register. Mapping of internal EEPROM is

controlled by four bits in the INITEE register. After reset EEPROM

address space begins at location $0800 but can be mapped to any 4K

byte boundary within the standard 64K byte address space. The

EEPROM block occupies the last 2K bytes of the 4K byte block.

EE[15:12] — Internal EEPROM map position

These bits specify the upper four bits of the 16-bit EEPROM address.

Normal modes: write once; special modes: write anytime. Read

anytime.

EEON — internal EEPROM On (Enabled)

Read or write anytime.

0 = Removes the EEPROM from the map.

1 = Places the on-chip EEPROM in the memory map at the

address selected by EE[15:12].

Flash EEPROM mapping through internal Memory Expansion

The Page Index register or PPAGE provides memory management for

the MC68HC908AZ60. PPAGE consists of three bits to indicate which

physical location is active within the windows of the MC68HC908AZ60.

The MC68HC908AZ60 has a user’s program space window, a register

INITEE— Initialization of Internal EEPROM Position Register $0012

Bit 7 654321Bit 0

EE15 EE14 EE13 EE12 0 0 0 EEON

RESET: 00000001

4-mapping

Resource Mapping

Flash EEPROM mapping through internal Memory Expansion

MC68HC912DG128

MOTOROLA Resource Mapping 65

space window for Flash module registers, and a test program space

window.

The user’s program page window consists of 16K Flash EEPROM bytes.

One of eight pages is viewed through this window for a total of 128K

accessible Flash EEPROM bytes.

The register space window consists of a 4-byte register block. One of

four pages is viewed through this window for each of the 32K flash

module register blocks of MC68HC908AZ60.

The test mode program page window consists of 32K Flash EEPROM

bytes. One of the four 32K byte arrays is viewed through this window for

a total 128K accessible Flash EEPROM bytes. This window is only

available in special mode for test purposes and replaces the user’s

program page window.

MC68HC908AZ60 has a five pin port, port K, for emulation and for

general purpose I/O. Three pins are used to emulate the three page

indices (PPAGE bits) and one pin is used as an emulation chip select.

When these four pins are not used for emulation they serve as general

purpose I/O pins. The fifth port K pin is used as a general purpose I/O

pin.

Program space

expansion

There are 128K bytes of Flash EEPROM for MC68HC908AZ60. With a

64K byte address space, the PPAGE register is needed to perform on

chip memory expansion. A program space window of 16K byte pages is

located from $8000 to $BFFF. Three page indices are used to point to

one of eight different 16K byte pages.

Table 11 Program space Page Index

Page Index 2

(PPAGE bit 2) Page Index 1

(PPAGE bit 1) Page Index 0

(PPAGE bit 0) 16K Program space Page Flash array

0 0 0 16K byte Page 0 00FEE32K

0 0 1 16K byte Page 1 00FEE32K

0 1 0 16K byte Page 2 01FEE32K

0 1 1 16K byte Page 3 01FEE32K

1 0 0 16K byte Page 4 10FEE32K

1 0 1 16K byte Page 5 10FEE32K

5-mapping

Resource Mapping

MC68HC912DG128

66 Resource Mapping MOTOROLA

* The 16K byte flash in program space page 6 can also be accessed at

a fixed location from $4000 to $7FFF. The 16K byte flash in program

space page 7 can also be accessed at a fixed location from $C000 to

$FFFF.

Flash register

space expansion

There are four 32K Flash arrays for MC68HC908AZ60 and each

requires a 4-byte register block. A register space window is used to

access one of the four 4-byte blocks and the PPAGE register to map

each one into the window. The register space window is located from

$00F4 to $00F7 after reset. Only two page indices are used to point to

one of the four pages of the register space.

Test mode

Program space

expansion

In special mode and for test purposes only, the 128K bytes of Flash

EEPROM for MC68HC908AZ60 can be accessed through a test

program space window of 32K bytes. This window replaces the user’s

program space window to be able to access an entire array. In special

mode and with ROMTST bit set in MISC register, a program space is

located from $8000 to $FFFF. Only two page indices are used to point

to one of the four 32K byte arrays. These indices can be viewed as

expanded addresses X16 and X15.

1 1 0 16K byte Page 6* 11FEE32K

1 1 1 16K byte Page 7* 11FEE32K

Table 11 Program space Page Index

Page Index 2

(PPAGE bit 2) Page Index 1

(PPAGE bit 1) Page Index 0

(PPAGE bit 0) 16K Program space Page Flash array

Table 12 Flash Register space Page Index

Page Index 2

(PPAGE bit

2) Page Index 1

(PPAGE bit 1) Page Index 0

(PPAGE bit 0) Flash register space Page Flash array

0 0 X $00F4-$00F7 Page 0 00FEE32K

0 1 X $00F4-$00F7 Page 1 01FEE32K

1 0 X $00F4-$00F7 Page 2 10FEE32K

1 1 X $00F4-$00F7 Page 3 11FEE32K

6-mapping

Resource Mapping

Flash EEPROM mapping through internal Memory Expansion

MC68HC912DG128

MOTOROLA Resource Mapping 67

7-mapping

Page Index

descriptions

Read and write anytime

Writes do not change pin state when pin configured for page index

emulation output.

This port is associated with page index emulation pins. When the port is

not enabled to emulate page index, the port pins are used as

general-purpose I/O. Port K bit 3 is used as a general purpose I/O pin

only. This register is not in the map in peripheral or expanded modes

while the EMK control bit in MODE register is set.

When inputs, these pins can be selected to be high impedance or pulled

up.

ECS — Emulation Chip Select of selected program space

When this signal is active low it indicates that the program space is

accessed. This also applies to test mode program space. An access

is made if address is at the program space window and either the

Flash or external memory is accessed. The ECS timing is E clock high

Table 13 Test mode program space Page Index

Page Index 2

(PPAGE bit 2) Page Index 1

(PPAGE bit 1) Page Index 0

(PPAGE bit 0) Flash register space Page Flash array

0 0 X 32K byte array Page 0 00FEE32K

0 1 X 32K byte array Page 1 01FEE32K

1 0 X 32K byte array Page 2 10FEE32K

1 1 X 32K byte array Page 3 11FEE32K

PORTK — Port K Data Register $00FC

Bit 7 6 5 4 3 2 1 Bit 0

PORT PK7 0 0 0 PK3 PK2 PK1 PK0

Emulation ECS 0 0 0 - PIX2 PIX1 PIX0

RESET: - 0 0 0 - - - -

Resource Mapping

MC68HC912DG128

68 Resource Mapping MOTOROLA

and can be stretched when accessing external memory depending on

the EXTR0 and EXTR1 bits in the MISC register. The ECS signal is

only active when the EMK bit is set.

PIX[2:0] — The content of the PPAGE register emulated externally.

This content indicates which Flash module register space is in the

memory map and which 16K byte Flash memory is in the program

space. In special mode and with ROMTST bit set, the content of the

Page Index register indicates which 32K byte Flash array is in the test

program space.

Read and write: anytime.

This register determines the primary direction for each port K pin

configured as general-purpose I/O.

0 = Associated pin is a high-impedance input.

1 = Associated pin is an output.

This register is not in the map in peripheral or expanded modes while the

EMK control bit is set.

Read and write: anytime.

This register determines the active page viewed through

MC68HC908AZ60 windows.

DDRK — Port K Data Direction Register $00FD

Bit 7 6 5 4 3 2 1 Bit 0

DDK7 0 0 0 DDK3 DDK2 DDK1 DDK0

RESET: 0 0 0 0 0 0 0 0

PPAGE — (Program) Page Index Register $00FF

Bit 7 6 5 4 3 2 1 Bit 0

0 0 0 0 0 PIX2 PIX1 PIX0

RESET: 0 0 0 0 0 0 0 0

8-mapping

Resource Mapping

Miscellaneous System Control Register

MC68HC912DG128

MOTOROLA Resource Mapping 69

9-mapping

CALL and RTC instructions have a special single wire mechanism to

read and write this register without using an address bus.

Miscellaneous System Control Register

Additional mapping and external resource controls are available. To use

external resources the part must be operated in one of the expanded

modes.

Normal modes: write once; Special modes: write anytime. Read

anytime.

ROMTST — FLASH EEPROM Test mode

In normal modes, this bit is forced to zero.

0 = 16K window for Flash memory is located from $8000-$BFFF

1 = 32K window for Flash memory is located from $8000-$FFFF

NDRF — Narrow Data Bus for Register-Following Map Space

This bit enables a narrow bus feature for the 1K byte

and allows 8-bit and 16-bit external memory devices to be mixed in a

system. In Expanded Narrow (eight bit) modes, Single Chip Modes,

and Peripheral mode, this bit has no effect.

0 = Makes Register-Following MAP space act as a full 16 bit data

bus.

1 = Makes the Register-Following MAP space act the same as an

8 bit only external data bus (data only goes through port A

externally).

MISC — Miscellaneous Mapping Control Register $0013

Bit 7 654321Bit 0 Mode

ROMTST NDRF RFSTR1 RFSTR0 EXSTR1 EXSTR0 ROMHM ROMON

RESET: 00001100Exp mode

RESET: 00001101

peripheral or

SC mode

Resource Mapping

MC68HC912DG128

70 Resource Mapping MOTOROLA

The Register-Following space is mapped from $0400 to $07FF after

reset, which is next to the register map. If the registers are moved this

space follows.

RFSTR1, RFSTR0 — Register Following Stretch

This two bit field determines the amount of clock stretch on accesses

to the 1K byte Register Following Map. It is valid regardless of the

state of the NDRF bit. In Single Chip and Peripheral Modes this bit

has no meaning or effect.

EXSTR1, EXSTR0 — External Access Stretch

This two bit field determines the amount of clock stretch on accesses

to an external address space. In Single Chip and Peripheral Modes

this bit has no meaning or effect.

ROMHM — Flash EEPROM only in second Half of Map

This bit has no meaning if ROMON bit is clear.

0 = The 16K byte of fixed Flash EEPROM in location $4000-$7FFF

can be accessed.

Table 14 RFSTR Stretch Bit Deﬁnition

RFSTR1 RFSTR0 Number of E Clocks

Stretched

00 0

01 1

10 2

11 3

Table 15 EXSTR Stretch Bit Deﬁnition

EXSTR1 EXSTR0 Number of E Clocks

Stretched

00 0

01 1

10 2

11 3

10-mapping

Resource Mapping

Mapping test registers

MC68HC912DG128

MOTOROLA Resource Mapping 71

11-mapping

1 = Disables direct access to 16K byte Flash EEPROM from

$4000-$7FFF in the memory map. The physical location of

this16K byte Flash can still be accessed through the Program

Page window.

In special mode and with ROMTST bit set, this bit will allow overlap of

the four 32K Flash arrays and overlap the four 4-byte Flash register

space in the same map space to be able to program all arrays at the

same time.

0 = The four 32K Flash arrays are accessed with four pages for

each.

1 = The four 32K Flash arrays coincide in the same space and are

selected at the same time for programming.

CAUTION:

Bit must be cleared before reading any of the arrays or registers.

ROMON — Enable Flash EEPROM

These bits are used to enable the Flash EEPROM arrays.

0 = Disables Flash EEPROM in the memory map.

1 = Enables Flash EEPROM in the memory map.

Mapping test registers

These registers are used in for testing the mapping logic. They can only

be read and after each read they get cleared. A write to each register will

have no effect.

MTST0 — Mapping Test Register 0 $00F8

Bit 7 654321Bit 0

MT07 MT06 MT05 MT04 MT03 MT02 MT01 MT00

RESET: 00000000

MTST1 — Mapping Test Register 1 $00F9

Bit 7 654321Bit 0

MT0F MT0E MT0D MT0C MT0B MT0A MT09 MT08

RESET: 00000000

Resource Mapping

MC68HC912DG128

72 Resource Mapping MOTOROLA

Memory Maps

The following diagrams illustrate the memory map for each mode of

operation immediately after reset.

MTST2 — Mapping Test Register 2 $00FA

Bit 7 654321Bit 0

MT17 MT16 MT15 MT14 MT13 MT12 MT11 MT10

RESET: 00000000

MTST3 — Mapping Test Register 3 $00FB

Bit 7 654321Bit 0

MT1F MT1E MT1D MT1C MT1B MT1A MT19 MT18

RESET: 00000000

12-mapping

Resource Mapping

Memory Maps

MC68HC912DG128

MOTOROLA Resource Mapping 73

13-mapping

Figure 8 MC68HC912DG128 Memory Map after reset

The following diagram illustrates the memory paging scheme.

$03FF REGISTERS

(MAPPABLE TO ANY 2K

8K bytes RAM

(MAPPABLE TO ANY 8K

EXPANDEDNORMAL

SINGLE CHIP SPECIAL

SINGLE CHIP

$0000

$3FFF

$2000

2K bytes EEPROM

(MAPPABLE TO ANY 4K

$0FFF

$0800

VECTORSVECTORSVECTORS

BDM

(if active)

$FFFF

$FF00

16K Page Window

Eight 16K Flash EEPROM pages

$BFFF

$8000

EXT

$A000 - $BFFF Protected BOOT

at odd programing pages

$0000

$2000

$0800

$1000

$8000

$FF00

$FFFF

$0400

16K Fixed Flash EEPROM

$4000

16K Fixed Flash EEPROM

$FFFF

$C000

$E000 - $FFFF Protected BOOT

$4000

$C000

Resource Mapping

MC68HC912DG128

74 Resource Mapping MOTOROLA

Figure 9 MC68HC912DG128 Memory Paging

* This 32K Flash

accessible as

pages 6 & 7 and

as unpaged

$4000 - $7FFF &

$C000 - $FFFF

NORMAL

SINGLE CHIP

00 Flash 32K

VECTORS

One 16K Page accessible at a time (selected by PPAGE value = 0 to 7)

$0000

$2000

$0800

$1000

$8000

$FF00

$FFFF

$0400

16K Flash

(Unpaged)

$4000

$C000

1234567

01 Flash 32K 10 Flash 32K 11 Flash 32K *

16K Flash

(Unpaged)

16K Flash

(Paged)

(8K Boot)

(8K Boot) (8K Boot) (8K Boot) (8K Boot)

$E000

14-mapping

MC68HC912DG128

MOTOROLA Bus Control and Input/Output 75

Bus Control and Input/Output

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75

Detecting Access Type from External Signals . . . . . . . . . . . . . . . . . .75

Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76

Introduction

Internally the MC68HC912DG128 has full 16-bit data paths, but

depending upon the operating mode and control registers, the external

multiplexed bus may be 8 or 16 bits. There are cases where 8-bit and

16-bit accesses can appear on adjacent cycles using the LSTRB signal

to indicate 8- or 16-bit data.

It is possible to have a mix of 8 and 16 bit peripherals attached to the

external multiplexed bus, using the NDRF bit in the MISC register while

in expanded wide modes.

Detecting Access Type from External Signals

The external signals LSTRB, R/W, and A0 can be used to determine the

type of bus access that is taking place. Accesses to the internal RAM

module are the only type of access that produce LSTRB = A0 = 1,

because the internal RAM is specifically designed to allow misaligned

16-bit accesses in a single cycle. In these cases the data for the address

that was accessed is on the low half of the data bus and the data for

address + 1 is on the high half of the data bus.

1-bus

Bus Control and Input/Output

MC68HC912DG128

76 Bus Control and Input/Output MOTOROLA

Registers

Not all registers are visible in the MC68HC912DG128 memory map

under certain conditions. In special peripheral mode the first 16 registers

associated with bus expansion are removed from the memory map.

In expanded modes, some or all of port A, port B, and port E are used

for expansion buses and control signals. In order to allow emulation of

the single-chip functions of these ports, some of these registers must be

rebuilt in an external port replacement unit. In any expanded mode, port

A, and port B, are used for address and data lines so registers for these

ports, as well as the data direction registers for these ports, are removed

from the on-chip memory map and become external accesses.

In any expanded mode, port E pins may be needed for bus control (e.g.,

ECLK, R/W). To regain the single-chip functions of port E, the emulate

port E (EME) control bit in the MODE register may be set. In this special

case of expanded mode and EME set, PORTE and DDRE registers are

removed from the on-chip memory map and become external accesses

so port E may be rebuilt externally.

Table 16 Access Type vs. Bus Control Pins

LSTRB A0 R/W Type of Access

1 0 1 8-bit read of an even address

0 1 1 8-bit read of an odd address

1 0 0 8-bit write of an even address

0 1 0 8-bit write of an odd address

0 0 1 16-bit read of an even address

111

16-bit read of an odd address

(low/high data swapped)

0 0 0 16-bit write to an even address

110

16-bit write to an odd address

(low/high data swapped)

2--bus

Bus Control and Input/Output

Registers

MC68HC912DG128

MOTOROLA Bus Control and Input/Output 77

Bits PA[7:0] are associated respectively with addresses ADDR[15:8],

DATA[15:8] and DATA[7:0], in narrow mode. When this port is not

used for external addresses such as in single-chip mode, these pins

can be used as general-purpose I/O. DDRA determines the primary

direction of each pin. This register is not in the on-chip map in

expanded and peripheral modes. Read and write anytime.

This register determines the primary direction for each port A pin

when functioning as a general-purpose I/O port. DDRA is not in the

on-chip map in expanded and peripheral modes. Read and write

anytime.

0 = Associated pin is a high-impedance input

1 = Associated pin is an output

Bits PB[7:0] are associated with addresses ADDR[7:0] and DATA[7:0]

(except in narrow mode) respectively. When this port is not used for

external addresses such as in single-chip mode, these pins can be

PORTA — Port A Register $0000

Bit 7 654321Bit 0

Single Chip PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0

RESET: ————————

Expanded

& Periph: ADDR15/

DATA15 ADDR14/

DATA14 ADDR13/

DATA13 ADDR12/

DATA12 ADDR11/

DATA11 ADDR10/

DATA10 ADDR9/

DATA9 ADDR8/

DATA8

Expanded

narrow ADDR15/

DATA15/

DATA7

ADDR14/

DATA14/

DATA6

ADDR13/

DATA13/

DATA5

ADDR12/

DATA12/

DATA4

ADDR11/

DATA11/

DATA3

ADDR10/

DATA10/

DATA2

ADDR9/

DATA9/

DATA1

ADDR8/

DATA8/

DATA0

DDRA — Port A Data Direction Register $0002

Bit 7 654321Bit 0

DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0

RESET: 00000000

PORTB — Port B Register $0001

Bit 7 654321Bit 0

Single Chip PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0

RESET: ————————

Expanded

& Periph: ADDR7/

DATA7 ADDR6/

DATA6 ADDR5/

DATA5 ADDR4/

DATA4 ADDR3/

DATA3 ADDR2/

DATA2 ADDR1/

DATA1 ADDR0/

DATA0

Expanded

narrow ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0

3-bus

Bus Control and Input/Output

MC68HC912DG128

78 Bus Control and Input/Output MOTOROLA

used as general-purpose I/O. DDRB determines the primary direction

of each pin. This register is not in the on-chip map in expanded and

peripheral modes. Read and write anytime.

This register determines the primary direction for each port B pin

when functioning as a general-purpose I/O port. DDRB is not in the

on-chip map in expanded and peripheral modes. Read and write

anytime.

0 = Associated pin is a high-impedance input

1 = Associated pin is an output

This register is associated with external bus control signals and

interrupt inputs, including data bus enable (DBE), mode select

(MODB/IPIPE1, MODA/IPIPE0), E clock, size (LSTRB), read/write

(R/W), IRQ, and XIRQ. When the associated pin is not used for one

of these specific functions, the pin can be used as general-purpose

I/O. The port E assignment register (PEAR) selects the function of

each pin. DDRE determines the primary direction of each port E pin

when configured to be general-purpose I/O.

Some of these pins have software selectable pull-ups (DBE, LSTRB,

R/W, and XIRQ). A single control bit enables the pull-ups for all these

pins which are configured as inputs. IRQ always has a pull-up.

This register is not in the map in peripheral mode or expanded modes

when the EME bit is set.

Read and write anytime.

DDRB — Port B Data Direction Register $0003

Bit 7 654321Bit 0

DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0

RESET: 00000000

PORTE — Port E Register $0008

BIT 7 654321BIT 0

PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0

RESET: ————————

Alt. Pin

Function DBE or

ECLK or

CAL

MODB or

IPIPE1 or

CGMTST MODA or

IPIPE0 ECLK LSTRB or

TAGLO R/W IRQ XIRQ

4-bus

Bus Control and Input/Output

Registers

MC68HC912DG128

MOTOROLA Bus Control and Input/Output 79

This register determines the primary direction for each port E pin

configured as general-purpose I/O.

0 = Associated pin is a high-impedance input

1 = Associated pin is an output

PE[1:0] are associated with XIRQ and IRQ and cannot be configured

as outputs. These pins can be read regardless of whether the

alternate interrupt functions are enabled.

This register is not in the map in peripheral mode and expanded

modes while the EME control bit is set.

Read and write anytime.

Port E serves as general purpose I/O lines or as system and bus

control signals. The PEAR register is used to choose between the

general-purpose I/O functions and the alternate bus control functions.

When an alternate control function is selected, the associated DDRE

bits are overridden.

The reset condition of this register depends on the mode of operation

because bus control signals are needed immediately after reset in

some modes.

DDRE — Port E Data Direction Register $0009

Bit 7 654321Bit 0

DDE7 DDE6 DDE5 DDE4 DDE3 DDE2 0 0

RESET: 00000000

PEAR — Port E Assignment Register $000A

BIT 7 654321BIT 0

NDBE CGMTE PIPOE NECLK LSTRE RDWE CALE DBENE

RESET: 00000000

Normal Ex-

panded

RESET: 00101100

Special Ex-

panded

RESET: 11010000Peripheral

RESET: 10010000

Normal sin-

gle chip

RESET: 00101100

Special sin-

gle chip

5-bus

Bus Control and Input/Output

MC68HC912DG128

80 Bus Control and Input/Output MOTOROLA

In normal single-chip mode, no external bus control signals are

needed so all of port E is configured for general-purpose I/O.

In normal expanded modes, the reset vector is located in external

memory. The DBE and E clock are required for de-multiplexing

address and data but LSTRB and R/W are only needed by the system

when there are external writable resources. Therefore in normal

expanded modes, the DBE and the E clock are configured for their

alternate bus control functions and the other bits of port E are

configured for general-purpose I/O. If the normal expanded system

needs any other bus control signals, PEAR would need to be written

before any access that needed the additional signals.

In special expanded modes, DBE, IPIPE1, IPIPE0, E, LSTRB, and

R/W are configured as bus-control signals.

In special single chip modes, DBE, IPIPE1, IPIPE0, E, LSTRB, R/W,

and CALE are configured as bus-control signals.

In peripheral mode, the PEAR register is not accessible for reads or

writes. However, the CGMTE control bit is reset to one to configure

PE6 as a test output for the CGM module.

NDBE — No Data Bus Enable

Normal: write once; Special: write anytime EXCEPT the first. Read

anytime.

0 = PE7 is used for DBE, external control of data enable on

memories, or inverted E clock.

1 = PE7 is CAL function if CALE bit is set in PEAR register or

general-purpose I/O otherwise.

The NDBE bit has no effect in Single Chip or Peripheral Modes and

PE7 is defaulted to the CAL function if CALE bit is set in PEAR

CGMTE — Clock Generator Module Testing Enable

Normal: write never; Special: write anytime EXCEPT the first time.

Read anytime.

0 = PE6 is general-purpose I/O or pipe output.

1 = PE6 is a test signal output from the CGM module (no effect in

single chip or normal expanded modes). PIPOE = 1 overrides

this function and forces PE6 to be a pipe status output signal.

6-bus

Bus Control and Input/Output

Registers

MC68HC912DG128

MOTOROLA Bus Control and Input/Output 81

7-bus

PIPOE — Pipe Status Signal Output Enable

Normal: write once; Special: write anytime EXCEPT the first time.

Read anytime.

0 = PE[6:5] are general-purpose I/O (if CGMTE = 1, PE6 is a test

output signal from the CGM module).

1 = PE[6:5] are outputs and indicate the state of the instruction

queue (only effective in expanded modes).

NECLK — No External E Clock

Normal single chip: write once; special single chip: write anytime; all

other modes: write never.

Read anytime. In peripheral mode, E is an input and in all other

modes, E is an output.

0 = PE4 is the external E-clock pin subject to the following

limitation: In single-chip modes, to get an E clock output signal,

it is necessary to have ESTR = 0 in addition to NECLK = 0. A

16-bit write to PEAR and MODE registers can configure all

three bits in one operation.

1 = PE4 is a general-purpose I/O pin.

LSTRE — Low Strobe (LSTRB) Enable

Normal: write once; Special: write anytime EXCEPT the first time.

Read anytime. This bit has no effect in single-chip modes or normal

expanded narrow mode.

0 = PE3 is a general-purpose I/O pin.

1 = PE3 is configured as the LSTRB bus-control output, provided

the MCU is not in single chip or normal expanded narrow

modes.

LSTRB is used during external writes. After reset in normal expanded

mode, LSTRB is disabled. If needed, it should be enabled before

external writes. External reads do not normally need LSTRB because

all 16 data bits can be driven even if the MCU only needs 8 bits of

data.

TAGLO is a shared function of the PE3/LSTRB pin. In special

expanded modes with LSTRE set and the BDM tagging on, a zero at

the falling edge of E tags the instruction word low byte being read into

the instruction queue.

Bus Control and Input/Output

MC68HC912DG128

82 Bus Control and Input/Output MOTOROLA

RDWE — Read/Write Enable

Normal: write once; Special: write anytime EXCEPT the first time.

Read anytime. This bit has no effect in single-chip modes.

0 = PE2 is a general-purpose I/O pin.

1 = PE2 is configured as the R/W pin. In single chip modes, RDWE

has no effect and PE2 is a general-purpose I/O pin.

R/W is used for external writes. After reset in normal expanded mode,

it is disabled. If needed it should be enabled before any external

writes.

CALE — Calibration Reference Enable

Read and write anytime.

0 = Calibration reference is disabled and PE7 is general purpose

I/O in single chip or peripheral modes or if NDBE bit is set.

1 = Calibration reference is enabled on PE7 in single chip and

peripheral modes or if NDBE bit is set.

DBENE — DBE or Inverted E Clock on PE7

Normal modes: write once. Special modes: write anytime EXCEPT

the first time. Read anytime.

DBENE controls which signal is output on PE7 when NDBE control bit

is cleared. The inverted E clock output can be used to latch the

address for de-multiplexing. It has the same behavior as the E clock,

except it is inverted. Please note that in the case of idle expansion

bus, the ‘not E clock’ signal could stay high for many cycles.

The DBENE bit has no effect in Single Chip or Peripheral Modes and

PE7 is defaulted to the CAL function if CALE bit is set in PEAR

0 = PE7 pin used for DBE external control of data enable on

memories in expanded modes when NDBE = 0

1 = PE7 pin used for inverted E clock output in expanded modes

when NDBE = 0

8-bus

Bus Control and Input/Output

Registers

MC68HC912DG128

MOTOROLA Bus Control and Input/Output 83

9-bus

These bits select pull-up resistors for any pin in the corresponding

port that is currently configured as an input. This register is not in the

map in peripheral mode.

Read and write anytime.

PUPK — Pull-Up Port K Enable

0 = Port K pull-ups are disabled.

1 = Enable pull-up devices for all port K input pins.

PUPJ — Pull-Up or Pull-Down Port J Enable

0 = Port J resistive loads (pull-ups or pull-downs) are disabled.

1 = Enable resistive load devices (pull-ups or pull-downs) for all

port J input pins.

PUPH — Pull-Up or Pull-Down Port H Enable

0 = Port H resistive loads (pull-ups or pull-downs) are disabled.

1 = Enable resistive load devices (pull-ups or pull-downs) for all

port H input pins.

PUPE — Pull-Up Port E Enable

0 = Port E pull-ups on PE7, PE3, PE2, and PE0 are disabled.

1 = Enable pull-up devices for port E input pins PE7, PE3, PE2, and

PE0.

When this bit is set port E input pins 7, 3, 2, & 0 have an active pull-up

device. Port E pin 1 has a resistor that is active at all times.

PUPB — Pull-Up Port B Enable

0 = Port B pull-ups are disabled.

1 = Enable pull-up devices for all port B input pins.

PUPA — Pull-Up Port A Enable

0 = Port A pull-ups are disabled.

1 = Enable pull-up devices for all port A input pins.

PUCR — Pull-Up Control Register $000C

Bit 7 654321Bit 0

PUPK PUPJ PUPH PUPE 0 0 PUPB PUPA

RESET: 00010000

Bus Control and Input/Output

MC68HC912DG128

84 Bus Control and Input/Output MOTOROLA

These bits select reduced drive for the associated port pins. This

gives reduced power consumption and reduced RFI with a slight

increase in transition time (depending on loading). The reduced drive

function is independent of which function is being used on a particular

port.

This register is not in the map in peripheral mode.

Normal: write once; Special: write anytime EXCEPT the first time.

Read anytime.

RDPK — Reduced Drive of Port K

0 = All port K output pins have full drive enabled.

1 = All port K output pins have reduced drive capability.

RDPJ — Reduced Drive of Port J

0 = All port J output pins have full drive enabled.

1 = All port J output pins have reduced drive capability.

RDPH — Reduced Drive of Port H

0 = All port H output pins have full drive enabled.

1 = All port H output pins have reduced drive capability.

RDPE — Reduced Drive of Port E

0 = All port E output pins have full drive enabled.

1 = All port E output pins have reduced drive capability.

RDPB — Reduced Drive of Port B

0 = All port B output pins have full drive enabled.

1 = All port B output pins have reduced drive capability.

RDPA — Reduced Drive of Port A

0 = All port A output pins have full drive enabled.

1 = All port A output pins have reduced drive capability.

RDRIV — Reduced Drive of I/O Lines $000D

Bit 7 654321Bit 0

RDPK RDPJ RDPH RDPE 0 0 RDPB RDPA

RESET: 00000000

10-bus

MC68HC912DG128

MOTOROLA Flash EEPROM 85

Flash EEPROM

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85

Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Flash EEPROM Control Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Flash EEPROM Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Flash EEPROM Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87

Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .91

Programming the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . .94

Erasing the Flash EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97

Program/Erase Protection Interlocks . . . . . . . . . . . . . . . . . . . . . . . . .99

Stop or Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .99

Test Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .100

Introduction

The four Flash EEPROM array modules 00FEE32K, 01FEE32K,

10FEE32K and 11FEE32K for the MC68HC912DG128 serve as

electrically erasable and programmable, non-volatile ROM emulation

memory. The modules can be used for program code that must either

execute at high speed or is frequently executed, such as operating

system kernels and standard subroutines, or they can be used for static

data which is read frequently. The Flash EEPROM modules are ideal for

program storage for single-chip applications allowing for field

reprogramming.

1-ﬂash

Flash EEPROM

MC68HC912DG128

86 Flash EEPROM MOTOROLA

Overview

Each 32K Flash EEPROM array is arranged in a 16-bit configuration and

may be read as either bytes, aligned words or misaligned words. Access

time is one bus cycle for byte and aligned word access and two bus

cycles for misaligned word operations.

Each Flash EEPROM module requires an external program/erase

voltage (VFP) to program or erase the Flash EEPROM array. The

external program/erase voltage is provided to the Flash EEPROM

module via an external VFP pin. To prevent damage to the flash array,

VFP should always be greater than or equal to VDD−0.5V. Programming

is by byte or aligned word. The Flash EEPROM module supports bulk

erase only.

Each Flash EEPROM module has hardware interlocks which protect

stored data from accidental corruption. An erase- and

program-protected 8-Kbyte block for boot routines is located at the top

of each 32-Kbyte array. Since boot programs must be available at all

times, the only useful boot block is at $E000–$FFFF location. All paged

boot blocks can be used as protected program space if desired.

Flash EEPROM Control Block

A 4-byte register block for each module controls the Flash EEPROM

operation. Configuration information is specified and programmed

independently from the contents of the Flash EEPROM array. At reset,

the 4-byte register section starts at address $00F4 and points to the

00FEE32K register block.

Flash EEPROM Arrays

After reset, a fixed 32K Flash EEPROM array, 11FEE32K, is located

from addresses $4000 to $7FFF and from $C000 to $FFFF. The other

three 32K Flash EEPROM arrays 00FEE32K, 01FEE32K and

2--ﬂash

Flash EEPROM

Flash EEPROM Registers

MC68HC912DG128

MOTOROLA Flash EEPROM 87

10FEE32K, are mapped through a 16K byte program page window

located from addresses $8000 to $BFFF. The page window has eight

16K byte pages. The last two pages also map the physical location of the

fixed 32K Flash EEPROM array 11FEE32K. In expanded modes, the

Flash EEPROM arrays are turned off. See Operating Modes.

Flash EEPROM Registers

Each 32K byte Flash EEPROM module has a set of registers. The

Each register page of four bytes maps the register space for each Flash

module and each page is selected by the PPAGE register. See

Resource Mapping

In normal modes the LOCK bit can only be written once after reset.

LOCK — Lock Register Bit

0 = Enable write to FEEMCR register

1 = Disable write to FEEMCR register

This register controls the operation of the Flash EEPROM array.

BOOTP cannot be changed when the LOCK control bit in the

FEELCK register is set or if ENPE in the FEECTL register is set.

FEELCK — Flash EEPROM Lock Control Register $00F4

Bit 7 6 5 4 3 2 1 Bit 0

0 0 0 0 0 0 0 LOCK

RESET: 0 0 0 0 0 0 0 0

FEEMCR — Flash EEPROM Module Configuration Register $00F5

Bit 7 6 5 4 3 2 1 Bit 0

0 0 0 0 0 0 0 BOOTP

RESET: 0 0 0 0 0 0 0 1

3-ﬂash

Flash EEPROM

MC68HC912DG128

88 Flash EEPROM MOTOROLA

BOOTP — Boot Protect

The boot blocks are located at $E000–$FFFF and $A000–$BFFF for

odd program pages for each Flash EEPROM module. Since boot

programs must be available at all times, the only useful boot block is

at $E000–$FFFF location. All paged boot blocks can be used as

protected program space if desired.

0 = Enable erase and program of 8K byte boot block

1 = Disable erase and program of 8K byte boot block

In normal mode, writes to FEETST control bits have no effect and always

read zero. The Flash EEPROM module cannot be placed in test mode

inadvertently during normal operation.

FSTE — Stress Test Enable

0 = Disables the gate/drain stress circuitry

1 = Enables the gate/drain stress circuitry

GADR — Gate/Drain Stress Test Select

0 = Selects the drain stress circuitry

1 = Selects the gate stress circuitry

HVT — Stress Test High Voltage Status

0 = High voltage not present during stress test

1 = High voltage present during stress test

FENLV — Enable Low Voltage

0 = Disables low voltage transistor in current reference circuit

1 = Enables low voltage transistor in current reference circuit

FEETST — Flash EEPROM Module Test Register $00F6

Bit 7 6 5 4 3 2 1 Bit 0

FSTE GADR HVT FENLV FDISVFP VTCK STRE MWPR

RESET: 0 0 0 0 0 0 0 0

4-ﬂash

Flash EEPROM

Flash EEPROM Registers

MC68HC912DG128

MOTOROLA Flash EEPROM 89

FDISVFP — Disable Status VFP Voltage Lock

When the VFP pin is below normal programming voltage the Flash

module will not allow writing to the LAT bit; the user cannot erase or

program the Flash module. The FDISVFP control bit enables writing

to the LAT bit regardless of the voltage on the VFP pin.

0 = Enable the automatic lock mechanism if VFP is low

1 = Disable the automatic lock mechanism if VFP is low

VTCK — VT Check Test Enable

When VTCK is set, the Flash EEPROM module uses the VFP pin to

control the control gate voltage; the sense amp time-out path is

disabled. This allows for indirect measurements of the bit cells

program and erase threshold. If VFP < VZBRK (breakdown voltage) the

control gate will equal the VFP voltage.

If VFP > VZBRK the control gate will be regulated by the following

equation: Vcontrol gate = VZBRK + 0.44 × (VFP − VZBRK)

0 = VT test disable

1 = VT test enable

STRE — Spare Test Row Enable

The spare test row consists of one Flash EEPROM array row. The

reserved word at location 31 contains production test information

which must be maintained through several erase cycles. When STRE

is set, the decoding for the spare test row overrides the address lines

which normally select the other rows in the array.

0 = LIB accesses are to the Flash EEPROM array

1 = Spare test row in array enabled if SMOD is active

MWPR — Multiple Word Programming

Used primarily for testing, if MWPR = 1, the two least-significant

address lines ADDR[1:0] will be ignored when programming a Flash

EEPROM location. The word location addressed if ADDR[1:0] = 00,

along with the word location addressed if ADDR[1:0] = 10, will both be

programmed with the same word data from the programming latches.

This bit should not be changed during programming.

0 = Multiple word programming disabled

1 = Program 32 bits of data

5-ﬂash

Flash EEPROM

MC68HC912DG128

90 Flash EEPROM MOTOROLA

This register controls the programming and erasure of the Flash

EEPROM.

FEESWAI — Flash EEPROM Stop in Wait Control

0 = Do not halt Flash EEPROM clock when the part is in wait mode.

1 = Halt Flash EEPROM clock when the part is in wait mode.

SVFP — Status VFP Voltage

SVFP is a read only bit.

0 = Voltage of VFP pin is below normal programming voltage levels

1 = Voltage of VFP pin is above normal programming voltage levels

ERAS — Erase Control

This bit can be read anytime or written when ENPE = 0. When set, all

locations in the array will be erased at the same time. The boot block

will be erased only if BOOTP = 0. This bit also affects the result of

attempted array reads. See Table 17 for more information. Status of

ERAS cannot change if ENPE is set.

0 = Flash EEPROM configured for programming

1 = Flash EEPROM configured for erasure

LAT — Latch Control

This bit can be read anytime or written when ENPE = 0. When set, the

Flash EEPROM is configured for programming or erasure and, upon

the next valid write to the array, the address and data will be latched

for the programming sequence. See Table 17 for the effects of LAT

on array reads. A high voltage detect circuit on the VFP pin will prevent

assertion of the LAT bit when the programming voltage is at normal

levels.

0 = Programming latches disabled

1 = Programming latches enabled

FEECTL — Flash EEPROM Control Register $00F7

Bit 7 6 5 4 3 2 1 Bit 0

0 0 0 FEESWAI SVFP ERAS LAT ENPE

RESET: 0 0 0 0 0 0 0 0

6-ﬂash

Flash EEPROM

Operation

MC68HC912DG128

MOTOROLA Flash EEPROM 91

7-ﬂash

ENPE — Enable Programming/Erase

0 = Disables program/erase voltage to Flash EEPROM

1 = Applies program/erase voltage to Flash EEPROM

ENPE can be asserted only after LAT has been asserted and a write

to the data and address latches has occurred. If an attempt is made

to assert ENPE when LAT is negated, or if the latches have not been

written to after LAT was asserted, ENPE will remain negated after the

write cycle is complete.

The LAT, ERAS and BOOTP bits cannot be changed when ENPE is

asserted. A write to FEECTL may only affect the state of ENPE.

Attempts to read a Flash EEPROM array location in the Flash

EEPROM module while ENPE is asserted will not return the data

addressed. See Table 17 for more information.

Flash EEPROM module control registers may be read or written while

ENPE is asserted. If ENPE is asserted and LAT is negated on the

same write access, no programming or erasure will be performed.

Operation

The Flash EEPROM can contain program and data. On reset, it can

operate as a bootstrap memory to provide the CPU with internal

initialization information during the reset sequence.

Bootstrap

Operation

Single-Chip Mode

After reset, the CPU controlling the system will begin booting up by

fetching the first program address from address $FFFE.

Table 17 Effects of ENPE, LAT and ERAS on Array Reads

ENPE LAT ERAS Result of Read

0 0 – Normal read of location addressed

0 1 0 Read of location being programmed

0 1 1 Normal read of location addressed

1 – – Read cycle is ignored

Flash EEPROM

MC68HC912DG128

92 Flash EEPROM MOTOROLA

Normal Operation The Flash EEPROM allows a byte or aligned word read/write in one bus

cycle. Misaligned word read/write require an additional bus cycle. The

Flash EEPROM array responds to read operations only. Write

operations are ignored.

Program/Erase

Operation

An unprogrammed Flash EEPROM bit has a logic state of one. A bit

must be programmed to change its state from one to zero. Erasing a bit

returns it to a logic one. The Flash EEPROM has a minimum

program/erase life of 100 cycles. Programming or erasing the Flash

EEPROM is accomplished by a series of control register writes and a

write to a set of programming latches.

Programming is restricted to a single byte or aligned word at a time as

determined by internal signal SZ8 and ADDR[0]. The Flash EEPROM

must first be completely erased prior to programming final data values.

It is possible to program a location in the Flash EEPROM without erasing

the entire array if the new value does not require the changing of bit

values from zero to one.

Read/Write Accesses During Program/Erase — During program or

erase operations, read and write accesses may be different from those

during normal operation and are affected by the state of the control bits

in the Flash EEPROM control register (FEECTL). The next write to any

valid address to the array after LAT is set will cause the address and

data to be latched into the programming latches. Once the address and

data are latched, write accesses to the array will be ignored while LAT is

set. Writes to the control registers will occur normally.

Program/Erase Verification — When programming or erasing the

Flash EEPROM array, a special verification method is required to ensure

that the program/erase process is reliable, and also to provide the

longest possible life expectancy. This method requires stopping the

program/erase sequence at periods of tPPULSE (tEPULSE for erasing) to

determine if the Flash EEPROM is programmed/erased. After the

location reaches the proper value, it must continue to be

programmed/erased with additional margin pulses to ensure that it will

remain programmed/erased. Failure to provide the margin pulses could

lead to corrupted or unreliable data.

8-ﬂash

Flash EEPROM

Operation

MC68HC912DG128

MOTOROLA Flash EEPROM 93

9-ﬂash

Program/Erase Sequence — To begin a program or erase sequence

the external VFP voltage must be applied and stabilized. The ERAS bit

must be set or cleared, depending on whether a program sequence or

an erase sequence is to occur. The LAT bit will be set to cause any

subsequent data written to a valid address within the Flash EEPROM to

be latched into the programming address and data latches. The next

Flash array write cycle must be either to the location that is to be

programmed if a programming sequence is being performed, or, if

erasing, to any valid Flash EEPROM array location. Writing the new

address and data information to the Flash EEPROM is followed by

assertion of ENPE to turn on the program/erase voltage to

program/erase the new location(s). The LAT bit must be asserted and

the address and data latched to allow the setting of the ENPE control bit.

If the data and address have not been latched, an attempt to assert

ENPE will be ignored and ENPE will remain negated after the write cycle

to FEECTL is completed. The LAT bit must remain asserted and the

ERAS bit must remain in its current state as long as ENPE is asserted.

A write to the LAT bit to clear it while ENPE is set will be ignored. That

is, after the write cycle, LAT will remain asserted. Likewise, an attempt

to change the state of ERAS will be ignored and the state of the ERAS

bit will remain unchanged.

The programming software is responsible for all timing during a program

sequence. This includes the total number of program pulses (nPP), the

length of the program pulse (tPPULSE), the program margin pulses (pm)

and the delay between turning off the high voltage and verifying the

operation (tVPROG).

The erase software is responsible for all timing during an erase

sequence. This includes the total number of erase pulses (em), the

length of the erase pulse (tEPULSE), the erase margin pulse or pulses,

and the delay between turning off the high voltage and verifying the

operation (tVERASE).

Software also controls the supply of the proper program/erase voltage to

the VFP pin, and should be at the proper level before ENPE is set during

a program/erase sequence.

A program/erase cycle should not be in progress when starting another

program/erase, or while attempting to read from the array.

Flash EEPROM

MC68HC912DG128

94 Flash EEPROM MOTOROLA

NOTE:

Although clearing ENPE disables the program/erase voltage (V

) from

the V

pin to the array, care must be taken to ensure that V

is at V

whenever programming/erasing is not in progress. Not doing so could

damage the part. Ensuring that V

is always greater or equal to V

can be accomplished by controlling the V

power supply with the

programming software via an output pin. Alternatively, all programming

and erasing can be done prior to installing the device on an application

circuit board which can always connect V

to V

. Programming can

also be accomplished by plugging the board into a special programming

fixture which provides program/erase voltage to the V

pin.

Programming the Flash EEPROM

Programming the Flash EEPROM is accomplished by the following

sequence. The VFP pin voltage must be at the proper level prior to

executing step 4 the first time.

1. Apply program/erase voltage to the VFP pin.

2. Set the PPAGE to point to the 16K Flash window to be

programmed and corresponding register block. Clear ERAS and

set the LAT bit in the FEECTL register to establish program mode

and enable programming address and data latches.

3. Write data to a valid address. The address and data is latched. If

BOOTP is asserted, an attempt to program an address in the boot

block will be ignored.

4. Apply programming voltage by setting ENPE.

5. Delay for one programming pulse (tPPULSE).

6. Remove programming voltage by clearing ENPE.

7. Delay while high voltage is turning off (tVPROG).

8. Read the address location to verify that it has been programmed

9. If the location is not programmed, repeat steps 4 through 7 until

the location is programmed or until the specified maximum

number of program pulses has been reached (nPP)

10. If the location is programmed, repeat the same number of pulses

as required to program the location. This provides 100% program

margin.

10-ﬂash

Flash EEPROM

Programming the Flash EEPROM

MC68HC912DG128

MOTOROLA Flash EEPROM 95

11-ﬂash

11. Read the address location to verify that it remains programmed.

12. Clear LAT.

13. If there are more locations to program, repeat steps 2 through 10.

14. Turn off VFP (reduce voltage on VFP pin to VDD).

The flowchart in Figure 10 demonstrates the recommended

programming sequence.

Flash EEPROM

MC68HC912DG128

96 Flash EEPROM MOTOROLA

Figure 10 Program Sequence Flow

START PROG

WRITE DATA

TO ADDRESS

SET ENPE

READ

GET NEXT

ADDRESS/DATA

LOCATION FAILED

LOCATION

CLEAR MARGIN FLAG

INCREMENT

nPP COUNTER

DECREMENT

nPP COUNTER

YES

TO PROGRAM

TURN ON VFP

DELAY FOR DURATION

OF PROGRAM PULSE

(tPPULSE)

CLEAR ENPE

DELAY BEFORE VERIFY

MARGIN FLAG

SET? NO

YES

DATA

CORRECT?

SET

MARGIN FLAG

DATA

CORRECT?

nPP = 0?

DONE?

TURN OFF VFP

(tVPROG)

nPP = 50?

YES

DONE PROG

CLEAR PROGRAM PULSE COUNTER (nPP)

CLEAR LAT

WRITE PPAGE

CLEAR ERAS

SET LAT

12-ﬂash

Flash EEPROM

Erasing the Flash EEPROM

MC68HC912DG128

MOTOROLA Flash EEPROM 97

13-ﬂash

Erasing the Flash EEPROM

The following sequence demonstrates the recommended procedure for

erasing any of the Flash EEPROM array. The VFP pin voltage must be

at the proper level prior to executing step 4 the first time.

1. Turn on VFP (apply program/erase voltage to the VFP pin).

2. Set the PPAGE register to point to the 32K Flash array to be

erased. Set the LAT bit and ERAS bit to configure the Flash

EEPROM for erasing.

3. Write to any valid address in the 32K Flash array. This allows the

erase voltage to be turned on; the data written and the address

written are not important. The boot block will be erased only if the

control bit BOOTP is negated.

4. Apply erase voltage by setting ENPE.

5. Delay for a single erase pulse (tEPULSE).

6. Remove erase voltage by clearing ENPE.

7. Delay while high voltage is turning off (tVERASE).

8. Read the entire array to ensure that the Flash EEPROM is erased.

9. If all of the Flash EEPROM locations are not erased, repeat steps

4 through 7 until either the remaining locations are erased, or until

the maximum erase pulses have been applied (nEP)

10. If all of the Flash EEPROM locations are erased, repeat the same

number of pulses as required to erase the array. This provides

100% erase margin.

11. Read the entire array to ensure that the Flash EEPROM is erased.

12. Clear LAT.

13. Turn off VFP (reduce voltage on VFP pin to VDD).

The flowchart in Figure 11 demonstrates the recommended erase

sequence.

Flash EEPROM

MC68HC912DG128

98 Flash EEPROM MOTOROLA

Figure 11 Erase Sequence Flow

START ERASE

WRITE PPAGE

WRITE TO ARRAY

SET ENPE

READ

ARRAY FAILED TO ERASE

ARRAY

CLEAR MARGIN FLAG

INCREMENT

nEP COUNTER

DECREMENT

nEP COUNTER

YES

TURN ON VFP

DELAY FOR DURATION

OF ERASE PULSE

(tEPULSE)

CLEAR ENPE

DELAY BEFORE VERIFY

MARGIN FLAG

SET? NO

YES

ARRAY

ERASED?

SET

MARGIN FLAG

nEP = 0?

TURN OFF VFP

(tVERASE)

nEP = 5?

YES

ARRAY ERASED

CLEAR ERASE PULSE COUNTER (nEP)

CLEAR LAT

ARRAY

ERASED?

SET ERAS

SET LAT

14-ﬂash

Flash EEPROM

Program/Erase Protection Interlocks

MC68HC912DG128

MOTOROLA Flash EEPROM 99

15-ﬂash

Program/Erase Protection Interlocks

The Flash EEPROM program and erase mechanisms provide maximum

protection from accidental programming or erasure.

The voltage required to program/erase the Flash EEPROM (VFP) is

supplied via an external pin. If VFP is not present, no

programming/erasing will occur. Furthermore, the program/erase

voltage will not be applied to the Flash EEPROM unless turned on by

setting a control bit (ENPE). The ENPE bit may not be set unless the

programming address and data latches have been written previously

with a valid address. The latches may not be written unless enabled by

setting a control bit (LAT). The LAT and ENPE control bits must be

written on separate writes to the control register (FEECTL) and must be

separated by a write to the programming latches. The ERAS and LAT

bits are also protected when ENPE is set. This prevents inadvertent

switching between erase/program mode and also prevents the latched

data and address from being changed after a program cycle has been

initiated.

Stop or Wait Mode

When stop or wait commands are executed, the MCU puts the Flash

EEPROM in stop or wait mode. In these modes the Flash module will

cease erasure or programming immediately. It is advised not to enter

stop or wait modes when programming the Flash array.

CAUTION:

The Flash EEPROM module requires a 250nsec delay for wake-up from

STOP mode. If the operating bus frequency is greater than 4MHz, the

Flash can not be used when recovering from STOP mode when the DLY

bit in INTCR register is cleared.

Flash EEPROM

MC68HC912DG128

100 Flash EEPROM MOTOROLA

Test Mode

The Flash EEPROM has some special test functions which are only

accessible when the device is in test mode. Test mode is indicated to the

Flash EEPROM module when the SMOD line on the LIB is asserted.

When SMOD is asserted, the special test control bits may be accessed

via the LIB to invoke the special test functions in the Flash EEPROM

module. When SMOD is not asserted, writes to the test control bits have

no effect and all bits in the test register FEETST will be cleared. This

ensures that Flash EEPROM test mode cannot be invoked inadvertently

during normal operation.

Note that the Flash EEPROM module will operate normally, even if

SMOD is asserted, until a special test function is invoked. The test mode

adds additional features over normal mode which allow the tests to be

performed even after the device is installed in the final product.

16-ﬂash

MC68HC912DG128

MOTOROLA EEPROM 101

EEPROM

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101

EEPROM Programmer’s Model . . . . . . . . . . . . . . . . . . . . . . . . . . . .102

EEPROM Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103

Introduction

The MC68HC912DG128 EEPROM nonvolatile memory is arranged in a

16-bit configuration. The EEPROM array may be read as either bytes,

aligned words or misaligned words. Access times is one bus cycle for

byte and aligned word access and two bus cycles for misaligned word

operations.

Programming is by byte or aligned word. Attempts to program or erase

misaligned words will fail. Only the lower byte will be latched and

programmed or erased. Programming and erasing of the user EEPROM

can be done in all modes.

Each EEPROM byte or aligned word must be erased before

programming. The EEPROM module supports byte, aligned word, row

(32 bytes) or bulk erase, all using the internal charge pump. Bulk erasure

of odd and even rows is also possible in test modes; the erased state is

$FF. The EEPROM module has hardware interlocks which protect

stored data from corruption by accidentally enabling the program/erase

voltage. Programming voltage is derived from the internal VDD supply

with an internal charge pump.

1-eeprom

EEPROM

MC68HC912DG128

102 EEPROM MOTOROLA

EEPROM ProgrammerÕs Model

The EEPROM module consists of two separately addressable sections.

The first is a four-byte memory mapped control register block used for

control, testing and configuration of the EEPROM array. The second

section is the EEPROM array itself.

At reset, the four-byte register section starts at address $00F0 and the

EEPROM array is located from addresses $0800 to $0FFF. For

information on re-mapping the register block and EEPROM address

space, refer to Operating Modes.

Read/write access to the memory array section can be enabled or

disabled by the EEON control bit in the INITEE register. This feature

allows the access of memory mapped resources that have lower priority

than the EEPROM memory array. EEPROM control registers can be

accessed and EEPROM locations may be programmed or erased

regardless of the state of EEON.

It is required to discontinue program/erase operations during WAIT. For

lowest power consumption during WAIT, stop program/erase by turning

off EEPGM.

If the STOP mode is entered during programming or erasing,

program/erase voltage will be automatically turned off and the RC clock

(if enabled) is stopped. However, the EEPGM control bit will remain set.

When STOP mode is terminated, the program/erase voltage will be

automatically turned back on if EEPGM is set.

At low bus frequencies, the RC clock must be turned on for

program/erase.

The EEPROM module contains an extra byte called SHADOW byte

which is loaded at reset into the EEMCR register.

To program the SHADOW byte, when in special modes (SMODN=0),

the NOSHB bit in EEMCR register must be cleared. Normal

programming routines are used to program the SHADOW byte which

becomes accessible at address $0FC0 when NOSHB is cleared.

At the next reset the SHADOW byte data is loaded into the EEMCR.

The SHADOW byte can be protected from being programmed or erased

by setting the SHPROT bit of EEPROT register.

2--eeprom

EEPROM

EEPROM Control Registers

MC68HC912DG128

MOTOROLA EEPROM 103

EEPROM Control Registers

1. Bits 4 and 5 have test functions and should not be programmed.

2. Loaded from SHADOW byte.

Bits[7:4] are loaded at reset from the EEPROM SHADOW byte.

NOTE:

The bits 5 and 4 are reserved for test purposes. These locations in

SHADOW byte should not be programmed otherwise some locations of

regular EEPROM array will be no more visible.

NOBDML — Background Debug Mode Lockout Disable

0 = The BDM lockout is enabled.

1 = The BDM lockout is disabled.

Loaded from SHADOW byte at reset.

Read anytime. Write anytime in special modes (SMODN=0).

NOSHB — SHADOW Byte Disable

0 = The SHADOW byte enabled and accessible at address $0FC0.

1 = Regular EEPROM array at address $0FC0.

Loaded from SHADOW byte at reset.

Read anytime. Write anytime in special modes (SMODN=0).

When NOSHB cleared, the regular EEPROM array byte at address

$0FC0 is no more visible. The SHADOW byte is accessed instead for

both read and program/erase operations. BULK, ODD and EVEN

program/erase only applies if SHADOW byte is enabled.

NOTE:

The bit 6 in SHADOW byte should not be programmed in order to have

the full EEPROM array visible.

EESWAI — EEPROM Stops in Wait Mode

0 = The module is not affected during WAIT mode

1 = The module ceases to be clocked during WAIT mode

Read and write anytime.

NOTE:

The EESWAI bit should be cleared if the WAIT mode vectors are

mapped in the EEPROM array.

EEMCR — EEPROM Module Configuration $00F0

Bit 7 654321Bit 0

NOBDML NOSHB RESERVED(1) 1 EESWAI PROTLCK EERC

RESET: —(2) —(2) —(2) —(2) 1100

3-eeprom

EEPROM

MC68HC912DG128

104 EEPROM MOTOROLA

PROTLCK — Block Protect Write Lock

0 = Block protect bits and bulk erase protection bit can be written

1 = Block protect bits are locked

Read anytime. Write once in normal modes (SMODN = 1), set and

clear any time in special modes (SMODN = 0).

EERC — EEPROM Charge Pump Clock

0 = System clock is used as clock source for the internal charge

pump. Internal RC oscillator is stopped.

1 = Internal RC oscillator drives the charge pump. The RC oscillator

is required when the system bus clock is lower than fPROG.

Read and write anytime.

Prevents accidental writes to EEPROM. Read anytime. Write anytime if

EEPGM = 0 and PROTLCK = 0.

SHPROT — SHADOW Byte Protection

0 = The SHADOW byte can be programmed and erased.

1 = The SHADOW byte is protected from being programmed and

erased.

BPROT[5:0] — EEPROM Block Protection

0 = Associated EEPROM block can be programmed and erased.

1 = Associated EEPROM block is protected from being

programmed and erased.

EEPROT — EEPROM Block Protect $00F1

Bit 7 654321Bit 0

SHPROT 1 BPROT5 BPROT4 BPROT3 BPROT2 BPROT1 BPROT0

RESET: 11111111

Table 18 2K byte EEPROM Block Protection

Bit Name Block Protected Block Size

BPROT5 $0800 to $0BFF 1024 Bytes

BPROT4 $0C00 to $0DFF 512 Bytes

BPROT3 $0E00 to $0EFF 256 Bytes

BPROT2 $0F00 to $0F7F 128 Bytes

BPROT1 $0F80 to $0FBF 64 Bytes

BPROT0 $0FC0 to $0FFF 64 Bytes

4-eeprom

EEPROM

EEPROM Control Registers

MC68HC912DG128

MOTOROLA EEPROM 105

Read anytime. Write in special modes only (SMODN = 0). These bits are

used for test purposes only. In normal modes the bits are forced to zero.

EEODD — Odd Row Programming

0 = Odd row bulk programming/erasing is disabled.

1 = Bulk program/erase all odd rows.

EEVEN — Even Row Programming

0 = Even row bulk programming/erasing is disabled.

1 = Bulk program/erase all even rows.

MARG — Program and Erase Voltage Margin Test Enable

0 = Normal operation.

1 = Program and Erase Margin test.

This bit is used to evaluate the program/erase voltage margin.

EECPD — Charge Pump Disable

0 = Charge pump is turned on during program/erase.

1 = Disable charge pump.

EECPRD — Charge Pump Ramp Disable

Known to enhance write/erase endurance of EEPROM cells.

0 = Charge pump is turned on progressively during program/erase.

1 = Disable charge pump controlled ramp up.

EECPM — Charge Pump Monitor Enable

0 = Normal operation.

1 = Output the charge pump voltage on the IRQ/VPP pin.

EETST — EEPROM Test $00F2

Bit 7 654321Bit 0

EEODD EEVEN MARG EECPD EECPRD 0 EECPM 0

RESET: 00000000

5-eeprom

EEPROM

MC68HC912DG128

106 EEPROM MOTOROLA

BULKP — Bulk Erase Protection

0 = EEPROM can be bulk erased.

1 = EEPROM is protected from being bulk or row erased.

Read anytime. Write anytime if EEPGM = 0 and PROTLCK = 0.

BYTE — Byte and Aligned Word Erase

0 = Bulk or row erase is enabled.

1 = One byte or one aligned word erase only.

Read anytime. Write anytime if EEPGM = 0.

ROW — Row or Bulk Erase (when BYTE = 0)

0 = Erase entire EEPROM array.

1 = Erase only one 32-byte row.

Read anytime. Write anytime if EEPGM = 0.

BYTE and ROW have no effect when ERASE = 0

If BYTE = 1 and test mode is not enabled, only the location specified

by the address written to the programming latches will be erased. The

operation will be a byte or an aligned word erase depending on the

size of written data.

ERASE — Erase Control

0 = EEPROM configuration for programming.

1 = EEPROM configuration for erasure.

Read anytime. Write anytime if EEPGM = 0.

Configures the EEPROM for erasure or programming.

When test mode is not enabled and unless BULKP is set, erasure is

by byte, aligned word, row or bulk.

EEPROG — EEPROM Control $00F3

Bit 7 654321Bit 0

BULKP 0 0 BYTE ROW ERASE EELAT EEPGM

RESET: 10000000

Table 19 Erase Selection

BYTE ROW Block size

0 0 Bulk erase entire EEPROM array

0 1 Row erase 32 bytes

1 0 Byte or aligned word erase

1 1 Byte or aligned word erase

6-eeprom

EEPROM

EEPROM Control Registers

MC68HC912DG128

MOTOROLA EEPROM 107

7-eeprom

EELAT — EEPROM Latch Control

0 = EEPROM set up for normal reads.

1 = EEPROM address and data bus latches set up for

programming or erasing.

Read anytime. Write anytime if EEPGM = 0.

BYTE, ROW, ERASE and EELAT bits can be written simultaneously

or in any sequence.

EEPGM — Program and Erase Enable

0 = Disables program/erase voltage to EEPROM.

1 = Applies program/erase voltage to EEPROM.

The EEPGM bit can be set only after EELAT has been set. When

EELAT and EEPGM are set simultaneously, EEPGM remains clear

but EELAT is set.

The BULKP, BYTE, ROW, ERASE and EELAT bits cannot be

changed when EEPGM is set. To complete a program or erase, two

successive writes to clear EEPGM and EELAT bits are required

before reading the programmed data. A write to an EEPROM location

has no effect when EEPGM is set. Latched address and data cannot

be modified during program or erase.

A program or erase operation should follow the sequence below:

1. Write BYTE, ROW and ERASE to the desired value, write EELAT

= 1

2. Write a byte or an aligned word to an EEPROM address

3. Write EEPGM = 1

4. Wait for programming (tPROG) or erase (terase) delay time

5. Write EEPGM = 0

6. Write EELAT = 0

It is possible to program/erase more bytes or words without intermediate

EEPROM reads, by jumping from step 5 to step 2.

EEPROM

MC68HC912DG128

108 EEPROM MOTOROLA

8-eeprom

MC68HC912DG128

MOTOROLA Resets and Interrupts 109

Resets and Interrupts

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Exception Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109

Maskable interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Latching of Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110

Interrupt Control and Priority Registers. . . . . . . . . . . . . . . . . . . . . . .112

Interrupt test registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .114

Resets. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115

Effects of Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .116

Introduction

CPU12 exceptions include resets and interrupts. Each exception has an

associated 16-bit vector, which points to the memory location where the

routine that handles the exception is located. Vectors are stored in the

upper 128 bytes of the standard 64K byte address map.

The six highest vector addresses are used for resets and non-maskable

interrupt sources. The remainder of the vectors are used for maskable

interrupts, and all must be initialized to point to the address of the

appropriate service routine.

Exception Priority

A hardware priority hierarchy determines which reset or interrupt is

serviced first when simultaneous requests are made. Six sources are not

1-reset

Resets and

MC68HC912DG128

110 Resets and Interrupts MOTOROLA

maskable. The remaining sources are maskable, and any one of them

can be given priority over other maskable interrupts.

The priorities of the non-maskable sources are:

1. POR or RESET pin

2. Clock monitor reset

3. COP watchdog reset

4. Unimplemented instruction trap

5. Software interrupt instruction (SWI)

6. XIRQ signal (if X bit in CCR = 0)

Maskable interrupts

Maskable interrupt sources include on-chip peripheral systems and

external interrupt service requests. Interrupts from these sources are

recognized when the global interrupt mask bit (I) in the CCR is cleared. The

default state of the I bit out of reset is one, but it can be written at any time.

Interrupt sources are prioritized by default but any one maskable interrupt

source may be assigned the highest priority by means of the HPRIO

An interrupt that is assigned highest priority is still subject to global

masking by the I bit in the CCR, or by any associated local bits. Interrupt

vectors are not affected by priority assignment. HPRIO can only be

written while the I bit is set (interrupts inhibited). Table 20 lists interrupt

sources and vectors in default order of priority. Before masking an

interrupt by clearing the corresponding local enable bit, it is required to

set the I-bit to avoid an SWI.

Latching of Interrupts

XIRQ is always level triggered and IRQ can be selected as a level

triggered interrupt. These level triggered interrupt pins should only be

2--reset

Resets and Interrupts

Latching of Interrupts

MC68HC912DG128

MOTOROLA Resets and Interrupts 111

released during the appropriate interrupt service routine. Generally the

interrupt service routine will handshake with the interrupting logic to

release the pin. In this way, the MCU will never start the interrupt service

sequence only to determine that there is no longer an interrupt source.

In event that this does occur the trap vector will be taken.

If IRQ is selected as an edge triggered interrupt, the hold time of the level

after the active edge is independent of when the interrupt is serviced. As

long as the minimum hold time is met, the interrupt will be latched inside

the MCU. In this case the IRQ edge interrupt latch is cleared

automatically when the interrupt is serviced.

All of the remaining interrupts are latched by the MCU with a flag bit.

These interrupt flags should be cleared during an interrupt service

routine or when interrupts are masked by the I bit. By doing this, the

MCU will never get an unknown interrupt source and take the trap

vector.

Table 20 Interrupt Vector Map

Vector Address Interrupt Source CCR

Mask Local Enable HPRIO Value to

Elevate

$FFFE, $FFFF Reset None None –

$FFFC, $FFFD Clock monitor fail reset None COPCTL (CME, FCME) –

$FFFA, $FFFB COP failure reset None COP rate selected –

$FFF8, $FFF9 Unimplemented instruction trap None None –

$FFF6, $FFF7 SWI None None –

$FFF4, $FFF5 XIRQ X bit None –

$FFF2, $FFF3 IRQ I bit INTCR (IRQEN) $F2

$FFF0, $FFF1 Real time interrupt I bit RTICTL (RTIE) $F0

$FFEE, $FFEF Timer channel 0 I bit TMSK1 (C0I) $EE

$FFEC, $FFED Timer channel 1 I bit TMSK1 (C1I) $EC

$FFEA, $FFEB Timer channel 2 I bit TMSK1 (C2I) $EA

$FFE8, $FFE9 Timer channel 3 I bit TMSK1 (C3I) $E8

$FFE6, $FFE7 Timer channel 4 I bit TMSK1 (C4I) $E6

$FFE4, $FFE5 Timer channel 5 I bit TMSK1 (C5I) $E4

$FFE2, $FFE3 Timer channel 6 I bit TMSK1 (C6I) $E2

$FFE0, $FFE1 Timer channel 7 I bit TMSK1 (C7I) $E0

$FFDE, $FFDF Timer overﬂow I bit TMSK2 (TOI) $DE

$FFDC, $FFDD Pulse accumulator overﬂow I bit PACTL (PAOVI) $DC

$FFDA, $FFDB Pulse accumulator input edge I bit PACTL (PAI) $DA

$FFD8, $FFD9 SPI serial transfer complete I bit SP0CR1 (SPIE) $D8

3-reset

Resets and

MC68HC912DG128

112 Resets and Interrupts MOTOROLA

Interrupt Control and Priority Registers

IRQE — IRQ Select Edge Sensitive Only

0 = IRQ configured for low-level recognition.

1 = IRQ configured to respond only to falling edges (on pin PE1/

IRQ).

$FFD6, $FFD7 SCI 0 I bit SC0CR2

(TIE, TCIE, RIE, ILIE) $D6

$FFD4, $FFD5 SCI 1 I bit SC1CR2

(TIE, TCIE, RIE, ILIE) $D4

$FFD2, $FFD3 ATD0 or ATD1 I bit ATDxCTL2 (ASCIE) $D2

$FFD0, $FFD1 MSCAN 0 wake-up I bit C0RIER (WUPIE) $D0

$FFCE, $FFCF Key wake-up J or H I bit KWIEJ[7:0] and

KWIEH[7:0] $CE

$FFCC, $FFCD Modulus down counter underﬂow I bit MCCTL (MCZI) $CC

$FFCA, $FFCB Pulse Accumulator B Overﬂow I bit PBCTL (PBOVI) $CA

$FFC8, $FFC9 MSCAN 0 errors I bit

C0RIER (RWRNIE,

TWRNIE,

RERRIE, TERRIE,

BOFFIE, OVRIE)

$C8

$FFC6, $FFC7 MSCAN 0 receive I bit C0RIER (RXFIE) $C6

$FFC4, $FFC5 MSCAN 0 transmit I bit C0TCR (TXEIE[2:0]) $C4

$FFC2, $FFC3 CGM lock and limp home I bit PLLCR (LOCKIE, LHIE) $C2

$FFC0, $FFC1 IIC Bus I bit IBCR (IBIE) $C0

$FFBE, $FFBF MSCAN 1 wake-up I bit C1RIER (WUPIE) $BE

$FFBC, $FFBD MSCAN 1 errors I bit

C1RIER (RWRNIE,

TWRNIE,

RERRIE, TERRIE,

BOFFIE, OVRIE)

$BC

$FFBA, $FFBB MSCAN 1 receive I bit C1RIER (RXFIE) $BA

$FFB8, $FFB9 MSCAN 1 transmit I bit C1TCR (TXEIE[2:0]) $B8

$FFB6, $FFB7 Reserved I bit $B6

$FF80–$FFB5 Reserved I bit $80–$B4

INTCR — Interrupt Control Register $001E

Bit 7 654321Bit 0

IRQE IRQEN DLY 00000

RESET: 01100000

Table 20 Interrupt Vector Map

Vector Address Interrupt Source CCR

Mask Local Enable HPRIO Value to

Elevate

4-reset

Resets and Interrupts

Interrupt Control and Priority Registers

MC68HC912DG128

MOTOROLA Resets and Interrupts 113

IRQE can be read anytime and written once in normal modes. In

special modes, IRQE can be read anytime and written anytime,

except the first write is ignored.

IRQEN — External IRQ Enable

The IRQ pin has an internal pull-up.

0 = External IRQ pin is disconnected from interrupt logic.

1 = External IRQ pin is connected to interrupt logic.

IRQEN can be read and written anytime in all modes.

DLY — Enable Oscillator Start-up Delay on Exit from STOP

The delay time of about 4096 cycles is based on the X clock rate

chosen.

0 = No stabilization delay imposed on exit from STOP mode. A

stable external oscillator must be supplied.

1 = Stabilization delay is imposed before processing resumes after

STOP.

DLY can be read anytime and written once in normal modes. In

special modes, DLY can be read and written anytime.

Write only if I mask in CCR = 1 (interrupts inhibited). Read anytime.

To give a maskable interrupt source highest priority, write the low byte

of the vector address to the HPRIO register. For example, writing $F0 to

HPRIO would assign highest maskable interrupt priority to the real-time

interrupt timer ($FFF0). If an un-implemented vector address or a

non-I-masked vector address (value higher than $F2) is written, then

IRQ will be the default highest priority interrupt.

HPRIO — Highest Priority I Interrupt $001F

Bit 7 654321Bit 0

1 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL1 0

RESET: 11110010

5-reset

Resets and

MC68HC912DG128

114 Resets and Interrupts MOTOROLA

Interrupt test registers

These registers are used in special modes for testing the interrupt logic

and priority without needing to know which modules and what functions

are used to generate the interrupts.Each bit is used to force a specific

interrupt vector by writing it to 1.Bits are named with B6 through F4 to

indicate vectors $FFB6 through $FFF4. These bits are also used in

special modes to view that an interrupt caused by a module has reached

the interrupt module.

These registers can only be read in special modes (read in normal mode

will return $00). Reading these registers at the same time as the interrupt

is changing will cause an indeterminate value to be read. These

registers can only be written in special mode.

ITST0 — Interrupt Test Register 0 $0018

Bit 7 654321Bit 0

ITE6 ITE8 ITEA ITEC ITEE ITF0 ITF2 ITF4

RESET: 00000000

ITST1 — Interrupt Test Register 1 $0019

Bit 7 654321Bit 0

ITD6 ITD8 ITDA ITDC ITDE ITE0 ITE2 ITE4

RESET: 00000000

ITST2 — Interrupt Test Register 2 $001A

Bit 7 654321Bit 0

ITC6 ITC8 ITCA ITCC ITCE ITD0 ITD2 ITD4

RESET: 00000000

ITST3 — Interrupt Test Register 3 $001B

Bit 7 654321Bit 0

ITB6 ITB8 ITBA ITBC ITBE ITC0 ITC2 ITC4

RESET: 00000000

6-reset

Resets and Interrupts

Resets

MC68HC912DG128

MOTOROLA Resets and Interrupts 115

7-reset

Resets

There are four possible sources of reset. Power-on reset (POR), and

external reset on the RESET pin share the normal reset vector. The

computer operating properly (COP) reset and the clock monitor reset

each has a vector. Entry into reset is asynchronous and does not require

a clock but the MCU cannot sequence out of reset without a system

clock.

Power-On Reset A positive transition on VDD causes a power-on reset (POR). An external

voltage level detector, or other external reset circuits, are the usual

source of reset in a system. The POR circuit only initializes internal

circuitry during cold starts and cannot be used to force a reset as system

voltage drops.

It is important to use an external low voltage reset circuit (for example:

MC34064 or MC33464) to prevent power transitions or corruption of

RAM or EEPROM.

External Reset The CPU distinguishes between internal and external reset conditions

by sensing whether the reset pin rises to a logic one in less than nine

E-clock cycles after an internal device releases reset. When a reset

condition is sensed, an internal circuit drives the RESET pin low and a

clocked reset sequence controls when the MCU can begin normal

processing. In the case of a clock monitor error, a 4096 cycle oscillator

start-up delay is imposed before the reset recovery sequence starts

(reset is driven low throughout this 4096 cycle delay). The internal reset

recovery sequence then drives reset low for 16 to 17 cycles and releases

the drive to allow reset to rise. Nine E-clock cycles later the reset pin is

sampled. If the pin is still held low, the CPU assumes that an external

reset has occurred. If the pin is high, it indicates that the reset was

initiated internally by either the COP system or the clock monitor.

To prevent a COP reset from being detected during an external reset,

hold the reset pin low for at least 32 cycles. To prevent a clock monitor

reset from being detected during an external reset, hold the reset pin low

for at least 4096 + 32 cycles. An external RC power-up delay circuit on

Resets and

MC68HC912DG128

116 Resets and Interrupts MOTOROLA

the reset pin is not recommended — circuit charge time can cause the

MCU to misinterpret the type of reset that has occurred.

COP Reset The MCU includes a computer operating properly (COP) system to help

protect against software failures. When COP is enabled, software must

write $55 and $AA (in this order) to the COPRST register in order to keep

a watchdog timer from timing out. Other instructions may be executed

between these writes. A write of any value other than $55 or $AA or

software failing to execute the sequence properly causes a COP reset

to occur. In addition, windowed COP operation can be selected. In this

mode, a write to the COPRST register must occur in the last 25% of the

selected period. A premature write will also reset the part.

Clock Monitor

Reset

If clock frequency falls below a predetermined limit when the clock

monitor is enabled, a reset occurs.

Effects of Reset

When a reset occurs, MCU registers and control bits are changed to

known start-up states, as follows.

Operating Mode

and Memory Map

Operating mode and default memory mapping are determined by the

states of the BKGD, MODA, and MODB pins during reset. The SMODN,

MODA, and MODB bits in the MODE register reflect the status of the

mode-select inputs at the rising edge of reset. Operating mode and

default maps can subsequently be changed according to strictly defined

rules.

Clock and

Watchdog

Control Logic

The COP watchdog system is enabled, with the CR[2:0] bits set for the

longest duration time-out. The clock monitor is disabled. The RTIF flag

is cleared and automatic hardware interrupts are masked. The rate

control bits are cleared, and must be initialized before the RTI system is

used. The DLY control bit is set to specify an oscillator start-up delay

upon recovery from STOP mode.

8-reset

Resets and Interrupts

Effects of Reset

MC68HC912DG128

MOTOROLA Resets and Interrupts 117

9-reset

Interrupts PSEL is initialized in the HPRIO register with the value $F2, causing the

external IRQ pin to have the highest I-bit interrupt priority. The IRQ pin

is configured for level-sensitive operation (for wired-OR systems).

However, the interrupt mask bits in the CPU12 CCR are set to mask X-

and I-related interrupt requests.

Parallel I/O If the MCU comes out of reset in a single-chip mode, all ports are

configured as general-purpose high-impedance inputs.

If the MCU comes out of reset in an expanded mode, port A and port B

are used for the address/data bus, and port E pins are normally used to

control the external bus (operation of port E pins can be affected by the

PEAR register). Out of reset, port J, port H, port K, port IB, port P, port

S, port T, port AD0 and port AD1 are all configured as general-purpose

inputs.

Central Processing

Unit

After reset, the CPU fetches a vector from the appropriate address, then

begins executing instructions. The stack pointer and other CPU registers

are indeterminate immediately after reset. The CCR X and I interrupt

mask bits are set to mask any interrupt requests. The S bit is also set to

inhibit the STOP instruction.

Memory After reset, the internal register block is located from $0000 to $03FF,

RAM is at $2000 to $3FFF, and EEPROM is located at $0800 to $0FFF.

In single chip mode one 32-Kbyte FLASH EEPROM module is located

from $4000 to $7FFF and $C000 to $FFFF, and the other three 32-Kbyte

FLASH EEPROM modules are accessible through the program page

window located from $8000 to $BFFF. The first 32-Kbyte FLASH

EEPROM is also accessible through the program page window.

Other Resources The enhanced capture timer (ECT), pulse width modulation timer

(PWM), serial communications interfaces (SCI0 and SCI1), serial

peripheral interface (SPI), inter-IC bus (IIC), Motorola Scalable CANs

(MSCAN0 and MSCAN1) and analog-to-digital converters (ATD0 and

ATD1) are off after reset.

Resets and

MC68HC912DG128

118 Resets and Interrupts MOTOROLA

Once enabled, an interrupt request can be recognized at any time after

the I bit in the CCR is cleared. When an interrupt service request is

recognized, the CPU responds at the completion of the instruction being

executed. Interrupt latency varies according to the number of cycles

required to complete the instruction. Some of the longer instructions can

be interrupted and will resume normally after servicing the interrupt.

When the CPU begins to service an interrupt, the instruction queue is

cleared, the return address is calculated, and then it and the contents of

the CPU registers are stacked as shown in Table 21.

After the CCR is stacked, the I bit (and the X bit, if an XIRQ interrupt

service request is pending) is set to prevent other interrupts from

disrupting the interrupt service routine. The interrupt vector for the

highest priority source that was pending at the beginning of the interrupt

sequence is fetched, and execution continues at the referenced location.

At the end of the interrupt service routine, an RTI instruction restores the

content of all registers from information on the stack, and normal

program execution resumes.

If another interrupt is pending at the end of an interrupt service routine,

the register unstacking and restacking is bypassed and the vector of the

interrupt is fetched.

Table 21 Stacking Order on Entry to Interrupts

Memory Location CPU Registers

SP – 2 RTNH : RTNL

SP – 4 YH : YL

SP – 6 XH : XL

SP – 8 B : A

SP – 9 CCR

10-reset

MC68HC912DG128

MOTOROLA I/O Ports With Key Wake-Up 119

I/O Ports With Key Wake-Up

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119

Key Wake-up and port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . .120

Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124

Introduction

The MC68HC912DG128 offers 16 additional I/O ports with key wake-up

capability.

The key wake-up feature of the MC68HC912DG128 issues an interrupt

that will wake up the CPU when it is in the STOP or WAIT mode. Two

ports are associated with the key wake-up function: port H and port J.

Port H and port J wake-ups are triggered with a either a rising or falling

signal edge. For each pin which has an interrupt enabled, there is a path

to the interrupt request signal which has no clocked devices when the

part is in stop mode. This allows an active edge to bring the part out of

stop.

Digital filtering is included to prevent pulses shorter than a specified

value from waking the part from STOP.

An interrupt is generated when a bit in the KWIFH or KWIFJ register and

its corresponding KWIEH or KWIEJ bit are both set. All 16 bits/pins

share the same interrupt vector. Key wake-ups can be used with the pins

configured as inputs or outputs.

Default register addresses, as established after reset, are indicated in

the following descriptions. For information on re-mapping the register

block, refer to Operating Modes.

1-kwu

I/O Ports With Key Wake-Up

MC68HC912DG128

120 I/O Ports With Key Wake-Up MOTOROLA

Key Wake-up and port Registers

Read and write anytime.

Data direction register J is associated with port J and designates each

pin as an input or output.

Read and write anytime

DDRJ[7:0] — Data Direction Port J

0 = Associated pin is an input

1 = Associated pin is an output

PORTJ — Port J Register $0028

Bit 7 654321Bit 0

PORT PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0

KWU KWJ7 KWJ6 KWJ5 KWJ4 KWJ3 KWJ2 KWJ1 KWJ0

RESET: --------

PORTH — Port H Register $0029

Bit 7 654321Bit 0

PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0

KWU KWH7 KWH6 KWH5 KWH4 KWH3 KWH2 KWH1 KWH0

RESET: --------

DDRJ — Port J Data Direction Register $002A

Bit 7 654321Bit 0

DDJ7 DDJ6 DDJ5 DDJ4 DDJ3 DDJ2 DDJ1 DDJ0

RESET: 00000000

2--kwu

I/O Ports With Key Wake-Up

Key Wake-up and port Registers

MC68HC912DG128

MOTOROLA I/O Ports With Key Wake-Up 121

Data direction register H is associated with port H and designates each

pin as an input or output. Read and write anytime.

DDRH[7:0] — Data Direction Port H

0 = Associated pin is an input

1 = Associated pin is an output

Read and write anytime.

KWIEJ[7:0] — Key Wake-up Port J Interrupt Enables

0 = Interrupt for the associated bit is disabled

1 = Interrupt for the associated bit is enabled

Read and write anytime.

KWIEH[7:0] — Key Wake-up Port H Interrupt Enables

0 = Interrupt for the associated bit is disabled

1 = Interrupt for the associated bit is enabled

DDRH — Port H Data Direction Register $002B

Bit 7 654321Bit 0

DDH7 DDH6 DDH5 DDH4 DDH3 DDH2 DDH1 DDH0

RESET: 00000000

KWIEJ — Key Wake-up Port J Interrupt Enable Register $002C

Bit 7 654321Bit 0

KWIEJ7 KWIEJ6 KWIEJ5 KWIEJ4 KWIEJ3 KWIEJ2 KWIEJ1 KWIEJ0

RESET: 00000000

KWIEH — Key Wake-up Port H Interrupt Enable Register $002D

Bit 7 654321Bit 0

KWIEH7 KWIEH6 KWIEH5 KWIEH4 KWIEH3 KWIEH2 KWIEH1 KWIEH0

RESET: 00000000

3-kwu

I/O Ports With Key Wake-Up

MC68HC912DG128

122 I/O Ports With Key Wake-Up MOTOROLA

Read and write anytime.

Each flag is set by an active edge on its associated input pin. This could

be a rising or falling edge based on the state of the KWPJ register. To

clear the flag, write one to the corresponding bit in KWIFJ.

Initialize this register after initializing KWPJ so that illegal flags can be

cleared.

KWIFJ[7:0] — Key Wake-up Port J Flags

0 = Active edge on the associated bit has not occurred

1 = Active edge on the associated bit has occurred (an interrupt will

occur if the associated enable bit is set).

Read and write anytime.

Each flag is set by an active edge on its associated input pin. This could

be a rising or falling edge based on the state of the KWPH register. To

clear the flag, write one to the corresponding bit in KWIFH.

Initialize this register after initializing KWPH so that illegal flags can be

cleared.

KWIFH[7:0] — Key Wake-up Port H Flags

0 = Active edge on the associated bit has not occurred

1 = Active edge on the associated bit has occurred (an interrupt will

occur if the associated enable bit is set)

KWIFJ — Key Wake-up Port J Flag Register $002E

Bit 7 654321Bit 0

KWIFJ7 KWIFJ6 KWIFJ5 KWIFJ4 KWIFJ3 KWIFJ2 KWIFJ1 KWIFJ0

RESET: 00000000

KWIFH — Key Wake-up Port H Flag Register $002F

Bit 7 654321Bit 0

KWIFH7 KWIFH6 KWIFH5 KWIFH4 KWIFH3 KWIFH2 KWIFH1 KWIFH0

RESET: 00000000

4-kwu

I/O Ports With Key Wake-Up

Key Wake-up and port Registers

MC68HC912DG128

MOTOROLA I/O Ports With Key Wake-Up 123

Read and write anytime. It is best to clear the flags after initializing this

flag to become set.

KWPJ[7:0] — Key Wake-up Port J Polarity Selects

0 = Falling edge on the associated port J pin sets the associated

flag bit in the KWIFJ register and a resistive pull-up device is

connected to associated port J input pin.

1 = Rising edge on the associated port J pin sets the associated

flag bit in the KWIFJ register and a resistive pull-down device

is connected to associated port J input pin.

Read and write anytime. It is best to clear the flags after initializing this

flag to become set.

KWPH[7:0] — Key Wake-up Port H Polarity Selects

0 = Falling edge on the associated port H pin sets the associated

flag bit in the KWIFH register and a resistive pull-up device is

connected to associated port H input pin.

1 = Rising edge on the associated port H pin sets the associated

flag bit in the KWIFH register and a resistive pull-down device

is connected to associated port H input pin.

KWPJ — Key Wake-up Port J Polarity Register $0030

Bit 7 654321Bit 0

KWPJ7 KWPJ6 KWPJ5 KWPJ4 KWPJ3 KWPJ2 KWPJ1 KWPJ0

RESET: 00000000

KWPH — Key Wake-up Port H Polarity Register $0031

Bit 7 654321Bit 0

KWPH7 KWPH6 KWPH5 KWPH4 KWPH3 KWPH2 KWPH1 KWPH0

RESET: 00000000

5-kwu

I/O Ports With Key Wake-Up

MC68HC912DG128

124 I/O Ports With Key Wake-Up MOTOROLA

Timing Specifications

Figure 12 STOP Key Wake-up Filter

Glitch, ﬁltered out, no STOP wake-up

Valid STOP Wake-Up pulse

tKWSTP min.

tKWSTP max.

6-kwu

MC68HC912DG128

MOTOROLA Clock Functions 125

Clock Functions

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125

Phase-Locked Loop (PLL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126

Acquisition and Tracking Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . .128

Limp-Home and Fast STOP Recovery modes . . . . . . . . . . . . . . . . .130

System Clock Frequency formulas . . . . . . . . . . . . . . . . . . . . . . . . . .141

Clock Divider Chains. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .141

Computer Operating Properly (COP) . . . . . . . . . . . . . . . . . . . . . . . .146

Real-Time Interrupt. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Clock Monitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147

Clock Function Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148

Introduction

Clock generation circuitry generates the internal and external E-clock

signals as well as internal clock signals used by the CPU and on-chip

peripherals. A clock monitor circuit, a computer operating properly

(COP) watchdog circuit, and a periodic interrupt circuit are also

incorporated into the MC68HC912DG128.

Clock Sources

A compatible external clock signal can be applied to the EXTAL pin or

the MCU can generate a clock signal using an on-chip oscillator circuit

and an external crystal or ceramic resonator. The MCU uses several

types of internal clock signals derived from the primary clock signal: T

clocks, E clock, P clock, M clock, S clock, X clock and B clock. The T

1-clock

Clock Functions

MC68HC912DG128

126 Clock Functions MOTOROLA

clocks are used by the CPU. The E and P clocks are used by the bus

interfaces, IIC, SPI, PWM, ATD0 and ATD1. The M clock is either PCLK

or XCLK, and drives on-chip modules such as SCI0, SC1 and ECT. The

X clock drives on-chip modules such as RTI, COP, and restart-from-stop

delay time. The S (SLWCLK) clock is used as a calibration output signal.

Each MSCAN module is clocked by EXTALi or SYSCLK, under control

of an MSCAN bit. The clock monitor is clocked by EXTALi. The BDM

system is clocked by BCLK or ECLK, under control of a BDM bit.

Figure 13 shows some of the clock timing relationships. See also

Figure 18.

Figure 13 Internal Clock Relationships

Phase-Locked Loop (PLL)

The phase-locked loop (PLL) of the MC68HC912DG128 is designed for

robust operation in an Automotive environment. The proposed PLL

crystal or ceramic resonator reference of 0.5 to 8MHz is selected for the

wide availability of components with good stability in the desired

temperature range. Please refer to Figure 18 in section Clock Divider

Chains for an overview of system clocks.

An oscillator design with reduced power consumption allows for slow

wait operation with a typical power supply current lower than a

T1CLK

T2CLK

T3CLK

T4CLK

INT ECLK

PCLK

XCLK

CANCLK

2--clock

Clock Functions

Phase-Locked Loop (PLL)

MC68HC912DG128

MOTOROLA Clock Functions 127

milli-ampere. The PLL circuitry can be bypassed when the VDDPLL

supply is at VSS level. In this case the oscillator buffer has a stronger

drive capability, for a crystal at twice the bus frequency. Refer to Figure 3

in Pinout and Signal Descriptions.

Under control of the PSTP bit it is possible to enter STOP mode with the

whole device in STOP except for the oscillator that is still running.

Figure 14 PLL Functional Diagram

The slow mode clock divider is included to deliver a lower clock

frequency for the SCI baud rate generators, the ECT timer module, and

the RTI and COP clocks. The slow clock bus frequencies divide the

crystal frequency in a programmable range of 4 to 252, with steps of 4.

The PLL may be used to run the MCU from a different time base than

the incoming crystal value. It creates an integer multiple of a reference

frequency. For increased flexibility, the crystal clock can be divided by

values in a range of 1 – 8 (in unit steps) to generate the reference

frequency. The PLL can multiply this reference clock in a range of 1 to

64. Although it is possible to set the divider to command a very high clock

frequency, do not exceed the specified bus frequency limit for the MCU.

REDUCED

CONSUMPTION

OSCILLATOR

EXTAL

XTAL EXTALi

PLLCLK

REFERENCE

PROGRAMMABLE

DIVIDER PDET

PHASE

DETECTOR

REFDV <2:0>

LOOP

PROGRAMMABLE

DIVIDER

SYN <5:0>

CPUMP VCO

LOCK

LOOP

FILTER XFC

PAD

DOWN

LOCK

DETECTOR

REFCLK

DIVCLK

SLOW MODE

PROGRAMMABLE

CLOCK DIVIDER

SLDV <5:0>

XCLK

EXTALi

÷2

SLWCLK VDDPLL

x 2

3-clock

Clock Functions

MC68HC912DG128

128 Clock Functions MOTOROLA

If the PLL is selected, it will continue to run when in WAIT mode resulting

in more power consumption than normal. To take full advantage of the

reduced power consumption of WAIT mode, turn off the PLL before

going into WAIT. Please note that in this case the PLL stabilization time

applies.

The PLL operation is suspended in STOP mode. After STOP exit

followed by the stabilization time, it resumes operation at the same

frequency, provided the AUTO bit is set.

A passive external loop filter must be placed on the control line (XFC

pad). The filter is a second-order, low-pass filter to eliminate the VCO

input ripple. Values of components in the diagram are dependent upon

the desired VCO operation. See Section XFC.

Acquisition and Tracking Modes

The lock detector compares the frequencies of the VCO feedback clock,

DIVCLK, and the final reference clock, REFCLK. Therefore, the speed

of the lock detector is directly proportional to the final reference

frequency. The circuit determines the mode of the PLL and the lock

condition based on this comparison.

The PLL filter is manually or automatically configured into one of two

operating modes:

• Acquisition mode — In acquisition mode, the filter can make large

frequency corrections to the VCO. This mode is used at PLL

start-up or when the PLL has suffered a severe noise hit and the

VCO frequency is far off the desired frequency. When in

acquisition mode, the ACQ bit is clear in the PLL control register.

• Tracking mode — In tracking mode, the filter makes only small

corrections to the frequency of the VCO. PLL jitter is much lower

in tracking mode, but the response to noise is also slower. The

PLL enters tracking mode when the VCO frequency is nearly

correct. The PLL is automatically in tracking mode when not in

acquisition mode or when the ACQ bit is set.

4-clock

Clock Functions

Acquisition and Tracking Modes

MC68HC912DG128

MOTOROLA Clock Functions 129

The PLL can change the bandwidth or operational mode of the loop filter

manually or automatically.

In automatic bandwidth control mode (AUTO = 1), the lock detector

automatically switches between acquisition and tracking modes.

Automatic bandwidth control mode also is used to determine when the

VCO clock, PLLCLK, is safe to use as the source for the base clock,

SYSCLK. If PLL LOCK interrupt requests are enabled, the software can

wait for an interrupt request and then check the LOCK bit. If CPU

interrupts are disabled, software can poll the LOCK bit continuously

(during PLL start-up, usually) or at periodic intervals. In either case,

when the LOCK bit is set, the PLLCLK clock is safe to use as the source

for the base clock. See Clock Divider Chains. If the VCO is selected as

the source for the base clock and the LOCK bit is clear, the PLL has

suffered a severe noise hit and the software must take appropriate

action, depending on the application.

The following conditions apply when the PLL is in automatic bandwidth

control mode:

• The ACQ bit is a read-only indicator of the mode of the filter.

• The ACQ bit is set when the VCO frequency is within a certain

tolerance, ∆trk, and is cleared when the VCO frequency is out of a

certain tolerance, ∆unt.

• The LOCK bit is a read-only indicator of the locked state of the

PLL.

• The LOCK bit is set when the VCO frequency is within a certain

tolerance, ∆Lock, and is cleared when the VCO frequency is out of

a certain tolerance, ∆unl.

• CPU interrupts can occur if enabled (LOCKIE = 1) when the lock

condition changes, toggling the LOCK bit.

The PLL also can operate in manual mode (AUTO = 0). Manual mode is

used by systems that do not require an indicator of the lock condition for

proper operation. Such systems typically operate well below the

maximum fSYS frequency and require fast start-up. The following

conditions apply when in manual mode:

5-clock

Clock Functions

MC68HC912DG128

130 Clock Functions MOTOROLA

• ACQ is a writable control bit that controls the mode of the filter.

Before turning on the PLL in manual mode, the ACQ bit must be

clear.

• Before entering tracking mode (ACQ = 1), software must wait a

given time, tacq, after turning on the PLL by setting PLLON in the

PLL control register.

• Software must wait a given time, tal, after entering tracking mode

before selecting the PLLCLK as the SYSCLK clock source

(BCSP = 1).

• The LOCK bit is disabled.

• CPU interrupts from the LOCK bit are disabled.

Limp-Home and Fast STOP Recovery modes

The VCO has a minimum operating frequency, fVCOMIN. If the crystal

frequency is not available due to a failure or due to long crystal start-up

time, the MCU system clock can be supplied by the VCO. This mode of

operation is called Limp-Home mode. This mode is only available if the

VDDPLL supply voltage is at VDD level.

The Clock Monitor (see section Clock Monitor) can detect the loss of the

EXTALi external clock input signal, regardless of whether it is used as

the source of MCU clocks or as the PLL reference clock. The clock

monitor control bits CME and FCME are used to enable or disable the

external clock detection.

The lack of external clock can occur in three configurations, which are

described below:

1. During normal clock operation.

2. At Power-On Reset.

3. In the STOP exit sequence.

6-clock

Clock Functions

Limp-Home and Fast STOP Recovery modes

MC68HC912DG128

MOTOROLA Clock Functions 131

7-clock

Clock Loss during

Normal Operation

The no limp-home mode bit, NOLHM, determines how the MCU

responds to an external clock loss in the first case. When the NOLHM bit

is set, with CME or FCME set, and a loss of clock is detected by the clock

monitor circuit, the MCU resets. This is the same behavior as standard

M68HC12 circuits without PLL or operation with VDDPLL at VSS level.

When the NOLHM bit is cleared with CME or FCME set, and a loss of

clock is detected by the clock monitor circuit, the PLL VCO clock at its

minimum frequency is provided as the system clock, allowing the MCU

to continue operating. An MCU using the forced minimum VCO clock as

the system clock is said to be operating in “limp-home” mode. In

limp-home mode, PLLON and BCSP outputs are forced high and MCS

is forced low. XCLK, BCLK and MCLK are forced to be PCLK, which is

supplied by the VCO. The LHOME flag in the PLLFLG register indicates

that the MCU is running in limp-home mode. A change of this flag sets

the limp-home interrupt flag and if enabled by the LHIE bit, the

limp-home mode interrupt is requested.

Figure 15 Clock Loss during Normal Operation

Each time the 13-stage counter reaches a count of 4096 XCLK cycles,

a check of the clock monitor status is performed. When the presence of

an external clock is detected, the MCU leaves limp-home mode and the

0 --> 4096

Limp-Home

(Clocked by XCLK)

BCSP Restore BCSP

SYSCLK PLLCLK (Limp-Home) Restore PLLCLK or EXTALi

EXTALi

13-stage counter

Clock Monitor Fail

0 --> 4096

Clock Functions

MC68HC912DG128

132 Clock Functions MOTOROLA

LHOME flag is cleared. This also sets the limp-home interrupt flag. Upon

leaving limp-home mode, BCSP and MCS are restored to their values

before the clock loss, and XCLK, BCLK and MCLK return to their

previous frequencies. If AUTO and BCSP were set before the clock loss,

the sysclk ramps-up and the PLL locks at the previously selected

frequency. To prevent PLL operation when the external clock frequency

comes back, the software should clear the BCSP bit while running in

limp-home mode.

The two shaded regions A and B in Figure 15 present a risk of code

runaway if the MCU is clocked by EXTALi and the PLL is not used.

If the MCU is clocked by PLL, the risk of code runaway is very low

or inexistent as the transition from PLL to limp-home and vice

versa is smooth.

In the region A, there is a delay between the loss of clock and its

detection by the clock monitor . When the EXTALi clock signal is

disturbed, the clock generation circuitry may receive improper signal and

it will feed the CPU with incorrect clocks. This may lead to a code

runaway.

In the region B, as the 13-stage counter is free running, the count of

4096 may be reached when amplitude of the EXTALi clock is not

stabilized. In this case an improper EXTALi is sent to the clock

generation circuitry when the limp-home mode is exited. This may cause

a code runaway.

NOTE:

The COP watch dog should always be enabled in order to reset the MCU

in case of a code runaway situation.

No Clock at

Power-On Reset

When VDDPLL supply voltage is at VDD level, any reset sets the Clock

Monitor Enable bit (CME), the PLLON bit and clears the NOLHM bit.

Therefore, if the MCU is powered up without an external clock,

limp-home mode is activated.

During a normal power up sequence, after the POR pulse falling edge,

the VCO supplies the limp-home clock frequency to the 13-stage

counter, as BCSP output is forced high and MCS is forced low. XCLK,

BCLK and MCLK are forced to be PCLK, which is supplied by the VCO.

8-clock

Clock Functions

Limp-Home and Fast STOP Recovery modes

MC68HC912DG128

MOTOROLA Clock Functions 133

9-clock

Figure 16 No Clock at Power-On Reset

After the 13-stage counter reaches a count of 4096 XCLK cycles, reset

is released. At this time, if the clock monitor indicates the presence of an

external clock, the limp-home mode is de-asserted and the MCU exits

reset normally, using EXTALi clock. In the case of crystal start-up time

longer than the initial count of 4096 XCLK cycles, or in the absence of

an external clock, the MCU leaves the reset state in limp-home mode,

with both LHOME flag set and LHIF limp-home interrupt request set, to

indicate it is not operating at the desired frequency. Each time the

13-stage counter reaches a count of 4096 XCLK cycles, a check of the

clock monitor status is performed. When the presence of an external

clock is detected, the LHOME flag is cleared. This sets the limp-home

VDD

Power-On Detector

Clock Monitor Fail

EXTALi

13-stage counter

Internal reset

0 --> 4096

Limp-Home

(Clocked by XCLK)

BCSP Reset: BCSP = 0

SYSCLK PLLCLK (L.H.) EXTALi

SYSCLK PLLCLK (Software check of Limp-Home Flag) EXTALi

(Slow EXTALi)

0 --> 4096

(Slow EXTALi)

Clock Functions

MC68HC912DG128

134 Clock Functions MOTOROLA

interrupt flag and if enabled by the LHIE bit, the limp-home mode

interrupt is requested.

STOP Exit and Fast

STOP Recovery

If NOLHM bit and the CME (or FCME) bit are set, a clock monitor failure

is detected when a STOP instruction is executed and the MCU resets.

If NOLHM bit is set and CME (or FCME) bit is cleared, the MCU goes

into STOP mode when a STOP instruction is executed.

STOP mode is exited with an external reset, an external interrupt from

IRQ or XIRQ, a Key Wake-Up interrupt from port J or port H, or an

MSCAN Wake-Up interrupt.

Figure 17 STOP Exit and Fast STOP Recovery

If NOLHM bit is cleared, the CME (or FCME) bit is masked when STOP

instruction is executed to prevent a clock monitor failure. When coming

out of STOP mode, the CME (or FCME) bit is no longer masked and the

Clock Monitor Fail

EXTALi

13-stage counter 0 --> 4096

Limp-Home

(Clocked by XCLK)

BCSP Restore BCSP

SYSCLK PLLCLK (L.H.) Restore PLLCLK or EXTALi

STOP (DLY = 1)

STOP (DLY = 0)

10-clock

Clock Functions

Limp-Home and Fast STOP Recovery modes

MC68HC912DG128

MOTOROLA Clock Functions 135

11-clock

clock monitor is forced to be enabled. The MCU goes into limp-home

mode and the VCO supplies the limp-home clock frequency to the

13-stage counter with XCLK. The BCSP output is forced high, MCS is

forced low, and BCLK and MCLK are forced to be PCLK, which is also

supplied by VCO.

A normal STOP exit sequence with a crystal oscillator requires a set DLY

bit to allow for crystal oscillator stabilization. After a count of 4096

X clock cycles at the limp-home frequency, if the clock monitor indicates

the presence of an external clock, the limp-home mode is de-asserted

and the MCU exits STOP normally, using EXTALi clock. In the case of

crystal start-up time being longer than the initial count of 4096 XCLK

cycles, or in the absence of an external clock, the MCU recovers from

STOP in limp-home mode, with both LHOME flag set and LHIF

limp-home interrupt request set, to indicate it is not operating at the

desired frequency. Each time the 13-stage counter reaches a count of

4096 XCLK cycles, a check of the clock monitor status is performed.

When the presence of an external clock is detected, the LHOME flag is

cleared. This sets the limp-home interrupt flag and if enabled by the

LHIE bit, the limp-home mode interrupt is requested.

It is also possible to exit STOP with DLY bit cleared, using a crystal

oscillator. In this case, STOP is de-asserted without delay and the MCU

can execute software in limp-home mode, until the crystal oscillator has

started and is stable. This is called “Fast STOP recovery”. In this case,

after a count of 4096 X clock cycles at the limp-home frequency, if the

clock monitor indicates the presence of an external clock, the limp-home

mode is de-asserted and the LHOME flag is cleared. This also sets the

limp-home interrupt flag. Upon leaving limp-home mode, BCSP and

MCS are restored to their values before the loss of clock, and XCLK,

BCLK and MCLK return to their previous frequencies. If AUTO and

BCSP were set before the clock loss, the sysclk ramps-up and the PLL

locks at the previously selected frequency. To prevent PLL operation

when the external clock frequency comes back, the software should

clear the BCSP bit while running in limp-home mode.

It is possible to exit STOP with DLY bit cleared, when an external clock

is supplied. In this case the LHOME flag is never set and STOP is

de-asserted without delay.

Clock Functions

MC68HC912DG128

136 Clock Functions MOTOROLA

PLL Register

Description

Read anytime, write anytime, except when BCSP = 1.

If the PLL is on, the count in the loop divider (SYNR) register effectively

multiplies up the bus frequency from the PLL reference frequency by

SYNR + 1. Internally, SYSCLK runs at twice the bus frequency. Caution

should be used not to exceed the maximum rated operating frequency

for the CPU.

Read anytime, write anytime, except when BCSP = 1.

The reference divider bits provides a finer granularity for the PLL

multiplier steps. The reference frequency is divided by REFDV + 1.

Always reads zero, except in test modes.

SYNR — Synthesizer Register $0038

Bit 7 654321Bit 0

0 0 SYN5 SYN4 SYN3 SYN2 SYN1 SYN0

RESET: 00000000

REFDV — Reference Divider Register $0039

Bit 7 654321Bit 0

00000REFDV2 REFDV1 REFDV0

RESET: 00000000

CGTFLG — Clock Generator Test Register $003A

Bit 7 654321Bit 0

TSTOUT7 TSTOUT6 TSTOUT5 TSTOUT4 TSTOUT3 TSTOUT2 TSTOUT1 TSTOUT0

RESET: 00000000

12-clock

Clock Functions

Limp-Home and Fast STOP Recovery modes

MC68HC912DG128

MOTOROLA Clock Functions 137

13-clock

Read anytime, refer to each bit for write conditions.

LOCKIF — PLL Lock Interrupt Flag

0 = No change in LOCK bit.

1 = LOCK condition has changed, either from a locked state to an

unlocked state or vice versa.

To clear the flag, write one to this bit in PLLFLG. Cleared by

limp-home mode.

LOCK — Locked Phase Lock Loop Circuit

If AUTO = 0, reads always as 0.

If AUTO = 1

0 = PLL VCO is not within the desired tolerance of the target

frequency.

1 = After the phase lock loop circuit is turned on, indicates the PLL

VCO is within the desired tolerance of the target frequency.

Write has no effect on the LOCK bit. This bit is cleared by the

limp-home mode as the lock detector cannot operate without the

reference frequency.

LHIF — Limp-Home Interrupt Flag

0 = No change in LHOME bit.

1 = LHOME condition has changed, either entered or exited

limp-home mode.

To clear the flag, write one to this bit in PLLFLG.

LHOME — Limp-Home Mode Status

0 = MCU is operating normally, with EXTALi clock available for

generating clocks or as PLL reference.

1 = Loss of reference clock. PLL VCO limp-home frequency is

supplied to the MCU.

For limp-home mode, see Limp-Home and Fast STOP Recovery

modes.

PLLFLG — PLL Flags $003B

Bit 7 654321Bit 0

LOCKIF LOCK 0000LHIF LHOME

RESET: 00000000

Clock Functions

MC68HC912DG128

138 Clock Functions MOTOROLA

1. Set when VDDPLL power supply is high; Forced to 0 when VDDPLL is low.

2. Cleared when VDDPLL power supply is high; Forced to 1 when VDDPLL is low.

Read and write anytime. Exceptions are listed below for each bit.

LOCKIE — PLL LOCK Interrupt Enable

0 = PLL LOCK interrupt is disabled

1 = PLL LOCK interrupt is enabled

Forced to 0 when AUTO = 0 or when VDDPLL = 0. AUTO must be set

already, before LOCKIE can be written to ‘1’.

PLLON — Phase Lock Loop On

0 = Turns the PLL off.

1 = Turns on the phase lock loop circuit. If AUTO is set, the PLL will

lock automatically.

Cannot be cleared when BCSP = 1. Forced to 0 when VDDPLL is at

VSS level. In limp-home mode, the output of PLLON is forced to 1, but

the PLLON bit reads the latched value.

AUTO — Automatic Bandwidth Control

0 = Automatic Mode Control is disabled and the PLL is under

software control, using ACQ bit.

1 = Automatic Mode Control is enabled. ACQ bit is read only.

Automatic bandwidth control selects either the high bandwidth

(acquisition) mode or the low bandwidth (tracking) mode depending

on how close to the desired frequency the VCO is running.

ACQ — Not in Acquisition

If AUTO = 1 (ACQ is Read Only)

0 = PLL VCO is not within the desired tolerance of the target

frequency. The loop filter is in high bandwidth, acquisition

mode.

1 = After the phase lock loop circuit is turned on, indicates the PLL

VCO is within the desired tolerance of the target frequency.

The loop filter is in low bandwidth, tracking mode.

PLLCR — PLL Control Register $003C

Bit 7 654321Bit 0

LOCKIE PLLON AUTO ACQ 0 PSTP LHIE NOLHM

RESET: 0 —(1) 10000—

(2)

14-clock

Clock Functions

Limp-Home and Fast STOP Recovery modes

MC68HC912DG128

MOTOROLA Clock Functions 139

15-clock

If AUTO = 0

0 = High bandwidth software selected

1 = Low bandwidth software selected

PSTP — Pseudo-STOP Enable

0 = Pseudo-STOP oscillator mode is disabled

1 = Pseudo-STOP oscillator mode is enabled

In Pseudo-STOP mode, the oscillator is still running while the MCU is

maintained in STOP mode. This allows for a faster STOP recovery

and reduces the mechanical stress and aging of the resonator in case

frequent STOP conditions, at the expense of a slightly increased

power consumption.

LHIE — Limp-Home Interrupt Enable

0 = Limp-Home interrupt is disabled

1 = Limp-Home interrupt is enabled

Forced to 0 when VDDPLL is at VSS level.

NOLHM —No Limp-Home Mode

0 = Loss of reference clock forces the MCU in limp-home mode.

1 = Loss of reference clock causes standard Clock Monitor reset.

Read anytime; Normal modes: write once; Special modes: write

anytime. Forced to 1 when VDDPLL is at VSS level.

Read and write anytime. Exceptions are listed below for each bit.

BCSP — Bus Clock Select PLL

0 = SYSCLK is derived from the crystal clock or from SLWCLK.

1 = SYSCLK source is the PLL.

Cannot be set when PLLON = 0. In limp-home mode, the output of

BCSP is forced to 1, but the BCSP bit reads the latched value.

BCSP and BCSS bits determine the clock used by the main system

including the CPU and buses.

CLKSEL — Clock Generator Clock select Register $003D

Bit 7 654321Bit 0

0 BCSP BCSS 0 0 MCS 0 0

RESET: 00000000

Clock Functions

MC68HC912DG128

140 Clock Functions MOTOROLA

BCSS — Bus Clock Select Slow

0 = SYSCLK is derived from the crystal clock, EXTALi.

1 = SYSCLK source is the Slow clock, SLWCLK.

This bit has no effect when BCSP is set.

MCS — Module Clock Select

0 = M clock is the same as P clock.

1 = M clock is derived from Slow clock SLWCLK.

This bit determines the clock used by the ECT module and the baud

rate generators of the SCIs. In limp-home mode, the output of MCS is

forced to 0, but the MCS bit reads the latched value.

Read and write anytime.

A write to this register changes the SLWCLK frequency with minimum

delay (less than one SLWCLK cycle), thus allowing immediate tune-up

of the performance versus power consumption for the modules using

this clock. The frequency divide ratio is 2 times SLOW, hence the divide

range is 2 to 126, by steps of 2. When SLOW = 0, the divider is

bypassed. The generation of E, P and X, clocks further divides SLWCLK

by 2. Hence, the final ratio of Bus to EXTALi Frequency is programmable

to 2, 4, 8, 12, 16..., 252, by steps of 4. SLWCLK is a 50% duty cycle

signal.

Reads $00 except in test modes.

SLOW — Slow mode Divider Register $003E

Bit 7 654321Bit 0

0 0 SLDV5 SLDV4 SLDV3 SLDV2 SLDV1 SLDV0

RESET: 00000000

CGTCTL — Clock Generator Test Control Register $003F

Bit 7 654321Bit 0

OPNLE TRK TSTCLKE TST4 TST3 TST2 TST1 TST0

RESET: 00000000

16-clock

Clock Functions

System Clock Frequency formulas

MC68HC912DG128

MOTOROLA Clock Functions 141

17-clock

System Clock Frequency formulas

See Figure 18:

SLWCLK = EXTALi / ( 2 x SLOW ) SLOW = 1,2,..63

SLWCLK = EXTALi SLOW = 0

PLLCLK = 2 x EXTALi x (SYNR + 1) / (REFDV + 1)

XCLK = SLWCLK / 2

PCLK = SYSCLK / 2

BCLK1 = EXTALi / 2

Boolean equations:

MCLK = (MCS & XCLK) | (MCS & PCLK)

SYSCLK =

(BCSP & PLLCLK) | (BCSP & BCSS & EXTALi) | (BCSP & BCSS & SLWCLK)

BDM system = (BCLK & CLKSW) | (ECLK & CLKSW)

1. If SYSCLK is slower than EXTALi (BCSS=1, BCSP=0, SLOW>0), BCLK becomes ECLK.

NOTE:

During limp-home mode PCLK, ECLK, BCLK, MCLK and XCLK are

supplied by VCO (PLLCLK).

Clock Divider Chains

Figure 18, Figure 19, Figure 20, Figure 21, and Figure 22 summarize

the clock divider chains for the various peripherals on the

MC68HC912DG128.

Clock Functions

MC68HC912DG128

142 Clock Functions MOTOROLA

Figure 18 Clock Generation Chain

Bus clock select bits BCSP and BCSS in the clock select register

(CLKSEL) determine which clock drives SYSCLK for the main system

including the CPU and buses. BCSS has no effect if BCSP is set. During

the transition, the clock select output will be held low and all CPU activity

will cease until the transition is complete.

REDUCED

CONSUMPTION

OSCILLATOR

PHASE

LOCK

LOOP

EXTAL

XTAL

0:0

SYSCLK

BUSES,

IIC, SPI,

PWM,

ATD0, ATD1

RTI, COP

BCSP BCSS

SLOW

MODE

CLOCK

EXTALi

SLWCLK

PLLCLK

0:1

BCSP BCSS

1:x

BCSP BCSS

MCS = 0

MCS = 1

÷ 2

÷2

MSCAN0

CLKSRC0

TCLKs

T CLOCK

GENERATOR

E AND P

CLOCK PCLK

ECLK

XCLK

SCI0, SCI1,

ECT

TO CPU

SYNC

MCLK

TO BDM

÷ 2 BCLK

SYNC

TO CAL

TO CLOCK

MONITOR

MSCAN1

CLKSRC1

18-clock

Clock Functions

Clock Divider Chains

MC68HC912DG128

MOTOROLA Clock Functions 143

19-clock

The Module Clock Select bit MCS determines the clock used by the ECT

and the baud rate generators of the SCIs. In limp-home mode, the output

of MCS is forced to 0, but the MCS bit reads the latched value. It allows

normal operation of the serial and timer subsystems at a fixed reference

frequency while allowing the CPU to operate at a higher, variable

frequency.

Figure 19 Clock Chain for SCI0, SCI1, RTI, COP

XCLK

SC0BD

MODULUS DIVIDER:

÷ 1, 2, 3, 4, 5, 6,...,8190, 8191

SCI0

RECEIVE

BAUD RATE (16x)

SCI0

TRANSMIT

BAUD RATE (1x)

BITS: RTR2, RTR1, RTR0

TO RTI

BITS: CR2, CR1, CR0

TO COP

÷ 16

SCI1

RECEIVE

BAUD RATE (16x)

SCI1

TRANSMIT

BAUD RATE (1x)

÷ 16

0:0:0

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

÷ 2

0:0:0

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

÷ 4

÷ 2

÷ 4

÷ 2

÷4REGISTER: COPCTL

SC1BD

MODULUS DIVIDER:

÷ 1, 2, 3, 4, 5, 6,...,8190, 8191

HC12 CLOCK CHAIN SCI RTI COP

BIT:RTBYP

÷ 2048

MCLK

Clock Functions

MC68HC912DG128

144 Clock Functions MOTOROLA

Figure 20 Clock Chain for IIC

÷ 2

0:0:0

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

÷ 2

BITS: IBC5, IBC4, IBC3

PCLK

PRESCALAR

SHIFTER TAPS

0:0:X

BITS: IBC2, IBC1, IBC0

0:1:X

1:0:X

1:1:X

0:0:0

0:0:1

1:0:0

1:0:1

0:1:0

0:1:1

1:1:0

1:1:1

SDA HOLD

SCL DIVIDER

20-clock

Clock Functions

Clock Divider Chains

MC68HC912DG128

MOTOROLA Clock Functions 145

21-clock

Figure 21 Clock Chain for ECT

BITS: PR2, PR1, PR0

MCLK

PAMOD

PACLK

PULSE ACC

LOW BYTE PACLK/256

PULSE ACC

HIGH BYTE

PACLK/65536

(PAOV)

GATE

LOGIC

BITS: PAEN, CLK1, CLK0

TEN

PAEN

0:0:0

0:0:1

÷ 2

0:1:0

÷ 2

0:1:1

÷ 2

1:0:0

÷ 2

1:0:1

÷ 2

1:1:0

÷ 2

1:1:1

÷ 2

BITS: MCPR1, MCPR0

MCEN REGISTER: MCCTL

0:0

0:1

÷ 4

1:0

÷ 2

1:1

÷ 2

0:x:x

1:0:0

1:0:1

1:1:0

1:1:1

T O TIMER

MAIN

COUNTE

MODU-

LUS

DOWN

PORT T7

Clock Functions

MC68HC912DG128

146 Clock Functions MOTOROLA

Figure 22 Clock Chain for SPI, ATD0, ATD1 and BDM

Computer Operating Properly (COP)

The COP or watchdog timer is an added check that a program is running

and sequencing properly. When the COP is being used, software is

responsible for keeping a free running watchdog timer from timing out. If

the watchdog timer times out it is an indication that the software is no

longer being executed in the intended sequence; thus a system reset is

initiated. Three control bits allow selection of seven COP time-out

periods. When COP is enabled, sometime during the selected period the

program must write $55 and $AA (in this order) to the COPRST register.

If the program fails to do this the part will reset. If any value other than

$55 or $AA is written, the part is reset.

In addition, windowed COP operation can be selected. In this mode,

writes to the COPRST register must occur in the last 25% of the selected

period. A premature write will also reset the part.

PCLK

BITS: SPR2, SPR1, SPR0

SPI

BIT RATE

5-BIT MODULUS

COUNTER (PR0-PR4) TO ATD0

and ATD1

ECLK

BKGD

BDM BIT CLOCK:

Receive: Detect falling edge,

count 12 E clocks, Sample input

Transmit 1: Detect falling edge,

count 6 E clocks while output is

high impedance, Drive out 1 E

cycle pulse high, high imped-

ance output again

Transmit 0: Detect falling edge,

Drive out low, count 9 E clocks,

Drive out 1 E cycle pulse high,

high impedance output

SYNCHRONIZER

LOGIC

BKGD IN

BKGD OUT

BKGD DIRECTION

÷ 2

0:0:0

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

÷ 2

÷ 2 REGISTER: SP0BR

HC12 CLOCK CHAIN SPI ATD BDM

CLKSW

BCLK

22-clock

Clock Functions

Real-Time Interrupt

MC68HC912DG128

MOTOROLA Clock Functions 147

23-clock

Real-Time Interrupt

There is a real time (periodic) interrupt available to the user. This

interrupt will occur at one of seven selected rates. An interrupt flag and

an interrupt enable bit are associated with this function. There are three

bits for the rate select.

Clock Monitor

The clock monitor circuit is based on an internal resistor-capacitor (RC)

time delay. If no EXTALi clock edges are detected within this RC time

delay, the clock monitor can optionally generate a system reset. The

clock monitor function is enabled/disabled by the CME control bit in the

COPCTL register. This time-out is based on an RC delay so that the

clock monitor can operate without any EXTALi clock.

Clock monitor time-outs are shown in Table 22. The corresponding

EXTALi clock period with an ideal 50% duty cycle is twice this time-out

value.

Table 22 Clock Monitor Time-Outs

Supply Range

5 V +/– 10% 2–20 µS

3 V +/– 10% 2–50 µS

Clock Functions

MC68HC912DG128

148 Clock Functions MOTOROLA

Clock Function Registers

All register addresses shown reflect the reset state. Registers may be

mapped to any 2K byte space.

RTIE — Real Time Interrupt Enable

Read and write anytime.

0 = Interrupt requests from RTI are disabled.

1 = Interrupt will be requested whenever RTIF is set.

RSWAI — RTI and COP Stop While in Wait

Write once in normal modes, anytime in special modes. Read

anytime.

0 = Allows the RTI and COP to continue running in wait.

1 = Disables both the RTI and COP whenever the part goes into

Wait.

RSBCK — RTI and COP Stop While in Background Debug Mode

Write once in normal modes, anytime in special modes. Read

anytime.

0 = Allows the RTI and COP to continue running while in

background mode.

1 = Disables both the RTI and COP when the part is in background

mode. This is useful for emulation.

RTBYP — Real Time Interrupt Divider Chain Bypass

Write not allowed in normal modes, anytime in special modes. Read

anytime.

0 = Divider chain functions normally.

1 = Divider chain is bypassed, allows faster testing (the divider

chain is normally XCLK divided by 213, when bypassed

becomes XCLK divided by 4).

RTICTL — Real-Time Interrupt Control Register $0014

Bit 7 654321Bit 0

RTIE RSWAI RSBCK Reserved RTBYP RTR2 RTR1 RTR0

RESET: 00000000

24-clock

Clock Functions

Clock Function Registers

MC68HC912DG128

MOTOROLA Clock Functions 149

25-clock

RTR2, RTR1, RTR0 — Real-Time Interrupt Rate Select

Read and write anytime.

Rate select for real-time interrupt. The clock used for this module is

the XCLK.

RTIF — Real Time Interrupt Flag

This bit is cleared automatically by a write to this register with this bit

set.

0 = Time-out has not yet occurred.

1 = Set when the time-out period is met.

Read and write anytime.

Table 23 Real Time Interrupt Rates

RTR2 RTR1 RTR0 Divide X By: Time-Out Period

X = 125 KHz Time-Out Period

X = 500 KHz Time-Out Period

X = 2.0 MHz Time-Out Period

X = 8.0 MHz

0 0 0 OFF OFF OFF OFF OFF

001 2

13 65.536 ms 16.384 ms 4.096 ms 1.024 ms

010 2

14 131.72 ms 32.768 ms 8.196 ms 2.048 ms

011 2

15 263.44 ms 65.536 ms 16.384 ms 4.096 ms

100 2

16 526.88 ms 131.72 ms 32.768 ms 8.196 ms

101 2

17 1.05 s 263.44 ms 65.536 ms 16.384 ms

110 2

18 2.11 s 526.88 ms 131.72 ms 32.768 ms

111 2

19 4.22 s 1.05 s 263.44 ms 65.536 ms

RTIFLG — Real Time Interrupt Flag Register$0015

Bit 7 654321Bit 0

RTIF 0000000

RESET: 00000000

COPCTL — COP Control Register$0016

Bit 7 654321Bit 0

CME FCME FCMCOP WCOP DISR CR2 CR1 CR0

RESET: 0/1 0000111Normal

RESET: 0/1 0001111Special

Clock Functions

MC68HC912DG128

150 Clock Functions MOTOROLA

CME — Clock Monitor Enable

If FCME is set, this bit has no meaning nor effect.

0 = Clock monitor is disabled. Slow clocks and stop instruction may

be used.

1 = Slow or stopped clocks (including the stop instruction) will

cause a clock reset sequence or limp-home mode. See

Limp-Home and Fast STOP Recovery modes.

On reset

CME is 1 if VDDPLL is high

CME is 0 if VDDPLL is low.

FCME — Force Clock Monitor Enable

Write once in normal modes, anytime in special modes. Read

anytime.

In normal modes, when this bit is set, the clock monitor function

cannot be disabled until a reset occurs.

0 = Clock monitor follows the state of the CME bit.

1 = Slow or stopped clocks will cause a clock reset sequence or

limp-home mode. See Limp-Home and Fast STOP Recovery

modes.

FCMCOP — Force Clock Monitor Reset or COP Watchdog Reset

Writes are not allowed in normal modes, anytime in special modes.

Read anytime.

If DISR is set, this bit has no effect.

0 = Normal operation.

1 = A clock monitor failure reset or a COP failure reset is forced

depending on the state of CME and if COP is enabled.

1. Highest priority interrupt vector is serviced.

CME COP enabled Forced reset

0 0 none

0 1 COP failure

1 0 Clock monitor failure

1 1 Both(1)

26-clock

Clock Functions

Clock Function Registers

MC68HC912DG128

MOTOROLA Clock Functions 151

27-clock

WCOP — Window COP mode

Write once in normal modes, anytime in special modes. Read

anytime.

0 = Normal COP operation

1 = Window COP operation

When set, a write to the COPRST register must occur in the last 25%

of the selected period. A premature write will also reset the part. As

long as all writes occur during this window, $55 can be written as often

as desired. Once $AA is written the time-out logic restarts and the

user must wait until the next window before writing to COPRST.

Please note, there is a fixed time uncertainty about the exact COP

counter state when reset, as the initial prescale clock divider in the

RTI section is not cleared when the COP counter is cleared. This

means the effective window is reduced by this uncertainty. Table 24

below shows the exact duration of this window for the seven available

COP rates.

DISR — Disable Resets from COP Watchdog and Clock Monitor

Writes are not allowed in normal modes, anytime in special modes.

Read anytime.

0 = Normal operation.

1 = Regardless of other control bit states, COP and clock monitor

will not generate a system reset.

CR2, CR1, CR0 — COP Watchdog Timer Rate select bits

These bits select the COP time-out rate. The clock used for this

module is the XCLK.

Write once in normal modes, anytime in special modes. Read

anytime.

Clock Functions

MC68HC912DG128

152 Clock Functions MOTOROLA

1. Time for writing $55 following previous COP restart of time-out logic due to writing $AA.

2. Please refer to WCOP bit description above.

3. Window COP cannot be used at this rate.

Always reads $00.

Writing $55 to this address is the first step of the COP watchdog

sequence.

Writing $AA to this address is the second step of the COP watchdog

sequence. Other instructions may be executed between these writes but

both must be completed in the correct order prior to time-out to avoid a

watchdog reset. Writing anything other than $55 or $AA causes a COP

reset to occur.

Table 24 COP Watchdog Rates

CR2 CR1 CR0 Divide X

clock by 8.0 MHz X clock.

Time-out

Window COP enabled:

Window

start (1) Window end Effective

Window (2)

0 0 0 OFF OFF OFF OFF OFF

001 2

13 1.024 ms -0/+0.256 ms 0.768 ms 0.768 ms 0 % (3)

010 2

15 4.096 ms -0/+0.256 ms 3.072 ms 3.840 ms 18.8 %

011 2

17 16.384 ms -0/+0.256 ms 12.288 ms 16.128 ms 23.4 %

100 2

19 65.536 ms -0/+1.024 ms 49.152 ms 64.512 ms 23.4 %

101 2

21 262.144 ms -0/+1.024 ms 196.608 ms 261.120 ms 24.6 %

110 2

22 524.288 ms -0/+1.024 ms 393.216 ms 523.264 ms 24.8 %

111 2

23 1.048576 s -0/+1.024 ms 786.432 ms 1.047552 s 24.9 %

COPRST — Arm/Reset COP Timer Register $0017

Bit 7 654321Bit 0

RESET: 00000000

28-clock

MC68HC912DG128

MOTOROLA Pulse-Width Modulator 153

Pulse-Width Modulator

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153

PWM Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157

PWM Boundary Cases . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .168

Introduction

The pulse-width modulator (PWM) subsystem provides four

independent 8-bit PWM waveforms or two 16-bit PWM waveforms or a

combination of one 16-bit and two 8-bit PWM waveforms. Each

waveform channel has a programmable period and a programmable

duty-cycle as well as a dedicated counter. A flexible clock select scheme

allows four different clock sources to be used with the counters. Each of

the modulators can create independent, continuous waveforms with

software-selectable duty rates from 0 percent to 100 percent. The PWM

outputs can be programmed as left-aligned outputs or center-aligned

outputs.

The period and duty registers are double buffered so that if they change

while the channel is enabled, the change will not take effect until the

counter rolls over or the channel is disabled. If the channel is not

enabled, then writes to the period and/or duty register will go directly to

the latches as well as the buffer, thus ensuring that the PWM output will

always be either the old waveform or the new waveform, not some

variation in between.

A change in duty or period can be forced into immediate effect by writing

the new value to the duty and/or period registers and then writing to the

counter. This causes the counter to reset and the new duty and/or period

values to be latched. In addition, since the counter is readable it is

1-pwm

Pulse-Width Modulator

MC68HC912DG128

154 Pulse-Width Modulator MOTOROLA

possible to know where the count is with respect to the duty value and

software can be used to make adjustments by turning the enable bit off

and on.

The four PWM channel outputs share general-purpose port P pins.

Enabling PWM pins takes precedence over the general-purpose port.

When PWM are not in use, the port pins may be used for discrete input/

output.

Figure 23 Block Diagram of PWM Left-Aligned Output Channel

GATE PWCNTx

8-BIT COMPARE =

PWDTYx

8-BIT COMPARE =

PWPERx

UP/DOWN FROM PORT P

DATA REGISTER

TO PIN

DRIVER

PPOLx

CLOCK SOURCE

(ECLK or Scaled ECLK)

(CLOCK EDGE SYNC) RESET

CENTR = 0

MUX MUX

PWPER

PWDTY

PWENx

PPOL = 0

PPOL = 1

SYNC

2--pwm

Pulse-Width Modulator

Introduction

MC68HC912DG128

MOTOROLA Pulse-Width Modulator 155

Figure 24 Block Diagram of PWM Center-Aligned Output Channel

GATE PWCNTx

8-BIT COMPARE =

PWDTYx

8-BIT COMPARE =

PWPERx

RESET FROM PORT P

DATA REGISTER

TO PIN

DRIVER

PPOLx

CLOCK SOURCE

(ECLK or Scaled ECLK)

(CLOCK EDGE SYNC)

UP/DOWN

CENTR = 1

MUX MUX

PWDTY

PWENx

PPOL = 1

PPOL = 0

(DUTY CYCLE)

(PERIOD)

PWPER × 2

(PWPER − PWDTY) × 2 PWDTY

SYNC

3-pwm

Pulse-Width Modulator

MC68HC912DG128

156 Pulse-Width Modulator MOTOROLA

Figure 25 PWM Clock Sources

8-BIT DOWN COUNTER

PCLK2

MUX

PCLK3

MUX

CLOCK TO PWM

CHANNEL 2

CLOCK TO PWM

CHANNEL 3

÷ 2

PWSCNT1

8-BIT SCALE REGISTER

PWSCAL1

CLOCK B

CLOCK S1**

**CLOCK S1 = (CLOCK B)/2, (CLOCK B)/4, (CLOCK B)/6,... (CLOCK B)/512

÷ 2

0:0:0

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

÷ 2

0:0:0

0:0:1

0:1:0

0:1:1

1:0:0

1:0:1

1:1:0

1:1:1

8-BIT DOWN COUNTER

PCLK0

MUX

PCLK1

MUX

CLOCK TO PWM

CHANNEL 0

CLOCK TO PWM

CHANNEL 1

÷ 2

PWSCNT0

8-BIT SCALE REGISTER

PWSCAL0

CLOCK A

CLOCK S0*

*CLOCK S0 = (CLOCK A)/2, (CLOCK A)/4, (CLOCK A)/6,... (CLOCK A)/512

PCKB2,

PCKB0

PCKB1,

= 0

BITS:

PCKA2,

PCKA0

PCKA1,

PWPRES

PSBCK

LIMBDM

ECLK

PSBCK IS BIT 0 OF PWCTL REGISTER.

INTERNAL SIGNAL LIMBDM IS ONE IF THE MCU IS IN BACKGROUND DEBUG MODE.

4-pwm

Pulse-Width Modulator

PWM Register Descriptions

MC68HC912DG128

MOTOROLA Pulse-Width Modulator 157

PWM Register Descriptions

Read and write anytime.

CON23 — Concatenate PWM Channels 2 and 3

When concatenated, channel 2 becomes the high-order byte and

channel 3 becomes the low-order byte. Channel 2 output pin is used

as the output for this 16-bit PWM (bit 2 of port P). Channel 3

clock-select control bits determines the clock source. Channel 3

output pin becomes a general purpose I/O.

0 = Channels 2 and 3 are separate 8-bit PWMs.

1 = Channels 2 and 3 are concatenated to create one 16-bit PWM

channel.

CON01 — Concatenate PWM Channels 0 and 1

When concatenated, channel 0 becomes the high-order byte and

channel 1 becomes the low-order byte. Channel 0 output pin is used

as the output for this 16-bit PWM (bit 0 of port P). Channel 1

clock-select control bits determine the clock source. Channel 1 output

pin becomes a general purpose I/O.

0 = Channels 0 and 1 are separate 8-bit PWMs.

1 = Channels 0 and 1 are concatenated to create one 16-bit PWM

channel.

PCKA2 – PCKA0 — Prescaler for Clock A

Clock A is one of two clock sources which may be used for channels

0 and 1. These three bits determine the rate of clock A, as shown in

Table 25.

PCKB2 – PCKB0 — Prescaler for Clock B

Clock B is one of two clock sources which may be used for channels

2 and 3. These three bits determine the rate of clock B, as shown in

Table 25.

PWCLK — PWM Clocks and Concatenate $0040

Bit 7 6 5 4 3 2 1 Bit 0

CON23 CON01 PCKA2 PCKA1 PCKA0 PCKB2 PCKB1 PCKB0

RESET: 0 0 0 0 0 0 0 0

5-pwm

Pulse-Width Modulator

MC68HC912DG128

158 Pulse-Width Modulator MOTOROLA

Read and write anytime.

PCLK3 — PWM Channel 3 Clock Select

0 = Clock B is the clock source for channel 3.

1 = Clock S1 is the clock source for channel 3.

PCLK2 — PWM Channel 2 Clock Select

0 = Clock B is the clock source for channel 2.

1 = Clock S1 is the clock source for channel 2.

PCLK1 — PWM Channel 1 Clock Select

0 = Clock A is the clock source for channel 1.

1 = Clock S0 is the clock source for channel 1.

PCLK0 — PWM Channel 0 Clock Select

0 = Clock A is the clock source for channel 0.

1 = Clock S0 is the clock source for channel 0.

If a clock select is changed while a PWM signal is being generated, a

truncated or stretched pulse may occur during the transition.

Table 25 Clock A and Clock B Prescaler

PCKA2

(PCKB2) PCKA1

(PCKB1) PCKA0

(PCKB0) Value of

Clock A (B)

000 P

001 P ÷ 2

010 P ÷ 4

011 P ÷ 8

100 P ÷ 16

101 P ÷ 32

110 P ÷ 64

111P ÷ 128

PWPOL — PWM Clock Select and Polarity $0041

Bit 7 6 5 4 3 2 1 Bit 0

PCLK3 PCLK2 PCLK1 PCLK0 PPOL3 PPOL2 PPOL1 PPOL0

RESET: 0 0 0 0 0 0 0 0

6-pwm

Pulse-Width Modulator

PWM Register Descriptions

MC68HC912DG128

MOTOROLA Pulse-Width Modulator 159

7-pwm

The following four bits apply in left-aligned mode only:

PPOL3 — PWM Channel 3 Polarity

0 = Channel 3 output is low at the beginning of the period; high

when the duty count is reached.

1 = Channel 3 output is high at the beginning of the period; low

when the duty count is reached.

PPOL2 — PWM Channel 2 Polarity

0 = Channel 2 output is low at the beginning of the period; high

when the duty count is reached.

1 = Channel 2 output is high at the beginning of the period; low

when the duty count is reached.

PPOL1 — PWM Channel 1 Polarity

0 = Channel 1 output is low at the beginning of the period; high

when the duty count is reached.

1 = Channel 1 output is high at the beginning of the period; low

when the duty count is reached.

PPOL0 — PWM Channel 0 Polarity

0 = Channel 0 output is low at the beginning of the period; high

when the duty count is reached.

1 = Channel 0 output is high at the beginning of the period; low

when the duty count is reached.

Depending on the polarity bit, the duty registers may contain the count

of either the high time or the low time. If the polarity bit is zero and left

alignment is selected, the duty registers contain a count of the low

time. If the polarity bit is one, the duty registers contain a count of the

high time.

Pulse-Width Modulator

MC68HC912DG128

160 Pulse-Width Modulator MOTOROLA

Setting any of the PWENx bits causes the associated port P line to

become an output regardless of the state of the associated data

direction register (DDRP) bit. This does not change the state of the data

direction bit. When PWENx returns to zero, the data direction bit controls

I/O direction. On the front end of the PWM channel, the scaler clock is

enabled to the PWM circuit by the PWENx enable bit being high. When

all four PWM channels are disabled, the prescaler counter shuts off to

save power. There is an edge-synchronizing gate circuit to guarantee

that the clock will only be enabled or disabled at an edge.

Read and write anytime.

PWEN3 — PWM Channel 3 Enable

The pulse modulated signal will be available at port P, bit 3 when its

clock source begins its next cycle.

0 = Channel 3 is disabled.

1 = Channel 3 is enabled.

PWEN2 — PWM Channel 2 Enable

The pulse modulated signal will be available at port P, bit 2 when its

clock source begins its next cycle.

0 = Channel 2 is disabled.

1 = Channel 2 is enabled.

PWEN1 — PWM Channel 1 Enable

The pulse modulated signal will be available at port P, bit 1 when its

clock source begins its next cycle.

0 = Channel 1 is disabled.

1 = Channel 1 is enabled.

PWEN0 — PWM Channel 0 Enable

The pulse modulated signal will be available at port P, bit 0 when its

clock source begins its next cycle.

0 = Channel 0 is disabled.

1 = Channel 0 is enabled.

PWEN — PWM Enable $0042

Bit 7 6 5 4 3 2 1 Bit 0

0 0 0 0 PWEN3 PWEN2 PWEN1 PWEN0

RESET: 0 0 0 0 0 0 0 0

8-pwm

Pulse-Width Modulator

PWM Register Descriptions

MC68HC912DG128

MOTOROLA Pulse-Width Modulator 161

9-pwm

PWPRES is a free-running 7-bit counter. Read anytime. Write only in

special mode (SMOD = 1).

Read and write anytime. A write will cause the scaler counter PWSCNT0

to load the PWSCAL0 value unless in special mode with DISCAL = 1 in

the PWTST register.

PWM channels 0 and 1 can select clock S0 (scaled) as its input clock by

setting the control bit PCLK0 and PCLK1 respectively. Clock S0 is

generated by dividing clock A by the value in the PWSCAL0 register + 1

and dividing again by two. When PWSCAL0 = $FF, clock A is divided by

256 then divided by two to generate clock S0.

PWSCNT0 is a down-counter that, upon reaching $00, loads the value

of PWSCAL0. Read any time.

PWPRES — PWM Prescale Counter $0043

Bit 7 6 5 4 3 2 1 Bit 0

0 Bit 6 5 4 3 2 1 Bit 0

RESET: 0 0 0 0 0 0 0 0

PWSCAL0 — PWM Scale Register 0 $0044

Bit 7 6 5 4 3 2 1 Bit 0

RESET: 0 0 0 0 0 0 0 0

PWSCNT0 — PWM Scale Counter 0 Value $0045

Bit 7 6 5 4 3 2 1 Bit 0

RESET: 0 0 0 0 0 0 0 0

Pulse-Width Modulator

MC68HC912DG128

162 Pulse-Width Modulator MOTOROLA

Read and write anytime. A write will cause the scaler counter PWSCNT1

to load the PWSCAL1 value unless in special mode with DISCAL = 1 in

the PWTST register.

PWM channels 2 and 3 can select clock S1 (scaled) as its input clock by

setting the control bit PCLK2 and PCLK3 respectively. Clock S1 is

generated by dividing clock B by the value in the PWSCAL1 register + 1

and dividing again by two. When PWSCAL1 = $FF, clock B is divided by

256 then divided by two to generate clock S1.

PWSCNT1 is a down-counter that, upon reaching $00, loads the value

of PWSCAL1. Read any time.

Read and write anytime. A write will cause the PWM counter to reset to

$00.

In special mode, if DISCR = 1, a write does not reset the PWM counter.

PWSCAL1 — PWM Scale Register 1 $0046

Bit 7 6 5 4 3 2 1 Bit 0

RESET: 0 0 0 0 0 0 0 0

PWSCNT1 — PWM Scale Counter 1 Value $0047

Bit 7 6 5 4 3 2 1 Bit 0

RESET: 0 0 0 0 0 0 0 0

PWCNTx — PWM Channel Counters

Bit 7 6 5 4 3 2 1 Bit 0

PWCNT0 Bit 7 6 5 4 3 2 1 Bit 0 $0048

PWCNT1 Bit 7 6 5 4 3 2 1 Bit 0 $0049

PWCNT2 Bit 7 6 5 4 3 2 1 Bit 0 $004A

PWCNT3 Bit 7 6 5 4 3 2 1 Bit 0 $004B

RESET: 0 0 0 0 0 0 0 0

10-pwm

Pulse-Width Modulator

PWM Register Descriptions

MC68HC912DG128

MOTOROLA Pulse-Width Modulator 163

11-pwm

The PWM counters are not reset when PWM channels are disabled. The

counters must be reset prior to a new enable.

Each counter may be read any time without affecting the count or the

operation of the corresponding PWM channel. Writes to a counter cause

the counter to be reset to $00 and force an immediate load of both duty

and period registers with new values. To avoid a truncated PWM period,

write to a counter while the counter is disabled. In left-aligned output

mode, resetting the counter and starting the waveform output is

controlled by a match between the period register and the value in the

counter. In center-aligned output mode the counters operate as up/down

counters, where a match in period changes the counter direction. The

duty register changes the state of the output during the period to

determine the duty.

When a channel is enabled, the associated PWM counter starts at the

count in the PWCNTx register using the clock selected for that channel.

In special mode, when DISCP = 1 and configured for left-aligned output,

a match of period does not reset the associated PWM counter.

Read and write anytime.

The value in the period register determines the period of the associated

PWM channel. If written while the channel is enabled, the new value will

not take effect until the existing period terminates, forcing the counter to

reset. The new period is then latched and is used until a new period

value is written. Reading this register returns the most recent value

written. To start a new period immediately, write the new period value

PWPERx — PWM Channel Period Registers

Bit 7 6 5 4 3 2 1 Bit 0

PWPER0 Bit 7 6 5 4 3 2 1 Bit 0 $004C

PWPER1 Bit 7 6 5 4 3 2 1 Bit 0 $004D

PWPER2 Bit 7 6 5 4 3 2 1 Bit 0 $004E

PWPER3 Bit 7 6 5 4 3 2 1 Bit 0 $004F

RESET: 1 1 1 1 1 1 1 1

Pulse-Width Modulator

MC68HC912DG128

164 Pulse-Width Modulator MOTOROLA

and then write the counter forcing a new period to start with the new

period value.

Period = Channel-Clock-Period × (PWPER + 1) (CENTR = 0)

Period = Channel-Clock-Period × (2 × PWPER) (CENTR = 1)

Read and write anytime.

The value in each duty register determines the duty of the associated

PWM channel. When the duty value is equal to the counter value, the

output changes state. If the register is written while the channel is

enabled, the new value is held in a buffer until the counter rolls over

or the channel is disabled. Reading this register returns the most

recent value written.

If the duty register is greater than or equal to the value in the period

to $FF the output will always be in the state which would normally be

the state opposite the PPOLx value.

Left-Aligned-Output Mode (CENTR = 0):

Duty cycle = [(PWDTYx+1)/(PWPERx+1)] × 100% (PPOLx = 1)

Duty cycle = [(PWPERx−PWDTYx)/(PWPERx+1)] × 100% (PPOLx = 0)

Center-Aligned-Output Mode (CENTR = 1):

Duty cycle = [(PWPERx−PWDTYx)/PWPERx] × 100% (PPOLx = 0)

Duty cycle = [PWDTYx/PWPERx] × 100% (PPOLx = 1)

PWDTYx — PWM Channel Duty Registers

Bit 7 6 5 4 3 2 1 Bit 0

PWDTY0 Bit 7 6 5 4 3 2 1 Bit 0 $0050

PWDTY1 Bit 7 6 5 4 3 2 1 Bit 0 $0051

PWDTY2 Bit 7 6 5 4 3 2 1 Bit 0 $0052

PWDTY3 Bit 7 6 5 4 3 2 1 Bit 0 $0053

RESET: 1 1 1 1 1 1 1 1

12-pwm

Pulse-Width Modulator

PWM Register Descriptions

MC68HC912DG128

MOTOROLA Pulse-Width Modulator 165

13-pwm

Read and write anytime.

PSWAI — PWM Halts while in Wait Mode

0 = Allows PWM main clock generator to continue while in wait

mode.

1 = Halt PWM main clock generator when the part is in wait mode.

CENTR — Center-Aligned Output Mode

To avoid irregularities in the PWM output mode, write the CENTR bit

only when PWM channels are disabled.

0 = PWM channels operate in left-aligned output mode

1 = PWM channels operate in center-aligned output mode

RDPP — Reduced Drive of Port P

0 = All port P output pins have normal drive capability.

1 = All port P output pins have reduced drive capability.

PUPP — Pull-Up Port P Enable

0 = All port P pins have an active pull-up device disabled.

1 = All port P pins have an active pull-up device enabled.

PSBCK — PWM Stops while in Background Mode

0 = Allows PWM to continue while in background mode.

1 = Disable PWM input clock when the part is in background mode.

PWCTL — PWM Control Register $0054

Bit 7 6 5 4 3 2 1 Bit 0

0 0 0 PSWAI CENTR RDPP PUPP PSBCK

RESET: 0 0 0 0 0 0 0 0

Pulse-Width Modulator

MC68HC912DG128

166 Pulse-Width Modulator MOTOROLA

Read anytime but write only in special mode (SMODN = 0). These bits

are available only in special mode and are reset in normal mode.

DISCR — Disable Reset of Channel Counter on Write to Channel

Counter

0 = Normal operation. Write to PWM channel counter will reset

channel counter.

1 = Write to PWM channel counter does not reset channel counter.

DISCP — Disable Compare Count Period

0 = Normal operation

1 = In left-aligned output mode, match of period does not reset the

associated PWM counter register.

DISCAL — Disable Load of Scale-Counters on Write to the Associated

Scale-Registers

0 = Normal operation

1 = Write to PWSCAL0 and PWSCAL1 does not load scale

counters

PWTST — PWM Special Mode Register (“Test”) $0055

Bit 7 6 5 4 3 2 1 Bit 0

DISCR DISCP DISCAL 0 0 0 0 0

RESET: 0 0 0 0 0 0 0 0

14-pwm

Pulse-Width Modulator

PWM Register Descriptions

MC68HC912DG128

MOTOROLA Pulse-Width Modulator 167

15-pwm

PORTP can be read anytime.

PWM functions share port P pins 3 to 0 and take precedence over the

general-purpose port when enabled.

When configured as input, a read will return the pin level. For port bits 7

to 4 it will read zero because there are no available external pins.

When configured as output, a read will return the latched output data.

For port bits 7 to 4 it will read the last value written. A write will drive

associated pins only if configured for output and the corresponding PWM

channel is not enabled.

After reset, all pins are general-purpose, high-impedance inputs.

DDRP determines pin direction of port P when used for general-purpose

I/O.

DDRP[7:4] — This bits served as memory locations since there are no

corresponding port pins.

DDRP[3:0] — Data Direction Port P pin 0-3

0 = I/O pin configured as high impedance input

1 = I/O pin configured for output.

PORTP — Port P Data Register $0056

Bit 7 6 5 4 3 2 1 Bit 0

PP7 PP6 PP5 PP4 PP3 PP2 PP1 PP0

PWM – – – – PWM3 PWM2 PWM1 PWM0

RESET: – – – – – – – –

DDRP — Port P Data Direction Register $0057

Bit 7 6 5 4 3 2 1 Bit 0

DDP7 DDP6 DDP5 DDP4 DDP3 DDP2 DDP1 DDP0

RESET: 0 0 0 0 0 0 0 0

Pulse-Width Modulator

MC68HC912DG128

168 Pulse-Width Modulator MOTOROLA

PWM Boundary Cases

The boundary conditions for the PWM channel duty registers and the

PWM channel period registers cause these results:

Table 26 PWM Left-Aligned Boundary Conditions

PWDTYx PWPERx PPOLx Output

$FF >$00 1 Low

$FF >$00 0 High

≥PWPERx – 1 High

≥PWPERx – 0 Low

– $00 1 High

– $00 0 Low

Table 27 PWM Center-Aligned Boundary Conditions

PWDTYx PWPERx PPOLx Output

$00 >$00 1 Low

$00 >$00 0 High

≥PWPERx – 1 High

≥PWPERx – 0 Low

– $00 1 High

– $00 0 Low

16-pwm

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 169

Enhanced Capture Timer

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169

Enhanced Capture Timer Modes of Operation . . . . . . . . . . . . . . . . .176

Timer Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179

Timer and Modulus Counter Operation in Different Modes. . . . . . . .204

Introduction

The HC12 Enhanced Capture Timer module has the features of the

HC12 Standard Timer module enhanced by additional features in order

to enlarge the field of applications, in particular for automotive ABS

applications.

The additional features permit the operation of this timer module in a

mode similar to the Input Control Timer implemented on

MC68HC11NB4.

These additional features are:

• 16-Bit Buffer Register for four Input Capture (IC) channels.

• Four 8-Bit Pulse Accumulators with 8-bit buffer registers

associated with the four buffered IC channels. Configurable also

as two 16-Bit Pulse Accumulators.

• 16-Bit Modulus Down-Counter with 4-bit Prescaler.

• Four user selectable Delay Counters for input noise immunity

increase.

• Main Timer Prescaler extended to 7-bit.

1-ect

Enhanced Capture Timer

MC68HC912DG128

170 Enhanced Capture Timer MOTOROLA

This design specification describes the standard timer as well as the

additional features.

The basic timer consists of a 16-bit, software-programmable counter

driven by a prescaler. This timer can be used for many purposes,

including input waveform measurements while simultaneously

generating an output waveform. Pulse widths can vary from

microseconds to many seconds.

A full access for the counter registers or the input capture/output

compare registers should take place in one clock cycle. Accessing high

byte and low byte separately for all of these registers may not yield the

same result as accessing them in one word.

2--ect

Enhanced Capture Timer

Introduction

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 171

Figure 26 Timer Block Diagram in Latch Mode

16 BIT MAIN TIMER

PT1

Comparator

TC0H hold register

PT0

PT3

PT2

PT4

PT5

PT6

PT7

EDG0

EDG1

EDG2

EDG3

MUX

Prescaler

M clock

16-bit load register

16-bit modulus

0RESET

EDG0

EDG1

EDG2

EDG4

EDG5

EDG3

EDG6

EDG7

÷ 1, 2, ..., 128

÷ 1, 4, 8, 16

16-bit Free-running

LATCH

Underflow

main timer

Prescaler

TC0 capture/compare register

Comparator

TC1 capture/compare register

Comparator

TC2 capture/compare register

Comparator

TC3 capture/compare register

Comparator

TC4 capture/compare register

Comparator

TC5 capture/compare register

Comparator

TC6 capture/compare register

Comparator

TC7 capture/compare register

Pin logic

Delay counter

M clock

TC1H hold register

TC2H hold register

TC3H hold register

MUX

PA0H hold register

PAC0

0RESET

PA1H hold register

PAC1

0RESET

PA2H hold register

PAC2

0RESET

PA3H hold register

PAC3

Write $0000

to modulus counter

ICLAT, LATQ, BUFEN

(force latch)

LATQ

(MDC latch enable)

down counter

3-ect

Enhanced Capture Timer

MC68HC912DG128

172 Enhanced Capture Timer MOTOROLA

Figure 27 Timer Block Diagram in Queue Mode

16 BIT MAIN TIMER

PT1

Comparator

TC0H hold register

PT0

PT3

PT2

PT4

PT5

PT6

PT7

EDG0

EDG1

EDG2

EDG3

MUX

Prescaler

M clock

16-bit load register

16-bit modulus

0RESET

EDG0

EDG1

EDG2

EDG4

EDG5

EDG3

EDG6

EDG7

÷1, 2, ..., 128

÷ 1, 4, 8, 16

16-bit Free-running

LATCH0

main timer

Prescaler

TC0 capture/compare register

Comparator

TC1 capture/compare register

Comparator

TC2 capture/compare register

Comparator

TC3 capture/compare register

Comparator

TC4 capture/compare register

Comparator

TC5 capture/compare register

Comparator

TC6 capture/compare register

Comparator

TC7 capture/compare register

Pin logic

Delay counter

M clock

TC1H hold register

TC2H hold register

TC3H hold register

MUX

PA0H hold register

PAC0

0RESET

PA1H hold register

PAC1

0RESET

PA2H hold register

PAC2

0RESET

PA3H hold register

PAC3

LATCH1

LATCH3 LATCH2

LATQ, BUFEN

(queue mode)

Read TC3H

hold register

Read TC2H

hold register

Read TC1H

hold register

Read TC0H

hold register

down counter

4-ect

Enhanced Capture Timer

Introduction

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 173

Figure 28 8-Bit Pulse Accumulators Block Diagram

Host CPU data bus

PT0

Load holding register and reset pulse accumulator

EDG3

EDG2

EDG1

EDG0

Edge detector Delay counter

Interrupt

PT1 Edge detector Delay counter

PT2 Edge detector Delay counter

PT3 Edge detector Delay counter

8-bit PAC0 (PACN0)

PA0H holding register

8-bit PAC1 (PACN1)

PA1H holding register

8-bit PAC2 (PACN2)

PA2H holding register

8-bit PAC3 (PACN3)

PA3H holding register

5-ect

Enhanced Capture Timer

MC68HC912DG128

174 Enhanced Capture Timer MOTOROLA

Figure 29 16-Bit Pulse Accumulators Block Diagram

Edge detector

8-bit PAC2

Intermodule Bus

8-bit PAC3

PT7

PT0

M clock

Divide by 64

Clock select

CLK0

CLK1 4:1 MUX

TIMCLK

PACLK

PACLK / 256

PA CLK / 65536

Prescaled clock

from timer

(Timer clock)

Interrupt

MUX

(PAMOD)

Edge detector

PACA

Delay counter

(PACN3) (PACN2)

8-bit PAC08-bit PAC1

Interrupt

PACB

(PACN1) (PACN0)

6-ect

Enhanced Capture Timer

Introduction

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 175

7-ect

Figure 30 Block Diagram for Port7 with Output compare / Pulse Accumulator A

Figure 31 C3F-C0F Interrupt Flag Setting

Pulse accumulator A PAD

(OM7=1 or OL7=1) or (OC7M7 = 1)

OC7

PTn Edge detector Delay counter

16-bit Main Timer

TCn Input Capture Reg.

TCnH I.C. Holding Reg. BUFEN • LATQ • TFMOD

Set CnF Interrupt

Enhanced Capture Timer

MC68HC912DG128

176 Enhanced Capture Timer MOTOROLA

Enhanced Capture Timer Modes of Operation

The Enhanced Capture Timer has 8 Input Capture, Output Compare (IC/

OC) channels same as on the HC12 standard timer (timer channels TC0

to TC7). When channels are selected as input capture by selecting the

IOSx bit in TIOS register, they are called Input Capture (IC) channels.

Four IC channels are the same as on the standard timer with one capture

associated input pin.

Four other IC channels, in addition to the capture register, have also one

buffer called holding register. This permits to memorize two different

timer values without generation of any interrupt.

Four 8-bit pulse accumulators are associated with the four buffered IC

channels. Each pulse accumulator has a holding register to memorize

their value by an action on its external input. Each pair of pulse

accumulators can be used as a 16-bit pulse accumulator.

The 16-bit modulus down-counter can control the transfer of the IC

registers contents and the pulse accumulators to the respective holding

registers for a given period, every time the count reaches zero.

The modulus down-counter can also be used as a stand-alone time base

with periodic interrupt capability.

IC Channels The IC channels are composed of four standard IC registers and four

buffered IC channels.

An IC register is empty when it has been read or latched into the

holding register.

A holding register is empty when it has been read.

Non-Buffered IC

Channels The main timer value is memorized in the IC register by a valid input pin

transition. If the corresponding NOVWx bit of the ICOVW register is

cleared, with a new occurrence of a capture, the contents of IC register

are overwritten by the new value.

8-ect

Enhanced Capture Timer

Enhanced Capture Timer Modes of Operation

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 177

9-ect

If the corresponding NOVWx bit of the ICOVW register is set, the

capture register cannot be written unless it is empty.

This will prevent the captured value to be overwritten until it is read.

Buffered IC

Channels There are two modes of operations for the buffered IC channels.

• IC Latch Mode:

When enabled (LATQ=1), the main timer value is memorized in the IC

The value of the buffered IC register is latched to its holding register by

the Modulus counter for a given period when the count reaches zero, by

a write $0000 to the modulus counter or by a write to ICLAT in the

MCCTL register.

If the corresponding NOVWx bit of the ICOVW register is cleared, with a

new occurrence of a capture, the contents of IC register are overwritten

by the new value. In case of latching, the contents of its holding register

are overwritten.

If the corresponding NOVWx bit of the ICOVW register is set, the capture

are empty (see IC Channels). This will prevent the captured value to be

overwritten until it is read or latched in the holding register.

• IC queue mode:

When enabled (LATQ=0), the main timer value is memorized in the IC

If the corresponding NOVWx bit of the ICOVW register is cleared, with a

new occurrence of a capture, the value of the IC register will be transferred

to its holding register and the IC register memorizes the new timer value.

If the corresponding NOVWx bit of the ICOVW register is set, the capture

are empty (see IC Channels).

In queue mode, reads of holding register will latch the corresponding

pulse accumulator value to its holding register.

Enhanced Capture Timer

MC68HC912DG128

178 Enhanced Capture Timer MOTOROLA

Pulse

Accumulators

There are four 8-bit pulse accumulators with four 8-bit holding registers

associated with the four IC buffered channels. A pulse accumulator

counts the number of active edges at the input of its channel.

The user can prevent 8-bit pulse accumulators counting further than $FF

by PACMX control bit in ICSYS ($AB). In this case a value of $FF means

that 255 counts or more have occurred.

Each pair of pulse accumulators can be used as a 16-bit pulse

accumulator.

There are two modes of operation for the pulse accumulators.

Pulse

Accumulator

latch mode

The value of the pulse accumulator is transferred to its holding register

when the modulus down-counter reaches zero, a write $0000 to the

modulus counter or when the force latch control bit ICLAT is written.

At the same time the pulse accumulator is cleared.

Pulse

Accumulator

queue mode

When queue mode is enabled, reads of an input capture holding register

will transfer the contents of the associated pulse accumulator to its

holding register.

At the same time the pulse accumulator is cleared.

Modulus

Down-Counter

The modulus down-counter can be used as a time base to generate a

periodic interrupt. It can also be used to latch the values of the IC

registers and the pulse accumulators to their holding registers.

The action of latching can be programmed to be periodic or only once.

10-ect

Enhanced Capture Timer

Timer Register Descriptions

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 179

11-ect

Timer Register Descriptions

Input/output pins default to general-purpose I/O lines until an internal

function which uses that pin is specifically enabled. The timer overrides

the state of the DDR to force the I/O state of each associated port line

when an output compare using a port line is enabled. In these cases the

data direction bits will have no affect on these lines.

When a pin is assigned to output an on-chip peripheral function, writing

to this PORTT bit does not affect the pin but the data is stored in an

internal latch such that if the pin becomes available for general-purpose

output the driven level will be the last value written to the PORTT bit.

Read or write anytime.

IOS[7:0] — Input Capture or Output Compare Channel Configuration

0 = The corresponding channel acts as an input capture

1 = The corresponding channel acts as an output compare.

Read anytime but will always return $00 (1 state is transient). Write

anytime.

FOC[7:0] — Force Output Compare Action for Channel 7-0

A write to this register with the corresponding data bit(s) set causes

the action which is programmed for output compare “n” to occur

immediately. The action taken is the same as if a successful

comparison had just taken place with the TCn register except the

interrupt flag does not get set.

TIOS — Timer Input Capture/Output Compare Select $0080

Bit 7 6 5 4 3 2 1 Bit 0

IOS7 IOS6 IOS5 IOS4 IOS3 IOS2 IOS1 IOS0

RESET: 0 0 0 0 0 0 0 0

CFORC — Timer Compare Force Register $0081

Bit 7 6 5 4 3 2 1 Bit 0

FOC7 FOC6 FOC5 FOC4 FOC3 FOC2 FOC1 FOC0

RESET: 0 0 0 0 0 0 0 0

Enhanced Capture Timer

MC68HC912DG128

180 Enhanced Capture Timer MOTOROLA

Read or write anytime.

The bits of OC7M correspond bit-for-bit with the bits of timer port

(PORTT). Setting the OC7Mn will set the corresponding port to be an

output port regardless of the state of the DDRTn bit when the

corresponding TIOSn bit is set to be an output compare. This does not

change the state of the DDRT bits. At successful OC7, for eachbit that

is set in OC7M, the corresponding data bit in OC7D is stored to the

corresponding bit of the timer port.

NOTE:

OC7M has priority over output action on timer port enabled by OMn and

OLn bits in TCTL1 and TCTL2. If an OC7M bit is set, it prevents the

action of corresponding OM and OL bits on the selected timer port.

Read or write anytime.

The bits of OC7D correspond bit-for-bit with the bits of timer port

(PORTT). When a successful OC7 compare occurs, for each bit that is

set in OC7M, the corresponding data bit in OC7D is stored to the

corresponding bit of the timer port.

When the OC7Mn bit is set, a successful OC7 action will override a

successful OC[6:0] compare action during the same cycle; therefore, the

OCn action taken will depend on the corresponding OC7D bit.

OC7M — Output Compare 7 Mask Register $0082

Bit 7 6 5 4 3 2 1 Bit 0

OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7M0

RESET: 0 0 0 0 0 0 0 0

OC7D — Output Compare 7 Data Register $0083

Bit 7 6 5 4 3 2 1 Bit 0

OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0

RESET: 0 0 0 0 0 0 0 0

12-ect

Enhanced Capture Timer

Timer Register Descriptions

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 181

13-ect

The 16-bit main timer is an up counter.

A full access for the counter register should take place in one clock cycle.

A separate read/write for high byte and low byte will give a different result

than accessing them as a word.

Read anytime.

Write has no meaning or effect in the normal mode; only writable in

special modes (SMODN = 0).

The period of the first count after a write to the TCNT registers may be a

different size because the write is not synchronized with the prescaler

clock.

Read or write anytime.

TEN — Timer Enable

0 = Disables the main timer, including the counter. Can be used for

reducing power consumption.

1 = Allows the timer to function normally.

If for any reason the timer is not active, there is no ÷64 clock for the

pulse accumulator since the E÷64 is generated by the timer prescaler.

TSWAI — Timer Module Stops While in Wait

0 = Allows the timer module to continue running during wait.

1 = Disables the timer module when the MCU is in the wait mode.

Timer interrupts cannot be used to get the MCU out of wait.

TSWAI also affects pulse accumulators and modulus down counters.

TCNT — Timer Count Register $0084–$0085

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 6 5 4 3 2 1 Bit 0

RESET: 0 0 0 0 0 0 0 0

TSCR — Timer System Control Register $0086

Bit 7 6 5 4 3 2 1 Bit 0

TEN TSWAI TSBCK TFFCA

RESET: 0 0 0 0 0 0 0 0

Enhanced Capture Timer

MC68HC912DG128

182 Enhanced Capture Timer MOTOROLA

TSBCK — Timer and Modulus Counter Stop While in Background Mode

0 = Allows the timer and modulus counter to continue running while

in background mode.

1 = Disables the timer and modulus counter whenever the MCU is

in background mode. This is useful for emulation.

TBSCK does not stop the pulse accumulator.

TFFCA — Timer Fast Flag Clear All

0 = Allows the timer flag clearing to function normally.

1 = For TFLG1($8E), a read from an input capture or a write to the

output compare channel ($90–$9F) causes the corresponding

channel flag, CnF, to be cleared. For TFLG2 ($8F), any access

to the TCNT register ($84, $85) clears the TOF flag. Any

access to the PACN3 and PACN2 registers ($A2, $A3) clears

the PAOVF and PAIF flags in the PAFLG register ($A1). Any

access to the PACN1 and PACN0 registers ($A4, $A5) clears

the PBOVF flag in the PBFLG register ($B1). This has the

advantage of eliminating software overhead in a separate clear

sequence. Extra care is required to avoid accidental flag

clearing due to unintended accesses.

14-ect

Enhanced Capture Timer

Timer Register Descriptions

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 183

15-ect

Read or write anytime.

OMn — Output Mode

OLn — Output Level

These eight pairs of control bits are encoded to specify the output

action to be taken as a result of a successful OCn compare. When

either OMn or OLn is one, the pin associated with OCn becomes an

output tied to OCn regardless of the state of the associated DDRT bit.

NOTE:

To enable output action by OMn and OLn bits on timer port, the

corresponding bit in OC7M should be cleared.

To operate the 16-bit pulse accumulators A and B (PACA and PACB)

independently of input capture or output compare 7 and 0 respectively

the user must set the corresponding bits IOSn = 1, OMn = 0 and OLn

= 0. OC7M7 or OC7M0 in the OC7M register must also be cleared.

TQCR — Reserved $0087

Bit 7 6 5 4 3 2 1 Bit 0

RESET: 0 0 0 0 0 0 0 0

TCTL1 — Timer Control Register 1 $0088

Bit 7 6 5 4 3 2 1 Bit 0

OM7 OL7 OM6 OL6 OM5 OL5 OM4 OL4

RESET: 0 0 0 0 0 0 0 0

TCTL2 — Timer Control Register 2 $0089

Bit 7 6 5 4 3 2 1 Bit 0

OM3 OL3 OM2 OL2 OM1 OL1 OM0 OL0

RESET: 0 0 0 0 0 0 0 0

Table 28 Compare Result Output Action

OMn OLn Action

0 0 Timer disconnected from output pin logic

0 1 Toggle OCn output line

1 0 Clear OCn output line to zero

1 1 Set OCn output line to one

Enhanced Capture Timer

MC68HC912DG128

184 Enhanced Capture Timer MOTOROLA

Read or write anytime.

EDGnB, EDGnA — Input Capture Edge Control

These eight pairs of control bits configure the input capture edge

detector circuits.

Read or write anytime.

The bits in TMSK1 correspond bit-for-bit with the bits in the TFLG1

status register. If cleared, the corresponding flag is disabled from

causing a hardware interrupt. If set, the corresponding flag is enabled to

cause a hardware interrupt.

Read or write anytime.

C7I–C0I — Input Capture/Output Compare “x” Interrupt Enable.

TCTL3 — Timer Control Register 3 $008A

Bit 7 6 5 4 3 2 1 Bit 0

EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A

RESET: 0 0 0 0 0 0 0 0

TCTL4 — Timer Control Register 4 $008B

Bit 7 6 5 4 3 2 1 Bit 0

EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDG0B EDG0A

RESET: 0 0 0 0 0 0 0 0

Table 2 Edge Detector Circuit Configuration

EDGnB EDGnA Configuration

0 0 Capture disabled

0 1 Capture on rising edges only

1 0 Capture on falling edges only

1 1 Capture on any edge (rising or falling)

TMSK1 — Timer Interrupt Mask 1 $008C

Bit 7 6 5 4 3 2 1 Bit 0

C7I C6I C5I C4I C3I C2I C1I C0I

RESET: 0 0 0 0 0 0 0 0

16-ect

Enhanced Capture Timer

Timer Register Descriptions

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 185

17-ect

Read or write anytime.

TOI — Timer Overflow Interrupt Enable

0 = Interrupt inhibited

1 = Hardware interrupt requested when TOF flag set

PUPT — Timer Port Pull-Up Resistor Enable

This enable bit controls pull-up resistors on the timer port pins when

the pins are configured as inputs.

0 = Disable pull-up resistor function

1 = Enable pull-up resistor function

RDPT — Timer Port Drive Reduction

This bit reduces the effective output driver size which can reduce

power supply current and generated noise depending upon pin

0 = Normal output drive capability

1 = Enable output drive reduction function

TCRE — Timer Counter Reset Enable

This bit allows the timer counter to be reset by a successful output

compare 7 event. This mode of operation is similar to an up-counting

modulus counter.

0 = Counter reset inhibited and counter free runs

1 = Counter reset by a successful output compare 7

If TC7 = $0000 and TCRE = 1, TCNT will stay at $0000 continuously.

If TC7 = $FFFF and TCRE = 1, TOF will never be set when TCNT is

reset from $FFFF to $0000.

PR2, PR1, PR0 — Timer Prescaler Select

These three bits specify the number of ÷2 stages that are to be

inserted between the module clock and the main timer counter.

TMSK2 — Timer Interrupt Mask 2 $008D

Bit 7 6 5 4 3 2 1 Bit 0

TOI 0 PUPT RDPT TCRE PR2 PR1 PR0

RESET: 0 0 0 0 0 0 0 0

Enhanced Capture Timer

MC68HC912DG128

186 Enhanced Capture Timer MOTOROLA

The newly selected prescale factor will not take effect until the next

synchronized edge where all prescale counter stages equal zero.

TFLG1 indicates when interrupt conditions have occurred. To clear a bit

in the flag register, write a one to the bit.

Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with the

use of the ICOVW register ($AA) allows a timer interrupt to be generated

after capturing two values in the capture and holding registers instead of

generating an interrupt for every capture.

Read anytime. Write used in the clearing mechanism (set bits cause

corresponding bits to be cleared). Writing a zero will not affect current

status of the bit.

When TFFCA bit in TSCR register is set, a read from an input capture or

a write into an output compare channel ($90–$9F) will cause the

corresponding channel flag CnF to be cleared.

C7F–C0F — Input Capture/Output Compare Channel “n” Flag.

Table 29 Prescaler Selection

PR2 PR1 PR0 Prescale Factor

000 1

001 2

010 4

011 8

100 16

101 32

110 64

1 1 1 128

TFLG1 — Main Timer Interrupt Flag 1 $008E

Bit 7 6 5 4 3 2 1 Bit 0

C7F C6F C5F C4F C3F C2F C1F C0F

RESET: 0 0 0 0 0 0 0 0

18-ect

Enhanced Capture Timer

Timer Register Descriptions

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 187

19-ect

TFLG2 indicates when interrupt conditions have occurred. To clear a bit

in the flag register, set the bit to one.

Read anytime. Write used in clearing mechanism (set bits cause

corresponding bits to be cleared).

Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR

TOF — Timer Overflow Flag

Set when 16-bit free-running timer overflows from $FFFF to $0000.

This bit is cleared automatically by a write to the TFLG2 register with

bit 7 set. (See also TCRE control bit explanation.)

TFLG2 — Main Timer Interrupt Flag 2 $008F

Bit 7 6 5 4 3 2 1 Bit 0

TOF 0 0 0 0 0 0 0

RESET: 0 0 0 0 0 0 0 0

TC0 — Timer Input Capture/Output Compare Register 0 $0090–$0091

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 6 5 4 3 2 1 Bit 0

TC1 — Timer Input Capture/Output Compare Register 1 $0092–$0093

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 6 5 4 3 2 1 Bit 0

TC2 — Timer Input Capture/Output Compare Register 2 $0094–$0095

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 6 5 4 3 2 1 Bit 0

TC3 — Timer Input Capture/Output Compare Register 3 $0096–$0097

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 6 5 4 3 2 1 Bit 0

Enhanced Capture Timer

MC68HC912DG128

188 Enhanced Capture Timer MOTOROLA

Depending on the TIOS bit for the corresponding channel, these

registers are used to latch the value of the free-running counter when a

defined transition is sensed by the corresponding input capture edge

detector or to trigger an output action for output compare.

Read anytime. Write anytime for output compare function. Writes to

these registers have no meaning or effect during input capture. All timer

input capture/output compare registers are reset to $0000.

16-Bit Pulse Accumulator A (PACA) is formed by cascading the 8-bit

pulse accumulators PAC3 and PAC2.

When PAEN is set, the PACA is enabled. The PACA shares the input pin

with IC7.

Read: any time

Write: any time

TC4 — Timer Input Capture/Output Compare Register 4 $0098–$0099

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 6 5 4 3 2 1 Bit 0

TC5 — Timer Input Capture/Output Compare Register 5 $009A–$009B

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 6 5 4 3 2 1 Bit 0

TC6 — Timer Input Capture/Output Compare Register 6 $009C–$009D

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 6 5 4 3 2 1 Bit 0

TC7 — Timer Input Capture/Output Compare Register 7 $009E–$009F

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 6 5 4 3 2 1 Bit 0

PACTL — 16-Bit Pulse Accumulator A Control Register $00A0

BIT 7 6 5 4 3 2 1 BIT 0

0 PAEN PAMOD PEDGE CLK1 CLK0 PAOVI PAI

RESET: 0 0 0 0 0 0 0 0

20-ect

Enhanced Capture Timer

Timer Register Descriptions

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 189

21-ect

PAEN — Pulse Accumulator A System Enable

0 = 16-Bit Pulse Accumulator A system disabled. 8-bit PAC3 and

PAC2 can be enabled when their related enable bits in ICPACR

($A8) are set.

Pulse Accumulator Input Edge Flag (PAIF) function is disabled.

1 = Pulse Accumulator A system enabled. The two 8-bit pulse

accumulators PAC3 and PAC2 are cascaded to form the PACA

16-bit pulse accumulator. When PACA in enabled, the PACN3

and PACN2 registers contents are respectively the high and low

byte of the PACA.

PA3EN and PA2EN control bits in ICPACR ($A8) have no effect.

Pulse Accumulator Input Edge Flag (PAIF) function is enabled.

PAEN is independent from TEN. With timer disabled, the pulse

accumulator can still function unless pulse accumulator is disabled.

PAMOD — Pulse Accumulator Mode

0 = event counter mode

1 = gated time accumulation mode

PEDGE — Pulse Accumulator Edge Control

For PAMOD bit = 0 (event counter mode).

0 = falling edges on PT7 pin cause the count to be incremented

1 = rising edges on PT7 pin cause the count to be incremented

For PAMOD bit = 1 (gated time accumulation mode).

0 = PT7 input pin high enables M divided by 64 clock to Pulse

Accumulator and the trailing falling edge on PT7 sets the PAIF

flag.

1 = PT7 input pin low enables M divided by 64 clock to Pulse

Accumulator and the trailing rising edge on PT7 sets the PAIF

flag.

If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64

since the E÷64 clock is generated by the timer prescaler.

PAMOD PEDGE Pin Action

0 0 Falling edge

0 1 Rising edge

1 0 Div. by 64 clock enabled with pin high level

1 1 Div. by 64 clock enabled with pin low level

Enhanced Capture Timer

MC68HC912DG128

190 Enhanced Capture Timer MOTOROLA

CLK1, CLK0 — Clock Select Bits

If the pulse accumulator is disabled (PAEN = 0), the prescaler clock

from the timer is always used as an input clock to the timer counter.

The change from one selected clock to the other happens

immediately after these bits are written.

PAOVI — Pulse Accumulator A Overflow Interrupt enable

0 = interrupt inhibited

1 = interrupt requested if PAOVF is set

PAI — Pulse Accumulator Input Interrupt enable

0 = interrupt inhibited

1 = interrupt requested if PAIF is set

Read or write anytime. When the TFFCA bit in the TSCR register is set,

any access to the PACNT register will clear all the flags in the PAFLG

PAOVF — Pulse Accumulator A Overflow Flag

Set when the 16-bit pulse accumulator A overflows from $FFFF to

$0000,or when 8-bit pulse accumulator 3 (PAC3) overflows from $FF

to $00.

This bit is cleared automatically by a write to the PAFLG register with

bit 1 set.

CLK1 CLK0 Clock Source

0 0 Use timer prescaler clock as timer counter clock

0 1 Use PACLK as input to timer counter clock

1 0 Use PACLK/256 as timer counter clock frequency

Use PACLK/65536 as timer counter clock

frequency

PAFLG — Pulse Accumulator A Flag Register $00A1

BIT 7 6 5 4 3 2 1 BIT 0

0 0 0 0 0 0 PAOVF PAIF

RESET: 0 0 0 0 0 0 0 0

22-ect

Enhanced Capture Timer

Timer Register Descriptions

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 191

23-ect

PAIF — Pulse Accumulator Input edge Flag

Set when the selected edge is detected at the PT7 input pin. In event

mode the event edge triggers PAIF and in gated time accumulation

mode the trailing edge of the gate signal at the PT7 input pin triggers

PAIF.

This bit is cleared by a write to the PAFLG register with bit 0 set.

Any access to the PACN3, PACN2 registers will clear all the flags in

this register when TFFCA bit in register TSCR($86) is set.

Read or write any time.

The two 8-bit pulse accumulators PAC3 and PAC2 are cascaded to form

the PACA 16-bit pulse accumulator. When PACA in enabled (PAEN=1

in PACTL, $A0) the PACN3 and PACN2 registers contents are

respectively the high and low byte of the PACA.

When PACN3 overflows from $FF to $00, the Interrupt flag PAOVF in

PAFLG ($A1) is set.

Full count register access should take place in one clock cycle. A

separate read/write for high byte and low byte will give a different result

than accessing them as a word.

PACN3, PACN2 — Pulse Accumulators Count Registers $00A2, $00A3

BIT 7 6 5 4 3 2 1 BIT 0

$00A2 BIt 7 6 5 4 3 2 1 Bit 0 PACN3 (hi)

$00A3 Bit 7 6 5 4 3 2 1 Bit 0 PACN2 (lo)

RESET: 0 0 0 0 0 0 0 0

Enhanced Capture Timer

MC68HC912DG128

192 Enhanced Capture Timer MOTOROLA

Read or write any time.

The two 8-bit pulse accumulators PAC1 and PAC0 are cascaded to form

the PACB 16-bit pulse accumulator. When PACB in enabled, (PBEN=1

in PBCTL, $B0) the PACN1 and PACN0 registers contents are

respectively the high and low byte of the PACB.

When PACN1 overflows from $FF to $00, the Interrupt flag PBOVF in

PBFLG ($B1) is set.

Full count register access should take place in one clock cycle. A

separate read/write for high byte and low byte will give a different result

than accessing them as a word.

Read or write any time.

MCZI — Modulus Counter Underflow Interrupt Enable

0 = Modulus counter interrupt is disabled.

1 = Modulus counter interrupt is enabled.

MODMC — Modulus Mode Enable

0 = The counter counts once from the value written to it and will

stop at $0000.

1 = Modulus mode is enabled. When the counter reaches $0000,

the counter is loaded with the latest value written to the

modulus count register.

NOTE:

For proper operation, the MCEN bit should be cleared before modifying

the MODMC bit in order to reset the modulus counter to $FF.

PACN1, PACN0 — Pulse Accumulators Count Registers $00A4, $00A5

BIT 7 6 5 4 3 2 1 BIT 0

$00A4 BIt 7 6 5 4 3 2 1 Bit 0 PACN1 (hi)

$00A5 Bit 7 6 5 4 3 2 1 Bit 0 PACN0 (lo)

RESET: 0 0 0 0 0 0 0 0

MCCTL — 16-Bit Modulus Down-Counter Control Register $00A6

BIT 7 6 5 4 3 2 1 BIT 0

MCZI MODMC RDMCL ICLAT FLMC MCEN MCPR1 MCPR0

RESET: 0 0 0 0 0 0 0 0

24-ect

Enhanced Capture Timer

Timer Register Descriptions

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 193

25-ect

RDMCL — Read Modulus Down-Counter Load

0 = Reads of the modulus count register will return the present

value of the count register.

1 = Reads of the modulus count register will return the contents of

the load register.

ICLAT — Input Capture Force Latch Action

When input capture latch mode is enabled (LATQ and BUFEN bit in

ICSYS ($AB) are set), a write one to this bit immediately forces the

contents of the input capture registers TC0 to TC3 and their

corresponding 8-bit pulse accumulators to be latched into the

associated holding registers. The pulse accumulators will be

automatically cleared when the latch action occurs.

Writing zero to this bit has no effect. Read of this bit will return always

zero.

FLMC — Force Load Register into the Modulus Counter Count Register

This bit is active only when the modulus down-counter is enabled

(MCEN=1).

A write one into this bit loads the load register into the modulus

counter count register. This also resets the modulus counter

prescaler.

Write zero to this bit has no effect.

When MODMC=0, counter starts counting and stops at $0000.

Read of this bit will return always zero.

MCEN — Modulus Down-Counter Enable

0 = Modulus counter disabled.

1 = Modulus counter is enabled.

When MCEN=0, the counter is preset to $FFFF. This will prevent an

early interrupt flag when the modulus down-counter is enabled.

MCPR1, MCPR0 — Modulus Counter Prescaler select

These two bits specify the division rate of the modulus counter

prescaler.

Enhanced Capture Timer

MC68HC912DG128

194 Enhanced Capture Timer MOTOROLA

The newly selected prescaler division rate will not be effective until a

load of the load register into the modulus counter count register

occurs.

Read: any time

Write: Only for clearing bit 7

MCZF — Modulus Counter Underflow Interrupt Flag

The flag is set when the modulus down-counter reaches $0000.

A write one to this bit clears the flag. Write zero has no effect.

Any access to the MCCNT register will clear the MCZF flag in this

POLF3 – POLF0 — First Input Capture Polarity Status

This are read only bits. Write to these bits has no effect.

Each status bit gives the polarity of the first edge which has caused

an input capture to occur after capture latch has been read.

Each POLFx corresponds to a timer PORTx input.

0 = The first input capture has been caused by a falling edge.

1 = The first input capture has been caused by a rising edge.

MCPR1 MCPR0 Prescaler division rate

00 1

01 4

10 8

11 16

MCFLG — 16-Bit Modulus Down-Counter FLAG Register $00A7

BIT 7 6 5 4 3 2 1 BIT 0

MCZF 0 0 0 POLF3 POLF2 POLF1 POLF0

RESET: 0 0 0 0 0 0 0 0

26-ect

Enhanced Capture Timer

Timer Register Descriptions

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 195

27-ect

The 8-bit pulse accumulators PAC3 and PAC2 can be enabled only if

PAEN in PATCL ($A0) is cleared. If PAEN is set, PA3EN and PA2EN

have no effect.

The 8-bit pulse accumulators PAC1 and PAC0 can be enabled only if

PBEN in PBTCL ($B0) is cleared. If PBEN is set, PA1EN and PA0EN

have no effect.

Read or write any time.

PAxEN — 8-Bit Pulse Accumulator ‘x’ Enable

0 = 8-Bit Pulse Accumulator is disabled.

1 = 8-Bit Pulse Accumulator is enabled.

Read or write any time.

If enabled, after detection of a valid edge on input capture pin, the delay

counter counts the pre-selected number of M clock (module clock)

cycles, then it will generate a pulse on its output. The pulse is generated

only if the level of input signal, after the preset delay, is the opposite of

the level before the transition.This will avoid reaction to narrow input

pulses.

After counting, the counter will be cleared automatically.

Delay between two active edges of the input signal period should be

longer than the selected counter delay.

ICPAR — Input Control Pulse Accumulators Register $00A8

BIT 7 6 5 4 3 2 1 BIT 0

0 0 0 0 PA3EN PA2EN PA1EN PA0EN

RESET: 0 0 0 0 0 0 0 0

DLYCT — Delay Counter Control Register $00A9

BIT 7 6 5 4 3 2 1 BIT 0

0 0 0 0 0 0 DLY1 DLY0

RESET: 0 0 0 0 0 0 0 0

Enhanced Capture Timer

MC68HC912DG128

196 Enhanced Capture Timer MOTOROLA

DLYx — Delay Counter Select

Read or write any time.

An IC register is empty when it has been read or latched into the holding

A holding register is empty when it has been read.

NOVWx — No Input Capture Overwrite

0 = The contents of the related capture register or holding register

can be overwritten when a new input capture or latch occurs.

1 = The related capture register or holding register cannot be

written by an event unless they are empty (see IC Channels).

This will prevent the captured value to be overwritten until it is

read or latched in the holding register.

Read: any time

Write: May be written once (SMODN=1). Writes are always permitted

when SMODN=0.

DLY1 DLY0 Delay

0 0 Disabled (bypassed)

0 1 256M clock cycles

1 0 512M clock cycles

1 1 1024 M clock cycles

ICOVW — Input Control Overwrite Register $00AA

BIT 7 6 5 4 3 2 1 BIT 0

NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVW0

RESET: 0 0 0 0 0 0 0 0

ICSYS — Input Control System Control Register $00AB

BIT 7 6 5 4 3 2 1 BIT 0

SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ

RESET: 0 0 0 0 0 0 0 0

28-ect

Enhanced Capture Timer

Timer Register Descriptions

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 197

29-ect

SHxy — Share Input action of Input Capture Channels x and y

0 = Normal operation

1 = The channel input ‘x’ causes the same action on the channel

‘y’. The port pin ‘x’ and the corresponding edge detector is

used to be active on the channel ‘y’.

TFMOD — Timer Flag-setting Mode

Use of the TFMOD bit in the ICSYS register ($AB) in conjunction with

the use of the ICOVW register ($AA) allows a timer interrupt to be

generated after capturing two values in the capture and holding

registers instead of generating an interrupt for every capture.

By setting TFMOD in queue mode, when NOVW bit is set and the

corresponding capture and holding registers are emptied, an input

capture event will first update the related input capture register with

the main timer contents. At the next event the TCn data is transferred

to the TCnH register, The TCn is updated and the CnF interrupt flag

is set. See Figure 31.

In all other input capture cases the interrupt flag is set by a valid

external event on PTn.

0 = The timer flags C3F–C0F in TFLG1 ($8E) are set when a valid

input capture transition on the corresponding port pin occurs.

1 = If in queue mode (BUFEN=1 and LATQ=0), the timer flags

C3F–C0F in TFLG1 ($8E) are set only when a latch on the

corresponding holding register occurs.

If the queue mode is not engaged, the timer flags C3F–C0F are

set the same way as for TFMOD=0.

PACMX — 8-Bit Pulse Accumulators Maximum Count

0 = Normal operation. When the 8-bit pulse accumulator has

reached the value $FF, with the next active edge, it will be

incremented to $00.

1 = When the 8-bit pulse accumulator has reached the value $FF,

it will not be incremented further. The value $FF indicates a

count of 255 or more.

Enhanced Capture Timer

MC68HC912DG128

198 Enhanced Capture Timer MOTOROLA

BUFEN — IC Buffer Enable

0 = Input Capture and pulse accumulator holding registers are

disabled.

1 = Input Capture and pulse accumulator holding registers are

enabled. The latching mode is defined by LATQ control bit.

Write one into ICLAT bit in MCCTL ($A6), when LATQ is set

will produce latching of input capture and pulse accumulators

registers into their holding registers.

LATQ — Input Control Latch or Queue Mode Enable

The BUFEN control bit should be set in order to enable the IC and

pulse accumulators holding registers. Otherwise LATQ latching

modes are disabled.

Write one into ICLAT bit in MCCTL ($A6), when LATQ and BUFEN

are set will produce latching of input capture and pulse accumulators

registers into their holding registers.

0 = Queue Mode of Input Capture is enabled.

The main timer value is memorized in the IC register by a valid

input pin transition.

With a new occurrence of a capture, the value of the IC register

will be transferred to its holding register and the IC register

memorizes the new timer value.

1 = Latch Mode is enabled. Latching function occurs when

modulus down-counter reaches zero or a zero is written into

the count register MCCNT (see Buffered IC Channels).

With a latching event the contents of IC registers and 8-bit

pulse accumulators are transferred to their holding registers.

8-bit pulse accumulators are cleared.

30-ect

Enhanced Capture Timer

Timer Register Descriptions

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 199

31-ect

Read: any time

Write: only in special mode (SMOD = 1).

TCBYP — Main Timer Divider Chain Bypass

0 = Normal operation

1 = For testing only. The 16-bit free-running timer counter is divided

into two 8-bit halves and the prescaler is bypassed. The clock

drives both halves directly.

When the high byte of timer counter TCNT ($84) overflows

from $FF to $00, the TOF flag in TFLG2 ($8F) will be set.

Read: any time (inputs return pin level; outputs return data register

contents)

Write: data stored in an internal latch (drives pins only if configured for

output)

Since the Output Compare 7 shares the pin with Pulse Accumulator

input, the only way for Pulse accumulator to receive an independent

input from Output Compare 7 is setting both OM7 & OL7 to be zero, and

also OC7M7 in OC7M register to be zero.

OC7 is still able to reset the counter if enabled while PT7 is used as input

to Pulse Accumulator.

PORTT can be read anytime. When configured as an input, a read will

return the pin level. When configured as an output, a read will return the

latched output data.

TIMTST — Timer Test Register $00AD

BIT 7 6 5 4 3 2 1 BIT 0

0 0 0 0 0 0 TCBYP 0

RESET: 0 0 0 0 0 0 0 0

PORTT — Timer Port Data Register $00AE

BIT 7 6 5 4 3 2 1 BIT 0

PORT PT7 PT6 PT5 PT4 PT3 PT2 PT1 PT0

TIMER I/OC7 I/OC6 I/OC5 I/OC4 I/OC3 I/OC2 I/OC1 I/OC0

RESET: - - - - - - - -

Enhanced Capture Timer

MC68HC912DG128

200 Enhanced Capture Timer MOTOROLA

NOTE:

Writes do not change pin state when the pin is configured for timer

output. The minimum pulse width for pulse accumulator input should

always be greater than the width of two module clocks due to input

synchronizer circuitry. The minimum pulse width for the input capture

should always be greater than the width of two module clocks due to

input synchronizer circuitry.

Read or write any time.

0 = Configures the corresponding I/O pin for input only

1 = Configures the corresponding I/O pin for output.

The timer forces the I/O state to be an output for each timer port line

associated with an enabled output compare. In these cases the data

direction bits will not be changed, but have no effect on the direction

of these pins. The DDRT will revert to controlling the I/O direction of

a pin when the associated timer output compare is disabled. Input

captures do not override the DDRT settings.

Read or write any time.

16-Bit Pulse Accumulator B (PACB) is formed by cascading the 8-bit

pulse accumulators PAC1 and PAC0.

When PBEN is set, the PACB is enabled. The PACB shares the input pin

with IC0.

DDRT — Data Direction Register for Timer Port $00AF

BIT 7 6 5 4 3 2 1 BIT 0

DDT7 DDT6 DDT5 DDT4 DDT3 DDT2 DDT1 DDT0

RESET: 0 0 0 0 0 0 0 0

PBCTL — 16-Bit Pulse Accumulator B Control Register $00B0

BIT 7 6 5 4 3 2 1 BIT 0

0 PBEN 0 0 0 0 PBOVI 0

RESET: 0 0 0 0 0 0 0 0

32-ect

Enhanced Capture Timer

Timer Register Descriptions

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 201

33-ect

PBEN — Pulse Accumulator B System Enable

0 = 16-bit Pulse Accumulator system disabled. 8-bit PAC1 and

PAC0 can be enabled when their related enable bits in

ICPACR ($A8) are set.

1 = Pulse Accumulator B system enabled. The two 8-bit pulse

accumulators PAC1 and PAC0 are cascaded to form the

PACB 16-bit pulse accumulator. When PACB in enabled, the

PACN1 and PACN0 registers contents are respectively the

high and low byte of the PACB.

PA1EN and PA0EN control bits in ICPACR ($A8) have no

effect.

PBEN is independent from TEN. With timer disabled, the pulse

accumulator can still function unless pulse accumulator is disabled.

PBOVI — Pulse Accumulator B Overflow Interrupt enable

0 = interrupt inhibited

1 = interrupt requested if PBOVF is set

Read or write any time.

PBOVF — Pulse Accumulator B Overflow Flag

This bit is set when the 16-bit pulse accumulator B overflows from

$FFFF to $0000, or when 8-bit pulse accumulator 1 (PAC1) overflows

from $FF to $00.

This bit is cleared by a write to the PBFLG register with bit 1 set.

Any access to the PACN1 and PACN0 registers will clear the PBOVF

flag in this register when TFFCA bit in register TSCR($86) is set.

PBFLG — Pulse Accumulator B Flag Register $00B1

BIT 7 6 5 4 3 2 1 BIT 0

0 0 0 0 0 0 PBOVF 0

RESET: 0 0 0 0 0 0 0 0

Enhanced Capture Timer

MC68HC912DG128

202 Enhanced Capture Timer MOTOROLA

Read: any time

Write: has no effect.

These registers are used to latch the value of the corresponding pulse

accumulator when the related bits in register ICPAR ($A8) are enabled

(see Pulse Accumulators).

Read or write any time.

A full access for the counter register should take place in one clock cycle.

A separate read/write for high byte and low byte will give different result

than accessing them as a word.

If the RDMCL bit in MCCTL register is cleared, reads of the MCCNT

bit is set, reads of the MCCNT will return the contents of the load

If a $0000 is written into MCCNT and modulus counter while LATQ and

BUFEN in ICSYS ($AB) register are set, the input capture and pulse

accumulator registers will be latched.

With a $0000 write to the MCCNT, the modulus counter will stay at zero

and does not set the MCZF flag in MCFLG register.

PA3H–PA0H — 8-Bit Pulse Accumulators Holding Registers $00B2–$00B5

BIT 7 6 5 4 3 2 1 BIT 0

$00B2 BIt 7 6 5 4 3 2 1 Bit 0 PA3H

$00B3 Bit 7 6 5 4 3 2 1 Bit 0 PA2H

$00B4 BIt 7 6 5 4 3 2 1 Bit 0 PA1H

$00B5 Bit 7 6 5 4 3 2 1 Bit 0 PA0H

RESET: 0 0 0 0 0 0 0 0

MCCNT — Modulus Down-Counter Count Register $00B6, $00B7

BIT 7 6 5 4 3 2 1 BIT 0

$00B6 BIt 15 14 13 12 11 10 9 Bit 8 MCCNTH

$00B7 Bit 7 6 5 4 3 2 1 Bit 0 MCCNTL

RESET: 1 1 1 1 1 1 1 1

34-ect

Enhanced Capture Timer

Timer Register Descriptions

MC68HC912DG128

MOTOROLA Enhanced Capture Timer 203

35-ect

If modulus mode is enabled (MODMC=1), a write to this address will

update the load register with the value written to it. The count register will

not be updated with the new value until the next counter underflow.

The FLMC bit in MCCTL ($A6) can be used to immediately update the

count register with the new value if an immediate load is desired.

If modulus mode is not enabled (MODMC=0), a write to this address will

clear the prescaler and will immediately update the counter register with

the value written to it and down-counts once to $0000.

Read: any time

Write: has no effect.

These registers are used to latch the value of the input capture registers

TC0 – TC3. The corresponding IOSx bits in TIOS ($80) should be

cleared (see IC Channels).

TC0H — Timer Input Capture Holding Register 0 $00B8–$00B9

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 6 5 4 3 2 1 Bit 0

TC1H — Timer Input Capture Holding Register 1 $00BA–$00BB

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 6 5 4 3 2 1 Bit 0

TC2H — Timer Input Capture Holding Register 2 $00BC–$00BD

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 6 5 4 3 2 1 Bit 0

TC3H — Timer Input Capture Holding Register 3 $00BE–$00BF

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

Bit 7 6 5 4 3 2 1 Bit 0

Enhanced Capture Timer

MC68HC912DG128

204 Enhanced Capture Timer MOTOROLA

Timer and Modulus Counter Operation in Different Modes

STOP: Timer and modulus counter are off since clocks are

stopped.

BGDM: Timer and modulus counter keep on running, unless

TSBCK (REG$86, bit5) is set to one.

WAIT: Counters keep on running, unless TSWAI in TSCR ($86)

is set to one.

NORMAL: Timer and modulus counter keep on running, unless TEN

in TSCR($86) respectively MCEN in MCCTL ($A6) are

cleared.

TEN=0: All 16-bit timer operations are stopped, can only access

the registers.

MCEN=0: Modulus counter is stopped.

PAEN=1: 16-bit Pulse Accumulator A is active.

PAEN=0: 8-Bit Pulse Accumulators 3 and 2 can be enabled. (see

ICPAR)

PBEN=1: 16-bit Pulse Accumulator B is active.

PBEN=0: 8-Bit Pulse Accumulators 1 and 0 can be enabled. (see

ICPAR)

36-ect

MC68HC912DG128

MOTOROLA Multiple Serial Interface 205

Multiple Serial Interface

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205

Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .206

Serial Communication Interface (SCI). . . . . . . . . . . . . . . . . . . . . . . .206

Serial Peripheral Interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . .217

Port S . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226

Introduction

The multiple serial interface (MSI) module consists of three independent

serial I/O sub-systems: two serial communication interfaces (SCI0 and

SCI1) and the serial peripheral interface (SPI). Each serial pin shares

function with the general-purpose port pins of port S. The SCI

subsystems are NRZ type systems that are compatible with standard

RS-232 systems. These SCI systems have a new single wire operation

mode which allows the unused pin to be available as general-purpose I/

O. The SPI subsystem, which is compatible with the M68HC11 SPI,

includes new features such as SS output and bidirectional mode.

1-msi

Multiple Serial Interface

MC68HC912DG128

206 Multiple Serial Interface MOTOROLA

Block diagram

Figure 32 Multiple Serial Interface Block Diagram

Serial Communication Interface (SCI)

Two serial communication interfaces are available on the

MC68HC912DG128. These are NRZ format (one start, eight or nine

data, and one stop bit) asynchronous communication systems with

independent internal baud rate generation circuitry and SCI transmitters

and receivers. They can be configured for eight or nine data bits (one of

which may be designated as a parity bit, odd or even). If enabled, parity

is generated in hardware for transmitted and received data. Receiver

parity errors are flagged in hardware. The baud rate generator is based

on a modulus counter, allowing flexibility in choosing baud rates. There

is a receiver wake-up feature, an idle line detect feature, a loop-back

mode, and various error detection features. Two port pins for each SCI

provide the external interface for the transmitted data (TXD) and the

received data (RXD).

For a faster wake-up out of WAIT mode by a received SCI message,

both SCI have the capability of sending a receiver interrupt, if enabled,

when RAF (receiver active flag) is set. For compatibility with other

PS0

PS1

PS2

PS3

PS4

PS5

PS6

PS7

SCI0

SCI1

SPI

DDRS/IOCTLR

PORT S I/O DRIVERS

MSI RxD0

TxD0

RxD1

TxD1

MISO/SISO

MOSI/MOMI

SCK

CS/SS

HC12A4 MSI BLOCK

2--msi

Multiple Serial Interface

Serial Communication Interface (SCI)

MC68HC912DG128

MOTOROLA Multiple Serial Interface 207

M68HC12 products, this feature is active only in WAIT mode and is

disabled when VDDPLL supply is at VSS level.

Figure 33 Serial Communications Interface Block Diagram

Data Format The serial data format requires the following conditions:

• An idle-line in the high state before transmission or reception of a

message.

Rx Baud Rate

Tx Baud Rate

MCLK

DIVIDER 10-11 Bit SHIFT REG

MSB

TxD BUFFER/SCxDRL

TxMTR CONTROL

SCxCR2/SCI CTL 2

SCxCR1/SCI CTL 1

SCxSR1/INT STATUS

DATA RECOVERY

10-11 BIT SHIFT REG

TxD BUFFER/SCxDRL

SCxBD/SELECT

LSB

RxD

TxD

PIN CONTR OL / DDRS / PORT S

WAKE-UP LOGIC

SCxCR1/SCI CTL 1

SCxSR1/INT STATUS

SCxCR2/SCI CTL 2

INT REQUEST LOGIC

MSB LSB

INT REQUEST LOGIC

SCI RECEIVER

SCI TRANSMITTER

BAUD RATE

CLOCK

INTERNAL

LOGIC

DATA BUS

PARITY

DETECT

PARITY

GENERATOR

HC12A4 SCI BLOCK

3-msi

Multiple Serial Interface

MC68HC912DG128

208 Multiple Serial Interface MOTOROLA

• A start bit (logic zero), transmitted or received, that indicates the

start of each character.

• Data that is transmitted or received least significant bit (LSB) first.

• A stop bit (logic one), used to indicate the end of a frame. (A frame

consists of a start bit, a character of eight or nine data bits and a

stop bit.)

• A BREAK is defined as the transmission or reception of a logic

zero for one frame or more.

• This SCI supports hardware parity for transmit and receive.

SCI Baud Rate

Generation

The basis of the SCI baud rate generator is a 13-bit modulus counter.

This counter gives the generator the flexibility necessary to achieve a

reasonable level of independence from the CPU operating frequency

and still be able to produce standard baud rates with a minimal amount

of error. The clock source for the generator comes from the M Clock.

SCI Register

Descriptions

Control and data registers for the SCI subsystem are described below.

The memory address indicated for each register is the default address

that is in use after reset. Both SCI have identical control registers

mapped in two blocks of eight bytes.

Table 30 Baud Rate Generation

Desired

SCI Baud Rate BR Divisor for

M = 4.0 MHz BR Divisor for

M = 8.0 MHz

110 2273 4545

300 833 2273

600 417 833

1200 208 417

2400 104 208

4800 52 104

9600 26 52

14400 17 35

19200 13 26

38400 — 13

4-msi

Multiple Serial Interface

Serial Communication Interface (SCI)

MC68HC912DG128

MOTOROLA Multiple Serial Interface 209

SCxBDH and SCxBDL are considered together as a 16-bit baud rate

control register.

Read any time. Write SBR[12:0] anytime. Low order byte must be written

for change to take effect. Write SBR[15:13] only in special modes. The

value in SBR[12:0] determines the baud rate of the SCI. The desired

baud rate is determined by the following formula:

which is equivalent to:

BR is the value written to bits SBR[12:0] to establish baud rate.

NOTE:

The baud rate generator is disabled until TE or RE bit in SCxCR2

is disabled when SBR[12:0] = 0.

BTST — Reserved for test function

BSPL — Reserved for test function

BRLD — Reserved for test function

SC0BDH/SC1BDH — SCI Baud Rate Control Register $00C0/$00C8

Bit 7 654321Bit 0

BTST BSPL BRLD SBR12 SBR11 SBR10 SBR9 SBR8 High

RESET: 00000000

SC0BDL/SC1BDL — SCI Baud Rate Control Register $00C1/$00C9

Bit 7 654321Bit 0

SBR7 SBR6 SBR5 SBR4 SBR3 SBR2 SBR1 SBR0 Low

RESET: 00000100

SCI Baud Rate MCLK

16 BR×

--------------------=

BR MCLK

16 SCI Baud Rate×

------------------------------------------------=

5-msi

Multiple Serial Interface

MC68HC912DG128

210 Multiple Serial Interface MOTOROLA

Read or write anytime.

LOOPS — SCI LOOP Mode/Single Wire Mode Enable

0 = SCI transmit and receive sections operate normally.

1 = SCI receive section is disconnected from the RXD pin and the

RXD pin is available as general purpose I/O. The receiver input

is determined by the RSRC bit. The transmitter output is

controlled by the associated DDRS bit. Both the transmitter

and the receiver must be enabled to use the LOOP or the

single wire mode.

If the DDRS bit associated with the TXD pin is set during the LOOPS

= 1, the TXD pin outputs the SCI waveform. If the DDRS bit

associated with the TXD pin is clear during the LOOPS = 1, the TXD

pin becomes high (IDLE line state) for RSRC = 0 and high impedance

for RSRC = 1. Refer to Table 31.

WOMS — Wired-Or Mode for Serial Pins

This bit controls the two pins (TXD and RXD) associated with the SCIx

section.

0 = Pins operate in a normal mode with both high and low drive

capability. To affect the RXD bit, that bit would have to be

configured as an output (via DDRS0/2) which is the single wire

case when using the SCI. WOMS bit still affects

general-purpose output on TXD and RXD pins when SCIx is

not using these pins.

1 = Each pin operates in an open drain fashion if that pin is

declared as an output.

RSRC — Receiver Source

When LOOPS = 1, the RSRC bit determines the internal feedback

path for the receiver.

0 = Receiver input is connected to the transmitter internally (not

TXD pin)

1 = Receiver input is connected to the TXD pin

SC0CR1/SC1CR1 — SCI Control Register 1 $00C2/$00CA

Bit 7 654321Bit 0

LOOPS WOMS RSRC M WAKE ILT PE PT

RESET: 00000000

6-msi

Multiple Serial Interface

Serial Communication Interface (SCI)

MC68HC912DG128

MOTOROLA Multiple Serial Interface 211

7-msi

M — Mode (select character format)

0 = One start, eight data, one stop bit

1 = One start, eight data, ninth data, one stop bit

WAKE — Wake-up by Address Mark/Idle

0 = Wake up by IDLE line recognition

1 = Wake up by address mark (last data bit set)

ILT — Idle Line Type

Determines which of two types of idle line detection will be used by

the SCI receiver.

0 = Short idle line mode is enabled.

1 = Long idle line mode is detected.

In the short mode, the SCI circuitry begins counting ones in the search

for the idle line condition immediately after the start bit. This means

that the stop bit and any bits that were ones before the stop bit could

be counted in that string of ones, resulting in earlier recognition of an

idle line.

In the long mode, the SCI circuitry does not begin counting ones in the

search for the idle line condition until a stop bit is received. Therefore,

the last byte’s stop bit and preceding “1” bits do not affect how quickly

an idle line condition can be detected.

PE — Parity Enable

0 = Parity is disabled.

1 = Parity is enabled.

Table 31 Loop Mode Functions

LOOPS RSRC DDRS1(3) WOMS Function of Port S Bit 1/3

0 x x x Normal Operations

1 0 0 0/1 LOOP mode without TXD output(TXD = High Impedance)

1 0 1 1 LOOP mode with TXD output (CMOS)

1 0 1 1 LOOP mode with TXD output (open-drain)

11 0 x

Single wire mode without TXD output

(the pin is used as receiver input only, TXD = High Impedance)

11 1 0

Single wire mode with TXD output

(the output is also fed back to receiver input, CMOS)

1 1 1 1 Single wire mode for the receiving and transmitting(open-drain)

Multiple Serial Interface

MC68HC912DG128

212 Multiple Serial Interface MOTOROLA

PT — Parity Type

If parity is enabled, this bit determines even or odd parity for both the

receiver and the transmitter.

0 = Even parity is selected. An even number of ones in the data

character causes the parity bit to be zero and an odd number

of ones causes the parity bit to be one.

1 = Odd parity is selected. An odd number of ones in the data

character causes the parity bit to be zero and an even number

of ones causes the parity bit to be one.

Read or write anytime.

TIE — Transmit Interrupt Enable

0 = TDRE interrupts disabled

1 = SCI interrupt will be requested whenever the TDRE status flag

is set.

TCIE — Transmit Complete Interrupt Enable

0 = TC interrupts disabled

1 = SCI interrupt will be requested whenever the TC status flag is

set.

RIE — Receiver Interrupt Enable

0 = RDRF and OR interrupts disabled, RAF interrupt in WAIT mode

disabled

1 = SCI interrupt will be requested whenever the RDRF or OR

status flag is set, or when RAF is set while in WAIT mode with

VDDPLL high.

ILIE — Idle Line Interrupt Enable

0 = IDLE interrupts disabled

1 = SCI interrupt will be requested whenever the IDLE status flag

is set.

SC0CR2/SC1CR2 — SCI Control Register 2 $00C3/$00CB

Bit 7 654321Bit 0

TIE TCIE RIE ILIE TE RE RWU SBK

RESET: 00000000

8-msi

Multiple Serial Interface

Serial Communication Interface (SCI)

MC68HC912DG128

MOTOROLA Multiple Serial Interface 213

9-msi

TE — Transmitter Enable

0 = Transmitter disabled

1 = SCI transmit logic is enabled and the TXD pin (Port S bit 1/bit

3) is dedicated to the transmitter. The TE bit can be used to

queue an idle preamble.

RE — Receiver Enable

0 = Receiver disabled

1 = Enables the SCI receive circuitry.

RWU — Receiver Wake-Up Control

0 = Normal SCI Receiver

1 = Enables the wake-up function and inhibits further receiver

interrupts. Normally hardware wakes the receiver by

automatically clearing this bit.

SBK — Send Break

0 = Break generator off

1 = Generate a break code (at least 10 or 11 contiguous zeros).

As long as SBK remains set the transmitter will send zeros. When

SBK is changed to zero, the current frame of all zeros is finished

before the TxD line goes to the idle state. If SBK is toggled on and off,

the transmitter will send only 10 (or 11) zeros and then revert to mark

idle or sending data.

The bits in these registers are set by various conditions in the SCI

hardware and are automatically cleared by special acknowledge

sequences. The receive related flag bits in SCxSR1 (RDRF, IDLE,

OR, NF, FE, and PF) are all cleared by a read of the SCxSR1 register

followed by a read of the transmit/receive data register low byte.

However, only those bits which were set when SCxSR1 was read will

be cleared by the subsequent read of the transmit/receive data

SC0SR1/SC1SR1 — SCI Status Register 1 $00C4/$00CC

Bit 7 654321Bit 0

TDRE TC RDRF IDLE OR NF FE PF

RESET: 11000000

Multiple Serial Interface

MC68HC912DG128

214 Multiple Serial Interface MOTOROLA

are cleared by a read of the SCxSR1 register followed by a write to

the transmit/receive data register low byte.

Read anytime (used in auto clearing mechanism). Write has no

meaning or effect.

TDRE — Transmit Data Register Empty Flag

New data will not be transmitted unless SCxSR1 is read before writing

to the transmit data register. Reset sets this bit.

0 = SCxDR busy

1 = Any byte in the transmit data register is transferred to the serial

shift register so new data may now be written to the transmit

data register.

TC — Transmit Complete Flag

Flag is set when the transmitter is idle (no data, preamble, or break

transmission in progress). Clear by reading SCxSR1 with TC set and

then writing to SCxDR.

0 = Transmitter busy

1 = Transmitter is idle

RDRF — Receive Data Register Full Flag

Once cleared, IDLE is not set again until the RxD line has been active

and becomes idle again. RDRF is set if a received character is ready

to be read from SCxDR. Clear the RDRF flag by reading SCxSR1 with

RDRF set and then reading SCxDR.

0 = SCxDR empty

1 = SCxDR full

IDLE — Idle Line Detected Flag

Receiver idle line is detected (the receipt of a minimum of 10/11

consecutive ones). This bit will not be set by the idle line condition

when the RWU bit is set. Once cleared, IDLE will not be set again until

after RDRF has been set (after the line has been active and becomes

idle again).

0 = RxD line is idle

1 = RxD line is active

10-msi

Multiple Serial Interface

Serial Communication Interface (SCI)

MC68HC912DG128

MOTOROLA Multiple Serial Interface 215

11-msi

OR — Overrun Error Flag

New byte is ready to be transferred from the receive shift register to

the receive data register and the receive data register is already full

(RDRF bit is set). Data transfer is inhibited until this bit is cleared.

0 = No overrun

1 = Overrun detected

NF — Noise Error Flag

Set during the same cycle as the RDRF bit but not set in the case of

an overrun (OR).

0 = Unanimous decision

1 = Noise on a valid start bit, any of the data bits, or on the stop bit

FE — Framing Error Flag

Set when a zero is detected where a stop bit was expected. Clear the

FE flag by reading SCxSR1 with FE set and then reading SCxDR.

0 = Stop bit detected

1 = Zero detected rather than a stop bit

PF — Parity Error Flag

Indicates if received data’s parity matches parity bit. This feature is

active only when parity is enabled. The type of parity tested for is

determined by the PT (parity type) bit in SCxCR1.

0 = Parity correct

1 = Incorrect parity detected

Read anytime. Write has no meaning or effect.

RAF — Receiver Active Flag

This bit is controlled by the receiver front end. It is set during the RT1

time period of the start bit search. It is cleared when an idle state is

detected or when the receiver circuitry detects a false start bit

(generally due to noise or baud rate mismatch).

SC0SR2/SC1SR2 — SCI Status Register 2 $00C5/$00CD

Bit 7 654321Bit 0

0000000RAF

RESET: 00000000

Multiple Serial Interface

MC68HC912DG128

216 Multiple Serial Interface MOTOROLA

0 = A character is not being received

1 = A character is being received

If enabled with RIE = 1, RAF set generates an interrupt when

VDDPLL is high while in WAIT mode.

R8 — Receive Bit 8

Read anytime. Write has no meaning or affect.

This bit is the ninth serial data bit received when the SCI system is

configured for nine-data-bit operation.

T8 — Transmit Bit 8

Read or write anytime.

This bit is the ninth serial data bit transmitted when the SCI system is

configured for nine-data-bit operation. When using 9-bit data format

this bit does not have to be written for each data word. The same

value will be transmitted as the ninth bit until this bit is rewritten.

R7/T7–R0/T0 — Receive/Transmit Data Bits 7 to 0

Reads access the eight bits of the read-only SCI receive data register

(RDR). Writes access the eight bits of the write-only SCI transmit data

SCI. If the SCI is being used with a 7- or 8-bit data word, only SCxDRL

needs to be accessed. If a 9-bit format is used, the upper register

should be written first to ensure that it is transferred to the transmitter

shift register with the lower register.

SC0DRH/SC1DRH — SCI Data Register High $00C6/$00CE

Bit 7 654321Bit 0

R8T8000000

RESET: ————————

SC0DRL/SC1DRL — SCI Data Register Low $00C7/$00CF

Bit 7 654321Bit 0

R7/T7 R6/T6 R5/T5 R4/T4 R3/T3 R2/T2 R1/T1 R0/T0

RESET: ————————

12-msi

Multiple Serial Interface

Serial Peripheral Interface (SPI)

MC68HC912DG128

MOTOROLA Multiple Serial Interface 217

13-msi

Serial Peripheral Interface (SPI)

The serial peripheral interface allows the MC68HC912DG128 to

communicate synchronously with peripheral devices and other

microprocessors. The SPI system in the MC68HC912DG128 can

operate as a master or as a slave. The SPI is also capable of

interprocessor communications in a multiple master system.

When the SPI is enabled, all pins that are defined by the configuration

as inputs will be inputs regardless of the state of the DDRS bits for those

pins. All pins that are defined as SPI outputs will be outputs only if the

DDRS bits for those pins are set. Any SPI output whose corresponding

DDRS bit is cleared can be used as a general-purpose input.

A bidirectional serial pin is possible using the DDRS as the direction

control.

SPI Baud Rate

Generation

The E Clock is input to a divider series and the resulting SPI clock rate

may be selected to be E divided by 2, 4, 8, 16, 32, 64, 128 or 256. Three

bits in the SP0BR register control the SPI clock rate. This baud rate

generator is activated only when SPI is in the master mode and serial

transfer is taking place. Otherwise this divider is disabled to save power.

SPI Operation In the SPI system the 8-bit data register in the master and the 8-bit data

a data transfer operation is performed, this 16-bit register is serially

shifted eight bit positions by the SCK clock from the master so the data

is effectively exchanged between the master and the slave. Data written

to the SP0DR register of the master becomes the output data for the

slave and data read from the SP0DR register of the master after a

transfer operation is the input data from the slave.

Multiple Serial Interface

MC68HC912DG128

218 Multiple Serial Interface MOTOROLA

Figure 34 Serial Peripheral Interface Block Diagram

A clock phase control bit (CPHA) and a clock polarity control bit (CPOL)

in the SP0CR1 register select one of four possible clock formats to be

used by the SPI system. The CPOL bit simply selects non-inverted or

inverted clock. The CPHA bit is used to accommodate two

fundamentally different protocols by shifting the clock by one half cycle

or no phase shift.

CONTROL

LOGIC

8-BIT SHIFT REGISTER

READ DATA BUFFER

SHIFT CONTROL LOGIC

CLOCK

LOGIC

SPI CONTROL

SP0SR SPI STATUS REGISTER

SP0DR SPI DATA REGISTER

SPIF

WCOL

MODF

DIVIDER

SELECT

SP0BR SPI BAUD RATE REGISTER

÷2÷4÷8÷16 ÷32 ÷64 ÷128 ÷256

SPI

INTERRUPT

INTERNAL BUS

MCU P CLOCK

(SAME AS E RATE) S

SPR2

SPR1

SPR0

REQUEST

SPIE

SPE

MSTR

CPOL

CPHA

LSBF

PUPS

RDS

SWOM

SPC0

SSOE

SPE

CLOCK

MSTR

SWOM

MISO

PS4

SCK

PS6

PS7

MOSI

PS5

HC12 SPI BLOCK

SP0CR1 SPI CONTROL REGISTER 1 SP0CR2 SPI CONTROL REGISTER 2

14-msi

Multiple Serial Interface

Serial Peripheral Interface (SPI)

MC68HC912DG128

MOTOROLA Multiple Serial Interface 219

15-msi

Figure 35 SPI Clock Format 0 (CPHA = 0)

Begin End

SCK (CPOL=0)

SAMPLE I

CHANGE O

SEL SS (O)

Transfer

SCK (CPOL=1)

MSB ﬁrst (LSBF=0):

LSB ﬁrst (LSBF=1): MSB

LSB LSB

MSB

Bit 5

Bit 2

Bit 6

Bit 1 Bit 4

Bit 3 Bit 3

Bit 4 Bit 2

Bit 5 Bit 1

Bit 6

CHANGE O

SEL SS (I)

(MOSI pin)

(MISO pin)

(Master only)

(MOSI/MISO)

If next transfer begins here

for tT, tl, tL

Minimum 1/2 SCK

tItL

HC12 SPI CLOCK FORM 0

Multiple Serial Interface

MC68HC912DG128

220 Multiple Serial Interface MOTOROLA

Figure 36 SPI Clock Format 1 (CPHA = 1)

SS Output Available in master mode only, SS output is enabled with the SSOE bit

in the SP0CR1 register if the corresponding DDRS is set. The SS output

pin will be connected to the SS input pin of the external slave device. The

SS output automatically goes low for each transmission to select the

external device and it goes high during each idling state to deselect

external devices.

tLtT

for tT, tl, tL

Minimum 1/2 SCK

tItL

If next transfer begins here

Begin End

SCK (CPOL=0)

SAMPLE I

CHANGE O

SEL SS (O)

Transfer

SCK (CPOL=1)

MSB ﬁrst (LSBF=0):

LSB ﬁrst (LSBF=1): MSB

LSB LSB

MSB

Bit 5

Bit 2

Bit 6

Bit 1 Bit 4

Bit 3 Bit 3

Bit 4 Bit 2

Bit 5 Bit 1

Bit 6

CHANGE O

SEL SS (I)

(MOSI pin)

(MISO pin)

(Master only)

(MOSI/MISO)

HC12 SPI CLOCK FORM 1

Table 32 SS Output Selection

DDRS7 SSOE Master Mode Slave Mode

00SS Input with MODF Feature SS Input

0 1 Reserved SS Input

1 0 General-Purpose Output SS Input

11 SS Output SS Input

16-msi

Multiple Serial Interface

Serial Peripheral Interface (SPI)

MC68HC912DG128

MOTOROLA Multiple Serial Interface 221

17-msi

Bidirectional

Mode (MOMI or

SISO)

In bidirectional mode, the SPI uses only one serial data pin for external

device interface. The MSTR bit decides which pin to be used. The MOSI

pin becomes serial data I/O (MOMI) pin for the master mode, and the

MISO pin becomes serial data I/O (SISO) pin for the slave mode. The

direction of each serial I/O pin depends on the corresponding DDRS bit.

Descriptions

Control and data registers for the SPI subsystem are described below.

The memory address indicated for each register is the default address

that is in use after reset. For more information refer to Operating

Modes.

Read or write anytime.

SPIE — SPI Interrupt Enable

0 = SPI interrupts are inhibited

1 = Hardware interrupt sequence is requested each time the SPIF

or MODF status flag is set

Figure 37 Normal Mode and Bidirectional Mode

When SPE=1 Master Mode

MSTR=1 Slave Mode

MSTR=0

Normal

Mode

SPC0=0

SWOM enables open drain output. SWOM enables open drain output.

Bidirectional

Mode

SPC0=1

SWOM enables open drain output. PS4 becomes GPIO. SWOM enables open drain output. PS5 becomes GPIO.

SPI

DDRS5

Serial Out

Serial In

SPI

Serial In

Serial Out

DDRS4

SPI

MOMI

PS4

DDRS5

Serial Out

Serial In

SPI

PS5

SISO

DDRS4

Serial In

Serial Out

SP0CR1 — SPI Control Register 1 $00D0

Bit 7 654321Bit 0

SPIE SPE SWOM MSTR CPOL CPHA SSOE LSBF

RESET: 00000100

Multiple Serial Interface

MC68HC912DG128

222 Multiple Serial Interface MOTOROLA

SPE — SPI System Enable

0 = SPI internal hardware is initialized and SPI system is in a

low-power disabled state.

1 = PS[4:7] are dedicated to the SPI function

When MODF is set, SPE always reads zero. SP0CR1 must be written

as part of a mode fault recovery sequence.

SWOM — Port S Wired-OR Mode

Controls not only SPI output pins but also the general-purpose output

pins (PS[4:7]) which are not used by SPI.

0 = SPI and/or PS[4:7] output buffers operate normally

1 = SPI and/or PS[4:7] output buffers behave as open-drain

outputs

MSTR — SPI Master/Slave Mode Select

0 = Slave mode

1 = Master mode

When MODF is set, MSTR always reads zero. SP0CR1 must be

written as part of a mode fault recovery sequence.

CPOL, CPHA — SPI Clock Polarity, Clock Phase

These two bits are used to specify the clock format to be used in SPI

operations. When the clock polarity bit is cleared and data is not being

transferred, the SCK pin of the master device is low. When CPOL is

set, SCK idles high. See Figure 35 and Figure 36.

SSOE — Slave Select Output Enable

The SS output feature is enabled only in the master mode by

asserting the SSOE and DDRS7.

LSBF — SPI LSB First enable

0 = Data is transferred most significant bit first

1 = Data is transferred least significant bit first

Normally data is transferred most significant bit first.This bit does not

affect the position of the MSB and LSB in the data register. Reads and

writes of the data register will always have MSB in bit 7.

18-msi

Multiple Serial Interface

Serial Peripheral Interface (SPI)

MC68HC912DG128

MOTOROLA Multiple Serial Interface 223

19-msi

Read or write anytime.

PUPS — Pull-Up Port S Enable

0 = No internal pull-ups on port S

1 = All port S input pins have an active pull-up device. If a pin is

programmed as output, the pull-up device becomes inactive

RDPS — Reduce Drive of Port S

0 = Port S output drivers operate normally

1 = All port S output pins have reduced drive capability for lower

power and less noise

SSWAI — Serial Interface Stop in WAIT mode

0 = Serial interface clock operates normally

1 = Halt serial interface clock generation in WAIT mode

SPC0 — Serial Pin Control 0

This bit decides serial pin configurations with MSTR control bit.

1. The serial pin control 0 bit enables bidirectional configurations.

2. Slave output is enabled if DDRS4 = 1, SS = 0 and MSTR = 0. (#1, #3)

3. Master output is enabled if DDRS5 = 1 and MSTR = 1. (#2, #4)

4. SCK output is enabled if DDRS6 = 1 and MSTR = 1. (#2, #4)

5. SS output is enabled if DDRS7 = 1, SSOE = 1 and MSTR = 1. (#2, #4)

SP0CR2 — SPI Control Register 2 $00D1

Bit 7 654321Bit 0

0000PUPS RDPS SSWAI SPC0

RESET: 00001000

Pin Mode SPC0(1) MSTR MISO(2) MOSI(3) SCK(4) SS(5)

#1 Normal 0 0 Slave Out Slave In SCK In SS In

#2 1 Master In Master

Out SCK Out SS I/O

#3 Bidirectional 1 0 Slave I/O GPI/O SCK In SS In

#4 1 GPI/O Master I/O SCK Out SS I/O

Multiple Serial Interface

MC68HC912DG128

224 Multiple Serial Interface MOTOROLA

Read anytime. Write anytime.

At reset, E Clock divided by 2 is selected.

SPR[2:0] — SPI Clock (SCK) Rate Select Bits

These bits are used to specify the SPI clock rate.

Read anytime. Write has no meaning or effect.

SPIF — SPI Interrupt Request

SPIF is set after the eighth SCK cycle in a data transfer and it is

cleared by reading the SP0SR register (with SPIF set) followed by an

access (read or write) to the SPI data register.

WCOL — Write Collision Status Flag

The MCU write is disabled to avoid writing over the data being

transferred. No interrupt is generated because the error status flag

can be read upon completion of the transfer that was in progress at

SP0BR — SPI Baud Rate Register $00D2

Bit 7 654321Bit 0

00000SPR2 SPR1 SPR0

RESET: 00000000

Table 33 SPI Clock Rate Selection

SPR2 SPR1 SPR0 E Clock

Divisor Frequency at

E Clock = 4 MHz Frequency at

E Clock = 8 MHz

0 0 0 2 2.0 MHz 4.0 MHz

0 0 1 4 1.0 MHz 2.0 MHz

0 1 0 8 500 kHz 1.0 MHz

0 1 1 16 250 kHz 500 KHz

1 0 0 32 125 kHz 250 KHz

1 0 1 64 62.5 kHz 125 KHz

1 1 0 128 31.3 kHz 62.5 KHz

1 1 1 256 15.6 kHz 31.3 KHz

SP0SR — SPI Status Register $00D3

Bit 7 654321Bit 0

SPIF WCOL 0 MODF 0000

RESET: 00000000

20-msi

Multiple Serial Interface

Serial Peripheral Interface (SPI)

MC68HC912DG128

MOTOROLA Multiple Serial Interface 225

21-msi

the time of the error. Automatically cleared by a read of the SP0SR

(with WCOL set) followed by an access (read or write) to the SP0DR

0 = No write collision

1 = Indicates that a serial transfer was in progress when the MCU

tried to write new data into the SP0DR data register.

MODF — SPI Mode Error Interrupt Status Flag

This bit is set automatically by SPI hardware if the MSTR control bit is

set and the slave select input pin becomes zero. This condition is not

permitted in normal operation. In the case where DDRS bit 7 is set,

the PS7 pin is a general-purpose output pin or SS output pin rather

than being dedicated as the SS input for the SPI system. In this

special case the mode fault function is inhibited and MODF remains

cleared. This flag is automatically cleared by a read of the SP0SR

(with MODF set) followed by a write to the SP0CR1 register.

Read anytime (normally only after SPIF flag set). Write anytime (see

WCOL write collision flag).

Reset does not affect this address.

This 8-bit register is both the input and output register for SPI data.

Reads of this register are double buffered but writes cause data to

written directly into the serial shifter. In the SPI system the 8-bit data

by the MOSI and MISO wires to form a distributed 16-bit register. When

a data transfer operation is performed, this 16-bit register is serially

shifted eight bit positions by the SCK clock from the master so the data

is effectively exchanged between the master and the slave. Note that

some slave devices are very simple and either accept data from the

master without returning data to the master or pass data to the master

without requiring data from the master.

SP0DR — SPI Data Register $00D5

Bit 7 654321Bit 0

RESET: 00000000

Multiple Serial Interface

MC68HC912DG128

226 Multiple Serial Interface MOTOROLA

Port S

In all modes, port S bits PS[7:0] can be used for either general-purpose

I/O, or with the SCI and SPI subsystems. During reset, port S pins are

configured as high-impedance inputs (DDRS is cleared).

Read anytime (inputs return pin level; outputs return pin driver input

level). Write data stored in internal latch (drives pins only if configured

for output). Writes do not change pin state when pin configured for SPI

or SCI output.

After reset all bits are configured as general-purpose inputs.

Port S shares function with the on-chip serial systems (SPI and SCI0/1).

Read or write anytime.

After reset, all general-purpose I/O are configured for input only.

0 = Configure the corresponding I/O pin for input only

1 = Configure the corresponding I/O pin for output

DDS2, DDS0 — Data Direction for Port S Bit 2 and Bit 0

If the SCI receiver is configured for two-wire SCI operation,

corresponding port S pins will be input regardless of the state of these

bits.

PORTS — Port S Data Register $00D6

Bit 7 654321Bit 0

PS7 PS6 PS5 PS4 PS3 PS2 PS1 PS0

MSI SS

CS SCK MOSI

MOMI MISO

SISO TXD1 RXD1 TXD0 RXD0

RESET: --------

DDRS — Data Direction Register for Port S $00D7

Bit 7 654321Bit 0

DDS7 DDS6 DDS5 DDS4 DDS3 DDS2 DDS1 DDS0

RESET: 00000000

22-msi

Multiple Serial Interface

Port S

MC68HC912DG128

MOTOROLA Multiple Serial Interface 227

23-msi

DDS3, DDS1 — Data Direction for Port S Bit 3 and Bit 1

If the SCI transmitter is configured for two-wire SCI operation,

corresponding port S pins will be output regardless of the state of

these bits.

DDS[6:4] — Data Direction for Port S Bits 6 through 4

If the SPI is enabled and expects the corresponding port S pin to be

an input, it will be an input regardless of the state of the DDRS bit. If

the SPI is enabled and expects the bit to be an output, it will be an

output ONLY if the DDRS bit is set.

DDS7 — Data Direction for Port S Bit 7

In SPI slave mode, DDRS7 has no meaning or effect; the PS7 pin is

dedicated as the SS input. In SPI master mode, DDRS7 determines

whether PS7 is an error detect input to the SPI or a general-purpose

or slave select output line.

NOTE:

If mode fault error occurs bits 5, 6 and 7 are forced to zero.

Multiple Serial Interface

MC68HC912DG128

228 Multiple Serial Interface MOTOROLA

24-msi

MC68HC912DG128

MOTOROLA Inter-IC Bus 229

Inter-IC Bus

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .229

IIC Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .230

IIC System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

IIC Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .232

IIC Register Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236

IIC Programming Examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245

Introduction

The Inter-IC Bus (IIC or I2C) is a two-wire, bidirectional serial bus that

provides a simple, efﬁcient method of data exchange between devices.

Being a two-wire device, the IIC minimizes the need for large numbers

of connections between devices, and eliminates the need for an address

decoder.

This bus is suitable for applications requiring occasional

communications over a short distance between a number of devices. It

also provides flexibility, allowing additional devices to be connected to

the bus for further expansion and system development.

The interface is designed to operate up to 100kbps with maximum bus

loading and timing. The device is capable of operating at higher baud

rates, up to a maximum of clock/20, with reduced bus loading. The

maximum communication length and the number of devices that can be

connected are limited by a maximum bus capacitance of 400pF.

1-iicbus

Inter-IC Bus

MC68HC912DG128

230 Inter-IC Bus MOTOROLA

IIC Features

The IIC module has the following key features:

• Compatible with I2C Bus standard

• Multi-master operation

• Software programmable for one of 64 different serial clock

frequencies

• Software selectable acknowledge bit

• Interrupt driven byte-by-byte data transfer

• Arbitration lost interrupt with automatic mode switching from

master to slave

• Calling address identification interrupt

• Start and stop signal generation/detection

• Repeated start signal generation

• Acknowledge bit generation/detection

• Bus busy detection

• Eight-bit general purpose I/O port

A block diagram of the IIC module is shown in Figure 38.

2--iicbus

Inter-IC Bus

IIC Features

MC68HC912DG128

MOTOROLA Inter-IC Bus 231

Figure 38 IIC Block Diagram

Input

Sync

In/Out

Data

Shift

Address

Compare

SCL SDA

INTERRUPT

ADDR & CONTROL DATA

Clock

Control

Start,

Stop &

Arbitration

Control

CTRL_REG FREQ_REG ADDR_REG STATUS_REG DATA_REG

ADDR_DECODE DATA_MUX

3-iicbus

Inter-IC Bus

MC68HC912DG128

232 Inter-IC Bus MOTOROLA

IIC System Configuration

The IIC system uses a Serial Data line (SDA) and a Serial Clock Line

(SCL) for data transfer. All devices connected to it must have open drain

or open collector outputs. Logic “and” function is exercised on both lines

with external pull-up resistors, the value of these resistors is system

dependent.

IIC Protocol

Normally, a standard communication is composed of four parts: START

signal, slave address transmission, data transfer and STOP signal. They

are described briefly in the following sections and illustrated in Figure 39.

Figure 39 IIC Transmission Signals

SCL

SDA

Start

Signal Ack

Bit

12345678

MSB LSB 12345678

MSB LSB

Stop

Signal

SCL

SDA

12345678

MSB LSB 12 5 678

MSB LSB

Repeated

9 9

AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W XXX D7 D6 D5 D4 D3 D2 D1 D0

Calling Address Read/ Data Byte

AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W AD7 AD6 AD5 AD4 AD3 AD2 AD1 R/W

New Calling Address

Ack

Bit

Write

Start

Signal

Start

Signal Ack

Bit

Calling Address Read/

Write Stop

Signal

Ack

Bit

Read/

Write

4-iicbus

Inter-IC Bus

IIC Protocol

MC68HC912DG128

MOTOROLA Inter-IC Bus 233

START Signal When the bus is free, i.e. no master device is engaging the bus (both

SCL and SDA lines are at logical high), a master may initiate

communication by sending a START signal. As shown in Figure 39, a

START signal is defined as a high-to-low transition of SDA while SCL is

high. This signal denotes the beginning of a new data transfer (each data

transfer may contain several bytes of data) and wakes up all slaves.

Slave Address

Transmission

The first byte of data transfer immediately after the START signal is the

slave address transmitted by the master. This is a seven-bit calling

address followed by a R/W bit. The R/W bit tells the slave the desired

direction of data transfer.

1 = Read transfer, the slave transmits data to the master.

0 = Write transfer, the master transmits data to the slave.

Only the slave with a calling address that matches the one transmitted

by the master will respond by sending back an acknowledge bit. This is

done by pulling the SDA low at the 9th clock (see Figure 39).

Slave address - No two slaves in the system may have the same

address. If the IIC is master, it must not transmit an address that

is equal to its own slave address. The IIC cannot be master and

slave at the same time. If however arbitration is lost during an

address cycle the IIC will revert to slave mode and operate

correctly even if it is being addressed by another master.

Data Transfer Once successful slave addressing is achieved, the data transfer can

proceed byte-by-byte in a direction specified by the R/W bit sent by the

calling master.

NOTE:

All transfers that come after an address cycle are referred to as data

transfers, even if they carry sub-address information for the slave

device.

Each data byte is 8 bits long. Data may be changed only while SCL is

low and must be held stable while SCL is high as shown in Figure 39.

There is one clock pulse on SCL for each data bit, the MSB being

transferred first. Each data byte has to be followed by an acknowledge

5-iicbus

Inter-IC Bus

MC68HC912DG128

234 Inter-IC Bus MOTOROLA

bit, which is signalled from the receiving device by pulling the SDA low

at the ninth clock. So one complete data byte transfer needs nine clock

pulses.

If the slave receiver does not acknowledge the master, the SDA line

must be left high by the slave. The master can then generate a stop

signal to abort the data transfer or a start signal (repeated start) to

commence a new calling.

If the master receiver does not acknowledge the slave transmitter after

a byte transmission, it means 'end of data' to the slave, so the slave

releases the SDA line for the master to generate STOP or START signal.

STOP Signal The master can terminate the communication by generating a STOP

signal to free the bus. However, the master may generate a START

signal followed by a calling command without generating a STOP signal

first. This is called repeated START. A STOP signal is defined as a

low-to-high transition of SDA while SCL at logical “1” (see Figure 39).

The master can generate a STOP even if the slave has generated an

acknowledge at which point the slave must release the bus.

Repeated START

Signal

As shown in Figure 39, a repeated START signal is a START signal

generated without first generating a STOP signal to terminate the

communication. This is used by the master to communicate with another

slave or with the same slave in different mode (transmit/receive mode)

without releasing the bus.

Arbitration

Procedure

IIC is a true multi-master bus that allows more than one master to be

connected on it. If two or more masters try to control the bus at the same

time, a clock synchronization procedure determines the bus clock, for

which the low period is equal to the longest clock low period and the high

is equal to the shortest one among the masters. The relative priority of

the contending masters is determined by a data arbitration procedure, a

bus master loses arbitration if it transmits logic “1” while another master

transmits logic “0”. The losing masters immediately switch over to slave

receive mode and stop driving SDA output. In this case the transition

6-iicbus

Inter-IC Bus

IIC Protocol

MC68HC912DG128

MOTOROLA Inter-IC Bus 235

7-iicbus

from master to slave mode does not generate a STOP condition.

Meanwhile, a status bit is set by hardware to indicate loss of arbitration.

Clock

Synchronization

Since wire-AND logic is performed on SCL line, a high-to-low transition

on SCL line affects all the devices connected on the bus. The devices

start counting their low period and once a device's clock has gone low,

it holds the SCL line low until the clock high state is reached. However,

the change of low to high in this device clock may not change the state

of the SCL line if another device clock is still within its low period.

Therefore, synchronized clock SCL is held low by the device with the

longest low period. Devices with shorter low periods enter a high wait

state during this time (see Figure 40). When all devices concerned have

counted off their low period, the synchronized clock SCL line is released

and pulled high. There is then no difference between the device clocks

and the state of the SCL line and all the devices start counting their high

periods. The first device to complete its high period pulls the SCL line low

again.

Figure 40 IIC Clock Synchronization

Handshaking The clock synchronization mechanism can be used as a handshake in

data transfer. Slave devices may hold the SCL low after completion of

SCL1

SCL2

SCL

Internal Counter Reset

WAIT Start Counting High Period

Inter-IC Bus

MC68HC912DG128

236 Inter-IC Bus MOTOROLA

one byte transfer (9 bits). In such case, it halts the bus clock and forces

the master clock into wait states until the slave releases the SCL line.

Clock Stretching The clock synchronization mechanism can be used by slaves to slow

down the bit rate of a transfer. After the master has driven SCL low the

slave can drive SCL low for the required period and then release it. If the

slave SCL low period is greater than the master SCL low period then the

resulting SCL bus signal low period is stretched.

IIC Register Descriptions

Read and write anytime

This register contains the address the IIC will respond to when

addressed as a slave; note that it is not the address sent on the bus

during the address transfer

ADR7–ADR1 — Slave Address

Bit 1 to bit 7 contain the specific slave address to be used by the IIC

module.

The default mode of IIC is slave mode for an address match on the

bus.

Read and write anytime

IBAD — IIC Bus Address Register $00E0

Bit 7 654321Bit 0

ADR7 ADR6 ADR5 ADR4 ADR3 ADR2 ADR1 0

RESET: 00000000

IBFD — IIC Bus Frequency Divider Register $00E1

Bit 7 654321Bit 0

00IBC5 IBC4 IBC3 IBC2 IBC1 IBC0

RESET: 00000000

8-iicbus

Inter-IC Bus

IIC Register Descriptions

MC68HC912DG128

MOTOROLA Inter-IC Bus 237

9-iicbus

IBC5–IBC0 — IIC Bus Clock Rate 5–0

This field is used to prescale the clock for bit rate selection. The bit

clock generator is implemented as a prescaled shift register - IBC5-3

select the prescaler divider and IBC2-0 select the shift register tap

point. The IBC bits are decoded to give the Tap and Prescale values

as shown in Table 34.

The number of clocks from the falling edge of SCL to the first tap

(Tap[1]) is defined by the values shown in the scl2tap column of

Table 34, all subsequent tap points are separated by 2IBC5-3 as

shown in the tap2tap column in Table 34. The SCL Tap is used to

generated the SCL period and the SDA Tap is used to determine the

delay from the falling edge of SCL to SDA changing, the SDA hold

time.

The serial bit clock frequency is equal to the CPU clock frequency

divided by the divider shown in Table 3. The equation used to

generate the divider values from the IBFD bits is:

SCL Divider = 2 x ( scl2tap + [ ( SCL_Tap -1 ) x tap2tap ] + 2 )

The SDA hold delay is equal to the CPU clock period multiplied by the

SDA Hold value shown in Figure 3. The equation used to generate

the SDA Hold value from the IBFD bits is:

SDA Hold = scl2tap + [ ( SDA_Tap - 1 ) x tap2tap ] + 3

Table 34 IIC Tap and Prescale Values

IBC2-0

(bin) SCL Tap

(clocks) SDA Tap

(clocks) IBC5-3

(bin) scl2tap

(clocks) tap2tap

(clocks)

000 5 1 000 4 1

001 6 1 001 4 2

010 7 2 010 6 4

011 8 2 011 6 8

100 9 3 100 14 16

101 10 3 101 30 32

110 12 4 110 62 64

111 15 4 111 126 128

Inter-IC Bus

MC68HC912DG128

238 Inter-IC Bus MOTOROLA

Table 3 IIC Divider and SDA Hold values

IBC5-0

(hex) SCL Divider

(clocks) SDA Hold

(clocks) IBC5-0

(hex) SCL Divider

(clocks) SDA Hold

(clocks)

00 20 7 20 160 17

01 22 7 21 192 17

02 24 8 22 224 33

03 26 8 23 256 33

04 28 9 24 288 49

05 30 9 25 320 49

06 34 10 26 384 65

07 40 10 27 480 65

08 28 7 28 320 33

09 32 7 29 384 33

0A 36 9 2A 448 65

0B 40 9 2B 512 65

0C 44 11 2C 576 97

0D 48 11 2D 640 97

0E 56 13 2E 768 129

0F 68 13 2F 960 129

10 48 9 30 640 65

11 56 9 31 768 65

12 64 13 32 896 129

13 72 13 33 1024 129

14 80 17 34 1152 193

15 88 17 35 1280 193

16 104 21 36 1536 257

17 128 21 37 1920 257

18 80 9 38 1280 129

19 96 9 39 1536 129

1A 112 17 3A 1792 257

10-iicbus

Inter-IC Bus

IIC Register Descriptions

MC68HC912DG128

MOTOROLA Inter-IC Bus 239

11-iicbus

Read and write anytime

IBEN — IIC Bus Enable

This bit controls the software reset of the entire IIC module.

0 = The module is reset and disabled. This is the power-on reset

situation. When low the IIC system is held in reset but registers

can still be accessed.

1 = The IIC system is enabled. This bit must be set before any other

IBCR bits have any effect.

If the IIC module is enabled in the middle of a byte transfer the

interface behaves as follows: slave mode ignores the current transfer

on the bus and starts operating whenever a subsequent start

condition is detected. Master mode will not be aware that the bus is

busy, hence if a start cycle is initiated then the current bus cycle may

become corrupt. This would ultimately result in either the current bus

master or the IIC module losing arbitration, after which bus operation

would return to normal.

IBIE — IIC Bus Interrupt Enable

0 = Interrupts from the IIC module are disabled. Note that this does

not clear any currently pending interrupt condition.

1 = Interrupts from the IIC module are enabled. An IIC interrupt

occurs provided the IBIF bit in the status register is also set.

1B 128 17 3B 2048 257

1C 144 25 3C 2304 385

1D 160 25 3D 2560 385

1E 192 33 3E 3072 513

1F 240 33 3F 3840 513

Table 3 IIC Divider and SDA Hold values

IBC5-0

(hex) SCL Divider

(clocks) SDA Hold

(clocks) IBC5-0

(hex) SCL Divider

(clocks) SDA Hold

(clocks)

IBCR — IIC Bus Control Register $00E2

Bit 7 654321Bit 0

IBEN IBIE MS/SL Tx/Rx TXAK RSTA 0 IBSWAI

RESET: 00000000

Inter-IC Bus

MC68HC912DG128

240 Inter-IC Bus MOTOROLA

MS/SL — Master/Slave mode select bit

Upon reset, this bit is cleared. When this bit is changed from 0 to 1, a

START signal is generated on the bus, and the master mode is

selected. When this bit is changed from 1 to 0, a STOP signal is

generated and the operation mode changes from master to slave.

MS/SL is cleared without generating a STOP signal when the master

loses arbitration.

0 = Slave Mode

1 = Master Mode

Tx/Rx — Transmit/Receive mode select bit

This bit selects the direction of master and slave transfers. When

addressed as a slave this bit should be set by software according to

the SRW bit in the status register. In master mode this bit should be

set according to the type of transfer required. Therefore, for address

cycles, this bit will always be high.

0 = Receive

1 = Transmit

TXAK — Transmit Acknowledge enable

This bit specifies the value driven onto SDA during acknowledge

cycles for both master and slave receivers. Note that values written to

this bit are only used when the IIC is a receiver, not a transmitter.

0 = An acknowledge signal will be sent out to the bus at the 9th

clock bit after receiving one byte data

1 = No acknowledge signal response is sent (i.e., acknowledge bit

= 1)

RSTA — Repeat Start

Writing a 1 to this bit will generate a repeated START condition on the

bus, provided it is the current bus master. This bit will always be read

as a low. Attempting a repeated start at the wrong time, if the bus is

owned by another master, will result in loss of arbitration.

1 = Generate repeat start cycle

IBSWAI — IIC Stop in WAIT mode

0 = IIC module operates normally

1 = Halt clock generation of IIC module in WAIT mode

12-iicbus

Inter-IC Bus

IIC Register Descriptions

MC68HC912DG128

MOTOROLA Inter-IC Bus 241

13-iicbus

This status register is read-only with exception of bit 1 (IBIF) and bit 4

(IBAL), which are software clearable

TCF — Data transferring bit

While one byte of data is being transferred, this bit is cleared. It is set

by the falling edge of the 9th clock of a byte transfer.

0 = Transfer in progress

1 = Transfer complete

IAAS — Addressed as a slave bit

When its own specific address (IIC Bus Address Register) is matched

with the calling address, this bit is set. The CPU is interrupted

provided the IBIE is set. Then the CPU needs to check the SRW bit

and set its Tx/Rx mode accordingly. Writing to the IIC Bus Control

0 = Not addressed

1 = Addressed as a slave

IBB — IIC Bus busy bit

This bit indicates the status of the bus. When a START signal is

detected, the IBB is set. If a STOP signal is detected, it is cleared.

0 = Bus is idle

1 = Bus is busy

IBAL — Arbitration Lost

The arbitration lost bit (IBAL) is set by hardware when the arbitration

procedure is lost. Arbitration is lost in the following circumstances:

1. SDA sampled as low when the master drives a high during an

address or data transmit cycle.

2. SDA sampled as a low when the master drives a high during the

acknowledge bit of a data receive cycle.

3. A start cycle is attempted when the bus is busy.

4. A repeated start cycle is requested in slave mode.

IBSR — IIC Bus Status Register$00E3

Bit 7 654321Bit 0

TCF IAAS IBB IBAL 0 SRW IBIF RXAK

RESET: 10000000

Inter-IC Bus

MC68HC912DG128

242 Inter-IC Bus MOTOROLA

5. A stop condition is detected when the master did not request it.

This bit must be cleared by software, by writing a one to it.

SRW — Slave Read/Write

When IAAS is set this bit indicates the value of the R/W command bit

of the calling address sent from the master.

CAUTION:

This bit is only valid when the IIC is in slave mode, a complete address

transfer has occurred with an address match and no other transfers have

been initiated.

Checking this bit, the CPU can select slave transmit/receive mode

according to the command of the master.

0 = Slave receive, master writing to slave

1 = Slave transmit, master reading from slave

IBIF — IIC Bus Interrupt Flag

The IBIF bit is set when an interrupt is pending, which will cause a

processor interrupt request provided IBIE is set. IBIF is set when one

of the following events occurs:

1. Complete one byte transfer (set at the falling edge of the 9th

clock).

2. Receive a calling address that matches its own specific address in

slave receive mode.

3. Arbitration lost.

This bit must be cleared by software, writing a one to it, in the interrupt

routine.

RXAK — Received Acknowledge

The value of SDA during the acknowledge bit of a bus cycle. If the

received acknowledge bit (RXAK) is low, it indicates an acknowledge

signal has been received after the completion of 8 bits data

transmission on the bus. If RXAK is high, it means no acknowledge

signal is detected at the 9th clock.

0 = Acknowledge received

1 = No acknowledge received

14-iicbus

Inter-IC Bus

IIC Register Descriptions

MC68HC912DG128

MOTOROLA Inter-IC Bus 243

15-iicbus

Read and write anytime

In master transmit mode, when data is written to the IBDR a data transfer

is initiated. The most significant bit is sent first. In master receive mode,

reading this register initiates next byte data receiving. In slave mode, the

same functions are available after an address match has occurred.

NOTE:

In master transmit mode, the first byte of data written to IBDR following

assertion of MS/SL is used for the address transfer and should comprise

of the calling address (in position D7-D1) concatenated with the required

R/W bit (in position D0).

Read and write anytime

RDPIB - Reduced Drive of Port IB

0 = All port IB output pins have full drive enabled.

1 = All port IB output pins have reduced drive capability.

PUPIB - Pull-Up Port IB Enable

0 = Port IB pull-ups are disabled.

1 = Enable pull-up devices for port IB input pins [7:4]. Pull-ups for

port IB input pins [3:0] are always enabled.

IBDR — IIC Bus Data I/O Register $00E4

Bit 7 654321Bit 0

D7 D6 D5 D4 D3 D2 D1 D0 High

RESET: 00000000

IBPURD — Pull-Up and Reduced Drive for Port IB $00E5

Bit 7 654321Bit 0

0 0 0 RDPIB 0 0 0 PUPIB

RESET: 00000000

Inter-IC Bus

MC68HC912DG128

244 Inter-IC Bus MOTOROLA

Read and write anytime.

IIC functions SCL and SDA share port IB pins 7 and 6 and take

precedence over the general-purpose port when IIC is enabled. The

SCL and SDA output buffers behave as open-drain outputs.

When port is configured as input, a read will return the pin level. Port bits

3 through 0 have internal pull ups when configured as inputs so they will

read ones.

When configured as output, a read will return the latched output data.

Port bits 5 through 0 will read the last value written. A write will drive

associated pins only if configured for output and IIC is not enabled.

Port bits 3 through 0 do not have available external pins for

MC68HC912DG128.

Read and write anytime

DDRIB[7:2]— Port IB [7:2] Data direction

Each bit determines the primary direction for each pin configured as

general-purpose I/O.

0 = Associated pin is a high-impedance input.

1 = Associated pin is an output.

DDRIB[3:0] — These bits served as memory locations since there are

no corresponding external port pins for MC68HC912DG128.

PORTIB — Port Data IB Register $00E6

Bit 7 654321Bit 0

PIB7 PIB6 PIB5 PIB4 PIB3 PIB2 PIB1 PIB0

IICSCLSDA------

RESET: --------

DDRIB — Data Direction for Port IB Register $00E7

Bit 7 654321Bit 0

DDRIB7 DDRIB6 DDRIB5 DDRIB4 DDRIB3 DDRIB2 DDRIB1 DDRIB0

RESET: 00000000

16-iicbus

Inter-IC Bus

IIC Programming Examples

MC68HC912DG128

MOTOROLA Inter-IC Bus 245

17-iicbus

IIC Programming Examples

Initialization

Sequence

Reset will put the IIC Bus Control Register to its default status. Before

the interface can be used to transfer serial data, an initialization

procedure must be carried out, as follows:

1. Update the Frequency Divider Register (IBFD) and select the

required division ratio to obtain SCL frequency from system clock.

2. Update the IIC Bus Address Register (IBAD) to define its slave

address.

3. Set the IBEN bit of the IIC Bus Control Register (IBCR) to enable

the IIC interface system.

4. Modify the bits of the IIC Bus Control Register (IBCR) to select

Master/Slave mode, Transmit/Receive mode and interrupt enable

or not.

Generation of

START

After completion of the initialization procedure, serial data can be

transmitted by selecting the 'master transmitter' mode. If the device is

connected to a multi-master bus system, the state of the IIC Bus Busy

bit (IBB) must be tested to check whether the serial bus is free.

If the bus is free (IBB=0), the start condition and the first byte (the slave

address) can be sent. The data written to the data register comprises the

slave calling address and the LSB set to indicate the direction of transfer

required from the slave.

The bus free time (i.e., the time between a STOP condition and the

following START condition) is built into the hardware that generates the

START cycle. Depending on the relative frequencies of the system clock

and the SCL period it may be necessary to wait until the IIC is busy after

writing the calling address to the IBDR before proceeding with the

following instructions. This is illustrated in the following example.

An example of a program which generates the START signal and

transmits the first byte of data (slave address) is shown below:

CHFLAG BRSET IBSR,#$20,* ;WAIT FOR IBB FLAG TO CLEAR

TXSTART BSET IBCR,#$30 ;SET TRANSMIT AND MASTER MODE

Inter-IC Bus

MC68HC912DG128

246 Inter-IC Bus MOTOROLA

Post-Transfer

Software

Response

Transmission or reception of a byte will set the data transferring bit

(TCF) to 1, which indicates one byte communication is finished. The IIC

Bus interrupt bit (IBIF) is set also; an interrupt will be generated if the

interrupt function is enabled during initialization by setting the IBIE bit.

Software must clear the IBIF bit in the interrupt routine first. The TCF bit

will be cleared by reading from the IIC Bus Data I/O Register (IBDR) in

receive mode or writing to IBDR in transmit mode.

Software may service the IIC I/O in the main program by monitoring the

IBIF bit if the interrupt function is disabled. Note that polling should

monitor the IBIF bit rather than the TCF bit since their operation is

different when arbitration is lost.

Note that when an interrupt occurs at the end of the address cycle the

master will always be in transmit mode, i.e. the address is transmitted. If

master receive mode is required, indicated by R/W bit in IBDR, then the

Tx/Rx bit should be toggled at this stage.

During slave mode address cycles (IAAS=1) the SRW bit in the status

the Tx/Rx bit is programmed accordingly. For slave mode data cycles

(IAAS=0) the SRW bit is not valid, the Tx/Rx bit in the control register

should be read to determine the direction of the current transfer.

The following is an example of a software response by a 'master

transmitter' in the interrupt routine (see Figure 41).

;i.e. GENERATE START CONDITION

MOVB CALLING,IBDR ;TRANSMIT THE CALLING

;ADDRESS, D0=R/W

IBFREE BRCLR IBSR,#$20,* ;WAIT FOR IBB FLAG TO SET

CHFLAG BRSET IBSR,#$20,* ;WAIT FOR IBB FLAG TO CLEAR

ISR BCLR IBSR,#$02 ;CLEAR THE IBIF FLAG

BRCLR IBCR,#$20,SLAVE ;BRANCH IF IN SLAVE MODE

BRCLR IBCR,#$10,RECEIVE ;BRANCH IF IN RECEIVE MODE

BRSET IBSR,#$01,END ;IF NO ACK, END OF TRANSMISSION

TRANSMIT MOVB DATABUF,IBDR ;TRANSMIT NEXT BYTE OF DATA

18-iicbus

Inter-IC Bus

IIC Programming Examples

MC68HC912DG128

MOTOROLA Inter-IC Bus 247

19-iicbus

Generation of

STOP

A data transfer ends with a STOP signal generated by the 'master'

device. A master transmitter can simply generate a STOP signal after all

the data has been transmitted. The following is an example showing how

a stop condition is generated by a master transmitter.

If a master receiver wants to terminate a data transfer, it must inform the

slave transmitter by not acknowledging the last byte of data which can

be done by setting the transmit acknowledge bit (TXAK) before reading

the 2nd last byte of data. Before reading the last byte of data, a STOP

signal must be generated first. The following is an example showing how

a STOP signal is generated by a master receiver.

Generation of

Repeated START

At the end of data transfer, if the master still wants to communicate on

the bus, it can generate another START signal followed by another slave

address without first generating a STOP signal. A program example is

as shown.

MASTX TST TXCNT ;GET VALUE FROM THE

;TRANSMITING COUNTER

BEQ END ;END IF NO MORE DATA

BRSET IBSR,#$01,END ;END IF NO ACK

MOVB DATABUF,IBDR ;TRANSMIT NEXT BYTE OF DATA

DEC TXCNT ;DECREASE THE TXCNT

BRA EMASTX ;EXIT

END BCLR IBCR,#$20 ;GENERATE A STOP CONDITION

EMASTX RTI ;RETURN FROM INTERRUPT

MASR DEC RXCNT ;DECREASE THE RXCNT

BEQ ENMASR ;LAST BYTE TO BE READ

MOVB RXCNT,D1 ;CHECK SECOND LAST BYTE

DEC D1 ;TO BE READ

BNE NXMAR ;NOT LAST OR SECOND LAST

LAMAR BSET IBCR,#$08 ;SECOND LAST, DISABLE ACK

;TRANSMITTING

BRA NXMAR

ENMASR BCLR IBCR,#$20 ;LAST ONE, GENERATE ‘STOP’ SIGNAL

NXMAR MOVB IBDR,RXBUF ;READ DATA AND STORE

RTI

RESTART BSET IBCR,#$04 ANOTHER START (RESTART)

MOVB CALLING,IBDR ;TRANSMIT THE CALLING ADDRESS

;D0=R/W

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248 Inter-IC Bus MOTOROLA

Slave Mode In the slave interrupt service routine, the module addressed as slave bit

(IAAS) should be tested to check if a calling of its own address has just

been received (see Figure 41). If IAAS is set, software should set the

transmit/receive mode select bit (Tx/Rx bit of IBCR) according to the R/

W command bit (SRW). Writing to the IBCR clears the IAAS

automatically. Note that the only time IAAS is read as set is from the

interrupt at the end of the address cycle where an address match

occurred, interrupts resulting from subsequent data transfers will have

IAAS cleared. A data transfer may now be initiated by writing information

to IBDR, for slave transmits, or dummy reading from IBDR, in slave

receive mode. The slave will drive SCL low in-between byte transfers,

SCL is released when the IBDR is accessed in the required mode.

In slave transmitter routine, the received acknowledge bit (RXAK) must

be tested before transmitting the next byte of data. Setting RXAK means

an 'end of data' signal from the master receiver, after which it must be

switched from transmitter mode to receiver mode by software. A dummy

read then releases the SCL line so that the master can generate a STOP

signal.

Arbitration Lost If several masters try to engage the bus simultaneously, only one master

wins and the others lose arbitration. The devices which lost arbitration

are immediately switched to slave receive mode by the hardware. Their

data output to the SDA line is stopped, but SCL is still generated until the

end of the byte during which arbitration was lost. An interrupt occurs at

the falling edge of the ninth clock of this transfer with IBAL=1 and MS/

SL=0. If one master attempts to start transmission while the bus is being

engaged by another master, the hardware will inhibit the transmission;

switch the MS/SL bit from 1 to 0 without generating STOP condition;

generate an interrupt to CPU and set the IBAL to indicate that the

attempt to engage the bus is failed. When considering these cases, the

slave service routine should test the IBAL first and the software should

clear the IBAL bit if it is set.

20-iicbus

Inter-IC Bus

IIC Programming Examples

MC68HC912DG128

MOTOROLA Inter-IC Bus 249

21-iicbus

Figure 41 Flow-Chart of Typical IIC Interrupt Routine

Clear

Master

Mode

Tx/Rx

Last Byte

Transmitted

RXAK=0

End Of

Addr Cycle

(Master Rx)

Write Next

Byte To IBDR

Switch To

Rx Mode

Dummy Read

From IBDR Generate

Stop Signal Read Data

From IBDR

And Store

Set TXAK =1 Generate

Stop Signal

2nd Last

Byte To Be Read

Last

Byte To Be Read

Arbitration

Lost

Clear IBAL

IAAS=1

SRW=1

?TX/RX

Set TX

Mode

Write Data

To IBDR

Set RX

Mode

Dummy Read

From IBDR

ACK From

Receiver

Tx Next

Byte Read Data

From IBDR

And Store

Switch To

Rx Mode

Dummy Read

From IBDR

RTI

TX RX

(Write)

(Read)

IBIF

Address Transfer Data Transfer

Inter-IC Bus

MC68HC912DG128

250 Inter-IC Bus MOTOROLA

22-iicbus

MC68HC912DG128

MOTOROLA MSCAN Controller 251

MSCAN Controller

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .251

External Pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252

Message Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .253

Identifier Acceptance Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258

Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261

Protocol Violation Protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263

Low Power Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264

Timer Link . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267

Clock System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .268

Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270

Programmer’s Model of Message Storage . . . . . . . . . . . . . . . . . . . .271

Programmer’s Model of Control Registers . . . . . . . . . . . . . . . . . . . .276

Introduction

The MC68HC912DG128 has two identical msCAN12 modules identified

as CAN0 and CAN1. The information to follow describes one msCAN

unless specifically noted and register locations specifically relate to

CAN0. CAN1 registers are located 512 bytes from CAN0.

The msCAN12 is the specific implementation of the Motorola scalable

CAN (msCAN) concept targeted for the Motorola M68HC12

microcontroller family.

The module is a communication controller implementing the CAN 2.0 A/

B protocol as defined in the BOSCH specification dated September

1991.

1-mscan12

MSCAN Controller

MC68HC912DG128

252 MSCAN Controller MOTOROLA

The CAN protocol was primarily, but not only, designed to be used as a

vehicle serial data bus, meeting the specific requirements of this field:

real-time processing, reliable operation in the EMI environment of a

vehicle, cost-effectiveness and required bandwidth.

msCAN12 utilizes an advanced buffer arrangement resulting in a

predictable real-time behavior and simplifies the application software.

External Pins

The msCAN12 uses 2 external pins, 1 input (RxCAN) and 1 output

(TxCAN). The TxCAN output pin represents the logic level on the CAN:

0 is for a dominant state, and 1 is for a recessive state.

RxCAN is on bit 0 of Port CAN, TxCAN is on bit 1. The remaining six pins

of Port CAN are controlled by registers in the msCAN12 address space

(see msCAN12 Port CAN Control Register (PCTLCAN) and msCAN12

Port CAN Data Direction Register (DDRCAN)).

A typical CAN system with msCAN12 is shown in Figure 42 below.

Each CAN station is connected physically to the CAN bus lines through

a transceiver chip. The transceiver is capable of driving the large current

needed for the CAN and has current protection, against defected CAN

or defected stations.

2--mscan12

MSCAN Controller

Message Storage

MC68HC912DG128

MOTOROLA MSCAN Controller 253

Figure 42 The CAN System

Message Storage

msCAN12 facilitates a sophisticated message storage system which

addresses the requirements of a broad range of network applications.

Background Modern application layer software is built upon two fundamental

assumptions:

1. Any CAN node is able to send out a stream of scheduled

messages without releasing the bus between two messages.

Such nodes will arbitrate for the bus right after sending the

previous message and will only release the bus in case of lost

arbitration.

2. The internal message queue within any CAN node is organized

such that if more than one message is ready to be sent, the

highest priority message will be sent out first.

Above behavior can not be achieved with a single transmit buffer. That

buffer must be reloaded right after the previous message has been sent.

Transceiver

msCAN12

CAN system

CAN station 1 CAN station 2 CAN station n

CAN

TxCAN RxCAN

.....

Controller

3-mscan12

MSCAN Controller

MC68HC912DG128

254 MSCAN Controller MOTOROLA

This loading process lasts a definite amount of time and has to be

completed within the inter-frame sequence (IFS) in order to be able to

send an uninterrupted stream of messages. Even if this is feasible for

limited CAN bus speeds it requires that the CPU reacts with short

latencies to the transmit interrupt.

A double buffer scheme would de-couple the re-loading of the transmit

buffers from the actual message sending and as such reduces the

reactiveness requirements on the CPU. Problems may arise if the

sending of a message would be finished just while the CPU re-loads the

second buffer, no buffer would then be ready for transmission and the

bus would be released.

At least three transmit buffers are required to meet the first of above

requirements under all circumstances. The msCAN12 has three transmit

buffers.

The second requirement calls for some sort of internal prioritizing which

the msCAN12 implements with the local priority concept described

below.

Receive Structures The received messages are stored in a two stage input FIFO. The two

message buffers are mapped using a ping-pong arrangement into a

single memory area (see Figure 43). While the background receive

buffer (RxBG) is exclusively associated to the msCAN12, the foreground

receive buffer (RxFG) is addressed by the CPU12. This scheme

simplifies the handler software as only one address area is applicable for

the receive process.

Both buffers have a size of 13 bytes to store the CAN control bits, the

identifier (standard or extended) and the data contents (for details see

Programmer’s Model of Message Storage).

The receiver full flag (RXF) in the msCAN12 receiver flag register

(CRFLG) (see msCAN12 Receiver Flag Register (CRFLG)) signals the

status of the foreground receive buffer. When the buffer contains a

correctly received message with matching identifier this flag is set.

After the msCAN12 successfully received a message into the

background buffer and if the message passes the filter, it copies the

4-mscan12

MSCAN Controller

Message Storage

MC68HC912DG128

MOTOROLA MSCAN Controller 255

content of RxBG into RxFG1, sets the RXF flag, and emits a receive

interrupt to the CPU2. A new message (which may follow immediately

after the IFS field of the CAN frame) will be received into RxBG. The

over-writing of the background buffer is independent of the identifier filter

function.

The user’s receive handler has to read the received message from

RxFG and to reset the RXF flag in order to acknowledge the interrupt

and to release the foreground buffer.

An overrun condition occurs when both the foreground and the

background receive message buffers are filled with correctly received

messages with accepted identifiers and a further correctly received

message with accepted identifier is received from the bus. The latter

message will be discarded and an error interrupt with overrun indication

will occur if enabled. As long as both buffers remain filled, the msCAN12

is able to transmit messages but it will discard all incoming messages.

1. Only if the RXF flag is not set.

2. The receive interrupt will occur only if not masked. A polling scheme can be applied on RXF

also.

NOTE:

The msCAN12 will receive its own messages into the background

receive buffer RxBG but will not overwrite RxFG and will not emit a

receive interrupt nor will it acknowledge (ACK) its own messages on the

CAN bus. The exception to this rule is that when in loop-back mode

msCAN12 will treat its own messages exactly like all other incoming

messages.

5-mscan12

MSCAN Controller

MC68HC912DG128

256 MSCAN Controller MOTOROLA

Figure 43 User Model for Message Buffer Organization

Transmit Structures The msCAN12 has a triple transmit buffer scheme in order to allow

multiple messages to be set up in advance and to achieve an optimized

real-time performance. The three buffers are arranged as shown in

Figure 43.

All three buffers have a 13 byte data structure similar to the outline of the

receive buffers (see Programmer’s Model of Message Storage). An

additional transmit buffer priority register (TBPR) contains an 8-bit so

called local priority field (PRIO) (see Transmit Buffer Priority Registers

(TBPR)).

RxFG

RxBG

Tx0

RXF

TXE

PRIO

Tx1 TXE

PRIO

Tx2 TXE

PRIO

msCAN12 CPU bus

6-mscan12

MSCAN Controller

Message Storage

MC68HC912DG128

MOTOROLA MSCAN Controller 257

7-mscan12

In order to transmit a message, the CPU12 has to identify an available

transmit buffer which is indicated by a set transmit buffer empty (TXE)

flag in the msCAN12 transmitter flag register (CTFLG) (see msCAN12

Transmitter Flag Register (CTFLG)).

The CPU12 then stores the identifier, the control bits and the data

content into one of the transmit buffers. Finally, the buffer has to be

flagged as being ready for transmission by clearing the TXE flag.

The msCAN12 will then schedule the message for transmission and will

signal the successful transmission of the buffer by setting the TXE flag.

A transmit interrupt will be emitted1 when TXE is set and this can be

used to drive the application software to re-load the buffer.

In case more than one buffer is scheduled for transmission when the

CAN bus becomes available for arbitration, the msCAN12 uses the local

priority setting of the three buffers for prioritizing. For this purpose every

transmit buffer has an 8-bit local priority field (PRIO). The application

software sets this field when the message is set up. The local priority

reflects the priority of this particular message relative to the set of

messages being emitted from this node. The lowest binary value of the

PRIO field is defined to be the highest priority.

The internal scheduling process takes places whenever the msCAN12

arbitrates for the bus. This is also the case after the occurrence of a

transmission error.

When a high priority message is scheduled by the application software

it may become necessary to abort a lower priority message being set up

in one of the three transmit buffers. As messages that are already under

transmission can not be aborted, the user has to request the abort by

setting the corresponding abort request flag (ABTRQ) in the

transmission control register (CTCR). The msCAN12 grants the request,

if possible, by setting the corresponding abort request acknowledge

(ABTAK) and the TXE flag in order to release the buffer and by emitting

a transmit interrupt. The transmit interrupt handler software can tell from

1. The transmit interrupt will occur only if not masked. A polling scheme can be applied on TXE

also.

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MC68HC912DG128

258 MSCAN Controller MOTOROLA

the setting of the ABTAK flag whether the message was actually aborted

(ABTAK=1) or sent in the meantime (ABTAK=0).

Identifier Acceptance Filter

A very flexible programmable generic identifier acceptance filter has

been introduced in order to reduce the CPU interrupt loading. The filter

is programmable to operate in four different modes:

• Two identifier acceptance filters, each to be applied to the full 29

bits of the identifier and to the following bits of the CAN frame:

RTR, IDE, SRR. This mode implements a two filters for a full

length CAN 2.0B compliant extended identifier. Figure 44 shows

how the first 32-bit filter bank (CIDAR0–3, CIDMR0–3) produces

a filter 0 hit. Similarly, the second filter bank (CIDAR4–7,

CIDMR4–7) produces a filter 1 hit.

• Four identifier acceptance filters, each to be applied to a) the 11

bits of the identifier and the RTR bit of CAN 2.0A messages or b)

the 14 most significant bits of the identifier of CAN 2.0B messages.

Figure 45 shows how the first 32-bit filter bank (CIDAR0–3,

CIDMR0–3) produces filter 0 and 1 hits. Similarly, the second filter

bank (CIDAR4–7, CIDMR4–7) produces filter 2 and 3 hits.

• Eight identifier acceptance filters, each to be applied to the first 8

bits of the identifier. This mode implements eight independent

filters for the first 8 bit of a CAN 2.0A compliant standard identifier

or of a CAN 2.0B compliant extended identifier. Figure 46 shows

how the first 32-bit filter bank (CIDAR0–3, CIDMR0–3) produces

filter 0 to 3 hits. Similarly, the second filter bank (CIDAR4–7,

CIDMR4–7) produces filter 4 to 7 hits.

• Closed filter. No CAN message will be copied into the foreground

buffer RxFG, and the RXF flag will never be set.

8-mscan12

MSCAN Controller

Identifier Acceptance Filter

MC68HC912DG128

MOTOROLA MSCAN Controller 259

9-mscan12

Figure 44 32-bit Maskable Identifier Acceptance Filters

Figure 45 16-bit Maskable Acceptance Filters

CIDMR2

ID28 ID21 ID20 ID15 ID14 ID7 ID6 RTR

ID10 ID3 ID2 IDE

AM7

IDR0

IDR1

IDR2 IDR3

AM0 AM7 AM0 AM7 AM7AM0 AM0

AC7 AC0 AC7 AC0 AC7 AC0 AC7 AC0

CIDMRO CIDMR1 CIDMR3

CIDAR3CIDAR2CIDAR1CIDARO

ID accepted (Filter 0 hit)

ID28 ID21 ID20 ID15 ID14 ID7 ID6 RTR

ID10 ID3 ID2 IDE

AM7

IDR0

IDR1

IDR2 IDR3

AM0 AM7 AM0

AC7 AC0 AC7 AC0

CIDMRO CIDMR1

CIDAR1CIDARO

ID accepted (Filter 0 hit)

ID accepted (Filter 1 hit)

AM7 AM0 AM7 AM0

AC7 AC0 AC7 AC0

CIDMR2 CIDMR3

CIDAR3CIDAR2

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260 MSCAN Controller MOTOROLA

Figure 46 8-bit Maskable Acceptance Filters

The identifier acceptance registers (CIDAR0–7) define the acceptable

patterns of the standard or extended identifier (ID10–ID0 or ID28–ID0).

Any of these bits can be marked don’t care in the identifier mask

registers (CIDMR0–7).

A filter hit is indicated to the application software by a set RXF (receive

buffer full flag, see msCAN12 Receiver Flag Register (CRFLG)) and

ID28 ID21 ID20 ID15 ID14 ID7 ID6 RTR

ID10 ID3 ID2 IDE

AM7

IDR0

IDR1

IDR2 IDR3

AM0

AC7 AC0

CIDMRO

CIDARO

ID accepted (Filter 0 hit)

AM7 AM0

AC7 AC0

CIDMR1

CIDAR1

AM7 AM0

AC7 AC0

CIDMR2

CIDAR2

ID accepted (Filter 1 hit)

ID accepted (Filter 2 hit)

AM7 AM0

AC7 AC0

CIDMR3

CIDAR3

10-mscan12

MSCAN Controller

Interrupts

MC68HC912DG128

MOTOROLA MSCAN Controller 261

11-mscan12

three bits in the identifier acceptance control register (see msCAN12

Identifier Acceptance Control Register (CIDAC)). These identifier hit

flags (IDHIT2–0) clearly identify the filter section that caused the

acceptance. They simplify the application software’s task to identify the

cause of the receiver interrupt. In case that more than one hit occurs (two

or more filters match) the lower hit has priority.

A hit will also cause a receiver interrupt if enabled.

Interrupts

The msCAN12 supports four interrupt vectors mapped onto eleven

different interrupt sources, any of which can be individually masked (for

details see msCAN12 Receiver Flag Register (CRFLG) to msCAN12

Transmitter Control Register (CTCR)):

•

Transmit interrupt

: At least one of the three transmit buffers is

empty (not scheduled) and can be loaded to schedule a message

for transmission. The TXE flags of the empty message buffers are

set.

•

Receive interrupt

: A message has been successfully received and

loaded into the foreground receive buffer. This interrupt will be

emitted immediately after receiving the EOF symbol. The RXF flag

is set.

•

Wake-up interrupt

: An activity on the CAN bus occurred during

msCAN12 internal SLEEP mode.

•

Error interrupt

: An overrun, error or warning condition occurred.

The receiver flag register (CRFLG) will indicate one of the

following conditions:

–

Overrun:

an overrun condition as described in Receive

Structures has occurred.

–

Receiver warning

: the receive error counter has reached the

CPU warning limit of 96.

–

Transmitter warning

: the transmit error counter has reached

the CPU warning limit of 96.

MSCAN Controller

MC68HC912DG128

262 MSCAN Controller MOTOROLA

–

Receiver error passive

: the receive error counter has

exceeded the error passive limit of 127 and msCAN12 has

gone to error passive state.

–

Transmitter error passive

: the transmit error counter has

exceeded the error passive limit of 127 and msCAN12 has

gone to error passive state.

–

Bus off

: the transmit error counter has exceeded 255 and

msCAN12 has gone to BUSOFF state.

Interrupt

Acknowledge

Interrupts are directly associated with one or more status flags in either

the msCAN12 receiver flag register (CRFLG) or the msCAN12

transmitter flag register (CTFLG). Interrupts are pending as long as one

of the corresponding flags is set. The flags in above registers must be

reset within the interrupt handler in order to handshake the interrupt. The

flags are reset through writing a 1 to the corresponding bit position. A flag

can not be cleared if the respective condition still prevails.

NOTE:

Bit manipulation instructions (BSET) shall not be used to clear interrupt

flags.

Interrupt Vectors The msCAN12 supports four interrupt vectors as shown in Table 35. The

vector addresses and the relative interrupt priority are dependent on the

chip integration and to be defined.

12-mscan12

MSCAN Controller

Protocol Violation Protection

MC68HC912DG128

MOTOROLA MSCAN Controller 263

13-mscan12

Protocol Violation Protection

The msCAN12 will protect the user from accidentally violating the CAN

protocol through programming errors. The protection logic implements

the following features:

• The receive and transmit error counters cannot be written or

otherwise manipulated.

• All registers which control the configuration of the msCAN12 can

not be modified while the msCAN12 is on-line. The SFTRES bit in

CMCR0 (see msCAN12 Module Control Register (CMCR0))

serves as a lock to protect the following registers:

– msCAN12 module control register 1 (CMCR1)

– msCAN12 bus timing register 0 and 1 (CBTR0, CBTR1)

– msCAN12 identifier acceptance control register (CIDAC)

– msCAN12 identifier acceptance registers (CIDAR0–7)

– msCAN12 identifier mask registers (CIDMR0–7)

• The TxCAN pin is forced to recessive when the msCAN12 is in any

of the low power modes.

Table 35 msCAN12 Interrupt Vectors

Function Source Local Mask Global Mask

Wake-Up WUPIF WUPIE

I Bit

Error

Interrupts

RWRNIF RWRNIE

TWRNIF TWRNIE

RERRIF RERRIE

TERRIF TERRIE

BOFFIF BOFFIE

OVRIF OVRIE

Receive RXF RXFIE

Transmit TXE0 TXEIE0

TXE1 TXEIE1

TXE2 TXEIE2

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MC68HC912DG128

264 MSCAN Controller MOTOROLA

Low Power Modes

The msCAN12 has three modes with reduced power consumption

compared to normal mode. In SLEEP and SOFT_RESET mode, power

consumption is reduced by stopping all clocks except those to access

the registers. In POWER_DOWN mode, all clocks are stopped and no

power is consumed.

The WAI and STOP instructions put the MCU in low power consumption

stand-by modes. Table 36 summarizes the combinations of msCAN12

and CPU modes. A particular combination of modes is entered for the

given settings of the bits CSWAI, SLPAK, and SFTRES. For all modes,

an msCAN wake-up interrupt can occur only if SLPAK=WUPIE=1. While

the CPU is in Wait Mode, the msCAN12 can be operated in Normal

Mode and emit interrupts (registers can be accessed via background

debug mode).

1. X means don’t care.

msCAN12 SLEEP

Mode

The CPU can request the msCAN12 to enter this low-power mode by

asserting the SLPRQ bit in the module configuration register (see

Figure 47). The time when the msCAN12 will then enter SLEEP mode

depends on its current activity:

Table 36 msCAN12 vs. CPU operating modes

msCAN Mode CPU Mode

STOP WAIT RUN

POWER_DOWN CSWAI = X(1)

SLPAK = X

SFTRES = X

CSWAI = 1

SLPAK = X

SFTRES = X

SLEEP CSWAI = 0

SLPAK = 1

SFTRES = 0

CSWAI = X

SLPAK = 1

SFTRES = 0

SOFT_RESET CSWAI = 0

SLPAK = 0

SFTRES = 1

CSWAI = X

SLPAK = 0

SFTRES = 1

Normal CSWAI = 0

SLPAK = 0

SFTRES = 0

CSWAI = X

SLPAK = 0

SFTRES = 0

14-mscan12

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Low Power Modes

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15-mscan12

• if it is transmitting, it will continue to transmit until there is no more

message to be transmitted, and then go into SLEEP mode

• if it receiving, it will wait for the end of this message and then go

into SLEEP mode

• if it is neither transmitting nor receiving, it will immediately go into

SLEEP mode

The application software must avoid setting up a transmission (by

clearing one or more TXE flag(s)) and immediately request SLEEP

mode (by setting SLPRQ). It will then depend on the exact sequence of

operations whether the msCAN12 will start transmitting or go into

SLEEP mode directly.

During SLEEP mode, the SLPAK flag is set. The application software

should use SLPAK as a handshake indication for the request (SLPRQ)

to go into SLEEP mode. When in SLEEP mode, the msCAN12 stops its

internal clocks. Clocks to allow register accesses will still run. The

TxCAN pin will stay in recessive state. If RXF=1, the message can be

read and RXF can be cleared. However, if the msCAN12 is in bus-off

state, it stops counting 128*11 consecutive recessive bits due to the

stopped clocks. Likewise, copying of RxBG into RxFG will not take place

while in sleep mode. It is possible to access the transmit buffers and to

clear the TXE flags. No message abort will take place while in sleep

mode.

The msCAN12 will leave SLEEP mode (wake-up) when

• bus activity occurs or

• the MCU clears the SLPRQ bit or

• the MCU sets SFTRES.

NOTE:

The MCU cannot clear the SLPRQ bit before the msCAN12 is in SLEEP

mode (SLPAK = 1).

After wake-up, the msCAN12 waits for 11 consecutive recessive bits to

synchronize to the bus. As a consequence, if the msCAN12 is woken-up

by a CAN frame, this frame will not be received. The receive message

buffers (RxBG and RxFG) will contain messages if they were received

before sleep mode was entered. Pending copying of RxBG and RxFG,

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266 MSCAN Controller MOTOROLA

as well as pending message aborts and pending message

transmissions, will now be executed. If the msCAN12 is still in bus-off

state after sleep mode was left, it continues counting the 128*11

consecutive recessive bits.

Figure 47 SLEEP Request / Acknowledge Cycle

msCAN12

SOFT_RESET Mode

In SOFT_RESET mode, the msCAN12 is stopped. Registers can still be

accessed. This mode is used to initialize the module configuration, bit

timing, and the CAN message filter. See msCAN12 Module Control

mode.

When setting the SFTRES bit, the msCAN12 immediately stops all

ongoing transmissions and receptions, potentially causing the CAN

protocol violations. The user is responsible to take care that the

msCAN12 is not active when SOFT_RESET mode is entered. The

recommended procedure is to bring the msCAN12 into SLEEP mode

before the SFTRES bit is set.

msCAN12 Sleeping

SLPRQ = 1

SLPAK = 1

msCAN12 Running

SLPRQ = 0

SLPAK = 0

SLEEP Request

SLPRQ = 1

SLPAK = 0

MCU

msCAN12

MCU

or msCAN12

16-mscan12

MSCAN Controller

Timer Link

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MOTOROLA MSCAN Controller 267

17-mscan12

msCAN12

POWER_DOWN

Mode

The msCAN12 is in POWER_DOWN mode when

• the CPU is in STOP mode or

• the CPU is in WAIT mode and the CSWAI bit is set (see msCAN12

Module Control Register (CMCR0)).

When entering the POWER_DOWN mode, the msCAN12 immediately

stops all ongoing transmissions and receptions, potentially causing CAN

protocol violations. The user is responsible to take care that the

msCAN12 is not active when POWER_DOWN mode is entered. The

recommended procedure is to bring the msCAN12 into SLEEP mode

before the STOP instruction (or the WAI instruction, if CSWAI is set) is

executed.

To protect the CAN bus system from fatal consequences of violations to

above rule, the msCAN12 will drive the TxCAN pin into recessive state.

In POWER_DOWN mode, no registers can be accessed.

Programmable

Wake-Up Function

The msCAN12 can be programmed to apply a low-pass filter function to

the RxCAN input line while in SLEEP mode (see control bit WUPM in the

module control register, msCAN12 Module Control Register (CMCR0)).

This feature can be used to protect the msCAN12 from wake-up due to

short glitches on the CAN bus lines. Such glitches can result from

electromagnetic inference within noisy environments.

Timer Link

The msCAN12 will generate a timer signal whenever a valid frame has

been received. Because the CAN specification defines a frame to be

valid if no errors occurred before the EOF field has been transmitted

successfully, the timer signal will be generated right after the EOF. A

pulse of one bit time is generated. As the msCAN12 receiver engine

receives also the frames being sent by itself, a timer signal will also be

generated after a successful transmission.

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268 MSCAN Controller MOTOROLA

The previously described timer signal can be routed into the on-chip

timer module (ECT). Under the control of the timer link enable (TLNKEN)

bit in the CMCR0, this signal will be connected to the ECT timer channel

m input1.

After ECT timer has been programmed to capture rising edge events, it

can be used under software control to generate 16-bit time stamps which

can be stored with the received message.

1. The timer channel being used for the timer link for CAN0 is channel 4 and for CAN1 is channel

Clock System

Figure 48 shows the structure of the msCAN12 clock generation

circuitry. With this flexible clocking scheme the msCAN12 is able to

handle CAN bus rates ranging from 10 kbps up to 1 Mbps.

Figure 48 Clocking Scheme

The clock source bit (CLKSRC) in the msCAN12 module control register

(CMCR1) (see msCAN12 Bus Timing Register 0 (CBTR0)) defines

whether the msCAN12 is connected to the output of the crystal oscillator

(EXTALi) or to the system clock (SYSCLK).

The clock source has to be chosen such that the tight oscillator tolerance

requirements (up to 0.4%) of the CAN protocol are met. Additionally, for

high CAN bus rates (1 Mbps), a 50% duty cycle of the clock is required.

msCAN12CGM

SYSCLK

EXTALi

CGMCANCLK Prescaler

(1...64)

Time quanta

clock

CLKSRC

18-mscan12

MSCAN Controller

Clock System

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MOTOROLA MSCAN Controller 269

19-mscan12

For microcontrollers without the CGM module, CGMCANCLK is driven

from the crystal oscillator (EXTALi).

A programmable prescaler is used to generate out of msCANCLK the

time quanta (Tq) clock. A time quantum is the atomic unit of time handled

by the msCAN12. A bit time is subdivided into three segments1:

• SYNC_SEG: This segment has a fixed length of one time

quantum. Signal edges are expected to happen within this section.

• Time segment 1: This segment includes the PROP_SEG and the

PHASE_SEG1 of the CAN standard. It can be programmed by

setting the parameter TSEG1 to consist of 4 to 16 time quanta.

• Time segment 2: This segment represents the PHASE_SEG2 of

the CAN standard. It can be programmed by setting the TSEG2

parameter to be 2 to 8 time quanta long.

The synchronization jump width can be programmed in a range of 1 to 4

time quanta by setting the SJW parameter.

Above parameters can be set by programming the bus timing registers

(CBTR0–1, see msCAN12 Bus Timing Register 0 (CBTR0) and

msCAN12 Bus Timing Register 1 (CBTR1)).

It is the user’s responsibility to make sure that his bit time settings are in

compliance with the CAN standard. Figure 50 gives an overview on the

CAN conforming segment settings and the related parameter values.

1. For further explanation of the under-lying concepts please refer to ISO/DIS 11519-1, Section

10.3.

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270 MSCAN Controller MOTOROLA

Figure 49 Segments within the Bit Time

Memory Map

The msCAN12 occupies 128 bytes in the CPU12 memory space. The

background receive buffer can only be read in test mode.

Figure 50 CAN Standard Compliant Bit Time Segment Settings

Time Segment 1 TSEG1 Time Segment 2 TSEG2 Synchron.

Jump Width SJW

5 .. 10 4 .. 9 2 1 1 .. 2 0 .. 1

4 .. 11 3 .. 10 3 2 1 .. 3 0 .. 2

5 .. 12 4 .. 11 4 3 1 .. 4 0 .. 3

6 .. 13 5 .. 12 5 4 1 .. 4 0 .. 3

7 .. 14 6 .. 13 6 5 1 .. 4 0 .. 3

8 .. 15 7 .. 14 7 6 1 .. 4 0 .. 3

9 .. 16 8 .. 15 8 7 1 .. 4 0 .. 3

SYNC

_SEG Time segment 1 Time Seg. 2

1 4 ... 16 2 ... 8

8... 25 Time Quanta

= 1 Bit Time

NRZ Signal

Sample point

(single or triple sampling)

(PROP_SEG + PHASE_SEG1) (PHASE_SEG2)

Transmit point

20-mscan12

MSCAN Controller

Programmer’s Model of Message Storage

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MOTOROLA MSCAN Controller 271

21-mscan12

ProgrammerÕs Model of Message Storage

The following section details the organization of the receive and transmit

message buffers and the associated control registers. For reasons of

programmer interface simplification the receive and transmit message

buffers have the same outline. Each message buffer allocates 16 bytes

in the memory map containing a 13 byte data structure. An additional

transmit buffer priority register (TBPR) is defined for the transmit buffers.

Figure 51 msCAN12 Memory Map

$0100 Control registers

9 bytes

$0108

$0109 Reserved

5 bytes

$010D

$010E Error counters

2 bytes

$010F

$0110 Identiﬁer ﬁlter

16 bytes

$011F

$0120 Reserved

29 bytes

$013C

$013D Port CAN registers

3 bytes

$013F

$0140 Foreground Receive buffer

$014F

$0150 Transmit buffer 0

$015F

$0160 Transmit buffer 1

$016F

$0170 Transmit buffer 2

$017F

Figure 52 Message Buffer Organization

Address

(1) Register name

01x0 Identifier register 0

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272 MSCAN Controller MOTOROLA

1. x is 4, 5, 6, or 7 depending on which buffer RxFG,

Tx0, Tx1, or Tx2 respectively.

2. Not applicable for receive buffers

Message Buffer

Outline

Figure 53 shows the common 13 byte data structure of receive and

transmit buffers for extended identifiers. The mapping of standard

identifiers into the IDR registers is shown in Figure 54. All bits of the 13

byte data structure are undefined out of reset.

NOTE:

The foreground receive buffer can be read anytime but can not be

written. The transmit buffers can be read or written anytime.

01x1 Identiﬁer register 1

01x2 Identiﬁer register 2

01x3 Identiﬁer register 3

01x4 Data segment register 0

01x5 Data segment register 1

01x6 Data segment register 2

01x7 Data segment register 3

01x8 Data segment register 4

01x9 Data segment register 5

01xA Data segment register 6

01xB Data segment register 7

01xC Data length register

01xD Transmit buffer priority register(2)

01xE Unused

01xF Unused

Figure 52 Message Buffer Organization

Address

(1) Register name

Figure 53 Receive/Transmit Message Buffer Extended Identifier

ADDR(1) REGISTER R/W BIT 7 654321BIT 0

$01x0 IDR0 RID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21

$01x1 IDR1 RID20 ID19 ID18 SRR (1) IDE (1) ID17 ID16 ID15

$01x2 IDR2 RID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7

22-mscan12

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Programmer’s Model of Message Storage

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MOTOROLA MSCAN Controller 273

23-mscan12

1. x is 4, 5, 6, or 7 depending on which buffer RxFG, Tx0, Tx1, or Tx2 respectively.

Identifier Registers

(IDRn)

The identifiers consist of either 11 bits (ID10–ID0) for the standard, or 29

bits (ID28–ID0) for the extended format. ID10/28 is the most significant

bit and is transmitted first on the bus during the arbitration procedure.

$01x3 IDR3 RID6 ID5 ID4 ID3 ID2 ID1 ID0 RTR

$01x4 DSR0 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01x5 DSR1 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01x6 DSR2 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01x7 DSR3 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01x8 DSR4 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01x9 DSR5 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01xA DSR6 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01xB DSR7 RDB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

$01xC DLR RDLC3 DLC2 DLC1 DLC0

Figure 53 Receive/Transmit Message Buffer Extended Identifier

ADDR(1) REGISTER R/W BIT 7 654321BIT 0

Figure 54 Standard Identifier Mapping

ADDR(1) REGISTER R/W BIT 7 654321BIT 0

$01x0 IDR0 RID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3

$01x1 IDR1 RID2 ID1 ID0 RTR IDE(0)

$01x2 IDR2 R

$01x3 IDR3 R

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274 MSCAN Controller MOTOROLA

The priority of an identifier is defined to be highest for the smallest binary

number.

SRR — Substitute Remote Request

This fixed recessive bit is used only in extended format. It must be set

to 1 by the user for transmission buffers and will be stored as received

on the CAN bus for receive buffers.

IDE — ID Extended

This flag indicates whether the extended or standard identifier format

is applied in this buffer. In case of a receive buffer the flag is set as

being received and indicates to the CPU how to process the buffer

identifier registers. In case of a transmit buffer the flag indicates to the

msCAN12 what type of identifier to send.

0 = Standard format (11-bit)

1 = Extended format (29-bit)

RTR — Remote transmission request

This flag reflects the status of the Remote Transmission Request bit

in the CAN frame. In case of a receive buffer it indicates the status of

the received frame and allows to support the transmission of an

answering frame in software. In case of a transmit buffer this flag

defines the setting of the RTR bit to be sent.

0 = Data frame

1 = Remote frame

Data Length

This register keeps the data length field of the CAN frame.

DLC3 – DLC0 — Data length code bits

The data length code contains the number of bytes (data byte count)

of the respective message. At transmission of a remote frame, the

data length code is transmitted as programmed while the number of

transmitted bytes is always 0. The data byte count ranges from 0 to 8

for a data frame. Table 37 shows the effect of setting the DLC bits.

24-mscan12

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Programmer’s Model of Message Storage

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MOTOROLA MSCAN Controller 275

25-mscan12

Data Segment

Registers (DSRn)

The eight data segment registers contain the data to be transmitted or

being received. The number of bytes to be transmitted or being received

is determined by the data length code in the corresponding DLR.

Transmit Buffer Priority Registers (TBPR)

1. x is 5, 6, or 7 depending on which buffer Tx0, Tx1, or Tx2 respectively.

PRIO7 – PRIO0 — Local Priority

This field defines the local priority of the associated message buffer.

The local priority is used for the internal prioritizing process of the

msCAN12 and is defined to be highest for the smallest binary number.

The msCAN12 implements the following internal priorization

mechanism:

• All transmission buffers with a cleared TXE flag participate in the

priorisation right before the SOF (Start of Frame) is sent.

• The transmission buffer with the lowest local priority field wins the

priorisation.

Table 37 Data length codes

Data length code Data

byte

count

DLC3 DLC2 DLC1 DLC0

00000

00011

00102

00113

01004

01015

01106

01117

10008

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

TBPR(1) RPRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIO0

$01xD W

RESET --------

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276 MSCAN Controller MOTOROLA

• In case of more than one buffer having the same lowest priority the

message buffer with the lower index number wins.

NOTE:

To ensure data integrity, no registers of the transmit buffers shall be

written while the associated TXE flag is cleared.

To ensure data integrity, no registers of the receive buffer shall be read

while the RXF flag is cleared.

ProgrammerÕs Model of Control Registers

Overview The programmer’s model has been laid out for maximum simplicity and

efficiency.

msCAN12 Module Control Register (CMCR0)

CSWAI — CAN Stops in Wait Mode

0 = The module is not affected during WAIT mode.

1 = The module ceases to be clocked during WAIT mode.

SYNCH — Synchronized Status

This bit indicates whether the msCAN12 is synchronized to the CAN

bus and as such can participate in the communication process.

0 = msCAN12 is not synchronized to the CAN bus

1 = msCAN12 is synchronized to the CAN bus

TLNKEN — Timer Enable

This flag is used to establish a link between the msCAN12 and the

on-chip timer (see Timer Link).

0 = The port is connected to the timer input.

1 = The msCAN12 timer signal output is connected to the timer

input.

Bit 7 654321Bit 0

CMCR0 R 0 0 CSWAI SYNCH TLNKEN SLPAK SLPRQ SFTRES

$0100 W

RESET 00100001

26-mscan12

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Programmer’s Model of Control Registers

MC68HC912DG128

MOTOROLA MSCAN Controller 277

27-mscan12

SLPAK — SLEEP Mode Acknowledge

This flag indicates whether the msCAN12 is in module internal

SLEEP Mode. It shall be used as a handshake for the SLEEP Mode

request (see msCAN12 SLEEP Mode).

0 = Wake-up – The msCAN12 is not in SLEEP Mode.

1 = SLEEP – The msCAN12 is in SLEEP Mode.

SLPRQ — SLEEP request

This flag allows to request the msCAN12 to go into an internal

power-saving mode (see msCAN12 SLEEP Mode).

0 = Wake-up – The msCAN12 will function normally.

1 = SLEEP request – The msCAN12 will go into SLEEP Mode.

SFTRES— SOFT_RESET

When this bit is set by the CPU, the msCAN12 immediately enters the

SOFT_RESET state. Any ongoing transmission or reception is

aborted and synchronization to the bus is lost.

The following registers will go into and stay in the same state as out

of hard reset: CMCR0, CRFLG, CRIER, CTFLG, CTCR.

The registers CMCR1, CBTR0, CBTR1, CIDAC, CIDAR0–3,

CIDMR0–3 can only be written by the CPU when the msCAN12 is in

SOFT_RESET state. The values of the error counters are not affected

by SOFT_RESET.

When this bit is cleared by the CPU, the msCAN12 will try to

synchronize to the CAN bus: If the msCAN12 is not in BUSOFF state

it will be synchronized after 11 recessive bits on the bus; if the

msCAN12 is in BUSOFF state it continues to wait for 128 occurrences

of 11 recessive bits.

Clearing SFTRES and writing to other bits in CMCR0 must be in

separate instructions.

0 = Normal operation

1 = msCAN12 in SOFT_RESET state.

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278 MSCAN Controller MOTOROLA

msCAN12 Module Control Register (CMCR1)

LOOPB — Loop Back Self Test Mode

When this bit is set the msCAN12 performs an internal loop back

which can be used for self test operation: the bit stream output of the

transmitter is fed back to the receiver. The RxCAN input pin is ignored

and the TxCAN output goes to the recessive state (1). Note that in this

state the msCAN12 ignores the bit sent during the ACK slot of the

CAN frame Acknowledge field to insure proper reception of its own

message and will treat messages being received while in

transmission as received messages from remote nodes.

0 = Normal operation

1 = Activate loop back self test mode

WUPM — Wake-Up Mode

This flag defines whether the integrated low-pass filter is applied to

protect the msCAN12 from spurious wake-ups (see Programmable

Wake-Up Function).

0 = msCAN12 will wake up the CPU after any recessive to

dominant edge on the CAN bus.

1 = msCAN12 will wake up the CPU only in case of dominant pulse

on the bus which has a length of at least approximately Twup.

CLKSRC — msCAN12 Clock Source

This flag defines which clock source the msCAN12 module is driven

from (only for system with CGM module; see Clock System,

Figure 48).

0 = The msCAN12 clock source is EXTALi.

1 = The msCAN12 clock source is SYSCLK, twice the frequency of

ECLK.

NOTE:

The CMCR1 register can only be written if the SFTRES bit in CMCR0 is

set.

Bit 7 654321Bit 0

CMCR1 R 00000

LOOPB WUPM CLKSRC

$0101 W

RESET 00000000

28-mscan12

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Programmer’s Model of Control Registers

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MOTOROLA MSCAN Controller 279

29-mscan12

msCAN12 Bus Timing Register 0 (CBTR0)

SJW1, SJW0 — Synchronization Jump Width

The synchronization jump width defines the maximum number of time

quanta (Tq) clock cycles by which a bit may be shortened, or

lengthened, to achieve resynchronization on data transitions on the

bus (see Table 38).

BRP5 – BRP0 — Baud Rate Prescaler

These bits determine the time quanta (Tq) clock, which is used to

build up the individual bit timing, according to Table 39.

NOTE:

The CBTR0 register can only be written if the SFTRES bit in CMCR0 is

set.

Bit 7 654321Bit 0

CBTR0 R SJW1 SJW0 BRP5 BRP4 BRP3 BRP2 BRP1 BRP0

$0102 W

RESET 00000000

Table 38 Synchronization jump width

SJW1 SJW0 Synchronization jump width

0 0 1 Tq clock cycle

0 1 2 Tq clock cycles

1 0 3 Tq clock cycles

1 1 4 Tq clock cycles

Table 39 Baud rate prescaler

BRP5 BRP4 BRP3 BRP2 BRP1 BRP0 Prescaler value (P)

000000 1

000001 2

000010 3

000011 4

:::::: :

111111 64

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msCAN12 Bus Timing Register 1 (CBTR1)

SAMP — Sampling

This bit determines the number of samples of the serial bus to be

taken per bit time. If set three samples per bit are taken, the regular

one (sample point) and two preceding samples, using a majority rule.

For higher bit rates SAMP should be cleared, which means that only

one sample will be taken per bit.

0 = One sample per bit.

1 = Three samples per bit1.

TSEG22 – TSEG10 — Time Segment

Time segments within the bit time fix the number of clock cycles per

bit time, and the location of the sample point.

Time segment 1 (TSEG1) and time segment 2 (TSEG2) are

programmable as shown in Table 41.

1. In this case PHASE_SEG1 must be at least 2 TimeQuanta.

Bit 7 654321Bit 0

CBTR1 R SAMP TSEG22 TSEG21 TSEG20 TSEG13 TSEG12 TSEG11 TSEG10

$0103 W

RESET 00000000

Table 40 Time segment syntax

SYNC_SEG System expects transitions to occur on the bus during this period.

Transmit point A node in transmit mode will transfer a new value to the CAN bus at

this point.

Sample point A node in receive mode will sample the bus at this point. If the three

samples per bit option is selected then this point marks the position

of the third sample.

Table 41 Time segment values

TSEG13 TSEG12 TSEG11 TSEG10 Time segment 1 TSEG22 TSEG21 TSEG20 Time segment 2

0 0 0 0 1 Tq clock cycle 0 0 0 1 Tq clock cycle

0 0 0 1 2 Tq clock cycles 0 0 1 2 Tq clock cycles

0 0 1 0 3 Tq clock cycles . . . .

0 0 1 1 4 Tq clock cycles . . . .

. . . . . 1 1 1 8 Tq clock cycles

.... .

1 1 1 1 16 Tq clock cycles

30-mscan12

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Programmer’s Model of Control Registers

MC68HC912DG128

MOTOROLA MSCAN Controller 281

31-mscan12

The bit time is determined by the oscillator frequency, the baud rate

prescaler, and the number of time quanta (Tq) clock cycles per bit (as

shown above).

NOTE:

The CBTR1 register can only be written if the SFTRES bit in CMCR0 is

set.

msCAN12

Receiver Flag

All bits of this register are read and clear only. A flag can be cleared by

writing a 1 to the corresponding bit position. A flag can only be cleared

when the condition which caused the setting is no more valid. Writing a

0 has no effect on the flag setting. Every flag has an associated interrupt

enable flag in the CRIER register. A hard or soft reset will clear the

WUPIF — Wake-up Interrupt Flag

If the msCAN12 detects bus activity while it is in SLEEP Mode, it

clears the SLPAK bit in the CMCR0 register; the WUPIF bit will then

be set. If not masked, a Wake-Up interrupt is pending while this flag

is set.

0 = No wake-up activity has been observed while in SLEEP Mode.

1 = msCAN12 has detected activity on the bus and requested

wake-up.

RWRNIF — Receiver Warning Interrupt Flag

This bit will be set when the msCAN12 goes into warning status due

to the Receive Error counter (REC) exceeding 96 and neither one of

the Error interrupt flags or the Bus-Off interrupt flag is set1. If not

masked, an Error interrupt is pending while this flag is set.

0 = No receiver warning status has been reached.

1 = msCAN12 went into receiver warning status.

1. RWRNIF = (96 < REC) & RERRIF& TERRIF & BOFFIF

Bit 7 654321Bit 0

CRFLG R WUPIF RWRNIF TWRNIF RERRIF TERRIF BOFFIF OVRIF RXF

$0104 W

RESET 00000000

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282 MSCAN Controller MOTOROLA

TWRNIF — Transmitter Warning Interrupt Flag

This bit will be set when the msCAN12 goes into warning status due

to the Transmit Error counter (TEC) exceeding 96 and neither one of

the Error interrupt flags or the Bus-Off interrupt flag is set1. If not

masked, an Error interrupt is pending while this flag is set.

0 = No transmitter warning status has been reached.

1 = msCAN12 went into transmitter warning status.

RERRIF — Receiver Error Passive Interrupt Flag

This bit will be set when the msCAN12 goes into error passive status

due to the Receive Error counter (REC) exceeding 127 and the

Bus-Off interrupt flag is not set2. If not masked, an Error interrupt is

pending while this flag is set.

0 = No receiver error passive status has been reached.

1 = msCAN12 went into receiver error passive status.

TERRIF — Transmitter Error Passive Interrupt Flag

This bit will be set when the msCAN12 goes into error passive status

due to the Transmit Error counter (TEC) exceeding 127 and the

Bus-Off interrupt flag is not set3. If not masked, an Error interrupt is

pending while this flag is set.

0 = No transmitter error passive status has been reached.

1 = msCAN12 went into transmitter error passive status.

BOFFIF — BUSOFF Interrupt Flag

This bit will be set when the msCAN12 goes into BUSOFF status, due

to the Transmit Error counter exceeding 255. It cannot be cleared

before the msCAN12 has monitored 128*11 consecutive recessive

bits on the bus. If not masked, an Error interrupt is pending while this

flag is set.

0 = No BUSOFF status has been reached.

1 = msCAN12 went into BUSOFF status.

1. TWRNIF = (96 < TEC) & RERRIF& TERRIF & BOFFIF

2. RERRIF = (128 < REC < 255) & BOFFIF

3. TERRIF = (128 < TEC < 255) & BOFFIF

32-mscan12

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Programmer’s Model of Control Registers

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MOTOROLA MSCAN Controller 283

33-mscan12

OVRIF — Overrun Interrupt Flag

This bit will be set when a data overrun condition occurred. If not

masked, an Error interrupt is pending while this flag is set.

0 = No data overrun has occurred.

1 = A data overrun has been detected.

RXF — Receive Buffer Full

The RXF flag is set by the msCAN12 when a new message is

available in the foreground receive buffer. This flag indicates whether

the buffer is loaded with a correctly received message. After the CPU

has read that message from the receive buffer the RXF flag must be

handshaked (cleared) in order to release the buffer. A set RXF flag

prohibits the exchange of the background receive buffer into the

foreground buffer. If not masked, a Receive interrupt is pending while

this flag is set.

0 = The receive buffer is released (not full).

1 = The receive buffer is full. A new message is available.

NOTE:

The CRFLG register is held in the reset state if the SFTRES bit in

CMCR0 is set.

msCAN12 Receiver Interrupt Enable Register (CRIER)

WUPIE — Wake-up Interrupt Enable

0 = No interrupt will be generated from this event.

1 = A wake-up event will result in a wake-up interrupt.

RWRNIE — Receiver Warning Interrupt Enable

0 = No interrupt will be generated from this event.

1 = A receiver warning status event will result in an error interrupt.

TWRNIE — Transmitter Warning Interrupt Enable

0 = No interrupt will be generated from this event.

1 = A transmitter warning status event will result in an error

interrupt.

Bit 7 654321Bit 0

CRIER R WUPIE RWRNIE TWRNIE RERRIE TERRIE BOFFIE OVRIE RXFIE

$0105 W

RESET 00000000

MSCAN Controller

MC68HC912DG128

284 MSCAN Controller MOTOROLA

RERRIE — Receiver Error Passive Interrupt Enable

0 = No interrupt will be generated from this event.

1 = A receiver error passive status event will result in an error

interrupt.

TERRIE — Transmitter Error Passive Interrupt Enable

0 = No interrupt will be generated from this event.

1 = A transmitter error passive status event will result in an error

interrupt.

BOFFIE — BUSOFF Interrupt Enable

0 = No interrupt will be generated from this event.

1 = A BUSOFF event will result in an error interrupt.

OVRIE — Overrun Interrupt Enable

0 = No interrupt will be generated from this event.

1 = An overrun event will result in an error interrupt.

RXFIE — Receiver Full Interrupt Enable

0 = No interrupt will be generated from this event.

1 = A receive buffer full (successful message reception) event will

result in a receive interrupt.

NOTE:

The CRIER register is held in the reset state if the SFTRES bit in CMCR0

is set.

msCAN12

Transmitter Flag

The Abort Acknowledge flags are read only. The Transmitter Buffer

Empty flags are read and clear only. A flag can be cleared by writing a1

to the corresponding bit position. Writing a zero has no effect on the flag

setting. The Transmitter Buffer Empty flags each have an associated

interrupt enable flag in the CTCR register. A hard or soft reset will reset

the register.

Bit 7 654321Bit 0

CTFLG R 0 ABTAK2 ABTAK1 ABTAK0 0 TXE2 TXE1 TXE0

$0106 W

RESET 00000111

34-mscan12

MSCAN Controller

Programmer’s Model of Control Registers

MC68HC912DG128

MOTOROLA MSCAN Controller 285

35-mscan12

ABTAK2 – ABTAK0 — Abort Acknowledge

This flag acknowledges that a message has been aborted due to a

pending abort request from the CPU. After a particular message

buffer has been flagged empty, this flag can be used by the

application software to identify whether the message has been

aborted successfully or has been sent in the meantime. The flag is

reset implicitly whenever the associated TXE flag is set to 0.

0 = The massage has not been aborted, thus has been sent out.

1 = The message has been aborted.

TXE2 – TXE0 —Transmitter Buffer Empty

This flag indicates that the associated transmit message buffer is

empty, thus not scheduled for transmission. The CPU must

handshake (clear) the flag after a message has been set up in the

transmit buffer and is due for transmission. The msCAN12 will set the

flag after the message has been sent successfully. The flag will also

be set by the msCAN12 when the transmission request was

successfully aborted due to a pending abort request (msCAN12

Transmitter Control Register (CTCR)). If not masked, a transmit

interrupt is pending while this flag is set.

Clearing this flag will also clear the corresponding Abort Acknowledge

flag (ABTAK, see above). Setting this flag will clear the corresponding

Abort Request flag (ABTRQ, msCAN12 Transmitter Control Register

(CTCR)).

0 = The associated message buffer is full (loaded with a message

due for transmission).

1 = The associated message buffer is empty (not scheduled).

NOTE:

The CTFLG register is held in the reset state if the SFTRES bit in

CMCR0 is set.

MSCAN Controller

MC68HC912DG128

286 MSCAN Controller MOTOROLA

msCAN12 Transmitter Control Register (CTCR)

ABTRQ2 – ABTRQ0 — Abort Request

The CPU sets this bit to request that an already scheduled message

buffer (TXE = 0) shall be aborted. The msCAN12 will grant the

request when the message is not already under transmission. When

a message is aborted the associated TXE and the abort acknowledge

flag (ABTAK, see msCAN12 Transmitter Flag Register (CTFLG)) will

be set and an TXE interrupt will occur if enabled. The CPU can not

reset ABTRQx. ABTRQx is reset implicitly whenever the associated

TXE flag is set.

0 = No abort request.

1 = Abort request pending.

NOTE:

The software must not clear one or more of the TXE flags in CTFGL and

simultaneously set the respective ABTRQ bit(s).

TXEIE2 – TXEIE0 — Transmitter Empty Interrupt Enable

0 = No interrupt will be generated from this event.

1 = A transmitter empty (transmit buffer available for transmission)

event will result in a transmitter empty interrupt.

NOTE:

The CTCR register is held in the reset state if the SFTRES bit in CMCR0

is set.

Bit 7 654321Bit 0

CTCR R 0 ABTRQ2 ABTRQ1 ABTRQ0 0TXEIE2 TXEIE1 TXEIE0

$0107 W

RESET 00000000

36-mscan12

MSCAN Controller

Programmer’s Model of Control Registers

MC68HC912DG128

MOTOROLA MSCAN Controller 287

37-mscan12

msCAN12 Identifier Acceptance Control Register (CIDAC)

IDAM1 – IDAM0 — Identifier Acceptance Mode

The CPU sets these flags to define the identifier acceptance filter

organization (see Identifier Acceptance Filter). Table 41 summarizes

the different settings. In Filter Closed mode no messages will be

accepted such that the foreground buffer will never be reloaded.

IDHIT2 – IDHIT0 — Identifier Acceptance Hit Indicator

The msCAN12 sets these flags to indicate an identifier acceptance hit

(see Identifier Acceptance Filter). Table 41 summarizes the different

settings.

The IDHIT indicators are always related to the message in the

foreground buffer. When a message gets copied from the background to

the foreground buffer the indicators are updated as well.

NOTE:

The CIDAC register can only be written if the SFTRES bit in CMCR0 is

set.

Bit 7 654321Bit 0

CIDAC R 0 0 IDAM1 IDAM0 0 IDHIT2 IDHIT1 IDHIT0

$0108 W

RESET 00000000

Table 42 Identiﬁer Acceptance Mode Settings

IDAM1 IDAM0 Identifier Acceptance Mode

0 0 Two 32 bit Acceptance Filters

0 1 Four 16 bit Acceptance Filters

1 0 Eight 8 bit Acceptance Filters

1 1 Filter Closed

Table 43 Identiﬁer Acceptance Hit Indication

IDHIT2 IDHIT1 IDHIT0 Identifier Acceptance Hit

0 0 0 Filter 0 Hit

0 0 1 Filter 1 Hit

0 1 0 Filter 2 Hit

0 1 1 Filter 3 Hit

1 0 0 Filter 4 Hit

1 0 1 Filter 5 Hit

1 1 0 Filter 6 Hit

1 1 1 Filter 7 Hit

MSCAN Controller

MC68HC912DG128

288 MSCAN Controller MOTOROLA

msCAN12 Receive Error Counter (CRXERR)

This register reflects the status of the msCAN12 receive error counter.

The register is read only.

msCAN12 Transmit Error Counter (CTXERR)

This register reflects the status of the msCAN12 transmit error counter.

The register is read only.

NOTE:

Both error counters must only be read when in SLEEP or SOFT_RESET

mode.

msCAN12

Identifier

Acceptance

Registers

(CIDAR0Ð7)

On reception each message is written into the background receive

buffer. The CPU is only signalled to read the message however, if it

passes the criteria in the identifier acceptance and identifier mask

registers (accepted); otherwise, the message will be overwritten by the

next message (dropped).

The acceptance registers of the msCAN12 are applied on the IDR0 to

IDR3 registers of incoming messages in a bit by bit manner.

For extended identifiers all four acceptance and mask registers are

applied. For standard identifiers only the first two (CIDMR0/1 and

CIDAR0/1) are applied. In the latter case it is required to program the

three last bits (AM2 – AM0) in the mask register CIDMR1 to ‘don’t care’.

Bit 7 654321Bit 0

CRXERR R RXERR7 RXERR6 RXERR5 RXERR4 RXERR3 RXERR2 RXERR1 RXERR0

$010E W

RESET 00000000

Bit 7 654321Bit 0

CTXERR R TXERR7 TXERR6 TXERR5 TXERR4 TXERR3 TXERR2 TXERR1 TXERR0

$010F W

RESET 00000000

38-mscan12

MSCAN Controller

Programmer’s Model of Control Registers

MC68HC912DG128

MOTOROLA MSCAN Controller 289

39-mscan12

AC7 – AC0 — Acceptance Code Bits

AC7 – AC0 comprise a user defined sequence of bits with which the

corresponding bits of the related identifier register (IDRn) of the

receive message buffer are compared. The result of this comparison

is then masked with the corresponding identifier mask register.

NOTE:

The CIDAR0–7 registers can only be written if the SFTRES bit in

CMCR0 is set.

Figure 55 Identifier Acceptance Registers (1st bank)

Bit 7 654321Bit 0

CIDAR0 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

$0110 W

CIDAR1 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

$0111 W

CIDAR2 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

$0112 W

CIDAR3 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

$0113 W

RESET --------

Figure 56 Identifier Acceptance Registers (2nd bank)

Bit 7 654321Bit 0

CIDAR4 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

$0118 W

CIDAR5 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

$0119 W

CIDAR6 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

$011A W

CIDAR7 R AC7 AC6 AC5 AC4 AC3 AC2 AC1 AC0

$011B W

RESET --------

MSCAN Controller

MC68HC912DG128

290 MSCAN Controller MOTOROLA

msCAN12

Identifier Mask

Registers

(CIDMR0Ð7)

The identifier mask register specifies which of the corresponding bits in

the identifier acceptance register are relevant for acceptance filtering.

AM7 – AM0 — Acceptance Mask Bits

If a particular bit in this register is cleared this indicates that the

corresponding bit in the identifier acceptance register must be the

same as its identifier bit, before a match will be detected. The

message will be accepted if all such bits match. If a bit is set, it

indicates that the state of the corresponding bit in the identifier

acceptance register will not affect whether or not the message is

accepted.

0 = Match corresponding acceptance code register and identifier bits.

1 = Ignore corresponding acceptance code register bit.

NOTE:

The CIDMR0–7 registers can only be written if the SFTRES bit in

CMCR0 is set.

Figure 57 Identifier Mask Registers (1st bank)

Bit 7 654321Bit 0

CIDMR0 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

$0114 W

CIDMR1 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

$0115 W

CIDMR2 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

$0116 W

CIDMR3 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

$0117 W

RESET --------

Figure 58 Identifier Mask Registers (2nd bank)

Bit 7 654321Bit 0

CIDMR4 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

$011C W

CIDMR5 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

$011D W

CIDMR6 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

$011E W

CIDMR7 R AM7 AM6 AM5 AM4 AM3 AM2 AM1 AM0

$011F W

RESET --------

40-mscan12

MSCAN Controller

Programmer’s Model of Control Registers

MC68HC912DG128

MOTOROLA MSCAN Controller 291

41-mscan12

msCAN12 Port CAN Control Register (PCTLCAN)

The following bits control pins 7 through 2 of Port CAN when they are

implemented externally.

PUPCAN — Pull-Up Enable Port CAN

0 = Pull mode disabled for Port CAN.

1 = Pull mode enabled for Port CAN.

RDPCAN — Reduced Drive Port CAN

0 = Reduced drive disabled for Port CAN.

1 = Reduced drive enabled for Port CAN.

msCAN12 Port CAN Data Register (PORTCAN)

Port bits 7 to 2 will read zero when configured as inputs because they

are not implemented externally.

When configured as output, port bits 7 to 2 will read the last value

written.

Reading bits 1 and 0 returns the value of the TxCan and RxCan pins,

respectively.

TxCan and RxCan pins for CAN1 are not implemented for

MC68HC912DA128.

Bit 7 654321Bit 0

PCTLCAN R 000000

PUPCAN RDPCAN

$013D W

RESET 00000000

Bit 7 654321Bit 0

PORTCAN R PCAN7 PCAN6 PCAN5 PCAN4 PCAN3 PCAN2 TxCAN RxCAN

$013E W

RESET - - - - -

MSCAN Controller

MC68HC912DG128

292 MSCAN Controller MOTOROLA

msCAN12 Port CAN Data Direction Register (DDRCAN)

DDCAN7 – DDCAN2 — This bits served as memory locations since

there are no corresponding external port pins.

Bit 7 654321Bit 0

DDRCAN R DDCAN7 DDCAN6 DDCAN5 DDCAN4 DDCAN3 DDCAN2 00

$013F W

RESET 00000000

42-mscan12

MC68HC912DG128

MOTOROLA Analog-To-Digital Converter (ATD) 293

Analog-To-Digital Converter (ATD)

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .293

Functional Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294

ATD Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .295

ATD Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .304

Introduction

The MC68HC912DG128 has two identical ATD modules identified as

ATD0 and ATD1. Except for the VDDA and VSSA Analog supply voltage,

all pins are duplicated and indexed with ‘0’ or ‘1’ in the following

description. An ‘x’ indicates either ‘0’ or ‘1’.

The ATD module is an 8-channel, 10-bit, multiplexed-input

successive-approximation analog-to-digital converter, accurate to ±1

least significant bit (LSB). It does not require external sample and hold

circuits because of the type of charge redistribution technique used. The

ATD converter timing can be synchronized to the system P clock. The

ATD module consists of a 16-word (32-byte) memory-mapped control

1-atd

Analog-To-Digital Converter

MC68HC912DG128

294 Analog-To-Digital Converter (ATD) MOTOROLA

Figure 59 Analog-to-Digital Converter Block Diagram

Functional Description

A single conversion sequence consists of four or eight conversions,

depending on the state of the select 8 channel mode (S8CM) bit when

ATDCTL5 is written. There are eight basic conversion modes. In the

non-scan modes, the SCF bit is set after the sequence of four or eight

conversions has been performed and the ATD module halts. In the scan

modes, the SCF bit is set after the first sequence of four or eight

conversions has been performed, and the ATD module continues to

restart the sequence. In both modes, the CCF bit associated with each

conversion result. That flag is cleared automatically when that result

registers.

MODE AND TIMING CONTR OLS

ATD 0

ATD 1

ATD 2

ATD 3

ATD 4

ATD 5

ATD 6

ATD 7

SAR

RC DAC ARRAY

AND COMPARATOR

INTERNAL BUS

VDDA

VSSA

VRLx

VRHx

CLOCK

SELECT/PRESCALE

ANALOG MUX

AND

SAMPLE BUFFER AMP

PORT AD

DATA INPUT REGISTER

ANx7/PADx7

ANx6/PADx6

ANx5/PADx5

ANx4/PADx4

ANx3/PADx3

ANx2/PADx2

ANx1/PADx1

ANx0/PADx0

REFERENCE

SUPPLY

HC12 ATD BLOCK

2--atd

Analog-To-Digital Converter (ATD)

ATD Registers

MC68HC912DG128

MOTOROLA Analog-To-Digital Converter (ATD) 295

ATD Registers

Control and data registers for the ATD modules are described below.

Both ATDs have identical control registers mapped in two blocks of 16

bytes.

Writes to this register will abort current conversion sequence.

READ: any time WRITE: any time.

WRITE: Write to this register has no meaning.

READ: Special Mode only.

The ATD control register 2 and 3 are used to select the power up mode,

interrupt control, and freeze control. Writes to these registers abort any

current conversion sequence.

Read or write anytime except ASCIF bit, which cannot be written.

Bit positions ATDCTL2[4:2] and ATDCTL3[7:2] are unused and always

read as zeros.

ATD0CTL0/ATD1CTL0 — Reserved $0060/$01E0

Bit 7 654321Bit 0

RESET: 00000000

ATD0CTL1/ATD1CTL1 — Reserved $0061/$01E1

Bit 7 654321Bit 0

RESET: 00000000

ATD0CTL2/ATD1CTL2 — ATD Control Register 2 $0062/$01E2

Bit 7 654321Bit 0

ADPU AFFC ASWAI 0 0 0 ASCIE ASCIF

RESET: 00000000

3-atd

Analog-To-Digital Converter

MC68HC912DG128

296 Analog-To-Digital Converter (ATD) MOTOROLA

ADPU — ATD Disable

0 = Disables the ATD, including the analog section for reduction in

power consumption.

1 = Allows the ATD to function normally.

Software can disable the clock signal to the A/D converter and power

down the analog circuits to reduce power consumption. When reset

to zero, the ADPU bit aborts any conversion sequence in progress.

Because the bias currents to the analog circuits are turned off, the

ATD requires a period of recovery time to stabilize the analog circuits

after setting the ADPU bit.

AFFC — ATD Fast Flag Clear All

0 = ATD flag clearing operates normally (read the status register

before reading the result register to clear the associated CCF

bit).

1 = Changes all ATD conversion complete flags to a fast clear

sequence. Any access to a result register (ATD0–7) will cause

the associated CCF flag to clear automatically if it was set at

the time.

ASWAI — ATD Stops in Wait Mode

0 = ATD continues to run when the MCU is in wait mode

1 = ATD stops to save power when the MCU is in wait mode

When the ASWAI bit is set and the module enters wait mode, most of the

clocks stop and the analog portion powers down. When the module

comes out of wait, it is recommended that a stabilization delay (stop and

ATD power up recovery time, tSR) is allowed before new conversions are

started. Additionally, the ATD does not re-initialize automatically on

leaving wait mode.

ASCIE — ATD Sequence Complete Interrupt Enable

0 = Disables ATD interrupt

1 = Enables ATD interrupt on sequence complete

ASCIF — ATD Sequence Complete Interrupt Flag

Cannot be written in any mode.

0 = No ATD interrupt occurred

1 = ATD sequence complete

4-atd

Analog-To-Digital Converter (ATD)

ATD Registers

MC68HC912DG128

MOTOROLA Analog-To-Digital Converter (ATD) 297

FRZ1, FRZ0 — Background Debug (Freeze) Enable (suspend module

operation at breakpoint)

When debugging an application, it is useful in many cases to have the

ATD pause when a breakpoint is encountered. These two bits

determine how the ATD will respond when background debug mode

becomes active.

The ATD control register 4 is used to select the clock source and set

up the prescaler. Writes to the ATD control registers initiate a new

conversion sequence. If a write occurs while a conversion is in

progress, the conversion is aborted and ATD activity halts until a write

to ATDCTL5 occurs.

RES10 — 10 bit Mode

0 = 8 bit operation

1 = 1= 10 bit operation

SMP1, SMP0 — Select Sample Time

Used to select one of four sample times after the buffered sample and

transfer has occurred.

ATD0CTL3/ATD1CTL3 — ATD Control Register 3 $0063/$01E3

Bit 7 654321Bit 0

000000FRZ1 FRZ0

RESET: 00000000

Table 44 ATD Response to Background Debug Enable

FRZ1 FRZ0 ATD Response

0 0 Continue conversions in active background mode

0 1 Reserved

1 0 Finish current conversion, then freeze

1 1 Freeze when BDM is active

ATD0CTL4/ATD1CTL4 — ATD Control Register 4 $0064/$01E4

Bit 7 654321Bit 0

RES10 SMP1 SMP0 PRS4 PRS3 PRS2 PRS1 PRS0

RESET: 00000001

5-atd

Analog-To-Digital Converter

MC68HC912DG128

298 Analog-To-Digital Converter (ATD) MOTOROLA

PRS4, PRS3, PRS2, PRS1, PRS0 — Select Divide-By Factor for ATD

P-Clock Prescaler.

The binary value written to these bits (1 to 31) selects the divide-by

factor for the modulo counter-based prescaler. The P clock is divided

by this value plus one and then fed into a ÷2 circuit to generate the

ATD module clock. The divide-by-two circuit insures symmetry of the

output clock signal. Clearing these bits causes the prescale value

default to one which results in a ÷2 prescale factor. This signal is then

fed into the ÷2 logic. The reset state divides the P clock by a total of

four and is appropriate for nominal operation at 2 MHz. Table 46

shows the divide-by operation and the appropriate range of system

clock frequencies.

1. Maximum conversion frequency is 2 MHz. Maximum P clock divisor value will become

maximum conversion rate that can be used on this ATD module.

2. Minimum conversion frequency is 500 kHz. Minimum P clock divisor value will become

minimum conversion rate that this ATD can perform.

Table 45 Final Sample Time Selection

SMP1 SMP0 Final Sample Time

0 0 2 A/D clock periods

0 1 4 A/D clock periods

1 0 8 A/D clock periods

1 1 16 A/D clock periods

Table 46 Clock Prescaler Values

Prescale

Value Total

Divisor Max P Clock(1) Min P Clock(2)

00000 ÷2 4 MHz 1 MHz

00001 ÷4 8 MHz 2 MHz

00010 ÷6 8 MHz 3 MHz

00011 ÷8 8 MHz 4 MHz

00100 ÷10 8 MHz 5 MHz

00101 ÷12 8 MHz 6 MHz

00110 ÷14 8 MHz 7 MHz

00111 ÷16 8 MHz 8 MHz

01xxx Do Not Use

1xxxx

6-atd

Analog-To-Digital Converter (ATD)

ATD Registers

MC68HC912DG128

MOTOROLA Analog-To-Digital Converter (ATD) 299

7-atd

The ATD control register 5 is used to select the conversion modes,

the conversion channel(s), and initiate conversions.

Read or write any time. Writes to the ATD control registers initiate a

new conversion sequence. If a conversion sequence is in progress

when a write occurs, that sequence is aborted and the SCF and CCF

bits are reset.

S8CM — Select 8 Channel Mode

0 = Conversion sequence consists of four conversions

1 = Conversion sequence consists of eight conversions

SCAN — Enable Continuous Channel Scan

0 = Single conversion sequence

1 = Continuous conversion sequences (scan mode)

When a conversion sequence is initiated by a write to the ATDCTL

eight, depending on the S8CM bit) conversions or continuously

performing four (or eight) conversion sequences.

MULT — Enable Multichannel Conversion

0 = ATD sequencer runs all four or eight conversions on a single

input channel selected via the CD, CC, CB, and CA bits.

1 = ATD sequencer runs each of the four or eight conversions on

sequential channels in a specific group. Refer to Table 47.

ATD0CTL5/ATD1CTL5 — ATD Control Register 5 $0065/$01E5

Bit 7 654321Bit 0

0 S8CM SCAN MULT CD CC CB CA

RESET: 00000000

Analog-To-Digital Converter

MC68HC912DG128

300 Analog-To-Digital Converter (ATD) MOTOROLA

CD, CC, CB, and CA — Channel Select for Conversion

Table 47 Multichannel Mode Result Register Assignment

S8CM CD CC CB CA Channel Signal Result in ADRxx

if MULT = 1

000

0 0 AN0 ADRx0

0 1 AN1 ADRx1

1 0 AN2 ADRx2

1 1 AN3 ADRx3

001

0 0 AN4 ADRx0

0 1 AN5 ADRx1

1 0 AN6 ADRx2

1 1 AN7 ADRx3

010

0 0 Reserved ADRx0

0 1 Reserved ADRx1

1 0 Reserved ADRx2

1 1 Reserved ADRx3

011

00V

RH ADRx0

01V

RL ADRx1

10(V

RH + VRL)/2 ADRx2

1 1 TEST/Reserved ADRx3

0 0 0 AN0 ADRx0

0 0 1 AN1 ADRx1

0 1 0 AN2 ADRx2

0 1 1 AN3 ADRx3

1 0 0 AN4 ADRx4

1 0 1 AN5 ADRx5

1 1 0 AN6 ADRx6

1 1 1 AN7 ADRx7

0 0 0 Reserved ADRx0

0 0 1 Reserved ADRx1

0 1 0 Reserved ADRx2

0 1 1 Reserved ADRx3

100V

RH ADRx4

101V

RL ADRx5

110(V

RH + VRL)/2 ADRx6

1 1 1 TEST/Reserved ADRx7

Shaded bits are “don’t care” if MULT = 1 and the entire block of four or eight channels make up

a conversion sequence. When MULT = 0, all four bits (CD, CC, CB, and CA) must be specified

and a conversion sequence consists of four or eight consecutive conversions of the single spec-

ified channel.

8-atd

Analog-To-Digital Converter (ATD)

ATD Registers

MC68HC912DG128

MOTOROLA Analog-To-Digital Converter (ATD) 301

9-atd

The ATD status registers contain the flags indicating the completion of

ATD conversions.

Normally, it is read-only. In special mode, the SCF bit and the CCF bits

may also be written.

SCF — Sequence Complete Flag

This bit is set at the end of the conversion sequence when in the

single conversion sequence mode (SCAN = 0 in ATDCTL5) and is set

at the end of the first conversion sequence when in the continuous

conversion mode (SCAN = 1 in ATDCTL5). When AFFC = 0, SCF is

cleared when a write is performed to ATDCTL5 to initiate a new

conversion sequence. When AFFC = 1, SCF is cleared after the first

result register is read.

CC[2:0] — Conversion Counter for Current Sequence of Four or Eight

Conversions

This 3-bit value reflects the contents of the conversion counter pointer

in a four or eight count sequence. This value also reflects which result

being converted.

CCF[7:0] — Conversion Complete Flags

Each of these bits are associated with an individual ATD result

the associated ATD channel and remains set until that ATD result

of whether a status register read has been performed (i.e., a status

ATD0STAT0/ATD1STAT0 — ATD Status Register $0066/$01E6

Bit 7 654321Bit 0

SCF0000CC2CC1CC0

RESET: 00000000

ATD0STAT1/ATD1STAT1 — ATD Status Register $0067/$01E7

Bit 7 654321Bit 0

CCF7 CCF6 CCF5 CCF4 CCF3 CCF2 CCF1 CCF0

RESET: 00000000

Analog-To-Digital Converter

MC68HC912DG128

302 Analog-To-Digital Converter (ATD) MOTOROLA

AFFC = 1). Otherwise the status register must be read to clear the

flag.

The test registers control various special modes which are used

during manufacturing. The test register can be read or written only in

the special modes. In the normal modes, reads of the test register

return zero and writes have no effect.

SAR[9:0] — SAR Data

Reads of this byte return the current value in the SAR. Writes to this

byte change the SAR to the value written. Bits SAR[9:0] reflect the ten

SAR bits used during the resolution process for a 10-bit result.

RST — Module Reset Bit

When set, this bit causes all registers and activity in the module to

assume the same state as out of power-on reset (except for ADPU bit

in ATDCTL2, which remains set, allowing the ATD module to remain

enabled).

TSTOUT — Multiplex Output of TST[3:0] (Factory Use)

TST[3:0] — Test Bits 3 to 0 (Reserved)

Selects one of 16 reserved factory testing modes

ATD0TESTH/ATD1TESTH — ATD Test Register $0068/$01E8

Bit 7 654321Bit 0

SAR9 SAR8 SAR7 SAR6 SAR5 SAR4 SAR3 SAR2

RESET: 00000000

ATD0TESTL/ATD1TESTL — ATD Test Register $0069/$01E9

Bit 7 654321Bit 0

SAR1 SAR0 RST TSTOUT TST3 TST2 TST1 TST0

RESET: 00000000

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Analog-To-Digital Converter (ATD)

ATD Registers

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PADx[7:0] — Port AD Data Input Bits

After reset these bits reflect the state of the input pins.

May be used for general-purpose digital input. When the software

reads PORTAD, it obtains the digital levels that appear on the

corresponding port AD pins. Pins with signals not meeting VIL or VIH

specifications will have an indeterminate value. Writes to this register

have no meaning at any time.

ADRxxH[15:8], ADRxxL[7:0] — ATD Conversion result

The reset condition for these registers is undefined.

These bits contain the left justified, unsigned result from the ATD

conversion. The channel from which this result was obtained is

dependent on the conversion mode selected. These registers are

always read-only in normal mode.

PORTAD0/PORTAD1 — Port AD Data Input Register $006F/$01EF

Bit 7 654321Bit 0

PADx7 PADx6 PADx5 PADx4 PADx3 PADx2 PADx1 PADx0

RESET: --------

ADRx0H — A/D Converter Result Register 0 $0070/$01F0

ADRx0L — A/D Converter Result Register 0 $0071/$01F1

ADRx1H — A/D Converter Result Register 1 $0072/$01F2

ADRx1L — A/D Converter Result Register 1 $0073/$01F3

ADRx2H — A/D Converter Result Register 2 $0074/$01F4

ADRx2L — A/D Converter Result Register 2 $0075/$01F5

ADRx3H — A/D Converter Result Register 3 $0076/$01F6

ADRx3L — A/D Converter Result Register 3 $0077/$01F7

ADRx4H — A/D Converter Result Register 4 $0078/$01F8

ADRx4L — A/D Converter Result Register 4 $0079/$01F9

ADRx5H — A/D Converter Result Register 5 $007A/$01FA

ADRx5L — A/D Converter Result Register 5 $007B/$01FB

ADRx6H — A/D Converter Result Register 6 $007C/$01FC

ADRx6L — A/D Converter Result Register 6 $007D/$01FD

ADRx7H — A/D Converter Result Register 7 $007E/$01FE

ADRx7L — A/D Converter Result Register 7 $007F/$01FF

ADRxxH Bit 15 654321Bit 8

ADRxxL Bit 7 Bit 6 000000

RESET: 00000000

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ATD Mode Operation

STOP — causes all clocks to halt (if the S bit in the CCR is zero). The

system is placed in a minimum-power standby mode. This aborts any

conversion sequence in progress.

WAIT — ATD conversion continues unless AWAI bit in ATDCTL2

BDM — Debug options available as set in register ATDCTL3.

USER — ATD continues running unless ADPU is cleared.

ADPU — ATD operations are stopped if ADPU = 0, but registers are

accessible.

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Development Support

General Description

Contents

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

Instruction Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305

Background Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307

Breakpoints. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321

Instruction Tagging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .328

Introduction

Development support involves complex interactions between

MC68HC912DG128 resources and external development systems. The

following section concerns instruction queue and queue tracking signals,

background debug mode, and instruction tagging.

Instruction Queue

The CPU12 instruction queue provides at least three bytes of program

information to the CPU when instruction execution begins. The CPU12

always completely finishes executing an instruction before beginning to

execute the next instruction. Status signals IPIPE[1:0] provide

information about data movement in the queue and indicate when the

CPU begins to execute instructions. This makes it possible to monitor

CPU activity on a cycle-by-cycle basis for debugging. Information

available on the IPIPE[1:0] pins is time multiplexed. External circuitry

can latch data movement information on rising edges of the E-clock

signal; execution start information can be latched on falling edges.

Table 48 shows the meaning of data on the pins.

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Program information is fetched a few cycles before it is used by the CPU.

In order to monitor cycle-by-cycle CPU activity, it is necessary to

externally reconstruct what is happening in the instruction queue.

Internally the MCU only needs to buffer the data from program fetches.

For system debug it is necessary to keep the data and its associated

address in the reconstructed instruction queue. The raw signals required

for reconstruction of the queue are ADDR, DATA, R/W, ECLK, and

status signals IPIPE[1:0].

The instruction queue consists of two 16-bit queue stages and a holding

latch on the input of the first stage. To advance the queue means to

move the word in the first stage to the second stage and move the word

from either the holding latch or the data bus input buffer into the first

stage. To start even (or odd) instruction means to execute the opcode in

the high-order (or low-order) byte of the second stage of the instruction

queue.

1. Refers to data that was on the bus at the previous E falling edge.

2. Refers to bus cycle starting at this E falling edge.

Table 48 IPIPE Decoding

Data Movement — IPIPE[1:0] Captured at Rising Edge of E Clock(1)

IPIPE[1:0] Mnemonic Meaning

0:0 — No Movement

0:1 LAT Latch Data From Bus

1:0 ALD Advance Queue and Load From Bus

1:1 ALL Advance Queue and Load From Latch

Execution Start — IPIPE[1:0] Captured at Falling Edge of E Clock(2)

IPIPE[1:0] Mnemonic Meaning

0:0 — No Start

0:1 INT Start Interrupt Sequence

1:0 SEV Start Even Instruction

1:1 SOD Start Odd Instruction

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Background Debug Mode

Background debug mode (BDM) is used for system development,

in-circuit testing, field testing, and programming. BDM is implemented in

on-chip hardware and provides a full set of debug options.

Because BDM control logic does not reside in the CPU, BDM hardware

commands can be executed while the CPU is operating normally. The

control logic generally uses CPU dead cycles to execute these

commands, but can steal cycles from the CPU when necessary. Other

BDM commands are firmware based, and require the CPU to be in

active background mode for execution. While BDM is active, the CPU

executes a firmware program located in a small on-chip ROM that is

available in the standard 64-Kbyte memory map only while BDM is

active.

The BDM control logic communicates with an external host development

system serially, via the BKGD pin. This single-wire approach minimizes

the number of pins needed for development support.

Enabling BDM

Firmware

Commands

BDM is available in all operating modes, but must be made active before

firmware commands can be executed. BDM is enabled by setting the

ENBDM bit in the BDM STATUS register via the single wire interface

(using a hardware command; WRITE_BD_BYTE at $FF01). BDM must

then be activated to map BDM registers and ROM to addresses $FF00

to $FFFF and to put the MCU in active background mode.

After the firmware is enabled, BDM can be activated by the hardware

BACKGROUND command, by the BDM tagging mechanism, or by the

CPU BGND instruction. An attempt to activate BDM before firmware has

been enabled causes the MCU to resume normal instruction execution

after a brief delay.

BDM becomes active at the next instruction boundary following

execution of the BDM BACKGROUND command, but tags activate BDM

before a tagged instruction is executed.

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In special single-chip mode, background operation is enabled and active

immediately out of reset. This active case replaces the M68HC11 boot

function, and allows programming a system with blank memory.

While BDM is active, a set of BDM control registers are mapped to

addresses $FF00 to $FF06. The BDM control logic uses these registers

which can be read anytime by BDM logic, not user programs. Refer to

BDM Registers for detailed descriptions.

Some on-chip peripherals have a BDM control bit which allows

suspending the peripheral function during BDM. For example, if the timer

control is enabled, the timer counter is stopped while in BDM. Once

normal program flow is continued, the timer counter is re-enabled to

simulate real-time operations.

BDM Serial

Interface

The BDM serial interface requires the external controller to generate a

falling edge on the BKGD pin to indicate the start of each bit time. The

external controller provides this falling edge whether data is transmitted

or received.

BKGD is a pseudo-open-drain pin that can be driven either by an

external controller or by the MCU. Data is transferred MSB first at 16

B-clock cycles per bit (nominal speed). The interface times out if 512

B-clock cycles occur between falling edges from the host. The hardware

clears the command register when a time-out occurs.

The BKGD pin can receive a high or low level or transmit a high or low

level. The following diagrams show timing for each of these cases.

Interface timing is synchronous to MCU clocks but asynchronous to the

external host. The internal clock signal is shown for reference in counting

cycles.

Figure 60 shows an external host transmitting a logic one or zero to the

BKGD pin of a target MC68HC912DG128 MCU. The host is

asynchronous to the target so there is a 0-to-1 cycle delay from the

host-generated falling edge to where the target perceives the beginning

of the bit time. Ten target B cycles later, the target senses the bit level

on the BKGD pin. Typically the host actively drives the

pseudo-open-drain BKGD pin during host-to-target transmissions to

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MOTOROLA Development Support 309

speed up rising edges. Since the target does not drive the BKGD pin

during this period, there is no need to treat the line as an open-drain

signal during host-to-target transmissions.

Figure 60 BDM Host to Target Serial Bit Timing

Figure 61 BDM Target to Host Serial Bit Timing (Logic 1)

10 CYCLES

B CLOCK

(TARGET MCU)

HOST

TRANSMIT 1

TARGET SENSES BIT

EARLIEST

START OF

NEXT BIT

SYNCHRONIZATION

UNCERTAINTY

PERCEIVED

START

OF BIT TIME

HOST

TRANSMIT 0

HC12A4 BDM HOST TO TARGET TIM

10 CYCLES

B CLOCK

(TARGET

MCU)

EARLIEST

START OF

NEXT BIT

BKGD PIN

PERCEIVED

START OF BIT

TIME

10 CYCLES

HOST SAMPLES

BKGD PIN

HOST

DRIVE T O

BKGD PIN

TARGET MCU

SPEEDUP PULSE

R-C RISE

HIGH-IMPEDANCE

HC12A4 BDM T ARGET TO HOST TIM 1

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Figure 61 shows the host receiving a logic one from the target

MC68HC912DG128 MCU. Since the host is asynchronous to the target

MCU, there is a 0-to-1 cycle delay from the host-generated falling edge

on BKGD to the perceived start of the bit time in the target MCU. The

host holds the BKGD pin low long enough for the target to recognize it

(at least two target B cycles). The host must release the low drive before

the target MCU drives a brief active-high speed-up pulse seven cycles

after the perceived start of the bit time. The host should sample the bit

level about ten cycles after it started the bit time.

Figure 62 BDM Target to Host Serial Bit Timing (Logic 0)

Figure 62 shows the host receiving a logic zero from the target

MC68HC912DG128 MCU. Since the host is asynchronous to the target

MCU, there is a 0-to-1 cycle delay from the host-generated falling edge

on BKGD to the start of the bit time as perceived by the target MCU. The

host initiates the bit time but the target MC68HC912DG128 finishes it.

Since the target wants the host to receive a logic zero, it drives the

BKGD pin low for 13 B-clock cycles, then briefly drives it high to speed

up the rising edge. The host samples the bit level about ten cycles after

starting the bit time.

10 CYCLES

B CLOCK

(TARGET

MCU)

EARLIEST

START OF

NEXT BIT

BKGD PIN

PERCEIVED

START OF BIT TIME

10 CYCLES

HOST SAMPLES

BKGD PIN

HOST

DRIVE T O

BKGD PIN

TARGET MCU

DRIVE AND

SPEEDUP PULSE

HIGH-IMPEDANCE

SPEEDUP PULSE

HC12A4 BDM T ARGET TO HOST TIM 0

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BDM Commands The BDM command set consists of two types: hardware and firmware.

Hardware commands allow target system memory to be read or

written.Target system memory includes all memory that is accessible by

the CPU12 including EEPROM, on-chip I/O and control registers, and

external memory that is connected to the target HC12 MCU.Hardware

commands are implemented in hardware logic and do not require the

HC12 MCU to be in BDM mode for execution.The control logic watches

the CPU12 buses to find a free bus cycle to execute the command so the

background access does not disturb the running application programs. If

a free cycle is not found within 128 B-clock cycles, the CPU12 is

momentarily frozen so the control logic can steal a cycle.Commands

implemented in BDM control logic are listed in Table 49.

1. Use these commands only for reading/writing to BDM locations.The BDM firmware ROM and BDM registers are not nor-

mally in the HC12 MCU memory map.Since these locations have the same addresses as some of the normal application

memory map, there needs to be a way to decide which physical locations are being accessed by the hardware BDM com-

mands.This gives rise to needing separate memory access commands for the BDM locations as opposed to the normal

application locations.In logic, this is accomplished by momentarily enabling the BDM memory resources, just for the access

cycles of the READ_BD and WRITE_BD commands.This logic allows the debugging system to unobtrusively access the

BDM locations even if the application program is running out of the same memory area in the normal application memory

map.

Table 49 Hardware Commands(1)

Command Opcode (Hex) Data Description

BACKGROUND 90 None Enter background mode if ﬁrmware enabled.

READ_BD_BYTE(1) E4 16-bit address

16-bit data out

Read from memory with BDM in map (ma y steal cycles

if external access) data for odd address on low byte,

data for even address on high byte.

READ_BD_WORD(1) EC 16-bit address

16-bit data out Read from memory with BDM in map (may steal cycles

if external access). Must be aligned access.

READ_BYTE E0 16-bit address

16-bit data out

Read from memory with BDM out of map (may steal

cycles if external access) data for odd address on low

byte, data for even address on high byte.

READ_WORD E8 16-bit address

16-bit data out Read from memory with BDM out of map (may steal

cycles if external access). Must be aligned access.

WRITE_BD_BYTE(1) C4 16-bit address

16-bit data in

Write to memory with BDM in map (may steal cycles if

e xternal access) data f or odd address on low b yte, data

for even address on high byte.

WRITE_BD_WORD(1) CC 16-bit address

16-bit data in Write to memory with BDM in map (may steal cycles if

external access). Must be aligned access.

WRITE_BYTE C0 16-bit address

16-bit data in

Write to memory with BDM out of map (may steal

cycles if external access) data for odd address on low

byte, data for even address on high byte.

WRITE_WORD C8 16-bit address

16-bit data in Write to memory with BDM out of map (may steal

cycles if external access). Must be aligned access.

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The second type of BDM commands are called ﬁrmware commands

implemented in a small ROM within the HC12 MCU .The CPU must be in

background mode to execute firmware commands. The usual way to get

to backg round mode is by the hardware command BA CKGROUND. The

BDM ROM is located at $FF20 to $FFFF while BDM is active. There are

also seven bytes of BDM registers located at $FF00 to $FF06 while BDM

is active. The CPU executes code in the BDM firmware to perform the

requested operation. The BDM firmware watches for serial commands

and executes them as they are received. The ﬁrmware commands are

shown in Table 50.

Each of the hardware and firmware BDM commands start with an 8-bit

command code (opcode). Depending upon the commands, a 16-bit

address and/or a 16-bit data word is required as indicated in the tables

by the command. All the read commands output 16-bits of data despite

the byte/word implication in the command name.

The external host should wait 150 BCLK cycles for a non-intrusive BDM

command to execute before another command is sent. This delay

includes 128 BCLK cycles for the maximum delay for a free cycle.For

data read commands, the host must insert this delay between sending

Table 50 BDM Firmware Commands

Command Opcode (Hex) Data Description

READ_NEXT 62 16-bit data out X = X + 2; Read next word pointed to by X

READ_PC 63 16-bit data out Read program counter

READ_D 64 16-bit data out Read D accumulator

READ_X 65 16-bit data out Read X index register

READ_Y 66 16-bit data out Read Y index register

READ_SP 67 16-bit data out Read stack pointer

WRITE_NEXT 42 16-bit data in X = X + 2; Write next word pointed to by X

WRITE_PC 43 16-bit data in Write program counter

WRITE_D 44 16-bit data in Write D accumulator

WRITE_X 45 16-bit data in Write X index register

WRITE_Y 46 16-bit data in Write Y index register

WRITE_SP 47 16-bit data in Write stack pointer

GO 08 None Go to user program

TRACE1 10 None Execute one user instruction then return to BDM

TAGGO 18 None Enable tagging and go to user program

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the address and attempting to read the data.In the case of a write

command, the host must delay after the data portion, before sending a

new command, to be sure the write has finished.

The external host should delay about 32 target BCLK cycles between a

firmware read command and the data portion of these commands. This

allows the BDM firmware to execute the instructions needed to get the

requested data into the BDM SHIFTER register.

The external host should delay about 32 target BCLK cycles after the

data portion of firmware write commands to allow BDM firmware to

complete the requested write operation before a new serial command

disturbs the BDM SHIFTER register.

The external host should delay about 64 target BCLK cycles after a

TRACE1 or GO command before starting any new serial command. This

delay is needed because the BDM SHIFTER register is used as a

temporary data holding register during the exit sequence to user code.

BDM logic retains control of the internal buses until a read or write is

completed.If an operation can be completed in a single cycle, it does not

intrude on normal CPU12 operation.However, if an operation requires

multiple cycles, CPU12 clocks are frozen until the operation is complete.

BDM Lockout The access to the MCU resources by BDM may be prevented by

enabling the BDM lockout feature. When enabled, the BDM lockout

mechanism prevents the BDM from being active. In this case the BDM

ROM is disabled and does not appear in the MCU memory map.

The BDM lockout is enabled by clearing NOBDML bit of EEMCR

EEPROM module. Modifying the state of the NOBDML and

corresponding EEPROM SHADOW bit is only possible in special modes.

Please refer to EEPROM for NOBDML information.

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Enabling the BDM

lockout Enabling the BDM lockout feature is only possible in special modes

(SMODN=0) and is accomplished by the following steps.

1. Remove the SHADOW byte protection by clearing SHPROT bit in

EEPROT register.

2. Clear NOSHB bit in EEMCR register to make the SHADOW byte

visible at $0FC0.

3. Program bit 7 of the SHADOW byte like a regular EEPROM

location at address $0FC0 (write $7F into address $0FC0). Do not

program other bits of the SHADOW byte (location $0FC0);

otherwise some regular EEPROM array locations will not be

visible. At the next reset, the SHADOW byte is loaded into the

EEMCR register. NOBDML bit in EEMCR will be cleared and BDM

will not be operational.

4. Protect the SHADOW byte by setting SHPROT bit in EEPROT

Disabling the BDM

lockout Disabling the BDM lockout is only possible in special modes

(SMODN=0). Follow the same steps as for enabling the BDM lockout,

but erase the SHADOW byte.

At the next reset, the SHADOW byte is loaded into the EEMCR register.

NOBDML bit in EEMCR will be set and BDM becomes operational.

BDM Registers Seven BDM registers are mapped into the standard 64-Kbyte address

space when BDM is active. Mapping is shown in Table 51.

Table 51 BDM registers

Address Register

$FF00 BDM Instruction Register

$FF01 BDM Status Register

$FF02 - $FF03 BDM Shift Register

$FF04 - $FF05 BDM Address Register

$FF06 BDM CCR Holding Register

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The content of the INSTRUCTION register is determined by the type of

background command being executed.The STATUS register indicates

BDM operating conditions.The SHIFT register contains data being

received or transmitted via the serial interface. The ADDRESS register

is temporary storage for BDM commands.The CCRSAV register

preserves the content of the CPU12 CCR while BDM is active.

The only registers of interest to users are the STATUS register and the

CCRSAV register.The other BDM registers are only used by the BDM

firmware to execute commands.The registers are accessed by means of

the hardware READ_BD and WRITE_BD commands, but should not be

written during BDM operation (except the CCRSAV register which could

be written to modify the CCR value).

STATUS The STATUS register is read and written by the BDM hardware as a

result of serial data shifted in on the BKGD pin.

Read: all modes.

Write: Bits 3 through 5, and bit 7 are writable in all modes. Bit 6,

BDMACT, can only be written if bit 7 H/F in the INSTRUCTION register

is a zero. Bit 2, CLKSW, can only be written if bit 7 H/F in the

INSTRUCTION register is a one. A user would never write ones to bits

3 through 5 because these bits are only used by BDM firmware.

1. ENBDM is set to 1 by the firmware in Special Single Chip mode.

ENBDM — Enable BDM (permit active background debug mode)

0 = BDM cannot be made active (hardware commands still

allowed).

1 = BDM can be made active to allow firmware commands.

STATUS— BDM Status Register(1) $FF01

BIT 7 654321BIT 0

ENBDM BDMACT ENTAG SDV TRACE CLKSW - -

RESET: 0

(NOTE 1) 1000000

Special Single

Chip & Periph

RESET: 00000000All other modes

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BDMACT — Background Mode Active Status

BDMACT becomes set as active BDM mode is entered so that the

BDM firmware ROM is enabled and put into the map. BDMACT is

cleared by a carefully timed store instruction in the BDM firmware as

part of the exit sequence to return to user code and remove the BDM

memory from the map. This bit has 4 clock cycles write delay.

0 = BDM is not active. BDM ROM and registers are not in map.

1 = BDM is active and waiting for serial commands. BDM ROM and

registers are in map

The user should be careful that the state of the BDMACT bit is not

unintentionally changed with the WRITE_NEXT firmware command. If it

is unintentionally changed from 1 to 0, it will cause a system runaway

because it would disable the BDM firmware ROM while the CPU12 was

executing BDM firmware. The following two commands show how

BDMACT may unintentionally get changed from 1 to 0.

WRITE_X with data $FEFE

WRITE_NEXT with data $C400

The first command writes the data $FEFE to the X index register. The

second command writes the data $C4 to the $FF00 INSTRUCTION

ENTAG — Tagging Enable

Set by the TAGGO command and cleared when BDM mode is

entered. The serial system is disabled and the tag function enabled

16 cycles after this bit is written.

0 = Tagging not enabled, or BDM active.

1 = Tagging active. BDM cannot process serial commands while

tagging is active.

SDV — Shifter Data Valid

Shows that valid data is in the serial interface shift register. Used by

the BDM firmware.

0 = No valid data. Shift operation is not complete.

1 = Valid Data. Shift operation is complete.

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TRACE — Asserted by the TRACE1 command

CLKSW — Clock Switch

0 = BDM system operates with BCLK.

1 = BDM system operates with ECLK.

The WRITE_BD_BYTE@FF01 command that changes CLKSW

including 150 cycles after the data portion of the command should be

timed at the old speed. Beginning with the start of the next BDM

command, the new clock can be used for timing BDM

communications.

If ECLK rate is slower than BCLK rate, CLKSW is ignored and BDM

system is forced to operate with ECLK.

INSTRUCTION -

Hardware

Instruction

Decode

The INSTRUCTION register is written by the BDM hardware as a result

of serial data shifted in on the BKGD pin. It is readable and writable in

Special Peripheral mode on the parallel bus. It is discussed here for two

conditions: when a hardware command is executed and when a

firmware command is executed.

Read and write: all modes

. The hardware clears the INSTRUCTION register if 512 BCLK cycles

occur between falling edges from the host.

The bits in the BDM instruction register have the following meanings

when a hardware command is executed.

H/F — Hardware/Firmware Flag

0 = Firmware command

1 = Hardware command

DATA — Data Flag - Shows that data accompanies the command.

0 = No data

1 = Data follows the command

INSTRUCTION— BDM Instruction Register (hardware command explanation) $FF00

BIT 7 654321BIT 0

H/F DATA R/W BKGND W/B BD/U 0 0

RESET: 00000000

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R/W — Read/Write Flag

0 = Write

1 = Read

BKGND — Hardware request to enter active background mode

0 = Not a hardware background command

1 = Hardware background command (INSTRUCTION = $90)

W/B — Word/Byte Transfer Flag

0 = Byte transfer

1 = Word transfer

BD/U — BDM Map/User Map Flag

Indicates whether BDM registers and ROM are mapped to addresses

$FF00 to $FFFF in the standard 64-Kbyte address space. Used only

by hardware read/write commands.

0 = BDM resources not in map

1 = BDM ROM and registers in map

The bits in the BDM instruction register have the following meanings

when a firmware command is executed.

H/F — Hardware/Firmware Flag

0 = Firmware command

1 = Hardware command

DATA — Data Flag – Shows that data accompanies the command.

0 = No data

1 = Data follows the command

R/W — Read/Write Flag

0 = Write

1 = Read

INSTRUCTION — BDM Instruction Register (firmware command bit explanation) $FF00

Bit 7 654321Bit 0

H/F DATA R/W TTAGO REGN

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TTAGO — Trace, Tag, Go Field

REGN — Register/Next Field

Indicates which register is being affected by a command. In the case of

a READ_NEXT or WRITE_NEXT command, index register X is

pre-incriminated by 2 and the word pointed to by X is then read or

written.

Table 52 TTAGO Decoding

TTAGO Value Instruction

00 —

01 GO

10 TRACE1

11 TAGGO

Table 53 REGN Decoding

REGN Value Instruction

000 —

001 —

010 READ/WRITE NEXT

011 PC

100 D

101 X

110 Y

111 SP

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320 Development Support MOTOROLA

SHIFTER This 16-bit shift register contains data being received or transmitted via

the serial interface. It is also used by the BDM firmware for temporary

storage.

Read: all modes (but not normally accessed by users)

Write: all modes (but not normally accessed by users)

ADDRESS This 16-bit address register is temporary storage for BDM hardware and

firmware commands.

Read: all modes (but not normally accessed by users)

Write: only by BDM hardware (state machine)

SHIFTER — BDM Shift Register – High Byte $FF02

BIT 15 14 13 12 11 10 9 BIT 8

S15 S14 S13 S12 S11 S10 S9 S8

RESET: XXXXXXXX

SHIFTER — BDM Shift Register – Low Byte $FF03

BIT 7 654321BIT 0

S7 S6 S5 S4 S3 S2 S1 S0

RESET: XXXXXXXX

ADDRESS — BDM Address Register – High Byte $FF04

BIT 15 14 13 12 11 10 9 BIT 8

A15 A14 A13 A12 A11 A10 A9 A8

RESET: XXXXXXXX

ADDRESS — BDM Address Register – High Byte $FF05

BIT 7 654321BIT 0

A7 A6 A5 A4 A3 A2 A1 A0

RESET: XXXXXXXX

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CCRSAV The CCRSAV register is used to save the CCR of the users program

when entering BDM. It is also used for temporary storage in the BDM

firmware.

Read and write: all modes

Breakpoints

1. Initialized to equal the CPU12 CCR register by the firmware.

Hardware breakpoints are used to debug software on the

MC68HC912DG128 by comparing actual address and data values to

predetermined data in setup registers. A successful comparison will

place the CPU in background debug mode (BDM) or initiate a software

interrupt (SWI). Breakpoint features designed into the MC68HC912B32

include:

• Mode selection for BDM or SWI generation

• Program fetch tagging for cycle of execution breakpoint

• Second address compare in dual address modes

• Range compare by disable of low byte address

• Data compare in full feature mode for non-tagged breakpoint

• Byte masking for high/low byte data compares

• R/W compare for non-tagged compares

• Tag inhibit on BDM TRACE

CCRSAV— BDM CCR Holding Register $FF06

BIT 7 654321BIT 0

CCR7 CCR6 CCR5 CCR4 CCR3 CCR2 CCR1 CCR0

RESET:

NOTE 1 (1) XXXXXXXX

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322 Development Support MOTOROLA

Breakpoint Modes Three modes of operation determine the type of breakpoint in effect.

• Dual address-only breakpoints, each of which will cause a

software interrupt (SWI)

• Single full-feature breakpoint which will cause the part to enter

background debug mode (BDM)

• Dual address-only breakpoints, each of which will cause the part

to enter BDM

Breakpoints will not occur when BDM is active.

SWI Dual Address

Mode In this mode, dual address-only breakpoints can be set, each of which

cause a software interrupt. This is the only breakpoint mode which can

force the CPU to execute a SWI. Program fetch tagging is the default in

this mode; data breakpoints are not possible. In the dual mode each

address breakpoint is affected by the BKPM bit and the BKALE bit. The

BKxRW and BKxRWE bits are ignored. In dual address mode the

BKDBE becomes an enable for the second address breakpoint. The

BKSZ8 bit will have no effect when in a dual address mode.

BDM Full

Breakpoint Mode A single full feature breakpoint which causes the part to enter

background debug mode. BDM mode may be entered by a breakpoint

only if an internal signal from the BDM indicates background debug

mode is enabled.

• Breakpoints are not allowed if the BDM mode is already active.

Active mode means the CPU is executing out of the BDM ROM.

• BDM should not be entered from a breakpoint unless the ENABLE

bit is set in the BDM. This is important because even if the

ENABLE bit in the BDM is negated the CPU actually does execute

the BDM ROM code. It checks the ENABLE and returns if not set.

If the BDM is not serviced by the monitor then the breakpoint

would be re-asserted when the BDM returns to normal CPU flow.

• There is no hardware to enforce restriction of breakpoint operation

if the BDM is not enabled.

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BDM Dual Address

Mode Dual address-only breakpoints, each of which cause the part to enter

background debug mode. In the dual mode each address breakpoint is

affected, consistent across modes, by the BKPM bit, the BKALE bit, and

the BKxRW and BKxRWE bits. In dual address mode the BKDBE

becomes an enable for the second address breakpoint. The BKSZ8 bit

will have no effect when in a dual address mode. BDM mode may be

entered by a breakpoint only if an internal signal from the BDM indicates

background debug mode is enabled.

• BKDBE will be used as an enable for the second address only

breakpoint.

• Breakpoints are not allowed if the BDM mode is already active.

Active mode means the CPU is executing out of the BDM ROM.

• BDM should not be entered from a breakpoint unless the ENABLE

bit is set in the BDM. This is important because even if the

ENABLE bit in the BDM is negated the CPU actually does execute

the BDM ROM code. It checks the ENABLE and returns if not set.

If the BDM is not serviced by the monitor then the breakpoint

would be re-asserted when the BDM returns to normal CPU flow.

There is no hardware to enforce restriction of breakpoint operation

if the BDM is not enabled.

Breakpoint

Registers

Breakpoint operation consists of comparing data in the breakpoint

address registers (BRKAH/BRKAL) to the address bus and comparing

data in the breakpoint data registers (BRKDH/BRKDL) to the data bus.

The breakpoint data registers can also be compared to the address bus.

The scope of comparison can be expanded by ignoring the least

significant byte of address or data matches.

The scope of comparison can be limited to program data only by setting

the BKPM bit in breakpoint control register 0.

To trace program flow, setting the BKPM bit causes address comparison

of program data only. Control bits are also available that allow checking

read/write matches.

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324 Development Support MOTOROLA

Read and write anytime.

This register is used to control the breakpoint logic.

BKEN1, BKEN0 — Breakpoint Mode Enable

BKPM — Break on Program Addresses

This bit controls whether the breakpoint will cause a break on a match

(next instruction boundary) or on a match that will be an executable

opcode. Data and non-executed opcodes cannot cause a break if this

bit is set. This bit has no meaning in SWI dual address mode. The

SWI mode only performs program breakpoints.

0 = On match, break at the next instruction boundary

1 = On match, break if the match is an instruction that will be

executed. This uses tagging as its breakpoint mechanism.

BK1ALE — Breakpoint 1 Range Control

Only valid in dual address mode.

0 = BRKDL will not be used to compare to the address bus.

1 = BRKDL will be used to compare to the address bus.

BK0ALE — Breakpoint 0 Range Control

Valid in all modes.

0 = BRKAL will not be used to compare to the address bus.

1 = BRKAL will be used to compare to the address bus.

BRKCT0 — Breakpoint Control Register 0 $0020

Bit 7 6 5 4 3 2 1 Bit 0

BKEN1 BKEN0 BKPM 0 BK1ALE BK0ALE 0 0

RESET: 0 0 0 0 0 0 0 0

Table 54 Breakpoint Mode Control

BKEN1 BKEN0 Mode Selected BRKAH/L Usage BRKDH/L

Usage R/W Range

0 0 Breakpoints Off — — — —

0 1 SWI — Dual Address Mode Address Match Address Match No Yes

1 0 BDM — Full Breakpoint Mode Address Match Data Match Yes Yes

1 1 BDM — Dual Address Mode Address Match Address Match Yes Yes

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MOTOROLA Development Support 325

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This register is read/write in all modes.

BKDBE — Enable Data Bus

Enables comparing of address or data bus values using the BRKDH/

L registers.

0 = The BRKDH/L registers are not used in any comparison

1 = The BRKDH/L registers are used to compare address or data

(depending upon the mode selections BKEN1,0)

BKMBH — Breakpoint Mask High

Disables the comparing of the high byte of data when in full breakpoint

mode. Used in conjunction with the BKDBE bit (which should be set)

0 = High byte of data bus (bits 15:8) are compared to BRKDH

1 = High byte is not used to in comparisons

BKMBL — Breakpoint Mask Low

Disables the matching of the low byte of data when in full breakpoint

mode. Used in conjunction with the BKDBE bit (which should be set)

0 = Low byte of data bus (bits 7:0) are compared to BRKDL

1 = Low byte is not used to in comparisons.

Table 55 Breakpoint Address Range Control

BK1ALE BK0ALE Address Range Selected

– 0 Upper 8-bit address only for full mode or dual mode BKP0

– 1 Full 16-bit address for full mode or dual mode BKP0

0 – Upper 8-bit address only for dual mode BKP1

1 – Full 16-bit address for dual mode BKP1

BRKCT1 — Breakpoint Control Register 1 $0021

Bit 7 6 5 4 3 2 1 Bit 0

0 BKDBE BKMBH BKMBL BK1RWE BK1RW BK0RWE BK0RW

RESET: 0 0 0 0 0 0 0 0

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326 Development Support MOTOROLA

BK1RWE — R/W Compare Enable

Enables the comparison of the R/W signal to further specify what

causes a match. This bit is NOT useful in program breakpoints or in

full breakpoint mode. This bit is used in conjunction with a second

address in dual address mode when BKDBE=1.

0 = R/W is not used in comparisons

1 = R/W is used in comparisons

BK1RW — R/W Compare Value

When BK1RWE = 1, this bit determines the type of bus cycle to

match.

0 = A write cycle will be matched

1 = A read cycle will be matched

BK0RWE — R/W Compare Enable

Enables the comparison of the R/W signal to further specify what

causes a match. This bit is not useful in program breakpoints.

0 = R/W is not used in the comparisons

1 = R/W is used in comparisons

BK0RW — R/W Compare Value

When BK0RWE = 1, this bit determines the type of bus cycle to match

on.0 = Write cycle will be matched

1 = Read cycle will be matched

Table 56 Breakpoint Read/Write Control

BK1RWE BK1RW BK0RWE BK0RW Read/Write Selected

––0X

R/W is don’t care for full mode or dual mode

BKP0

––10R/W is write for full mode or dual mode BKP0

––11R/W is read for full mode or dual mode BKP0

0X––R/W is don’t care for dual mode BKP1

10––R/W is write for dual mode BKP1

11––R/W is read for dual mode BKP1

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These bits are used to compare against the most significant byte of the

address bus.

These bits are used to compare against the least significant byte of the

address bus. These bits may be excluded from being used in the match

if BK0ALE = 0.

These bits are compared to the most significant byte of the data bus or

the most significant byte of the address bus in dual address modes.

BKEN[1:0], BKDBE, and BKMBH control how this byte will be used in the

breakpoint comparison.

These bits are compared to the least significant byte of the data bus or

the least significant byte of the address bus in dual address modes.

BKEN[1:0], BKDBE, BK1ALE, and BKMBL control how this byte will be

used in the breakpoint comparison.

BRKAH — Breakpoint Address Register, High Byte $0022

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

RESET: 0 0 0 0 0 0 0 0

BRKAL — Breakpoint Address Register, Low Byte $0023

Bit 7 6 5 4 3 2 1 Bit 0

RESET: 0 0 0 0 0 0 0 0

BRKDH — Breakpoint Data Register, High Byte $0024

Bit 7 6 5 4 3 2 1 Bit 0

Bit 15 14 13 12 11 10 9 Bit 8

RESET: 0 0 0 0 0 0 0 0

BRKDL — Breakpoint Data Register, Low Byte $0025

Bit 7 6 5 4 3 2 1 Bit 0

RESET: 0 0 0 0 0 0 0 0

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328 Development Support MOTOROLA

Instruction Tagging

The instruction queue and cycle-by-cycle CPU activity can be

reconstructed in real time or from trace history that was captured by a

logic analyzer. However, the reconstructed queue cannot be used to

stop the CPU at a specific instruction, because execution has already

begun by the time an operation is visible outside the MCU. A separate

instruction tagging mechanism is provided for this purpose.

Executing the BDM TAGGO command configures two MCU pins for

tagging. The TAGLO signal shares a pin with the LSTRB signal, and the

TAGHI signal shares a pin with the BKGD signal. Tagging information is

latched on the falling edge of ECLK.

Table 57 shows the functions of the two tagging pins. The pins operate

independently - the state of one pin does not affect the function of the

other. The presence of logic level zero on either pin at the fall of ECLK

performs the indicated function. Tagging is allowed in all modes.

Tagging is disabled when BDM becomes active and BDM serial

commands are not processed while tagging is active.

The tag follows program information as it advances through the queue.

When a tagged instruction reaches the head of the queue, the CPU

enters active background debugging mode rather than execute the

instruction.

Table 57 Tag Pin Function

TAGHI TAGLO Tag

1 1 no tag

1 0 low byte

0 1 high byte

0 0 both bytes

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MOTOROLA Electrical Characteristics – Preliminary Data 329

Electrical Characteristics

General Description

Contents

Important Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329

Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329

Tables of Data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331

Important Information

NOTE:

The electrical characteristics given in this section are preliminary and

should be used as a guide only. Values cannot be guaranteed by

Motorola and are subject to change without notice.

Introduction

The MC68HC912DG128 microcontroller unit (MCU) is a16-bit device

composed of standard on-chip peripherals including a 16-bit central

processing unit (CPU12), 128-Kbyte flash EEPROM, 8K byte RAM, 2K

byte EEPROM, two asynchronous serial communications interfaces

(SCI), a serial peripheral interface (SPI), an 8-channel, 16-bit timer,

two16-bit pulse accumulators and 16-bit down counter (ECT), two 10-bit

analog-to-digital converter (ADC), a four-channel pulse-width modulator

(PWM), an IIC interface module, and two MSCAN modules. The chip is

the first 16-bit microcontroller to include both byte-erasable EEPROM

and flash EEPROM on the same device. System resource mapping,

clock generation, interrupt control and bus interfacing are managed by

the Lite integration module (LIM). The MC68HC912DG128 has full 16-bit

data paths throughout, however, the multiplexed external bus can

operate in an 8-bit narrow mode so single 8-bit wide memory can be

interfaced for lower cost systems.

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MC68HC912DG128

330 Electrical Characteristics – Preliminary Data MOTOROLA

This supplement contains the most accurate electrical information for the

MC68HC912DG128 microcontroller available at the time of publication.

The information should be considered PRELIMINARY and is subject to

change. The following characteristics are contained in this document:

Maximum Ratings

Thermal Characteristics

DC Electrical Characteristics

Supply Current

ATD DC Electrical Characteristics

Analog Converter Characteristics (Operating)

ATD AC Characteristics (Operating)

ATD Maximum Ratings

EEPROM Characteristics

Flash EEPROM Characteristics

Pulse Width Modulator Characteristics

Control Timing

Peripheral Port Timing

Multiplexed Expansion Bus Timing

SPI Timing

CGM Characteristics

STOP Key Wake-up Filter

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MC68HC912DG128

MOTOROLA Electrical Characteristics – Preliminary Data 331

Tables of Data

1. Permanent damage can occur if maximum ratings are exceeded. Exposures to voltages or currents in excess of recom-

mended values affects device reliability. Device modules may not operate normally while being exposed to electrical ex-

tremes.

2. One pin at a time, observing maximum power dissipation limits. Internal circuitry protects the inputs against damage caused

by high static voltages or electric fields; however, normal precautions are necessary to avoid application of any voltage

higher than maximum-rated voltages to this high-impedance circuit. Extended operation at the maximum ratings can ad-

versely affect device reliability. Tying unused inputs to an appropriate logic voltage level (either GND or VDD) enhances

reliability of operation.

1. This is an approximate value, neglecting PI/O.

2. For most applications PI/O « PINT and can be neglected.

Table 58 Maximum Ratings(1)

Rating Symbol Value Unit

Supply voltage VDD, VDDA,

VDDX −0.3 to +6.5 V

Input voltage VIN −0.3 to +6.5 V

Operating temperature range TA

TL to TH

0 to +70

−40 to +85 °C

Storage temperature range Tstg −55 to +150 °C

Current drain per pin(2)

Excluding VDD and VSS IIN ±25 mA

VDD differential voltage VDD−VDDX 6.5 V

Table 59 Thermal Characteristics

Characteristic Symbol Value Unit

Average junction temperature TJTA + (PD × ΘJA)°C

Ambient temperature TAUser-determined °C

Package thermal resistance (junction-to-ambient)

112-pin quad ﬂat pack (QFP) ΘJA 85 °C/W

Total power dissipation(1) PD

PINT + PI/O or W

Device internal power dissipation PINT IDD × VDD W

I/O pin power dissipation(2) PI/O User-determined W

A constant(3) KP

D × (TA + 273°C) + ΘJA × PD2 W · °C

TJ273°C+

--------------------------

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332 Electrical Characteristics – Preliminary Data MOTOROLA

3. K is a constant pertaining to the device. Solve for K with a known TA and a measured PD (at equilibrium). Use this value of

K to solve for PD and TJ iteratively for any value of TA.

Table 60 DC Electrical Characteristics

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

Characteristic Symbol Min Max Unit

Input high voltage, all inputs VIH 0.7 × VDD VDD + 0.3 V

Input low voltage, all inputs VIL VSS−0.3 0.2 × VDD V

Output high voltage, all I/O and output pins except XTAL

Normal drive strength

IOH = −10.0 µA

IOH = −0.8 mA

Reduced drive strength

IOH = −4.0 µA

IOH = −0.3 mA

VOH

VDD − 0.2

VDD − 0.8

VDD − 0.2

VDD − 0.8

—

Output low voltage, all I/O and output pins except XTAL

Normal drive strength

IOL = 10.0 µA

IOL = 1.6 mA

Reduced drive strength

IOL = 3.6 µA

IOL = 0.6 mA

VOL

—

VSS+0.2

VSS+0.4

VSS+0.2

VSS+0.4

Input leakage current(1)

Vin = VDD or VSSAll input only pins except IRQ, ATD(2) and

VFP

Vin = VDD or VSSIRQ

Iin —

—±2.5

±10 µA

µA

Three-state leakage, I/O ports, BKGD, and RESET IOZ — ±2.5 µA

Input capacitance

All input pins and ATD pins (non-sampling)

ATD pins (sampling)

All I/O pins

Cin —

—

Output load capacitance

All outputs except PS[7:4]

PS[7:4] when conﬁgured as SPI CL—

— 90

200 pF

Programmable active pull-up/pull-down current

IRQ, XIRQ, DBE, LSTRB, R/W. ports A, B, H, J, K, P, S, T

MODA, MODB active pull down during reset

BKGD passive pull up

IAPU

500

µA

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MOTOROLA Electrical Characteristics – Preliminary Data 333

1. Specification is for parts in the -40 to +85°C range. Higher temperature ranges will result in increased

current leakage.

2. See <BOLD>Table 62 ATD DC Electrical Characteristics.

1. Includes IDD and IDDA.

Table 61 Supply Current

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

Characteristic Symbol 2 MHz 4 MHz 8 MHz Unit

Maximum total supply current

RUN:

Single-chip mode

Expanded mode

IDD TBD

TBD TBD

TBD mA

WAIT: (All peripheral functions shut down)

Single-chip mode

Expanded mode

WIDD TBD

TBD TBD

TBD mA

STOP:

Single-chip mode, no clocks

−40 to +85

+85 to +105

+105 to +125

SIDD 10

µA

Maximum power dissipation(1)

Single-chip mode

Expanded mode PDTBD

TBD TBD

TBD mW

Table 62 ATD DC Electrical Characteristics

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted

Characteristic Symbol Min Max Unit

Analog supply voltage VDDA 4.5 5.5 V

Analog supply currentNormal operation

STOP IDDA 1.0

10 mA

µA

Reference voltage, low VRL VSSA VDDA/2V

Reference voltage, high VRH VDDA/2V

DDA V

VREF differential reference voltage(1) VRH−VRL 4.5 5.5 V

Input voltage(2) VINDC VSSA VDDA V

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334 Electrical Characteristics – Preliminary Data MOTOROLA

1. Accuracy is guaranteed at VRH − VRL = 5.0V ±10%.

2. To obtain full-scale, full-range results, VSSA ≤ VRL ≤ VINDC ≤ VRH ≤ VDDA.

3. Maximum leakage occurs at maximum operating temperature. Current decreases by approximately one-half for each 10°C

decrease from maximum temperature.

1. VRH − VRL ≥ 5.12V; VDDA − VSSA = 5.12V

2. At VREF = 5.12V, one 8-bit count = 20 mV.

3. Eight-bit absolute error of 1 count (20 mV) includes 1/2 count (10 mV) inherent quantization error and 1/2 count (10 mV)

circuit (differential, integral, and offset) error.

4. Maximum source impedance is application-dependent. Error resulting from pin leakage depends on junction leakage into

the pin and on leakage due to charge-sharing with internal capacitance.

Error from junction leakage is a function of external source impedance and input leakage current. Expected error in result

value due to junction leakage is expressed in voltage (VERRJ):

VERRJ = RS × IOFF

where IOFF is a function of operating temperature. Charge-sharing effects with internal capacitors are a function of ATD clock

speed, the number of channels being scanned, and source impedance. For 8-bit conversions, charge pump leakage is

computed as follows: VERRJ = .25pF × VDDA × RS × ATDCLK/(8 × number of channels)

Input current, off channel(3) IOFF 100 µA

Reference supply current IREF 50 µA

Input capacitanceNot Sampling

Sampling CINN

CINS

15 pF

Table 62 ATD DC Electrical Characteristics

Table 63 Analog Converter Characteristics (Operating)

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted

Characteristic Symbol Min Typical Max Unit

10-bit resolution(1) 1 count 20 mV

Differential non-linearity(2) DNL −0.5 +0.5 count

Integral non-linearity(2) INL −1+1count

Absolute error(2),(3) 2, 4, 8, and 16 ATD sample clocks AE −1+1count

Maximum source impedance RS20 See

note(4) KΩ

Table 64 ATD AC Characteristics (Operating)

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, ATD Clock = 2 MHz, unless otherwise noted

Characteristic Symbol Min Max Unit

ATD operating clock frequency fATDCLK 0.5 2.0 MHz

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MOTOROLA Electrical Characteristics – Preliminary Data 335

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1. From the time ADPU is asserted until the time an ATD conversion can begin.

1. RC oscillator must be enabled if programming is desired and fSYS < fPROG.

Conversion time per channel

0.5 MHz ≤ fATDCLK ≤ 2 MHz

16 ATD clocks

30 ATD clocks

tCONV 8.0

15.0 32.0

60.0 µs

µs

Stop and ATD power up recovery time(1) VDDA = 5.0V tSR 10 µs

Table 64 ATD AC Characteristics (Operating)

Table 65 ATD Maximum Ratings

Characteristic Symbol Value Units

ATD reference voltage

VRH ≤ VDDA

VRL ≥ VSSA

VRH

VRL

−0.3 to +6.5

−0.3 to +6.5 V

VSS differential voltage |VSS−VSSA|0.1 V

VDD differential voltage VDD−VDDA

VDDA−VDD

6.5

0.3 V

VREF differential voltage |VRH−VRL|6.5 V

Reference to supply differential voltage |VRH−VDDA|6.5 V

Table 66 EEPROM Characteristics

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

Characteristic Symbol Min Typical Max Unit

Minimum programming clock frequency(1) fPROG 1.0 MHz

Programming time tPROG 10 ms

Clock recovery time, following STOP, to continue programming tCRSTOP tPROG+ 1ms

Erase time tERASE 10 ms

Write/erase endurance 10,000 30,000 cycles

Data retention 10 years

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MC68HC912DG128

336 Electrical Characteristics – Preliminary Data MOTOROLA

1. The number of margin pulses required is the same as the number of pulses used to program or erase.

Table 67 Flash EEPROM Characteristics

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

Characteristic Symbol Min Typical Max Units

Program/erase supply voltage:

Read only

Program / erase / verify VFP VDD−0.35

11.4 VDD

12 VDD+0.35

12.6 V

Program/erase supply current

Word program(VFP = 12V)

Erase(VFP = 12V) IFP 30

4mA

Number of programming pulses nPP 50 pulses

Programming pulse tPPULSE 20 25 µs

Program to verify time tVPROG 10 µs

Program margin pm100(1) %

Number of erase pulses nEP 5 pulses

Erase pulse tEPULSE 90 100 110 ms

Erase to verify time tVERASE 1 ms

Erase margin em100(1) %

Program/erase endurance 100 cycles

Data retention 10 years

Table 68 Pulse Width Modulator Characteristics

VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

Characteristic Symbol Min Max Unit

E-clock frequency feclk 8.0 MHz

A-clock frequency

Selectable faclk feclk/128 feclk Hz

B-clock frequency

Selectable fbclk feclk/128 feclk Hz

Left-aligned PWM frequency

8-bit

16-bit flpwm feclk/1M

feclk/256M feclk/2

feclk/2 Hz

Left-aligned PWM resolution rlpwm feclk/4K feclk Hz

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MOTOROLA Electrical Characteristics – Preliminary Data 337

9-elec

1. RESET is recognized during the first clock cycle it is held low. Internal circuitry then drives

the pin low for 16 clock cycles, releases the pin, and samples the pin level 8 cycles later

to determine the source of the interrupt.

Center-aligned PWM frequency

8-bit

16-bit fcpwm feclk/2M

feclk/512M feclk

feclk

Center-aligned PWM resolution rcpwm feclk/4K feclk Hz

Table 68 Pulse Width Modulator Characteristics

Table 69 Control Timing

Characteristic Symbol 8.0 MHz Unit

Min Max

Frequency of operation fodc 8.0 MHz

E-clock period tcyc 125 — ns

Crystal frequency fXTAL — 16.0 MHz

External oscillator frequency 2fodc 16.0 MHz

Processor control setup time

tPCSU = tcyc/4 + 40 tPCSU 71 — ns

Reset input pulse width

To guarantee external reset vector

Minimum input time (can be preempted by internal reset) PWRSTL 32

2—

—tcyc

tcyc

Mode programming setup time tMPS 4—t

cyc

Mode programming hold time tMPH 10 — ns

Interrupt pulse width, IRQ edge-sensitive mode

PWIRQ = 2tcyc + 20 PWIRQ 270 — ns

Wait recovery startup time tWRS — TBD tcyc

Timer input capture pulse width PWTIM TBD — ns

Pulse accumulator pulse width PWPA TBD — ns

Electrical Characteristics

MC68HC912DG128

338 Electrical Characteristics – Preliminary Data MOTOROLA

Figure 63 Timer Inputs

PT72

PT71

PT[7:0]2

PT[7:0]1

NOTES:

1. Rising edge sensitive input

2. Falling edge sensitive input

PWTIM

PWPA

10-elec

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MOTOROLA Electrical Characteristics – Preliminary Data 339

11-elec

Figure 64 POR and External Reset Timing Diagram

tPCSU

INTERNAL

MODA, MODB

ECLK

EXTAL

VDD

RESET

4098 tcyc

FREE

FFFEFFFE 3RD1ST 2ND FREE

FFFEFFFEFFFE

tMPH

PWRSTL

tMPS

ADDRESS PIPE PIPE PIPE 1ST

EXEC 3RD

PIPE

2ND

PIPE

1ST

PIPE 1ST

EXEC

NOTE: Reset timing is subject to change.

Electrical Characteristics

MC68HC912DG128

340 Electrical Characteristics – Preliminary Data MOTOROLA

Figure 65 STOP Recovery Timing Diagram

PWIRQ

tSTOPDELAY 3

IRQ1

IRQ

or XIRQ

ECLK

1ST

ADDRESS 4SP-9

FREE

VECTOR FREE

FREE

Resume program with instruction which follows the STOP instruction.

INTERNAL

ADDRESS 5

CLOCKS

NOTES:

1. Edge Sensitive IRQ pin (IRQE bit = 1)

2. Level sensitive IRQ pin (IRQE bit = 0)

3. tSTOPDELAY = 4098 tcyc if DLY bit = 1 or 2 t

cyc if DLY = 0.

4. XIRQ with X bit in CCR = 1.

5. IRQ or (XIRQ with X bit in CCR = 0).

OPT 1ST

2ND 3RD 1ST

EXEC

PIPE PIPE EXEC

SP-8

SP-6 FETCH

PIPE

SP-6 SP-8 SP-9

12-elec

Electrical Characteristics – Preliminary Data

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MC68HC912DG128

MOTOROLA Electrical Characteristics – Preliminary Data 341

13-elec

Figure 66 WAIT Recovery Timing Diagram

tPCSU

PC, IY, IX, B:A, , CCR

STACK REGISTERS

ECLK

R/W

ADDRESS

IRQ, XIRQ,

OR INTERNAL

INTERRUPTS

SP – 2 SP – 4 SP – 6 . . . SP – 9 SP – 9 SP – 9 . . . SP – 9 SP – 9 VECTOR FREE 1ST 2ND 3RD

PIPE

tWRS

NOTE: RESET also causes recovery from WAIT.

ADDRESS PIPE PIPE 1ST

EXEC

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342 Electrical Characteristics – Preliminary Data MOTOROLA

Figure 67 Interrupt Timing Diagram

ECLK

PWIRQ

1ST3RD

ADDRESS

IRQ1

SP – 9

tPCSU

IRQ2, XIRQ,

OR INTERNAL

INTERRUPT

VECTOR SP – 2 1ST SP – 4 SP – 6 2ND SP – 8

DATA VECT PC IY IX B:A CCR PROG

R/W

NOTES:

1. Edge sensitive IRQ pin (IRQE bit = 1)

2. Level sensitive IRQ pin (IRQE bit = 0)

FETCH

ADDR EXECPIPEPIPEPIPE

PROG

FETCH

PROG

FETCH

14-elec

Electrical Characteristics – Preliminary Data

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MC68HC912DG128

MOTOROLA Electrical Characteristics – Preliminary Data 343

15-elec

Figure 68 Port Read Timing Diagram

Figure 69 Port Write Timing Diagram

Table 70 Peripheral Port Timing

Characteristic Symbol 8.0 MHz Unit

Min Max

Frequency of operation (E-clock frequency) fodc 8.0 MHz

E-clock period tcyc 125 — ns

Peripheral data setup time

MCU read of ports tPDSU TBD — ns

Peripheral data hold time

MCU read of ports tPDH 0—ns

Delay time, peripheral data write

MCU write to ports tPWD —40ns

PORT RD TIM

ECLK

MCU READ OF PORT

PORTS

tPDSU tPDH

PORT WR TIM

ECLK

MCU WRITE TO PORT

PREVIOUS PORT DATA NEW DATA VALID

PORT A

tPWD

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344 Electrical Characteristics – Preliminary Data MOTOROLA

EXTREMELY PRELIMINARY - BEING CHARACTERIZED

1. All timings are calculated for normal port drives.

2. Crystal input is required to be within 45% to 55% duty.

3. Reduced drive must be off to meet these timings.

4. Unequalled loading of pins will affect relative timing numbers.

5. This characteristic is affected by clock stretch.

Add N × tcyc where N = 0, 1, 2, or 3, depending on the number of clock stretches.

6. Without TAG enabled.

Table 71 Multiplexed Expansion Bus Timing

VDD = 5.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted

Num Characteristic(1), (2), (3), (4) Delay Symbol 8 MHz Unit

Min Max

Frequency of operation (E-clock frequency) fodc 8.0 MHz

1Cycle time tcyc = 1/fo—t

cyc 125 — ns

2Pulse width, E low PWEL = tcyc/2 + delay −2PW

EL 60 ns

3Pulse width, E high(5) PWEH = tcyc/2 + delay −2PW

EH 60 ns

5Address delay time tAD = tcyc/4 + delay 9 tAD 40 ns

7Address valid time to ECLK rise tAV = PWEL − tAD —t

AV 20 ns

8Multiplexed address hold time tMAH = tcyc/4 + delay −10 tMAH 21 ns

9Address Hold to Data Valid — tAHDS 5

10 Data Hold to High Z tDHZ = tAD − 20 — tDHZ 20

11 Read data setup time — tDSR 18 ns

12 Read data hold time — tDHR 0ns

13 Write data delay time tDDW = tcyc/4 + delay 14 tDDW 45 ns

14 Write data hold time tDHW = tcyc/4 + delay −6t

DHW 25 ns

15 Write data setup time(5) tDSW = PWEH − tDDW —t

DSW 15 ns

16 Read/write delay time tRWD = tcyc/4 + delay 9 tRWD 40 ns

17 Read/write valid time to E rise tRWV = PWEL − tRWD —t

RWV 20 ns

18 Read/write hold time tRWH = tcyc/4 + delay −6t

RWH 25 ns

19 Low strobe(6) delay time tLSD = tcyc/4 + delay 9 tLSD 40 ns

20 Low strobe(6) valid time to E rise tLSV = PWEL − tLSD —t

LSV 20 ns

21 Low strobe(6) hold time tLSH = tcyc/4 + delay −6t

LSH 25 ns

22 Address access time(5) tACCA = tcyc − tAD − tDSR —t

ACCA 67 ns

23 Access time from E rise(5) tACCE = PWEH − tDSR —t

ACCE 42 ns

24 DBE delay from ECLK rise(5) tDBED = tcyc/4 + delay 6 tDBED 37 ns

25 DBE valid time tDBE = PWEH − tDBED —t

DBE 23 ns

26 DBE hold time from ECLK fall tDBEH 010ns

16-elec

Electrical Characteristics – Preliminary Data

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MC68HC912DG128

MOTOROLA Electrical Characteristics – Preliminary Data 345

17-elec

Figure 70 Multiplexed Expansion Bus Timing Diagram

DBE

24 25

ECLK

R/W

2 3

11 12

NOTE: Measurement points shown are 20% and 70% of V DD

16 17

READ

WRITE

LSTRB

2119 20

(W/O TAG ENABLED)

5 7 22

815

ADDRESS/DATA

MULTIPLEXED

ADDRESS

DATA

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MC68HC912DG128

346 Electrical Characteristics – Preliminary Data MOTOROLA

1. All AC timing is shown with respect to 20% VDD and 70% VDD levels unless otherwise noted.

Table 72 SPI Timing

(VDD = 5.0 Vdc ±10%, VSS = 0 Vdc, TA = TL to TH , 200 pF load on all SPI pins)(1)

Num Function Symbol Min Max Unit

Operating Frequency

Master

Slave fop DC

DC 1/2

1/2

E-clock

frequency

SCK Period

Master

Slave tsck 2

2256

—tcyc

tcyc

Enable Lead Time

Master

Slave tlead 1/2

1—

—tsck

tcyc

Enable Lag Time

Master

Slave tlag 1/2

1—

—tsck

tcyc

Clock (SCK) High or Low Time

Master

Slave twsck tcyc − 60

tcyc − 30 128 tcyc

—ns

Sequential Transf er Delay

Master

Slave ttd 1/2

1—

—tsck

tcyc

Data Setup Time (Inputs)

Master

Slave tsu 30

30 —

—ns

Data Hold Time (Inputs)

Master

Slave thi 0

30 —

—ns

Slave Access Time ta—1t

cyc

Slave MISO Disable Time tdis —1t

cyc

Data Valid (after SCK Edge)

Master

Slave tv—

—50

50 ns

Data Hold Time (Outputs)

Master

Slave tho 0

0—

—ns

Rise Time

Input

Output tri

tro

—

—tcyc − 30

30 ns

F all Time

Input

Output tﬁ

tfo

—

—tcyc − 30

30 ns

18-elec

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MC68HC912DG128

MOTOROLA Electrical Characteristics – Preliminary Data 347

19-elec

A) SPI Master Timing (CPHA =M 0)

B) SPI Master Timing (CPHA = 1)

Figure 71 SPI Timing Diagram (1 of 2)

SCK

(OUTPUT)

SCK

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

SS1

(OUTPUT)

6 7

MSB IN2

BIT 6 . . . 1

LSB IN

MSB OUT 2LSB OUT

BIT 6 . . . 1

(CPOL = 0)

(CPOL = 1)

1. SS output mode (DDS7 = 1, SSOE = 1).

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

SCK

(OUTPUT)

SCK

(OUTPUT)

MISO

(INPUT)

MOSI

(OUTPUT)

6 7

MSB IN2

BIT 6 . . . 1

LSB IN

MASTER MSB OUT 2MASTER LSB OUT

BIT 6 . . . 1

12 13

PORT DATA

(CPOL = 0)

(CPOL = 1)

PORT DATA

SS1

(OUTPUT) 5

213 12 3

1. SS output mode (DDS7 = 1, SSOE = 1).

2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.

Electrical Characteristics

MC68HC912DG128

348 Electrical Characteristics – Preliminary Data MOTOROLA

A) SPI Slave Timing (CPHA = 0)

B) SPI Slave Timing (CPHA = 1)

Figure 72 SPI Timing Diagram (2 of 2)

SCK

(INPUT)

SCK

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

(INPUT)

6 7

MSB IN

BIT 6 . . . 1

LSB IN

MSB OUT SLAVE LSB OUT

BIT 6 . . . 1

(CPOL = 0)

(CPOL = 1)

NOTE: Not defined but normally MSB of character just received.

SLAVE

SEE

NOTE

SPI SLAVE CPHA1

SCK

(INPUT)

SCK

(INPUT)

MOSI

(INPUT)

MISO

(OUTPUT)

6 7

MSB IN

BIT 6 . . . 1

LSB IN

MSB OUT SLAVE LSB OUT

BIT 6 . . . 1

12 13

SEE

(CPOL = 0)

(CPOL = 1)

(INPUT) 5

213 12 3

NOTE: Not defined but normally LSB of character just received.

SLAVE

NOTE

20-elec

Electrical Characteristics – Preliminary Data

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MC68HC912DG128

MOTOROLA Electrical Characteristics – Preliminary Data 349

1. VDDPLL at VDD level.

Table 73 CGM Characteristics

5.0 Volts +/- 10%

Characteristic Symbol Min. Max. Unit

PLL reference frequency, crystal oscillator range(1) fREF 0.5 8 MHz

System frequency fSYS D.C. 8 MHz

VCO range fVCO 2.5 8 MHz

VCO Limp-Home frequency fVCOMIN 0.5 2.5 MHz

Lock Detector transition from Acquisition to Tracking mode ∆trk 3% 4% —

Lock Detection ∆Lock 0% 1.5% —

Un-Lock Detection ∆unl 0.5% 2.5% —

Lock Detector transition from Tracking to Acquisition mode ∆unt 6% 8% —

PLLON Acquisition mode stabilization delay. tacq TBD ms

PLLON tracking mode stabilization delay. tal TBD ms

Table 74 STOP Key Wake-up Filter

Characteristic Symbol Min. Max. Unit

STOP Key Wake-Up Filter time tKWSTP 210µs

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MC68HC912DG128

350 Electrical Characteristics – Preliminary Data MOTOROLA

MC68HC912DG128

MOTOROLA Glossary 351

Glossary

A — See “accumulators (A, B and D).”

accumulators (A, B and D) — Two 8-bit and one 16-bit general-purpose registers in the CPU.

The CPU uses the accumulators to hold operands and results of arithmetic and logic

operations.

acquisition mode — A mode of PLL operation during startup before the PLL locks on a

frequency. Also see "tracking mode."

address bus — The set of wires that the CPU or DMA uses to read and write memory locations.

addressing mode — The way that the CPU determines the operand address for an instruction.

The M68HC12 CPU has 15 addressing modes.

ALU — See “arithmetic logic unit (ALU).”

arithmetic logic unit (ALU) — The portion of the CPU that contains the logic circuitry to perform

arithmetic, logic, and manipulation operations on operands.

asynchronous — Refers to logic circuits and operations that are not synchronized by a common

reference signal.

B — See “accumulators (A, B and D).”

baud rate — The total number of bits transmitted per unit of time.

BCD — See “binary-coded decimal (BCD).”

binary — Relating to the base 2 number system.

binary number system — The base 2 number system, having two digits, 0 and 1. Binary

arithmetic is convenient in digital circuit design because digital circuits have two

permissible voltage levels, low and high. The binary digits 0 and 1 can be interpreted to

correspond to the two digital voltage levels.

binary-coded decimal (BCD) — A notation that uses 4-bit binary numbers to represent the 10

decimal digits and that retains the same positional structure of a decimal number. For

example,

234 (decimal) = 0010 0011 0100 (BCD)

Glossary

MC68HC912DG128

352 Glossary MOTOROLA

bit — A binary digit. A bit has a value of either logic 0 or logic 1.

branch instruction — An instruction that causes the CPU to continue processing at a memory

location other than the next sequential address.

break module — The break module allows software to halt program execution at a

programmable point in order to enter a background routine.

breakpoint — A number written into the break address registers of the break module. When a

number appears on the internal address bus that is the same as the number in the break

address registers, the CPU executes the software interrupt instruction (SWI).

break interrupt — A software interrupt caused by the appearance on the internal address bus

of the same value that is written in the break address registers.

bus — A set of wires that transfers logic signals.

bus clock — The bus clock is derived from the CGMOUT output from the CGM. The bus clock

frequency, fop, is equal to the frequency of the oscillator output, CGMXCLK, divided by

four.

byte — A set of eight bits.

C — The carry/borrow bit in the condition code register. The CPU sets the carry/borrow bit when

an addition operation produces a carry out of bit 7 of the accumulator or when a

subtraction operation requires a borrow. Some logical operations and data manipulation

instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and

shifts and rotates).

CCR — See “condition code register.”

central processor unit (CPU) — The primary functioning unit of any computer system. The

CPU controls the execution of instructions.

CGM — See “clock generator module (CGM).”

clear — To change a bit from logic 1 to logic 0; the opposite of set.

clock — A square wave signal used to synchronize events in a computer.

Glossary

MC68HC912DG128

MOTOROLA Glossary 353

clock generator module (CGM) — The CGM module generates a base clock signal from which

the system clocks are derived. The CGM may include a crystal oscillator circuit and or

phase-locked loop (PLL) circuit.

comparator — A device that compares the magnitude of two inputs. A digital comparator defines

the equality or relative differences between two binary numbers.

computer operating properly module (COP) — A counter module that resets the MCU if

allowed to overflow.

condition code register (CCR) — An 8-bit register in the CPU that contains the interrupt mask

bit and five bits that indicate the results of the instruction just executed.

control bit — One bit of a register manipulated by software to control the operation of the

module.

control unit — One of two major units of the CPU. The control unit contains logic functions that

synchronize the machine and direct various operations. The control unit decodes

instructions and generates the internal control signals that perform the requested

operations. The outputs of the control unit drive the execution unit, which contains the

arithmetic logic unit (ALU), CPU registers, and bus interface.

COP — See "computer operating properly module (COP)."

counter clock — The input clock to the TIM counter. This clock is the output of the TIM

prescaler.

CPU — See “central processor unit (CPU).”

CPU12 — The CPU of the MC68HC12 Family.

CPU clock — The CPU clock is derived from the CGMOUT output from the CGM. The CPU

clock frequency is equal to the frequency of the oscillator output, CGMXCLK, divided by

four.

CPU cycles — A CPU cycle is one period of the internal bus clock, normally derived by dividing

a crystal oscillator source by two or more so the high and low times will be equal. The

length of time required to execute an instruction is measured in CPU clock cycles.

Glossary

MC68HC912DG128

354 Glossary MOTOROLA

CPU registers — Memory locations that are wired directly into the CPU logic instead of being

part of the addressable memory map. The CPU always has direct access to the

information in these registers. The CPU registers in an M68HC12 are:

• A (8-bit accumulator)

• B (8-bit accumulator)

• D (16-bit accumulator)

• IX (16-bit index register)

• IY (16-bit index register)

• SP (16-bit stack pointer)

• PC (16-bit program counter)

• CCR (8-bit condition code register containing the V, H, I, N, Z, and C bits)

CSIC — customer-specified integrated circuit

cycle time — The period of the operating frequency: tCYC = 1/fOP.

D — See “accumulators (A, B and D).”

decimal number system — Base 10 numbering system that uses the digits zero through nine.

direct memory access module (DMA) — A module that can perform data transfers between

any two CPU-addressable locations without CPU intervention. For transmitting or

receiving blocks of data to or from peripherals, DMA transfers are faster and more

code-efficient than CPU interrupts.

DMA — See "direct memory access module (DMA)."

DMA service request — A signal from a peripheral to the DMA module that enables the DMA

module to transfer data.

duty cycle — A ratio of the amount of time the signal is on versus the time it is off. Duty cycle is

usually represented by a percentage.

EEPROM — Electrically erasable, programmable, read-only memory. A nonvolatile type of

memory that can be electrically reprogrammed.

EPROM — Erasable, programmable, read-only memory. A nonvolatile type of memory that can

be erased by exposure to an ultraviolet light source and then reprogrammed.

exception — An event such as an interrupt or a reset that stops the sequential execution of the

instructions in the main program.

Glossary

MC68HC912DG128

MOTOROLA Glossary 355

external interrupt module (IRQ) — A module with both dedicated external interrupt pins and

port pins that can be enabled as interrupt pins.

fetch — To copy data from a memory location into the accumulator.

firmware — Instructions and data programmed into nonvolatile memory.

free-running counter — A device that counts from zero to a predetermined number, then rolls

over to zero and begins counting again.

full-duplex transmission — Communication on a channel in which data can be sent and

received simultaneously.

H — The half-carry bit in the condition code register of the CPU. This bit indicates a carry from

the low-order four bits of the accumulator value to the high-order four bits. The half-carry

bit is required for binary-coded decimal arithmetic operations. The decimal adjust

accumulator (DAA) instruction uses the state of the H and C bits to determine the

appropriate correction factor.

hexadecimal — Base 16 numbering system that uses the digits 0 through 9 and the letters A

through F.

high byte — The most significant eight bits of a word.

illegal address — An address not within the memory map

illegal opcode — A nonexistent opcode.

I — The interrupt mask bit in the condition code register of the CPU. When I is set, all interrupts

are disabled.

index registers (IX and IY) — Two 16-bit registers in the CPU. In the indexed addressing

modes, the CPU uses the contents of IX or IY to determine the effective address of the

operand. IX and IY can also serve as a temporary data storage locations.

input/output (I/O) — Input/output interfaces between a computer system and the external world.

A CPU reads an input to sense the level of an external signal and writes to an output to

change the level on an external signal.

Glossary

MC68HC912DG128

356 Glossary MOTOROLA

instructions — Operations that a CPU can perform. Instructions are expressed by programmers

as assembly language mnemonics. A CPU interprets an opcode and its associated

operand(s) and instruction.

interrupt — A temporary break in the sequential execution of a program to respond to signals

from peripheral devices by executing a subroutine.

interrupt request — A signal from a peripheral to the CPU intended to cause the CPU to

execute a subroutine.

I/O — See “input/output (I/0).”

IRQ — See "external interrupt module (IRQ)."

jitter — Short-term signal instability.

latch — A circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power

is applied to the circuit.

latency — The time lag between instruction completion and data movement.

least significant bit (LSB) — The rightmost digit of a binary number.

logic 1 — A voltage level approximately equal to the input power voltage (VDD).

logic 0 — A voltage level approximately equal to the ground voltage (VSS).

low byte — The least significant eight bits of a word.

low voltage inhibit module (LVI) — A module that monitors power supply voltage.

LVI — See "low voltage inhibit module (LVI)."

M68HC12 — A Motorola family of 8-bit MCUs.

mark/space — The logic 1/logic 0 convention used in formatting data in serial communication.

mask — 1. A logic circuit that forces a bit or group of bits to a desired state. 2. A photomask used

in integrated circuit fabrication to transfer an image onto silicon.

Glossary

MC68HC912DG128

MOTOROLA Glossary 357

mask option — A optional microcontroller feature that the customer chooses to enable or

disable.

mask option register (MOR) — An EPROM location containing bits that enable or disable

certain MCU features.

MCU — Microcontroller unit. See “microcontroller.”

memory location — Each M68HC12 memory location holds one byte of data and has a unique

address. To store information in a memory location, the CPU places the address of the

location on the address bus, the data information on the data bus, and asserts the write

signal. To read information from a memory location, the CPU places the address of the

location on the address bus and asserts the read signal. In response to the read signal,

the selected memory location places its data onto the data bus.

memory map — A pictorial representation of all memory locations in a computer system.

microcontroller — Microcontroller unit (MCU). A complete computer system, including a CPU,

memory, a clock oscillator, and input/output (I/O) on a single integrated circuit.

modulo counter — A counter that can be programmed to count to any number from zero to its

maximum possible modulus.

monitor ROM — A section of ROM that can execute commands from a host computer for testing

purposes.

MOR — See "mask option register (MOR)."

most significant bit (MSB) — The leftmost digit of a binary number.

multiplexer — A device that can select one of a number of inputs and pass the logic level of that

input on to the output.

N — The negative bit in the condition code register of the CPU. The CPU sets the negative bit

when an arithmetic operation, logical operation, or data manipulation produces a negative

result.

nibble — A set of four bits (half of a byte).

object code — The output from an assembler or compiler that is itself executable machine code,

or is suitable for processing to produce executable machine code.

Glossary

MC68HC912DG128

358 Glossary MOTOROLA

opcode — A binary code that instructs the CPU to perform an operation.

open-drain — An output that has no pullup transistor. An external pullup device can be

connected to the power supply to provide the logic 1 output voltage.

operand — Data on which an operation is performed. Usually a statement consists of an

operator and an operand. For example, the operator may be an add instruction, and the

operand may be the quantity to be added.

oscillator — A circuit that produces a constant frequency square wave that is used by the

computer as a timing and sequencing reference.

OTPROM — One-time programmable read-only memory. A nonvolatile type of memory that

cannot be reprogrammed.

overflow — A quantity that is too large to be contained in one byte or one word.

page zero — The first 256 bytes of memory (addresses $0000–$00FF).

parity — An error-checking scheme that counts the number of logic 1s in each byte transmitted.

In a system that uses odd parity, every byte is expected to have an odd number of logic

1s. In an even parity system, every byte should have an even number of logic 1s. In the

transmitter, a parity generator appends an extra bit to each byte to make the number of

logic 1s odd for odd parity or even for even parity. A parity checker in the receiver counts

the number of logic 1s in each byte. The parity checker generates an error signal if it finds

a byte with an incorrect number of logic 1s.

PC — See “program counter (PC).”

peripheral — A circuit not under direct CPU control.

phase-locked loop (PLL) — A oscillator circuit in which the frequency of the oscillator is

synchronized to a reference signal.

PLL — See "phase-locked loop (PLL)."

pointer — Pointer register. An index register is sometimes called a pointer register because its

contents are used in the calculation of the address of an operand, and therefore points to

the operand.

polarity — The two opposite logic levels, logic 1 and logic 0, which correspond to two different

voltage levels, VDD and VSS.

polling — Periodically reading a status bit to monitor the condition of a peripheral device.

Glossary

MC68HC912DG128

MOTOROLA Glossary 359

port — A set of wires for communicating with off-chip devices.

prescaler — A circuit that generates an output signal related to the input signal by a fractional

scale factor such as 1/2, 1/8, 1/10 etc.

program — A set of computer instructions that cause a computer to perform a desired operation

or operations.

program counter (PC) — A 16-bit register in the CPU. The PC register holds the address of the

next instruction or operand that the CPU will use.

pull — An instruction that copies into the accumulator the contents of a stack RAM location. The

stack RAM address is in the stack pointer.

pullup — A transistor in the output of a logic gate that connects the output to the logic 1 voltage

of the power supply.

pulse-width — The amount of time a signal is on as opposed to being in its off state.

pulse-width modulation (PWM) — Controlled variation (modulation) of the pulse width of a

signal with a constant frequency.

push — An instruction that copies the contents of the accumulator to the stack RAM. The stack

RAM address is in the stack pointer.

PWM period — The time required for one complete cycle of a PWM waveform.

RAM — Random access memory. All RAM locations can be read or written by the CPU. The

contents of a RAM memory location remain valid until the CPU writes a different value or

until power is turned off.

RC circuit — A circuit consisting of capacitors and resistors having a defined time constant.

read — To copy the contents of a memory location to the accumulator.

reserved memory location — A memory location that is used only in special factory test modes.

Writing to a reserved location has no effect. Reading a reserved location returns an

unpredictable value.

reset — To force a device to a known condition.

Glossary

MC68HC912DG128

360 Glossary MOTOROLA

ROM — Read-only memory. A type of memory that can be read but cannot be changed (written).

The contents of ROM must be specified before manufacturing the MCU.

SCI — See "serial communication interface module (SCI)."

serial — Pertaining to sequential transmission over a single line.

serial communications interface module (SCI) — A module that supports asynchronous

communication.

serial peripheral interface module (SPI) — A module that supports synchronous

communication.

set — To change a bit from logic 0 to logic 1; opposite of clear.

shift register — A chain of circuits that can retain the logic levels (logic 1 or logic 0) written to

them and that can shift the logic levels to the right or left through adjacent circuits in the

chain.

signed — A binary number notation that accommodates both positive and negative numbers.

The most significant bit is used to indicate whether the number is positive or negative,

normally logic 0 for positive and logic 1 for negative. The other seven bits indicate the

magnitude of the number.

software — Instructions and data that control the operation of a microcontroller.

software interrupt (SWI) — An instruction that causes an interrupt and its associated vector

fetch.

SPI — See "serial peripheral interface module (SPI)."

stack — A portion of RAM reserved for storage of CPU register contents and subroutine return

addresses.

stack pointer (SP) — A 16-bit register in the CPU containing the address of the next available

storage location on the stack.

start bit — A bit that signals the beginning of an asynchronous serial transmission.

status bit — A register bit that indicates the condition of a device.

stop bit — A bit that signals the end of an asynchronous serial transmission.

Glossary

MC68HC912DG128

MOTOROLA Glossary 361

subroutine — A sequence of instructions to be used more than once in the course of a program.

The last instruction in a subroutine is a return from subroutine (RTS) instruction. At each

place in the main program where the subroutine instructions are needed, a jump or branch

to subroutine (JSR or BSR) instruction is used to call the subroutine. The CPU leaves the

flow of the main program to execute the instructions in the subroutine. When the RTS

instruction is executed, the CPU returns to the main program where it left off.

synchronous — Refers to logic circuits and operations that are synchronized by a common

reference signal.

TIM — See "timer interface module (TIM)."

timer interface module (TIM) — A module used to relate events in a system to a point in time.

timer — A module used to relate events in a system to a point in time.

toggle — To change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0.

tracking mode — Mode of low-jitter PLL operation during which the PLL is locked on a

frequency. Also see "acquisition mode."

two’s complement — A means of performing binary subtraction using addition techniques. The

most significant bit of a two’s complement number indicates the sign of the number (1

indicates negative). The two’s complement negative of a number is obtained by inverting

each bit in the number and then adding 1 to the result.

unbuffered — Utilizes only one register for data; new data overwrites current data.

unimplemented memory location — A memory location that is not used. Writing to an

unimplemented location has no effect. Reading an unimplemented location returns an

unpredictable value. Executing an opcode at an unimplemented location causes an illegal

address reset.

V —The overflow bit in the condition code register of the CPU. The CPU sets the V bit when a

two's complement overflow occurs. The signed branch instructions BGT, BGE, BLE, and

BLT use the overflow bit.

variable — A value that changes during the course of program execution.

VCO — See "voltage-controlled oscillator."

Glossary

MC68HC912DG128

362 Glossary MOTOROLA

vector — A memory location that contains the address of the beginning of a subroutine written

to service an interrupt or reset.

voltage-controlled oscillator (VCO) — A circuit that produces an oscillating output signal of a

frequency that is controlled by a dc voltage applied to a control input.

waveform — A graphical representation in which the amplitude of a wave is plotted against time.

wired-OR — Connection of circuit outputs so that if any output is high, the connection point is

high.

word — A set of two bytes (16 bits).

write — The transfer of a byte of data from the CPU to a memory location.

X — The lower byte of the index register (H:X) in the CPU.

Z — The zero bit in the condition code register of the CPU. The CPU sets the zero bit when an

arithmetic operation, logical operation, or data manipulation produces a result of $00.

MC68HC912DG128

MOTOROLA Revision History 363

Revision History

Glossary

Major HC912DG128 specification changes Ð April 1999

The following are the functional differences between the devices

described in the preliminary document dated March 1988 and the

current version dated April 1999. This document is completely

reformatted in a new template. Note that there are now no section

numbers.

• Flash does not require 250nsec delay for wakeup from wait mode

with FEESWAI=1.

• Reset state of CALE bit in PEAR register is zero.

• PPGS function at PK7 has been replaced by an emulation chip

select function, ECS.

• After a monitor reset, a start-up delay is added for crystal

stabilization.

• BDM lockout is implemented as a new feature.

Revision History

MC68HC912DG128

364 Revision History MOTOROLA

MC68HC912DG128

MOTOROLA Literature Updates 365

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Literature Updates

MC68HC912DG128

366 Literature Updates MOTOROLA

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